JP6530835B2 - How to set on time - Google Patents

Description

  The present invention relates to an on-time setting circuit, and a power supply control IC and a switching power supply device using the same.

  A switching power supply of a non-linear control method (for example, fixed on time, fixed off time, or hysteresis window method) is a switching power supply of a linear control method (for example, voltage mode control method or current mode control method) In comparison, it has the feature that high load response characteristics can be obtained with a simple circuit configuration.

  In addition, some switching power supply devices have a function (so-called reverse current blocking function) of detecting reverse current of coil current at light load and forcibly turning off the synchronous rectification transistor.

  In addition, patent document 1 can be mentioned as an example of the prior art relevant to the above.

U.S. Patent No. 8476887

  However, in the conventional switching power supply, when a laminated ceramic capacitor with a small ESR (equivalent series resistance) is used as the output smoothing capacitor, the output ripple in the discontinuous current mode (= light load state where coil current reverses occur) The problem was that the

  In addition, in the conventional switching power supply, there is no hysteresis in the threshold of the load current at which switching between the continuous current mode (= heavy load state in which reverse current of coil current does not occur) and discontinuous current mode occurs. The switching between the two modes becomes unstable, and there is a problem that the transition between both modes occurs and the output ripple increases.

  In view of the above problems found by the inventors of the present invention, it is an object of the present invention to provide an on-time setting circuit capable of reducing output ripple, and a power control IC and a switching power supply using the same. To aim.

  The on-time setting circuit disclosed in the specification generates a desired output voltage from an input voltage by turning on / off an output transistor and a synchronous rectification transistor to drive a coil, and a switching power supply of a fixed on-time method. It is provided in the device, and in the current discontinuous mode, the on-time is shortened as the load is lighter (first configuration).

  The on-time setting circuit having the first configuration includes a first voltage generation unit that generates a first voltage of a ramp waveform that rises over the on-time, and a second voltage that generates a predetermined second voltage. The generation unit and the comparator for comparing the first voltage and the second voltage to end the on time, the second voltage generation unit may be configured to increase the light load as the load is lighter in the current discontinuous mode. It is good to make it the structure (2nd structure) which pulls down 2 voltage.

  Further, in the on-time setting circuit having the second configuration, the second voltage generation unit integrates the switch voltage appearing at the connection node between the output transistor and the synchronous rectification transistor or a divided voltage thereof and An RC filter for generating two voltages, a current path breaker for interrupting a current path from the input end of the switch voltage to the ground end when switching is stopped, and the second voltage by capacitively dividing the output voltage when switching is resumed It is good to make it the composition (the 3rd composition) including the pull up part which pulls up to a predetermined initial value momentarily.

  In the on-time setting circuit having the third configuration, the pull-up unit may be configured (fourth configuration) to be designed such that the initial value is lower as the load is lighter.

  Further, in the on-time setting circuit having the fourth configuration, the pull-up unit is configured such that the initial value is higher than the integral value obtained by the RC filter in a load region immediately before switching from the discontinuous current mode to the continuous current mode. The configuration may be designed to be high (fifth configuration).

  Further, in the on-time setting circuit having any one of the second to fifth configurations, the second voltage generator transiently lowers the second voltage at the time of switching from the discontinuous current mode to the continuous current mode. The configuration may include the pull-down portion (sixth configuration).

  Further, the on-time setting circuit disclosed in the present specification is an on-time fixed system in which a desired output voltage is generated from an input voltage by turning on / off an output transistor and a synchronous rectification transistor to drive a coil. The switching power supply apparatus is provided with a configuration (seventh configuration) for transiently shortening the on-time at the time of switching from the current discontinuous mode to the current continuous mode.

  The on-time setting circuit having the seventh configuration includes a first voltage generation unit that generates a first voltage of a ramp waveform that rises over the on-time, and a second voltage that generates a predetermined second voltage. The generation unit and the comparator for comparing the first voltage and the second voltage to end the on time, the second voltage generation unit switches from the current discontinuous mode to the current continuous mode The second voltage may be transiently lowered at an instant (eighth configuration).

  Further, the power supply control IC disclosed in the present specification includes: a ripple injection circuit that generates a feedback voltage by superimposing a ripple voltage simulating a coil current on the output voltage or the divided voltage thereof; and a predetermined reference voltage , A main comparator that compares the feedback voltage with the reference voltage to generate a comparison signal, and a one-shot pulse generation circuit that generates a one-shot pulse as a set signal according to the comparison signal And an RS flip-flop which sets the output signal to the first logic level according to the set signal and resets the output signal to the second logic level according to the reset signal, and the output signal has the first logic level. The above-described first to eighth embodiments generate a one-shot pulse in the reset signal when the on-time elapses after being set. An on-time setting circuit having one of the configurations, a gate driver circuit generating drive signals of the output transistor and the synchronous rectification transistor according to the output signal, and detecting the reverse current of the coil current to detect the synchronous rectification transistor And a reverse flow detection circuit for forcibly turning off the circuit. (9th configuration).

  Further, the switching power supply device disclosed in the present specification generates the output voltage from the input voltage by being partially or entirely externally attached to the power supply control IC having the ninth configuration and the power supply control IC. And a switch output stage (10th configuration).

  According to the invention disclosed in the present specification, it is possible to provide an on-time setting circuit capable of reducing output ripple, and a power control IC and a switching power supply using the same.

Block diagram showing the overall configuration of the switching power supply Timing chart showing switching operation under heavy load Timing chart showing reverse current blocking operation at light load Characteristic diagram of switch output stage 20 A schematic diagram showing the behavior of the coil current IL A circuit diagram showing a basic configuration of on time setting circuit 16 Timing chart showing the basic operation of the on-time setting circuit 16 A circuit diagram showing a first modification of the second voltage generation unit Y A circuit diagram showing a second modification of the second voltage generation unit Y Timing chart showing the pull-up operation of the second voltage VY A circuit diagram showing a third modification of the second voltage generation unit Y Timing chart showing the pull-down operation of the second voltage VY Ton-Iout correlation chart Timing chart showing an example of transition of output behavior with load increase / decrease Block diagram showing a configuration example of a television equipped with a switching power supply device Front view of a television equipped with a switching power supply Side view of a television equipped with a switching power supply Rear view of a television equipped with a switching power supply

<Switching power supply>
FIG. 1 is a block diagram showing an entire configuration of a switching power supply device. The switching power supply device 1 of this configuration example is a step-down DC / DC converter that generates an output voltage Vout from an input voltage Vin by a non-linear control method (bottom detection on-time fixed method). The switching power supply 1 includes a semiconductor device 10 and various discrete components (N-channel MOS [metal oxide semiconductor] field effect transistors N1 and N2 externally attached to the semiconductor device 10, a coil L1, a capacitor C1, and a resistor R1. And R2) and the switch output stage 20.

  The semiconductor device 10 is a main body (so-called power control IC) that controls the overall operation of the switching power supply device 1 in an integrated manner. The semiconductor device 10 has external terminals T1 to T7 (upper gate terminal T1, lower gate terminal T2, switch terminal T3, feedback terminal T4, input voltage terminal T5) as means for establishing electrical connection with the outside of the device. , And an output voltage terminal T6 and a ground terminal T7).

  The external terminal T1 is connected to the gate of the transistor N1. The external terminal T2 is connected to the gate of the transistor N2. The external terminal T3 is connected to an application terminal of the switch voltage Vsw (a connection node between the source of the transistor N1 and the drain of the transistor N2). The external terminal T4 is connected to an application terminal of the divided voltage Vdiv (a connection node between the resistor R1 and the resistor R2). The external terminal T5 is connected to the application terminal of the input voltage Vin. The external terminal T6 is connected to the application terminal of the output voltage Vout. The external terminal T7 is connected to the ground end.

  Next, the connection relationship of discrete components externally attached to the semiconductor device 10 will be described. The drain of the transistor N1 is connected to the application terminal of the input voltage Vin. The source of the transistor N2 is connected to the ground terminal. The source of the transistor N1 and the drain of the transistor N2 are both connected to the first end of the coil L1. The second end of the coil L1 and the first end of the capacitor C1 are both connected to the application end of the output voltage Vout. The second end of the capacitor C1 is connected to the ground end. The resistors R1 and R2 are connected in series between the application terminal of the output voltage Vout and the ground terminal.

  The transistor N1 is an output transistor that is on / off controlled according to a gate signal G1 input from the external terminal T1. The transistor N2 is a synchronous rectification transistor that is on / off controlled according to the gate signal G2 input from the external terminal T2. Note that a diode may be used instead of the transistor N2 as the rectifying element. The transistors N1 and N2 can also be incorporated in the semiconductor device 10. The coil L1 and the capacitor C1 function as a rectifying and smoothing unit that rectifies and smoothes a rectangular wave switch voltage Vsw appearing at the external terminal T3 to generate an output voltage Vout. The resistors R1 and R2 function as a divided voltage generation unit that divides the output voltage Vout to generate a divided voltage Vdiv. However, when the output voltage Vout is within the input dynamic range of the ripple injection circuit 11 (or the main comparator 13), the divided voltage generation unit may be omitted.

  Next, the internal configuration of the semiconductor device 10 will be described. The semiconductor device 10 includes a ripple injection circuit 11, a reference voltage generation circuit 12, a main comparator 13, a one-shot pulse generation circuit 14, an RS flip flop 15, an on time setting circuit 16, and a gate driver circuit 17. , And the backflow detection circuit 18 are integrated.

  The ripple injection circuit 11 adds the ripple voltage Vrpl (a pseudo ripple component simulating the coil current IL flowing through the coil L1) to the divided voltage Vdiv to generate a feedback voltage Vfb (= Vdiv + Vrpl). If such a ripple injection technique is introduced, stable switching control can be performed even if the ripple component of the output voltage Vout (and the divided voltage Vdiv as a whole) is not so large. It is possible to use a ceramic capacitor or the like. However, when the ripple component of the output voltage Vout is sufficiently large, the ripple injection circuit 11 can be omitted.

  The reference voltage generation circuit 12 generates a predetermined reference voltage Vref.

  The main comparator 13 compares the feedback voltage Vfb input to the inverting input terminal (-) with the reference voltage Vref input to the non-inverting input terminal (+) to generate a comparison signal S1. The comparison signal S1 is low when the feedback voltage Vfb is higher than the reference voltage Vref, and is high when the feedback voltage Vfb is lower than the reference voltage Vref.

  One-shot pulse generation circuit 14 generates a one-shot pulse (eg, falling pulse) as set signal S2 using the falling edge of comparison signal S1 as a trigger.

  The RS flip-flop 15 sets the output signal S4 to high level at the pulse edge (eg, falling edge) of the set signal S2 input to the set end (S), and the reset signal input to the reset end (R) The output signal S4 is reset to low level at the pulse edge (eg, falling edge) of S3.

  The on-time setting circuit 16 outputs the reset signal S3 after a predetermined on-time Ton elapses after the inverted output signal S4B (= logically inverted signal of the output signal S4) of the RS flip-flop 15 falls to low level. Generate a one-shot pulse (eg, falling pulse).

  The gate driver circuit 17 generates gate signals G1 and G2 in accordance with the output signal S4 of the RS flip flop 15, and switches the transistors N1 and N2 complementarily. The term "complementary" used in the present specification includes the case where on / off of the transistors N1 and N2 is completely reversed, and also the transistor N1 and N2 from the viewpoint of through current prevention. It also includes the case where a delay is given to the on / off transition timing (when a so-called simultaneous off period (dead time) is provided).

  The backflow detection circuit 18 monitors the backflow of the coil current IL (the coil current IL flowing from the coil L1 to the ground terminal via the transistor N2) to generate a backflow detection signal S5. The backflow detection signal S5 is latched at high level (logic level at the time of backflow detection) when backflow of the coil current IL is detected, and low level at the rising edge of the gate signal G1 in the next cycle (logic when no backflow detection) Reset to level). As a method of monitoring the backflow of the coil current IL, for example, a zero crossing point at which the switch voltage Vsw switches from negative to positive may be detected during the on period of the transistor N2. When the backflow detection signal S5 is at high level, the gate driver circuit 17 generates the gate signal G2 so as to forcibly turn off the transistor N2 without depending on the output signal S4.

  The ripple injection circuit 11, the reference voltage generation circuit 12, the main comparator 13, the one-shot pulse generation circuit 14, the RS flip flop 15, the on time setting circuit 16, the gate driver circuit 17, and the backflow detection circuit 18 A non-linear control method of generating the output voltage Vout from the input voltage Vin by performing on / off control of the transistors N1 and N2 according to the comparison result of the feedback voltage Vfb and the reference voltage Vref (bottom detection on time in this configuration example Functions as a fixed type switching control circuit.

<Switching operation>
FIG. 2 is a timing chart showing the switching operation under heavy load (in the continuous current mode), in which the feedback voltage Vfb, the set signal S2, the reset signal S3, and the output signal S4 are depicted sequentially from the top.

  At time t11, when the feedback voltage Vfb decreases to the reference voltage Vref, the set signal S2 falls to low level, and the output signal S4 is transitioned to high level. Therefore, the transistor N1 is turned on, and the feedback voltage Vfb turns to rise.

  Thereafter, when the reset signal S3 falls to low level at time t12 due to the elapse of the on time Ton, the output signal S4 is shifted to low level. Therefore, the transistor N1 is turned off, and the feedback voltage Vfb falls again.

  The gate driver circuit 17 generates gate signals G1 and G2 according to the output signal S4, and performs on / off control of the transistors N1 and N2 using these. Specifically, when the output signal S4 is at high level, basically, the gate signal G1 is set to high level to turn on the transistor N1, and the gate signal G2 is set to low level to turn off the transistor N2 Be done. Conversely, when the output signal S4 is at low level, basically, the gate signal G1 is at low level to turn off the transistor N1, and the gate signal G2 is at high level to turn on the transistor N2.

  Due to the on / off control of the transistors N1 and N2 described above, a switch voltage Vsw having a rectangular wave shape appears at the external terminal T3. The switch voltage Vsw is rectified and smoothed by the coil L1 and the capacitor C1 to generate an output voltage Vout. The output voltage Vout is divided by the resistors R1 and R2 to generate a divided voltage Vdiv (and thus a feedback voltage Vfb). By such output feedback control, in the switching power supply device 1, a desired output voltage Vout is generated from the input voltage Vin with an extremely simple configuration.

<Backflow blocking operation>
FIG. 3 is a timing chart showing the reverse current blocking operation at light load (in discontinuous current mode), and from top to bottom, gate signals G1 and G2, reverse current detection signal S5, coil current IL, and switch voltage Vsw It is depicted.

  During time t21 to t22, the gate signal G1 is at the high level, and the gate signal G2 is at the low level. Thus, the transistor N1 is turned on and the transistor N2 is turned off. Therefore, from time t21 to t22, the switch voltage Vsw rises to almost the input voltage Vin, and the coil current IL increases.

  At time t22, when the gate signal G1 falls to low level and the gate signal G2 rises to high level, the transistor N1 is turned off and the transistor N2 is turned on. Accordingly, the switch voltage Vsw drops to a negative voltage (= GND−IL × RN2, where RN2 is the on-resistance value of the transistor N2), and the coil current IL starts to decrease.

  Here, when the output current Iout flowing to the load is heavy enough, the energy stored in the coil L1 is large, so the coil current IL has a zero value until time t24 when the gate signal G1 is raised to the high level again. Continues to flow toward the load, and the switch voltage Vsw is maintained at a negative voltage. On the other hand, at the time of light load where the output current Iout flowing to the load is small, the energy stored in the coil L1 is small, so at time t23 the coil current IL falls below the zero value and backflow of the coil current IL occurs. The polarity of the voltage Vsw switches from negative to positive. In such a state, since the charge stored in the capacitor C1 is returned to the input side via the coil L1, the efficiency at the time of light load decreases.

  Therefore, switching power supply device 1 detects backflow of coil current IL (reverse polarity of switch voltage Vsw) using backflow detection circuit 18, and transistor N2 in the high level period (time t23 to t24) of backflow detection signal S5. Is configured to force off. With such a configuration, the backflow of the coil current IL can be cut off promptly, so that it is possible to eliminate the efficiency drop at the time of light load.

<On time setting circuit>
Next, the basic design concept of the on-time setting circuit 16 will be described with reference to FIGS. 4 and 5.

  FIG. 4 is a characteristic diagram of the switch output stage 20. As shown in FIG. In the figure, L is the inductance of coil L1, DCR is the equivalent series resistance of coil L1, RonH is the on resistance of transistor N1, RonL is the on resistance of transistor N2, and IL ~ is the average value of coil current IL. It shows.

  FIG. 5 is a schematic view showing the behavior of the coil current IL in the switching cycle Tsw. As shown in the figure, the coil current IL increases from the current value I0 to the current value I1 over the on time Ton (= the time when the transistor N1 is turned on and the transistor N2 is turned off), and then the off time Toff The current value I1 is decreased from the current value I1 to the current value I2 (= time during which the transistor N1 is turned off and the transistor N2 is turned on). The current values I1 and I2 can be respectively expressed by the following equations (1a) and (1b).

  In the steady state, I0 = I2 is established. Substituting this and arranging the equations (1a) and (1b), the following equation (2) is obtained.

  From the above equation (2), in order to make the switching period Tsw (that is, the switching frequency fsw (= 1 / Tsw)) constant, the current proportional to Vin− (RonH−RonL) × IL ̃ It can be seen that the required time for charging the capacitor from 0 V to Vout + (Ron L + DCR) × IL ̃ may be set as the on time Ton.

  Here, Vin−RonH × IL ̃ corresponds to the high level VswH of the switch voltage Vsw (= voltage level at the on time Ton), and −RonL × IL ̃ corresponds to the low level VswL of the switch voltage Vsw (= off time Toff) , And Vout + DCR × IL ̃ corresponds to the average potential of the switch voltage Vsw (hereinafter referred to as “average switch voltage Vsw ̃”).

  Therefore, assuming that Vin-RonH >>-RonL × IL ̃, in order to make the switching period Tsw constant, first, during the off time Toff, the capacitor is switched to the low level VswL of the switch voltage Vsw (= −RonL Then, when the transistor N1 is turned on, charging of the capacitor is started with a current proportional to the high level VswH (= Vin-Ron H x IL) of the switch voltage Vsw, and the capacitor potential is an average switch The on-time setting circuit 16 may be designed to set the required time until the voltage Vsw ~ is reached as the on-time Ton.

  FIG. 6 is a circuit diagram showing a basic configuration of on time setting circuit 16 designed based on the above design concept. The on-time setting circuit 16 of this configuration example includes a first voltage generation unit X, a second voltage generation unit Y, and a comparator Z.

  The first voltage generator X receives the switch voltage Vsw and the inverted output signal S4B, and generates a first voltage VX having a ramp waveform (or a triangular waveform or a slope waveform). The first voltage VX rises from the initial value with a predetermined slope in the on time Ton (= low level period of the inverted output signal S4B), and the initial value in the off time Toff (= high level period of the inverted output signal S4B). Reset to

  The second voltage generator Y receives the switch voltage Vsw and generates a second voltage VY. The second voltage VY corresponds to the reference voltage of the comparator Z.

  The comparator Z includes a first voltage VX input from the first voltage generator X to the inverting input terminal (-), and a second voltage VY input from the second voltage generator Y to the non-inverting input terminal (+), and To generate a reset signal S3. The reset signal S3 goes low when the first voltage VX is higher than the second voltage VY, and conversely goes high when the first voltage VX is lower than the second voltage VY. The falling edge of the reset signal S3 functions as an end trigger of the on time Ton.

  Next, the circuit configuration of the first voltage generation unit X will be described in detail with reference to the same drawing. The first voltage generation unit X includes resistors X1 to X5, a capacitor X6, P-channel MOS [metal-oxide-semiconductor] field effect transistors X7 and X8, N-channel MOS field effect transistors X9 to X12, and an operational amplifier And X13 and a discharge control unit X14.

  The first end of the resistor X1 (resistance value Rf) is connected to the input end of the switch voltage Vsw. The second end of the resistor X1 and the first end of the resistor X3 (resistance value Rhop) are both connected to the output end of the first voltage VX (= the inverting input end (−) of the comparator Z). The second end of the resistor X3 is connected to the first end of the capacitor X6 (capacitance Cf). The second end of the capacitor X6 is connected to the ground end.

  The non-inverting input terminal (+) of the operational amplifier X13 is connected to the output terminal of the first voltage VX. The output end of the operational amplifier X13 is connected to the gate of the transistor X9. The drain of the transistor X9 is connected to the inverting input terminal (-) of the operational amplifier X13 and the first end of the resistor X2 (resistance value Rf). The second end of the resistor X2 is connected to the ground end. The sources of the transistors X7 and X8 are both connected to the power supply terminal. The gates of the transistors X7 and X8 are both connected to the drain of the transistor X8. The drain of the transistor X7 is connected to the output end of the first voltage VX. The drain of the transistor X8 is connected to the drain of the transistor X9.

  The drain of the transistor X10 is connected to the first end of the capacitor X6. The source of the transistor X10 is connected to the ground terminal. The gate of the transistor X10 is connected to the first output terminal of the discharge control unit X14 (= output terminal of the first discharge control signal Sa). The first end of the resistor X4 (resistance value Rd) is connected to the input end of the switch voltage Vsw. The second end of the resistor X4 is connected to the drain of the transistor X11. The source of the transistor X11 and the drain of the transistor X12 are both connected to the first end of the capacitor X6. The source of the transistor X12 is connected to the first end of the resistor X5 (resistance value Rd). The second end of the resistor X5 is connected to the ground end. The gates of the transistors X11 and X12 are both connected to the second output terminal of the discharge control unit X14 (= output terminal of the second discharge control signal Sb). The discharge control unit X14 receives the inverted output signal S4B.

  In the first voltage generation unit X configured as described above, the resistors X1 and X2, the transistors X7 to X9, and the operational amplifier X13 correspond to a charging circuit of the capacitor X6. The first current IX1 (= (Vsw−VX) / Rf) flows through the resistor X1 according to the difference between the switch voltage Vsw and the first voltage VX. The operational amplifier X13 performs gate control of the transistor X9 so that the non-inverted input terminal (+) and the inverted input terminal (-) virtually short-circuit, so the first voltage VX appears at the first end of the resistor X2. Therefore, a second current IX2 (= VX / Rf) flows according to the first voltage VX through the resistor X2. The current mirror composed of the transistors X7 and X8 mirrors the second current IX2 and adds it to the first current IX1 to generate the third current I3 (= Vsw / Rf) according to the switch voltage Vsw.

  During the low level period (= on time Ton) of the inverted output signal S4B, the discharge control unit X14 turns off all the transistors X10 to X12, and the discharge path of the capacitor X6 is cut off. Therefore, since the capacitor X6 is charged by the third current I3, the first voltage VX rises.

  Since the first voltage VX starts to rise from zero when the capacitor X6 is charged, the second current IX2 also starts to increase from zero. Therefore, even if there is a slight start-up delay, the on-time Ton is not significantly affected.

  The resistor X3 generates a correction voltage for correcting the signal delay time generated in the main comparator 13, the gate driver circuit 17, and the like. By providing such a resistor X3, it becomes possible to perform delay time correction corresponding to Cf × Rhop. When the resistance value Rhop of the resistor X3 is changed, the input voltage dependent characteristic (Vin dependent characteristic) of the switching frequency fsw is changed. Therefore, it is desirable that the resistance value Rhop of the resistance X3 be adjusted to an optimal value according to the evaluation result in advance.

  Further, in the first voltage generation unit X configured as described above, the resistors X4 and X5, the transistors X10 to X12, and the discharge control unit X14 correspond to a discharge circuit of the capacitor X6. During the high level period (= off time Toff) of the inverted output signal S4B, the discharge control unit X14 first turns on the transistor X10 and turns off the transistors X11 and X12 for a predetermined minimum off time (for example, 100 ns). As a result, the capacitor X6 is quickly discharged to the GND potential (= 0 V) through the transistor X10.

  Thereafter, the discharge control unit X14 turns off the transistor X10 and turns on the transistors X11 and X12. As a result, the capacitor X6 is further discharged to a negative voltage (= VswL / 2) obtained by dividing the low level VswL of the switch voltage Vsw into 1/2.

  It should be noted that when the transistor N2 is forcibly turned off (at the time of reverse current interruption) in the current discontinuous mode, since both the transistors N1 and N2 are turned off, the switch voltage Vsw rises to almost the output voltage Vout. Therefore, when the transistors X11 and X12 are turned on as described above, the capacitor X6 is charged to 1⁄2 of the output voltage Vout during the off time Toff, so that the on time setting operation thereafter (= first voltage) The comparison operation between VX and the second voltage VY is disturbed. Therefore, in the current discontinuous mode, discharge control by the discharge control unit X14 is performed so as to fix the first voltage VX at the GND potential (= 0 V) during the high level period of the inverted output signal S4B. Specifically, the transistor X10 is turned on and the transistors X11 and X12 are turned off during the high level period of the inverted output signal S4B.

  Next, the circuit configuration of the second voltage generation unit Y will be described in detail with reference to the same drawing. The second voltage generator Y includes resistors Y1 to Y3 and capacitors Y4 and Y5.

  The first end of the resistor Y1 (resistance value: Rf1) is connected to the input end of the switch voltage Vsw. The second end of resistor Y1 is connected to the first end of resistor Y2 (resistance value: Rf1), the first end of resistor Y3 (resistance value: Rf2), and the first end of capacitor Y4 (capacitance value: Cf1) It is done. The second end of the resistor Y2 and the second end of the capacitor Y4 are both connected to the ground end. The second end of the resistor Y3 and the first end of the capacitor Y5 (capacitance value: Cf2) are both connected to the output end of the second voltage VY (= non-inverted input end (+) of the comparator Z). The second end of the capacitor Y5 is connected to the ground end.

  In the second voltage generation unit Y configured as described above, the resistors Y1 and Y2 function as a voltage divider circuit that generates a divided voltage (= Vsw / 2) of the switch voltage Vsw. The resistors Y1 and Y3 and the capacitors Y4 and Y5 function as a second-order RC low pass filter (RC integration circuit) that integrates the divided voltage (= Vsw / 2) of the switch voltage Vsw to generate the second voltage VY. Do. The second voltage generation unit Y of this configuration example generates a second voltage VY (= Vsw ̃ / 2) corresponding to 1⁄2 of the average switch voltage Vsw ̃.

  The order of the RC low pass filter is not limited to the second order, and may be a first order or a third order or more.

  When the second voltage VY is generated without dividing the switch voltage Vsw, the resistor Y2, the resistors X4 and X5, and the transistor X10 become unnecessary. However, since the fluctuation range of the first voltage VX becomes large, when handling the high input voltage Vin, it is necessary to pay attention to the withstand voltage design of the on-time setting circuit 16.

  FIG. 7 is a timing chart showing the basic operation of the on time setting circuit 16, and from the top, the switch voltage Vsw, the first voltage VX, the second voltage VY, the reset signal S3, the inverted output signal S4B, the first discharge control The signal Sa and the second discharge control signal Sb are depicted.

  Times t31 to t33 correspond to the high level period (= off time Toff) of the inverted output signal S4B. During the period, first, the first discharge control signal Sa is set to the high level, and the second discharge control signal Sb is set to the low level, for time t31 to t32. As a result, since the transistor X10 is turned on and the transistors X11 and X12 are turned off, the first voltage VX is quickly discharged to the GND potential (= 0 V).

  Next, at time t32 to t33, the first discharge control signal Sa is set to the low level, and the second discharge control signal Sb is set to the high level. As a result, the transistor X10 is turned off and the transistors X11 and X12 are turned on, so that the first voltage VX further divides the low level VswL of the switch voltage Vsw into 1/2 divided voltage (= VswL / 2). It is discharged.

  On the other hand, time t33 to time t34 correspond to a low level period (= on time Ton) of the inverted output signal S4B. During this period, both the first discharge control signal Sa and the second discharge control signal Sb are at low level. As a result, since the discharge path of the capacitor X6 is cut off, the charging of the capacitor X6 by the third current I3 proceeds, and the first voltage VX rises. Then, at time t34, when the first voltage VX becomes higher than the second voltage VY, the reset signal S3 falls to the low level, and the on time Ton ends. The same operation as described above is repeated after time t34.

  Thus, on-time setting circuit 16 discharges capacitor X6 to an initial value (= VswL / 2) corresponding to low level VswL of switch voltage Vsw during off-time Toff, and thereafter transistor N1 is turned on. At this point, the capacitor X6 starts to be charged by the third current IX3 proportional to the high level VswH of the switch voltage Vsw until the first voltage VX reaches the second voltage VY (= 1/2 of the average switch voltage Vsw). It is designed to set the required time of on as On time Ton.

  With such a configuration, it is possible to suppress the fluctuation of the switching frequency fsw without losing the merits of the non-linear control system. Therefore, it is possible to realize improvement in output voltage accuracy and load regulation characteristics, and facilitation of EMI (electromagnetic interference) countermeasures and noise countermeasures in set design. Also, the switching power supply device 1 can be applied without any problem as a power supply means of applications in which the fluctuation of the input voltage Vin is large and applications in which various output voltages Vout are required.

<Second Voltage Generation Unit (First Modification)>
FIG. 8 is a circuit diagram showing a first modification of the second voltage generator Y. As shown in FIG. The second voltage generation unit Y of this modification is based on the above basic configuration (FIG. 6), and further includes capacitors Y6 and Y7, P-channel MOS field effect transistors Y8 to Y10, and an N-channel MOS electric field. It includes effect transistors Y11 to Y14 and an inverter Y15. Therefore, with regard to circuit elements similar to the above basic configuration, duplicate explanations are omitted by attaching the same reference numerals as in FIG. 6, and in the following, the description will be made with emphasis on the features of the first modification.

  The first end of the capacitor Y6 (capacitance value: Cf1) is connected to the input end of the output voltage Vout. The second end of the capacitor Y6 is connected to the first end of the capacitor Y4.

  The second end of the resistor Y2 and the second end of the capacitor Y4 are not connected to the ground terminal, but are connected to the drain of the transistor Y13. The source of the transistor Y13 is connected to the ground terminal. The gate of the transistor Y13 is connected to the input end of the enable signal EN. Thus, the transistor Y13 is inserted between the resistor Y2 and the capacitor Y4 and the ground terminal.

  The source of the transistor Y8 is connected to the first end of the capacitor Y4. The drain of the transistor Y8 is connected to the second end of the capacitor Y4. The gate of the transistor Y8 is connected to the input end of the enable signal EN.

  The source of the transistor Y9 is connected to the first end of the capacitor Y6. The drain of the transistor Y9 is connected to the second end of the capacitor Y6. The gate of the transistor Y9 is connected to the input end of the enable signal EN.

  The second end of the resistor Y3 is connected not to the output end of the second voltage VY but to the drain of the transistor Y14. The source of the transistor Y14 is connected to the output end of the second voltage VY. The gate of the transistor Y14 is connected to the input end of the enable signal EN. Thus, the transistor Y14 is inserted between the second end of the resistor Y3 and the output end of the second voltage VY.

  The first end of the capacitor Y7 (capacitance value: Cf2) is connected to the drain of the transistor Y10. The second end of the capacitor Y7 is connected to the first end of the capacitor Y5.

  The source of the transistor Y10 is connected to the input end of the output voltage Vout. The drain of the transistor Y10 is connected to the first end of the capacitor Y7. The gate of the transistor Y10 is connected to the output end of the inverter Y15.

  The drain of the transistor Y11 is connected to the first end of the capacitor Y5. The source of the transistor Y11 is connected to the second end of the capacitor Y5. The gate of the transistor Y11 is connected to the output end of the inverter Y15. The input end of the inverter Y15 is connected to the input end of the enable signal EN.

  The drain of the transistor Y12 is connected to the first end of the capacitor Y7. The source of the transistor Y12 is connected to the second end of the capacitor Y7. The gate of the transistor Y12 is connected to the output end of the inverter Y15.

  The enable signal EN becomes low level when switching is stopped (= when reverse current of coil current IL is detected and both transistors N1 and N2 are turned off), and when switching is restarted (= transistor N1 is turned on in next cycle) ) Is a logic signal that goes high. As the enable signal EN, for example, it is possible to divert the reverse current detection signal S5 described above.

  When the enable signal EN is at low level, the transistors Y13 and Y14 are turned off, and the current path through the resistors Y1 and Y2 and the current path through the resistor Y3 are both cut off. That is, the transistors Y13 and Y14 function as a current path breaker that shuts off the current path from the input end of the switch voltage Vsw to the ground end when switching is stopped. With such a configuration, it is possible to realize power saving when switching is stopped.

  However, while the above current path is shut off, the second voltage VY drops to the GND potential (= 0 V). Therefore, at the time of resumption of switching, it is necessary to quickly raise the second voltage VY to the original voltage value (= Vsw ̃ / 2). However, in the integration process of the switch voltage Vsw by the RC low-pass filter, since the recovery of the second voltage VY takes a long time, the on-time setting operation is disturbed.

  On the other hand, the average switch voltage Vsw ̃ in the steady state substantially matches the output voltage Vout. In view of this fact, the second voltage generation unit Y of this modification divides the output voltage Vout by capacitance at the time of resumption of switching, whereby the second voltage VY has a predetermined initial value VY0 (= Vout / 2 ≒ Vsw ̃ / 2). ) Has a pull-up part that pulls up instantaneously.

  More specifically, in the second voltage generation unit Y of this modification, capacitors Y6 and Y7 are connected in series to capacitors Y4 and Y5 forming an RC low-pass filter. That is, between the input end of the output voltage Vout and the ground end, there are formed a first capacitive voltage dividing circuit consisting of capacitors Y4 and Y6 and a second capacitive voltage dividing circuit consisting of capacitors Y5 and Y7. Two capacitive voltage divider circuits function as pull-up units.

  When the enable signal EN rises from low level to high level and the transistor Y13 is turned on, a capacitive divided voltage (= Vout / 2) appears at the connection node between the capacitor Y4 and the capacitor Y6. Similarly, when the enable signal EN rises from the low level to the high level and the transistor Y10 is turned on, a capacitive divided voltage (= Vout / 2) appears at the connection node between the capacitor Y5 and the capacitor Y7.

  With such a configuration, the second voltage VY can be instantaneously raised to a predetermined initial value VY0 (= Vout / 2) without waiting for the integration process of the switch voltage Vsw by the RC low pass filter at the time of resumption of switching. Is possible. After the restart of the switching, the second voltage VY settles to the original voltage value (= the integral value Vsw ̃ / 2 obtained by the RC low pass filter) in accordance with the time constant of the RC low pass filter.

  Note that while the enable signal EN is at high level, the connection node between the resistors Y1 and Y2 is biased to Vout / 2 by the first capacitance voltage divider circuit, and the output terminal of the second voltage VY is the second capacitance. The bias circuit is biased to Vout / 2. Therefore, since the second voltage VY can easily follow the output fluctuation, it is possible to stabilize the behavior of the second voltage VY.

  Further, transistors Y8 and Y9, and transistors Y11 and Y12 are connected in parallel to capacitors Y4 to Y7, respectively. The transistors Y8 and Y9 and the transistors Y11 and Y12 are all turned on when the enable signal EN is at high level, and are turned off when the enable signal EN is at low level.

  Therefore, when the enable signal EN is raised to a high level at the time of resumption of switching, both ends of each of the capacitors Y4 to Y7 are shorted, and the charge stored in each is discharged. With such a configuration, the pull-up operation of the second voltage VY can be correctly performed each time switching is restarted.

<Second Voltage Generation Unit (Second Modified Example)>
FIG. 9 is a circuit diagram showing a second modification of the second voltage generator Y. As shown in FIG. The second voltage generation unit Y of this modification is based on the first modification (FIG. 8), and further includes a resistor Y18, capacitors Y16 and Y17, and an N-channel type as additional elements of the pull-up portion. And a MOS field effect transistor Y19. Therefore, the circuit elements similar to those of the first modification described above are given the same reference numerals as in FIG. 8 to omit duplicate descriptions, and in the following, the description will be made with emphasis on the features of the second modification. .

  A first end of the capacitor Y16 (capacitance value: Ch1) is connected to a first end of the capacitor Y7. The second end of the capacitor Y16 and the first end of the resistor Y18 (resistance value: Rh2) are both connected to the output end of the second voltage VY. The second end of the resistor Y18 is connected to the first end of the capacitor Y17 (capacitance value: Ch2). The second end of the capacitor Y17 is connected to the ground end.

  The drain of the transistor Y19 is connected to the first end of the resistor Y18. The source of the transistor Y19 is connected to the second end of the resistor Y18. The gate of the transistor Y19 is connected to the input end of the enable signal EN.

  In addition, since the pull-up unit of the second voltage generation unit Y is configured only by the passive device and the switch, a bias current is unnecessary, and it is possible to easily realize zero standby current. Also, in principle, there is no delay at startup.

  Next, the on-time modulation operation using the additional elements (capacitors Y16 and Y17, resistor Y18, and transistor Y19) described above will be described. When the capacitor Y17 is ignored, the addition of the capacitor Y16 makes the initial value VY1 of the second voltage VY at the time of resumption of switching the voltage value represented by the following equation (3). That is, the larger the capacitance value Ch1 of the capacitor Y16, the higher the initial value VY1 of the second voltage VY.

  On the other hand, when the capacitor Y16 is neglected, the initial value VY2 of the second voltage VY at the time of resumption of switching becomes a voltage value represented by the following equation (4) by adding the capacitor Y17. That is, the larger the capacitance value Ch2 of the capacitor Y17, the lower the initial value VY2 of the second voltage VY.

  However, the above equation (4) is satisfied when the capacitor Y17 is completely discharged at the time of switching restart, that is, the low level period of the enable signal EN (= off period of the transistor Y19) is the capacitor Y17. This is a case where it is longer than the time constant τ (= Ch2 × Rh2) of the RC circuit composed of the resistor Y18.

  As the low level period of the enable signal EN is shorter than the time constant τ, the charge of the capacitor Y17 remains undischarged more, so the effect of reducing the initial value of the second voltage VY decreases. That is, the reduction effect of the initial value by the capacitor Y17 becomes larger as the load is lighter (= the low level period of the enable signal EN is longer) and smaller as the load is heavier (= the low level period of the enable signal EN is shorter).

  The operations of the capacitors Y16 and Y17 described above are combined as follows.

  First, in the load region immediately before switching from the discontinuous current mode to the continuous current mode, the low level period of the enable signal EN is sufficiently shorter than the time constant τ described above, and the charge stored in the capacitor Y17 is hardly discharged. Become. Therefore, since the capacitor Y17 can be ignored, the second voltage VY is pulled up to the initial value VY1 represented by the equation (3) described earlier when switching is restarted.

  On the other hand, in the current discontinuous mode, when the load is sufficiently lightened and the capacitor Y17 is completely discharged during the low level period of the enable signal EN, the initial value VY3 of the second voltage VY at the resumption of switching is The voltage value is expressed by the following equation (5). This state corresponds to a state where capacitance division of the output voltage Vout is performed using all four capacitors (Y5, Y7, Y16, Y17).

  However, the above equation (5) is satisfied when the capacitor Y17 is completely discharged at the time of switching resumption, and the heavier the load (= the shorter the low level period of the enable signal EN becomes), the 2 The initial value of voltage VY approaches VY1 from VY3.

  The second voltage VY gradually settles from the initial value toward the original voltage value (= Vsw− / 2) after the restart of switching. However, after the resumption of switching, the first voltage VX crosses the second voltage VY before the voltage VY settles to the original voltage value. Therefore, the ON time Ton becomes longer as the initial value of the second voltage VY becomes higher, and conversely, the ON time Ton becomes shorter as the initial value of the second voltage VY becomes lower.

  Further, as understood from the above equation (5), VY3> VY0 is obtained if Ch1> Ch2, and VY3 <VY0 is obtained if Ch1 <Ch2. Therefore, desired on-time characteristics can be obtained by appropriately setting the capacitance values Ch1 and Ch2.

  FIG. 10 is a timing chart showing the pull-up operation of the second voltage VY, and the behavior of the enable signal EN and the second voltage VY is depicted sequentially from the top. At time t41, when the enable signal EN is raised to the high level, the second voltage VY is instantaneously pulled up to the initial value according to the load by the aforementioned pull-up operation.

  For example, as indicated by the solid line of the second voltage VY, the initial value VY1 of the second voltage VY is higher than the original voltage value (= Vsw ̃ / 2) in the load region immediately before switching from the discontinuous current mode to the continuous current mode. It is good to design a pull-up part so that it becomes high. With such a design, the backflow of the coil current IL is detected, and once transitioning to the current discontinuous mode, the on time Ton of the transistor N1 is intentionally extended. Therefore, since the peak value of the coil current IL is increased and the output current Iout supplied to the load is increased, the same output current Iout operates in the current discontinuous mode during the time constant in which the influence remains. Hysteresis at the time of transition from the current continuous mode to the current discontinuous mode is secured.

  Also, as indicated by the small broken line, large broken line, alternate long and short dash line, or two-dotted line of the second voltage VY, the pull-up portion is designed so that the initial value of the second voltage VY becomes lower as the load becomes lighter. You should keep it. By performing such a design, in the current discontinuous mode, the on-time Ton is shortened as the load is lighter, so that it is possible to reduce the output ripple at light load.

<Second Voltage Generation Unit (Third Modification)>
FIG. 11 is a circuit diagram showing a third modification of the second voltage generator Y. As shown in FIG. The second voltage generation unit Y of this modification is based on the second modification (FIG. 9) and further includes a capacitor Y20, a P-channel MOS field effect transistor Y21, and an N-channel MOS field effect transistor. And Y22. Therefore, the circuit elements similar to those of the second modification described above will be given the same reference numerals as in FIG. 9 to omit redundant descriptions, and in the following, the main features of the third modification will be mainly described. .

  The source of the transistor Y21 is connected to the output end of the second voltage VY. The drain of the transistor Y21 is connected to the first end of the capacitor Y20 (capacitance value Ch3) and the drain of the transistor Y22. The second end of the capacitor Y20 and the source of the transistor Y22 are both connected to the ground terminal. The gates of the transistors Y21 and Y22 are both connected to the input end of the operation mode determination signal SKIP.

  Operation mode determination signal SKIP is at a high level when backflow of coil current IL is detected and both transistors N1 and N2 are turned off (ie, in discontinuous current mode), and backflow of coil current IL is detected. When the transistor N1 is turned on (ie, in the current continuous mode) before turning on.

  The capacitor Y20 and the transistors Y21 and Y22 connected in this manner function as a pull-down unit that transiently lowers the second voltage VY when switched from the discontinuous current mode to the continuous current mode. The dynamic hysteresis application operation at the time of operation mode switching by the pull-down unit will be described in detail below.

  FIG. 12 is a timing chart showing the pull-down operation of the second voltage VY, and from the top, the coil current IL, the switch voltage Vsw, the enable signal EN, the operation mode determination signal SKIP, and the first voltage VX (broken line) and The second voltage VY (solid line) is depicted.

  Before time t109, it is a current discontinuous mode in which the coil current IL falls below the zero value during the off time Toff. When the switching is stopped, the second voltage generation unit Y is in the power saving state, and the second voltage VY is reduced to 0V. On the other hand, at the time of resumption of switching, the second voltage VY is instantaneously raised to an initial value higher than the original voltage value (= Vsw− / 2) (see time t101, time t104, or time t107). These operations are as described above.

  In the current discontinuous mode, the operation mode determination signal SKIP is maintained at high level. At this time, the transistor Y21 is turned off and the transistor Y22 is turned on. Therefore, since both ends of the capacitor Y20 are short-circuited, the pull-down portion does not affect the generation operation of the second voltage VY.

  On the other hand, at time t109, as transistor N1 is turned on before backflow of coil current IL is detected (= before enable signal EN falls to low level), operation mode determination signal SKIP rises to low level. It's down. At this time, the transistor Y21 is turned off and the transistor Y22 is turned on. Accordingly, since the capacitor Y20 is inserted between the output end of the second voltage VY and the ground end, the second voltage VY is transiently lowered.

  When the pull-down portion is not introduced, as indicated by the thin broken line in the figure, the second voltage VY gradually returns to the original voltage value Vsw ̃ / 2 according to the time constant τ of the RC low pass filter. To go. Therefore, even after the transition from the current discontinuous mode to the current continuous mode, the on-time Ton continues to be extended for a while, so the state in which the current discontinuous mode can be easily returned is continued.

  On the other hand, when the pull-down portion is introduced, once shifting to the current continuous mode, the second voltage VY is lowered and the on time Ton is shortened. As a result, the peak-to-peak value of the coil current IL is reduced, and the bottom value of the coil current IL is less likely to fall below the zero value, so the current continuous mode is maintained until the output current Iout is sufficiently reduced.

  In FIG. 11 and FIG. 12, based on the second modification (FIG. 9), the configuration in which the pull-down portion is introduced is described as an example, but the introduction target of the pull-down portion is limited to this. It is also possible to introduce a pull-down unit based on the above basic configuration (FIG. 6) and the first modification (FIG. 8).

<Correlation between on-time and output current>
FIG. 13 is a correlation diagram of the on time Ton and the output current Iout. In the current discontinuous mode (denoted as DCM [discontinuous current mode]) in which the output current Iout is smaller than the threshold current Ith, the smaller the output current Iout, the shorter the on-time Ton. Such an on-time modulation operation can prevent an increase in output ripple.

  On the other hand, in the current continuous mode (described as CCM [continuous current mode]) in which the output current Iout is larger than the threshold current Ith, the switching frequency fsw is affected by the on resistances of the transistors N1 and N2 and the equivalent series resistance of the coil L1. So that the on-time Ton is adjusted according to the output current Iout. As described above, in the adjustment operation of the on time Ton, the capacitor is set to the low level VswL (= −RonL × IL ̃) of the switch voltage Vsw during the off time Toff, and then the transistor N1 is turned on. At this point, the capacitor starts to be charged with a current proportional to the high level VswH (= Vin-Ron H x IL ~) of the switch voltage Vsw, and the required time for the capacitor potential to reach the average switch voltage Vsw ~ is set as the on time Ton It is realized by doing.

  Also, in the load region where switching between the current discontinuous mode and the current continuous mode occurs, hysteresis is given to the on time Ton. With such a configuration, the current continuous mode and the current discontinuous mode are not repeated irregularly at the transition from light load to heavy load (or at the transition from heavy load to light load). It is possible to prevent an increase in the ripple component of the output voltage Vout due to irregular mode transition.

<Simulation result>
FIG. 14 is a timing chart showing an example of transition of the output behavior according to the load increase and decrease, and from the top, the reset signal S3, the output voltage Vout, the switch voltage Vsw, the second voltage VY, the gate signal G1, the operation mode determination signal SKIP and output current Iout are depicted.

  As indicated by the regions P1 and P2, when the switching frequency fsw is lowered at light load, the second voltage VY is lowered and the on time Ton is shortened. This can prevent an increase in output ripple at light load.

  Further, as indicated by the regions P3 and P4, the second voltage VY is transiently lowered at the transition from the current discontinuous mode to the current continuous mode. On the other hand, as indicated by region P5, at the time of transition from the current continuous mode to the current discontinuous mode, the second voltage VY is pulled up to a voltage value higher than the integral value (= Vsw ̃ / 2) obtained by the RC low pass filter. Be As a result, hysteresis is given to the on-time Ton, which makes it possible to stabilize the transition between the two modes.

<Application to TV>
FIG. 15 is a block diagram showing a configuration example of a television equipped with the above switching power supply device. 16A to 16C are a front view, a side view, and a rear view of a television equipped with the above-described switching power supply device, respectively. The television A according to this configuration example includes a tuner unit A1, a decoder unit A2, a display unit A3, a speaker unit A4, an operation unit A5, an interface unit A6, a control unit A7, and a power supply unit A8. Have.

  The tuner unit A1 selects a broadcast signal of a desired channel from the reception signal received by the antenna A0 externally connected to the television A.

  The decoder unit A2 generates a video signal and an audio signal from the broadcast signal selected by the tuner A1. The decoder unit A2 also has a function of generating a video signal and an audio signal based on the external input signal from the interface unit A6.

  The display unit A3 outputs the video signal generated by the decoder unit A2 as a video.

  The speaker unit A4 outputs the sound signal generated by the decoder unit A2 as sound.

  The operation unit A5 is one of human interfaces for receiving user operations. As the operation unit A5, a button, a switch, a remote controller or the like can be used.

  The interface unit A6 is a front end that receives an external input signal from an external device (such as an optical disk player or a hard disk drive).

  Control part A7 controls operation of each above-mentioned each part A1-A6 in a centralized manner. As the control unit A7, a CPU (central processing unit) or the like can be used.

  The power supply unit A8 supplies power to the units A1 to A7. The switching power supply 1 described above can be suitably used as the power supply unit A8.

<Other Modifications>
In the above embodiment, the configuration in which the present invention is applied to the step-down switching power supply device is described as an example, but the application target of the present invention is not limited to this. For example, the switching power supply device The output stage of may be a boost type, a buck-boost type, or a reverse type.

  Further, in the above embodiment, the switching power supply device (on-time setting circuit) of the on-time fixed method has been described as an example, but the application target of the present invention is not limited thereto. It is possible to apply to the off-time fixed switching power supply (off-time setting circuit) by changing the RC network based on the technical idea of the invention.

  Thus, the configuration of the present invention can be modified in various ways without departing from the spirit of the invention in addition to the embodiment described above. That is, the above embodiments should be considered in all respects as illustrative and not restrictive, and the technical scope of the present invention is not the description of the above embodiments but the claims. It is to be understood that all changes which come within the meaning and range of equivalency of the claims are to be included.

  The switching power supply according to the present invention includes a power supply (for example, SOC [system-on-chip]) mounted on various electronic devices such as a liquid crystal display, a plasma display, a BD recorder / player, a set top box, and a personal computer. It can be used as a power supply for peripheral devices or peripheral devices.

1 Switching power supply device 10 Semiconductor device (power control IC)
11 ripple injection circuit 12 reference voltage generation circuit 13 main comparator 14 one shot pulse generation circuit 15 RS flip flop 16 on time setting circuit 17 gate driver circuit 18 reverse current detection circuit 20 switch output stage N1 N channel type MOS field effect transistor (output transistor )
N2 N-channel MOS field effect transistor (synchronous rectification transistor)
L1 coil R1, R2 resistance C1 capacitor T1 to T8 external terminal X first voltage generator X1 to X5 resistance X6 capacitor X7, X8 P channel type MOS field effect transistor X9 to X12 N channel type MOS field effect transistor X13 operational amplifier X14 discharge control Part Y Second voltage generation part Y1 to Y3, Y18 Resistance Y4 to Y7, Y16, Y17, Y20 Capacitor Y8 to Y10, Y21 P-channel type MOS field effect transistor Y11 to Y14, Y19, Y22 N-channel type MOS field effect transistor Y15 Inverter Z Comparator A Television A0 Antenna A1 Tuner A2 Decoder A3 Display A4 Speaker A5 Operation A6 Interface A7 Controller A8 Power A

Claims (5)

A method of setting an on-time in a fixed on-time switching type switching power supply in which an output voltage is generated from an input voltage by turning on / off an output transistor and a synchronous rectification transistor to drive a coil.
The current discontinuous mode is performed by comparing the first voltage of the ramp waveform rising over the on time with the second voltage which is lowered as the load is lighter in the current discontinuous mode and terminating the on time. Then, the lighter the load, the shorter the on-time ,
The switch voltage appearing at the connection node between the output transistor and the synchronous rectification transistor or its divided voltage is integrated to generate the second voltage, and a current path from the input end of the switch voltage to the ground end is used when switching is stopped. An on-time setting method comprising interrupting the switching voltage and dividing the output voltage by capacitance at the time of resumption of switching, thereby instantaneously raising the second voltage to a predetermined initial value . The on-time setting method according to claim 1 , wherein the initial value is lower as the load is lighter. 3. The on-time according to claim 2 , wherein the initial value is higher in the load region immediately before switching from the current discontinuous mode to the current continuous mode than the integrated value of the switch voltage or its divided voltage. Setting method. The on-time setting method according to any one of claims 1 to 3 , wherein the second voltage is transiently lowered when switching from the current discontinuous mode to the current continuous mode. A method of setting an on-time in a fixed on-time switching type switching power supply in which an output voltage is generated from an input voltage by turning on / off an output transistor and a synchronous rectification transistor to drive a coil.
The current discontinuous mode is performed by comparing the first voltage of the ramp waveform rising over the on time with the second voltage which is lowered as the load is lighter in the current discontinuous mode and terminating the on time. Then, the lighter the load, the shorter the on-time,
Features and to Luo emission time setting method to lower the second voltage transitionally at the time of switching to continuous current mode from the current discontinuous mode.