JP6046999B2 - Switching power supply - Google Patents

Description

  The present invention relates to a non-linear control type switching power supply apparatus.

  Patent Document 1 discloses a non-linear control type switching power supply device that generates an output voltage from an input voltage by performing on / off control of a switch element in accordance with an output signal of a main comparator that compares a feedback voltage with a reference voltage. It is disclosed.

  Patent Document 2 discloses a DC / DC converter that clamps an output signal of an error amplifier.

JP 2012-10579 A JP 2011-109806 A

  By the way, some non-linear control type switching power supply devices use an error amplifier to generate an error voltage corresponding to a difference between a feedback voltage and a reference voltage, and input the error voltage to a main comparator instead of the reference voltage. By adopting such a configuration, output feedback control can be performed so that the feedback voltage matches the reference voltage, so that the output characteristics (line regulation characteristics, load regulation characteristics, etc.) of the switching power supply device are improved. Is possible.

  However, in the above-described conventional configuration, the error amplifier reduces the error voltage as long as the feedback voltage exceeds the reference voltage in an ultra-light load state (a state close to no load) in which the output current to the load is approximately 0 A. Therefore, the error voltage decreases to 0 V (or in the vicinity thereof).

  If a sudden load change (a sudden increase in output current) occurs from the above ultra-light load state, the output voltage drops rapidly and the feedback voltage falls below the reference voltage, so the error amplifier switches from reducing the error voltage to increasing it. . However, the response capacity of the error amplifier is limited, and it takes a certain amount of time for the error voltage to return to the original voltage value (the voltage value after the transient response has elapsed). There was a problem that it would end up.

  Note that Patent Document 1 discloses an error amplifier (offset adjustment unit) that performs offset adjustment of a reference voltage according to a difference between a feedback voltage and a target voltage, but its output signal is used only as an offset adjustment signal. It is not input to the main comparator in place of the reference voltage. In this respect, the switching power supply device of Patent Document 1 is different from the above-described conventional configuration and the switching power supply device according to the present invention.

  In addition, the DC / DC converter of Patent Document 2 originally uses the linear control method (current mode PWM [pulse width modulation] control method) instead of the non-linear control method. It is also different from the switching power supply device.

  In view of the above-described problems found by the inventors of the present application, an object of the present invention is to provide a switching power supply device that can suppress output fluctuations at the time of sudden load change.

  In order to achieve the above object, a switching power supply according to the present invention compares an error amplifier that generates an error voltage according to a difference between a feedback voltage and a first reference voltage, and the feedback voltage and the error voltage. A main comparator that generates a comparison signal, an on-time setting unit that generates an on-time setting signal having a fixed pulse width according to the comparison signal, and on / off control of the switch element according to the on-time setting signal A driver that generates an output voltage from the input voltage, an error voltage monitoring unit that generates a lower limit detection signal by comparing the error voltage and the second reference voltage, and a first voltage and a first voltage according to the lower limit detection signal. A first selector that selectively outputs one of two voltages as the first reference voltage; and one of a third voltage and a fourth voltage that is selected as the second reference voltage according to the lower limit detection signal. Is a second selector for selectively outputting, a structure having a (first configuration) Te.

  In the switching power supply device having the first configuration, the second voltage is higher than the first voltage, the third voltage is lower than the first voltage, and the fourth voltage is higher than the third voltage. Also, a lower configuration (second configuration) is preferable.

  In the switching power supply device having the second configuration, the first selector raises the first reference voltage from the first voltage to the second voltage when the error voltage falls below the fourth voltage. On the other hand, when the error voltage exceeds the third voltage, the first voltage and the second voltage are reduced according to the lower limit detection signal so as to lower the first reference voltage from the second voltage to the first voltage. The second selector raises the second reference voltage from the fourth voltage to the third voltage when the error voltage falls below the fourth voltage, while the error voltage A configuration for performing selective output of the third voltage and the fourth voltage according to the lower limit detection signal so as to lower the second reference voltage from the third voltage to the fourth voltage when the voltage exceeds a third voltage. ( Better to 3 configuration).

  In the switching power supply device having the third configuration, the error amplifier may have a configuration (fourth configuration) in which the drive current is switched according to the lower limit detection signal.

  Further, in the switching power supply device having any one of the first to fourth configurations, the on-time setting unit includes a capacitor that generates a sawtooth voltage by charging and discharging, and a charging current of the capacitor according to the input voltage. A voltage / current conversion unit for generating a voltage, a charge / discharge switch for switching charge / discharge of the capacitor, a voltage / voltage conversion unit for generating a threshold voltage according to the output voltage, and comparing the sawtooth voltage with the threshold voltage And an RS flip-flop that sets / resets the ON time setting signal according to the comparison signal and the reset signal (fifth configuration). .

  In the switching power supply device having the fifth configuration, the on-time setting unit may include a configuration (sixth configuration) including an offset unit that offsets the threshold voltage.

  In the switching power supply device having the sixth configuration, the offset unit may be configured to variably control the offset amount of the threshold voltage according to the input voltage (seventh configuration).

  Further, in the switching power supply device having the seventh configuration, the voltage / current conversion unit generates an offset adjustment current of a system different from the charging current of the capacitor according to the input voltage, and the offset unit includes: A configuration (eighth configuration) in which the offset amount of the threshold voltage is variably controlled according to the offset adjustment current may be employed.

  In addition, the switching power supply device having any one of the first to eighth configurations further includes a backflow detection unit that detects a backflow current to the switch element and generates a backflow detection signal. The switch element may be forcibly turned off in accordance with the detection signal (ninth configuration).

  Further, the switching power supply device having any one of the first to ninth configurations may have a configuration (tenth configuration) further including a feedback voltage generation unit that divides the output voltage to generate the feedback voltage.

  Further, the switching power supply device having any one of the first to tenth configurations preferably has a configuration (eleventh configuration) further including a ripple injection unit for injecting a ripple component into the feedback voltage.

  Moreover, the electronic apparatus according to the present invention has a switching power supply device (a twelfth configuration) having any one of the first to eleventh configurations.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the switching power supply device which can suppress the output fluctuation | variation at the time of load sudden change.

The block diagram which shows 1st Embodiment of a switching power supply device Timing chart showing an example of switching operation under heavy load Timing chart showing an example of switching operation at light load Timing chart showing an example of switching operation at ultra-light load Timing chart showing an example of transient response during sudden load change The block diagram which shows 2nd Embodiment of a switching power supply device Timing chart showing an example of output behavior in the second embodiment The block diagram which shows 3rd Embodiment of a switching power supply device Timing chart showing an example of output behavior in the third embodiment The block diagram which shows the 1st structural example of the ON time setting part 15 Timing chart showing an example of on-time setting operation Timing chart showing occurrence of deviation of on-time Ton The block diagram which shows the 2nd structural example of the ON time setting part 15 Timing chart showing elimination of deviation of on-time Ton The circuit diagram which shows the detailed structure of the ON time setting part 15 External view of personal computer External view of digital multifunction device External view of mobile terminal (smartphone)

<Switching power supply device (first embodiment)>
FIG. 1 is a block diagram showing a first embodiment of a switching power supply device. The switching power supply device A of the first embodiment is a step-down DC / DC converter that generates an output voltage OUT from an input voltage IN by a non-linear control method (here, a bottom detection on-time fixed method). The switching power supply device A includes the semiconductor device 1 and various discrete components (inductors L1, capacitors C1 and C2, and resistors R1 and R2) that are externally attached to the semiconductor device 1.

  The semiconductor device 1 has external terminals T1 to T5 as means for establishing an electrical connection with the outside. Outside the semiconductor device 1, the external terminal (power supply terminal) T1 is connected to the application terminal of the input voltage IN. The external terminal (switch terminal) T2 is connected to the first end of the inductor L1. A rectangular wave switch voltage SW appears at the external terminal T2 in accordance with the on / off state of the transistors 11 and 12. The second end of the inductor L1, the first end of the capacitor C1, and the first end of the resistor R1 are all connected to the application terminal of the output voltage OUT. The second end of the capacitor C1 is connected to the ground end. The second end of the resistor R1 and the first end of the resistor R2 are both connected to the external terminal (feedback terminal) T4 of the semiconductor device 1. A second end of the resistor R2 is connected to the ground end. The resistors R1 and R2 function as a feedback voltage generation unit that outputs a feedback voltage FB obtained by dividing the output voltage OUT from each other connection node. The external terminal (ground terminal) T3 of the semiconductor device 1 is connected to the ground terminal. The external terminal (error amplifier terminal) T5 of the semiconductor device 1 is connected to the ground terminal via the capacitor C2. The capacitor C2 can also be built in the semiconductor device 1. In that case, the external terminal T5 becomes unnecessary.

  The semiconductor device 1 includes N-channel MOS field effect transistors 11 and 12, an error amplifier 13, a main comparator 14, an on-time setting unit 15, a backflow detection unit 16, a driver 17, a ripple injection unit 18, This is a monolithic semiconductor integrated circuit device (so-called switching power supply IC) in which an error voltage monitoring unit 19 and selectors 20 and 21 are integrated.

  The transistor 11 is a switch element (output transistor) that is connected between the external terminal T1 and the external terminal T2 and is on / off controlled according to the gate signal G1 input from the driver 17. Specifically speaking, the drain of the transistor 11 is connected to the external terminal T1. The source of the transistor 11 is connected to the external terminal T2. The gate of the transistor 11 is connected to the application terminal of the gate signal G1.

  The transistor 12 is a switching element (synchronous rectification transistor) connected between the external terminal T2 and the external terminal T3 and controlled to be turned on / off according to the gate signal G2 input from the driver 17. Specifically speaking, the drain of the transistor 12 is connected to the external terminal T2. The source of the transistor 12 is connected to the external terminal T3. The gate of the transistor 12 is connected to the application terminal for the gate signal G2. As the rectifying element, a diode may be used instead of the transistor 12.

  The error amplifier 13 generates an error voltage ERR corresponding to the difference between the ripple injected feedback voltage FB applied to the inverting input terminal (−) and the reference voltage REF1 applied to the non-inverting input terminal (+). . When the feedback voltage FB is lower than the reference voltage REF1, since the error amplifier 13 flows current toward the capacitor C2, the error voltage ERR increases. On the other hand, when the feedback voltage FB is higher than the reference voltage REF1, since the error amplifier 13 draws a current from the capacitor C2, the error voltage ERR decreases.

  The main comparator 14 compares the ripple injected feedback voltage FB (divided voltage of the output voltage OUT) applied to the inverting input terminal (−) and the error voltage ERR applied to the non-inverting input terminal (+). Thus, the comparison signal S1 is generated. When the feedback voltage FB is higher than the error voltage ERR, the comparison signal S1 is at a low level, and when the feedback voltage FB is lower than the error voltage ERR, the comparison signal S1 is at a high level.

  The on-time setting unit 15 generates an on-time setting signal S2 having a fixed pulse width according to the comparison signal S1. The on-time setting signal S2 rises to a high level when the comparison signal S1 rises to a high level, and then falls to a low level when the on-time Ton elapses. The configuration and operation of the on-time setting unit 15 will be described in detail later.

  The backflow detection unit 16 compares the switch voltage SW and the ground voltage GND while the transistor 12 is on, thereby detecting a backflow current to the transistor 12 and generating a backflow detection signal S3. The backflow detection signal S3 is at a low level when the switch voltage SW is lower than the ground voltage GND, and is at a high level when the switch voltage SW is higher than the ground voltage GND. That is, the backflow detection signal S3 becomes low level when the inductor current IL flows from the ground end to the inductor L1 via the transistor 12, and when the inductor current IL flows back from the inductor L1 to the ground end via the transistor 12. High level.

  The driver 17 generates the gate signals G1 and G2 in response to the on-time setting signal S2, and performs complementary (exclusive) on / off control of the transistors 11 and 12, thereby changing the output voltage OUT from the input voltage IN. Generate. Note that the term “complementary (exclusive)” used in this specification refers to the transistors 11 and 12 from the viewpoint of preventing through current, in addition to the case where the on / off states of the transistors 11 and 12 are completely reversed. This includes a case where a predetermined delay is given to the 12 on / off transition timings (when a simultaneous off period is provided). The driver 17 also has a function (switching stop function) that forcibly turns off the transistor 12 when the backflow detection signal S3 becomes a high level (when a backflow current to the transistor 12 is detected). By providing such a function, it becomes possible to cut off the backflow current to the transistor 12 and improve the efficiency at light load.

  The ripple injection unit 18 injects a ripple component generated using the gate signal G1 and the switch voltage SW into the feedback voltage FB input from the external terminal T4. If such a ripple injection technique is introduced, stable switching control can be performed even if the ripple component of the output voltage OUT (and thus the feedback voltage FB) is not so large. Therefore, as the capacitor C1, ESR [equivalent series It is possible to use an element (such as a multilayer ceramic capacitor) having a low resistance].

  The error voltage monitoring unit 19 is a comparator that compares the error voltage ERR applied to the inverting input terminal (−) with the reference voltage REF2 applied to the non-inverting input terminal (+) to generate the lower limit detection signal DET. is there. When the error voltage ERR is higher than the reference voltage REF2, the lower limit detection signal SDET is at a low level, and when the error voltage ERR is lower than the reference voltage REF2, the lower limit detection signal DET is at a high level.

  The selector 20 selectively outputs one of the first voltage REFa and the second voltage REFb as the reference voltage REF1 according to the lower limit detection signal DET. More specifically, the selector 20 selectively outputs the first voltage REFa as the reference voltage REF1 when the lower limit detection signal DET is at a low level, and the second voltage REFb when the lower limit detection signal DET is at a high level. Is selectively output as a reference voltage REF1. Note that the first voltage REFa corresponds to a target value of the feedback voltage FB at the normal time. The second voltage REFb corresponds to a nominal target value of the feedback voltage FB when the error voltage ERR is forcibly increased, and is set to a voltage value higher than the first voltage REFa (for example, REFb = REFa × 1.05). Yes.

  The selector 21 selectively outputs one of the third voltage REFc and the fourth voltage REFd as the reference voltage REF2 according to the lower limit detection signal DET. More specifically, the selector 21 selectively outputs the fourth voltage REFd as the reference voltage REF2 when the lower limit detection signal DET is at a low level, and the third voltage REFc when the lower limit detection signal DET is at a high level. Is selectively output as the reference voltage REF2. Note that the third voltage REFc corresponds to a forced rise release level of the error voltage ERR, and is set to a voltage value lower than the first voltage REFa (for example, REFc = REFa × 0.97). The fourth voltage REFd corresponds to the forcibly rising start level of the error voltage ERR (lower limit value of the error voltage ERR), and is set to a voltage value lower than the third voltage REFc (for example, REFd = REFa × 0.95). Yes.

  As each of the voltages REFa to REFd, it is desirable to use a constant voltage (such as a band gap voltage) that does not depend on fluctuations in the input voltage IN or the ambient temperature.

  FIG. 2 is a timing chart showing an example of switching operation under heavy load (continuous mode), and in order from the top, the output voltage OUT, the switch voltage SW, the inductor current IL, the feedback voltage FB, the error voltage ERR, and the comparison The signal S1, the on time setting signal S2, the backflow detection signal S3, the gate signals G1 and G2, and the lower limit detection signal DET are depicted.

  At time t11, when the feedback voltage FB falls below the error voltage ERR and the comparison signal S1 rises to a high level, the on-time setting signal S2 rises to a high level. Thereafter, the on-time setting signal S2 is maintained at a high level until a predetermined on-time Ton elapses.

  From time t11 to t12 (high level period of the on-time setting signal S2), the gate signal G1 becomes high level and the gate signal G2 becomes low level, so that the transistor 11 is turned on and the transistor 12 is turned off. Accordingly, at times t11 to t12, the switch voltage SW rises substantially to the input voltage IN, and the inductor current IL increases.

  At time t12, when the gate signal G1 falls to the low level and the gate signal G2 rises to the high level, the transistor 11 is turned off and the transistor 12 is turned on. Therefore, the switch voltage SW decreases to almost the ground voltage GND, and the inductor current IL starts to decrease.

  Here, if the output current Io flowing through the load is sufficiently large, the inductor current IL continues to flow toward the load without falling below the zero value until time t13 when the gate signal G1 rises to the high level again. Therefore, no backflow current is generated in the transistor 12, so that the backflow detection signal S3 does not rise to a high level.

  Thereafter, when the feedback voltage FB again falls below the error voltage ERR at time t13, the comparison signal S1 rises to a high level, and the same switching operation as described above is repeated.

  2, the error voltage ERR does not decrease to the fourth voltage REFd, so the lower limit detection signal DET is maintained at a low level.

  FIG. 3 is a timing chart showing an example of the switching operation at the time of light load (discontinuous mode). From the top, the output voltage OUT, the switch voltage SW, the inductor current IL, the feedback voltage FB, the error voltage ERR, The comparison signal S1, the on time setting signal S2, the backflow detection signal S3, the gate signals G1 and G2, and the lower limit detection signal DET are depicted.

  After the ON period (t21 to t22) of the transistor 11 elapses, at time t22, when the gate signal G1 is lowered to a low level and the gate signal G2 is raised to a high level, the transistor 11 is turned off, and the transistor 12 Is turned on. Therefore, the switch voltage SW decreases to almost the ground voltage GND, and the inductor current IL starts to decrease.

  Here, if the output current Io flowing through the load is sufficiently large, the coil current IL continues to flow toward the load without falling below the zero value until time t24 when the gate signal G1 rises to the high level again. On the other hand, when the output current Io flowing through the load is small and the load is light, the energy stored in the inductor L1 is small. Therefore, at time t23, the inductor current IL falls below the zero value, and a backflow current to the transistor 12 is generated. In such a state, the electric charge is thrown away to the ground terminal, which causes a reduction in efficiency at light load.

  Therefore, the switching power supply device A is configured to detect the backflow current to the transistor 12 using the backflow current detection unit 16 and forcibly turn off the transistor 12 at time t23 when the backflow detection signal S3 rises to a high level. Yes. By adopting such a configuration, it is possible to eliminate a decrease in efficiency at a light load.

  Note that, as the output current Io flowing through the load decreases, the output voltage OUT is less likely to decrease during the off-period of the transistor 11, so that the period during which the feedback voltage FB exceeds the reference voltage REF1 (= REFa) increases. The amount of decrease in ERR increases. However, in the example of FIG. 3, since the error voltage ERR starts to rise before falling below the fourth voltage REFd, the lower limit detection signal DET is maintained at a low level.

  Thereafter, when the feedback voltage FB again falls below the error voltage ERR at time t24, the comparison signal S1 rises to a high level, and the same switching operation as described above is repeated.

  FIG. 4 is a timing chart showing an example of the switching operation at the time of an ultra light load (in the discontinuous mode). In order from the top, the output voltage OUT, the switch voltage SW, the inductor current IL, the feedback voltage FB, and the error voltage ERR. The comparison signal S1, the ON time setting signal S2, the backflow detection signal S3, the gate signals G1 and G2, and the lower limit detection signal DET are depicted.

  In an ultralight load state (a state close to no load) in which the output current Io to the load is almost 0 A, the output voltage OUT hardly decreases after the transistors 11 to 12 are turned off. At this time, as long as the feedback voltage FB exceeds the reference voltage REF1 (= REFa), the error amplifier 13 continues to operate so as to reduce the error voltage ERR, so that the error voltage ERR remains at 0 V (or in the vicinity) as it is. It will decline.

  Therefore, the switching power supply device A according to the first embodiment includes an error voltage monitoring unit 19 that monitors the error voltage ERR and generates a lower limit detection signal DET, and a selector 20 that switches the reference voltages REF1 and REF2 according to the lower limit detection signal DET. And 21 are used to limit the lower limit value of the error voltage ERR. Hereinafter, a specific description will be given with reference to FIG.

  After the transistors 11 and 12 are turned off after time t31 to t33, when the error voltage ERR falls below the fourth voltage REFd and the lower limit detection signal DET rises to a high level at time t34, the reference voltage REF1 is changed from the voltage REFa to the voltage REFa. While being raised to REFb, the reference voltage REF2 is raised from the fourth voltage REFd to the third voltage REFc. When the feedback voltage FB falls below the reference voltage REF1 (= REFb) by raising the reference voltage REF1, the error voltage ERR starts to rise.

  Thereafter, at time t35, when the error voltage ERR exceeds the third voltage REFc and the lower limit detection signal DET falls to the low level, the reference voltage REF1 is lowered from the voltage REFb to the voltage REFa, and the reference voltage REF2 is changed to the third voltage. The voltage is reduced from REFc to the fourth voltage REFd.

  If the feedback voltage FB exceeds the reference voltage REF1 (= REFa) at the time when the lower limit detection signal DET falls to the low level, the error voltage ERR starts to decrease again, but the feedback voltage FB changes to the reference voltage REF1. If it is lower than (= REFa), the error voltage ERR continues to rise as it is (see comparison between time t35 and time t37).

  Thereafter, when the feedback voltage FB again falls below the error voltage ERR at time t38, the comparison signal S1 rises to a high level, and the same switching operation as described above is repeated.

  FIG. 5 is a timing chart showing an example of a transient response at the time of sudden load change (at the time of transition from an ultralight load state to a heavy load state). From the top, the output voltage OUT, the feedback voltage FB, the error voltage ERR, and the lower limit are shown. The detection signal DET and the output current Io are depicted.

  As described above, in the switching power supply device A of the first embodiment, the lower limit value of the error voltage ERR in the ultralight load state is limited by using the error voltage monitoring unit 19 and the selectors 20 and 21. With such a configuration, even when the output current Io suddenly increases at the time tx, the error voltage ERR follows this and quickly returns to the normal control level (= REFa). Therefore, compared with a configuration in which the lower limit value of the error voltage ERR is not limited (see the broken line in the figure), the response to a sudden load change is enhanced, so that fluctuations in the output voltage OUT can be suppressed to a small level.

  The error amplifier 13 may be configured such that the magnitude of the drive current can be switched according to the lower limit detection signal DET. More specifically, if the drive current of the error amplifier 13 is boosted during the high level period of the lower limit detection signal DET and the current output capability thereof is temporarily increased, only during the high level period of the lower limit detection signal DET. Since the error voltage ERR can be raised faster than usual, the responsiveness to a sudden load change can be further improved. If the drive current of the error amplifier 13 is steadily increased, the self-consumption current of the switching power supply device A is increased, and the phase margin of the output feedback loop is reduced, and oscillation is likely to occur. On the other hand, if the drive current of the error amplifier 13 is increased only during the high level period of the lower limit detection signal DET, the responsiveness to a sudden load change can be improved without causing the above problem.

  Further, in the switching power supply device A of the first embodiment, unlike the second embodiment to be described later, buffer processing of the error amplifier 13 (processing for switching the signal input path so as to use the error amplifier 13 as a buffer) is not performed. Therefore, unintended output fluctuations do not occur before and after buffer processing (before and after switching between the discontinuous mode and the continuous mode).

  In addition, unlike the third embodiment described later, the switching power supply device A of the first embodiment is not configured to forcibly raise the error voltage ERR using a clamper, so that the error amplifier 13 draws a current from the capacitor C2. It will not be in the state of trying to pull out to the maximum. Therefore, the error voltage ERR can be returned to the normal control level (= REFa) more quickly than in the third embodiment.

<Switching power supply device (second embodiment)>
FIG. 6 is a block diagram showing a second embodiment of the switching power supply device. The second embodiment has basically the same configuration as that of the first embodiment, and is characterized in that a selector 22 is provided instead of the error voltage monitoring unit 19 and the selectors 20 and 21. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 1, and redundant descriptions are omitted. In the following, only the characteristic portions of the second embodiment will be described. .

  The selector 22 connects the inverting input terminal (−) of the error amplifier 13 to the output terminal of the ripple injection unit 18 in the continuous mode, while the inverting input terminal (−) of the error amplifier 13 outputs the error amplifier 13 in the discontinuous mode. Connect to the end. That is, in the discontinuous mode, buffer processing of the error amplifier 13 (processing for switching the signal input path so that the error amplifier 13 is used as a buffer) is performed.

  FIG. 7 is a timing chart showing an example of output behavior in the second embodiment, in which an output voltage OUT, an error voltage ERR, and an output current Io are depicted in order from the top.

  In the discontinuous mode in which the output current Io is smaller than the threshold current Ith (before time ty), the error amplifier 13 functions as a buffer, so that the error voltage ERR is fixed to the reference voltage REF. Accordingly, since the error voltage ERR does not unnecessarily decrease excessively in the discontinuous mode, the error voltage ERR is made to respond without delay even when the load suddenly increases from an ultra-light load state, and the output voltage It is possible to suppress fluctuations in OUT.

  However, in the switching power supply device A of the second embodiment, the output control level (signal level to the inverting input terminal) of the error amplifier 13 changes before and after buffer processing (before and after switching between the discontinuous mode and the continuous mode). Therefore, even if a steep load fluctuation does not occur, an unintended transient fluctuation occurs in the output voltage OUT.

<Switching Power Supply Device (Third Embodiment)>
FIG. 8 is a block diagram showing a third embodiment of the switching power supply device. The third embodiment has basically the same configuration as that of the first embodiment, and is characterized in that a clamper 23 is provided in place of the error voltage monitoring unit 19 and the selectors 20 and 21. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 1, and redundant descriptions are omitted. In the following, only the characteristic parts of the third embodiment will be described. .

  The clamper 23 is an element or a circuit for forcibly raising the error voltage ERR so that the error voltage ERR does not fall below the clamp voltage Vclamp.

  FIG. 9 is a timing chart showing an example of the output behavior in the third embodiment, in which the output voltage OUT, the feedback voltage FB, the error voltage ERR, and the output current Io are depicted in order from the top.

  In the switching power supply device A of the third embodiment, the lower limit value of the error voltage ERR in the ultra light load state is limited using the clamper 23. By adopting such a configuration, even when the output current Io suddenly increases at time tz, compared to a configuration that does not limit the lower limit value of the error voltage ERR (see the broken line in the figure), The error voltage ERR can be returned to the normal control level (= REFa) more quickly.

  However, in the switching power supply device A of the third embodiment, since the error amplifier 13 is trying to draw the current from the capacitor C2 to the maximum at the time tz, compared with the previous first embodiment. It takes time to recover the error voltage ERR.

<On time setting section>
FIG. 10 is a block diagram illustrating a first configuration example of the on-time setting unit 15. The on-time setting unit 15 of the first configuration example includes an RS flip-flop 151, a voltage / current conversion unit 152, a capacitor 153, an N-channel MOS field effect transistor 154, a voltage / voltage conversion unit 155, an on-time A comparator 156.

  The RS flip-flop 151 sets the output signal Q (ON time setting signal S2) to the high level at the rising edge of the set signal S (comparison signal S1), and resets the output signal Q to the low level at the rising edge of the reset signal R. To do. The RS flip-flop 151 outputs an output signal Q and also outputs an inverted output signal QB obtained by logically inverting the output signal Q.

  The voltage / current conversion unit 152 generates a charging current Ia for the capacitor 153 by performing voltage / current conversion on the input voltage IN. The current value of the charging current Ia varies according to the voltage value of the input voltage IN. Specifically, the charging current Ia increases as the input voltage IN increases, and the charging current Ia decreases as the input voltage IN decreases.

  A first end of the capacitor 153 is connected to the voltage / current conversion unit 152. A second terminal of the capacitor 153 is connected to the ground terminal. When the transistor 154 is off, the capacitor 153 is charged by the charging current Ia, and the sawtooth voltage Va appearing at the first end of the capacitor 153 rises with a degree of increase (slope) corresponding to the input voltage IN. On the other hand, when the transistor 154 is on, the capacitor 153 is discharged through the transistor 154, and the sawtooth voltage Va rapidly decreases.

  The transistor 154 is a charge / discharge switch that switches charging / discharging of the capacitor 153 according to the inverted output signal QB. The drain of the transistor 154 is connected to the first end of the capacitor 153. The source of the transistor 154 is connected to the ground terminal. The gate of the transistor 154 is connected to the application terminal of the inverted output signal QB.

  The voltage / voltage conversion unit 155 generates a threshold voltage Vb corresponding to the output voltage OUT by performing voltage / voltage conversion on the output voltage OUT. The voltage value of the threshold voltage Vb varies according to the voltage value of the output voltage OUT. Specifically, the threshold voltage Vb increases as the output voltage OUT increases, and the threshold voltage Vb decreases as the output voltage OUT decreases.

  The on-time comparator 156 generates the reset signal R by comparing the sawtooth voltage Va input to the non-inverting input terminal (+) and the threshold voltage Vb input to the inverting input terminal (−). If the sawtooth voltage Va is higher than the threshold voltage Vb, the reset signal R is at a high level, and if the sawtooth voltage Va is lower than the threshold voltage Vb, the reset signal R is at a low level.

  FIG. 11 is a timing chart showing an example of the on-time setting operation (ideal state). In order from the top, the feedback voltage FB, the set signal S, the inverted output signal QB, the sawtooth voltage Va, the reset signal R, and the output Signal Q is depicted.

  When the feedback voltage FB falls below the error voltage ERR during the off period of the transistor 11, the set signal S rises to a high level and the output signal Q changes to a high level. Therefore, the transistor 11 is turned on, and the feedback voltage FB starts to increase. At this time, the transistor 154 is turned off with the low-level transition of the inverted output signal QB, so that charging of the capacitor 153 with the charging current Ia is started. As described above, the current value of the charging current Ia varies according to the voltage value of the input voltage IN. Therefore, the sawtooth voltage Va increases with a degree of increase (slope) corresponding to the input voltage IN.

  Thereafter, when the sawtooth voltage Va rises to a threshold voltage Vb (a divided voltage of the output voltage OUT), the reset signal R rises to a high level and the output signal Q changes to a low level. Therefore, the transistor 11 is turned off, and the feedback voltage FB starts to fall again. At this time, the transistor 154 is turned on with the high level transition of the inverted output signal QB. Therefore, the capacitor 153 is quickly discharged through the transistor 154, and the sawtooth voltage Va is lowered to a low level.

  The driver 17 generates gate signals G1 and G2 according to the on-time setting signal S2 (corresponding to the output signal Q), and performs on / off control of the transistors 11 and 12 using this. As a result, a rectangular wave switch voltage SW is output from the external terminal T2. The switch voltage SW is rectified and smoothed by the inductor L1 and the capacitor C1, and an output voltage OUT is generated. The output voltage OUT is divided by the resistors R1 and R2, and the feedback voltage FB described above is generated. With such output feedback control, the switching power supply device A generates a desired output voltage OUT from the input voltage IN with a very simple configuration.

  Here, the on-time setting unit 15 does not set the on-time Ton as a fixed value, but sets it as a fluctuation value according to the input voltage IN and the output voltage OUT. More specifically, the on-time setting unit 15 shortens the on-time Ton by increasing the degree of increase (slope) of the sawtooth voltage Va as the input voltage IN is higher, and the sawtooth voltage Va as the input voltage IN is lower. The on-time Ton is lengthened by reducing the degree of increase (inclination). Further, the ON time setting unit 15 decreases the ON time Ton by lowering the threshold voltage Vb as the output voltage OUT is lower, and increases the ON time Ton by increasing the threshold voltage Vb as the output voltage OUT is higher. In other words, the on-time setting unit 15 sets an on-time Ton proportional to the output voltage OUT in inverse proportion to the input voltage IN.

  By adopting such a configuration, fluctuations in the switching frequency can be suppressed without impairing the advantages of the nonlinear control method. Accordingly, it is possible to improve output voltage accuracy and load regulation characteristics, or to facilitate measures against EMI (electromagnetic interference) and noise in set design. Further, the switching power supply device A can be applied without any problem as a power supply means for an application having a large input voltage fluctuation or an application that requires various output voltages.

  However, when there is a circuit delay in the on-time comparator 156, as shown in FIG. 12, even after the sawtooth voltage Va exceeds the threshold voltage Vb, the reset signal R remains maintained at a low level. The reset signal R is raised to the high level only when the delay time Td has elapsed. As a result, the on-time Ton becomes longer (Ton → Ton ′) and the off-time Toff also becomes longer (Toff → Toff ′), so that the intended switching frequency cannot be obtained. In particular, the faster the switching frequency, the greater the frequency variation.

  FIG. 13 is a block diagram illustrating a second configuration example of the on-time setting unit 15. The second configuration example is basically the same configuration as the first configuration example, and is characterized in that an offset unit 157 that offsets the threshold voltage Vb according to the input voltage IN is provided. Therefore, the same components as those in the first configuration example are denoted by the same reference numerals as those in FIG. 10, and redundant description is omitted. In the following, only the characteristic portions of the second configuration example will be described. .

  The offset unit 157 subtracts the offset voltage Vofs from the threshold voltage Vb to generate an offset threshold voltage Vb2 (= Vb−Vofs), and applies this to the inverting input terminal (−) of the on-time comparator 156.

  In the on-time setting unit 15 of the second configuration example, the voltage / current conversion unit 152 is configured to generate an offset adjustment current Ib of a different system from the charging current Ia of the capacitor 153 according to the input voltage IN. The offset unit 157 is configured to variably control the offset voltage Vofs (corresponding to the offset amount of the threshold voltage Vb) in accordance with the offset adjustment current Ib (and thus the input voltage IN). Hereinafter, the technical significance of this configuration will be described in detail.

  When the capacitance value of the capacitor 153 is C, the on-time Ton set using the offset threshold voltage Vb2 can be calculated by the following equation (1).

Ton = (C × Vb2 / Ia) + Td
= {C × (Vb−Vofs) / Ia} + Td
= (C × Vb / Ia) − (C × Vofs / Ia) + Td (1)

  Here, since the first term on the right side (C × Vb / Ia) represents the on-time in an ideal state without the delay time Td, the second term on the right side (C × Vofs / Ia) is the third term on the right side (Td If the offset voltage Vofs is set so as to coincide with (), the circuit delay (delay time Td) of the on-time comparator 156 can be canceled (see FIG. 14).

  In the second term on the right side (C × Vofs / Ia), the capacitance value C is a fixed value, but the charging current Ia is a variable value proportional to the input voltage IN. Therefore, when the offset voltage Vofs is a fixed value, the second term on the right side (C × Vofs / Ia) fluctuates in inverse proportion to the input voltage IN. Therefore, depending on the voltage value of the input voltage IN, the third term on the right side (Td) cannot be canceled appropriately.

  On the other hand, when the offset voltage Vofs is a variable value proportional to the input voltage IN, the influence of the input voltage IN can be offset by the denominator and the numerator of the second term on the right side (C × Vofs / Ia). It is possible to appropriately cancel the third term (Td) on the right side without depending on the voltage value of the input voltage IN.

  Thus, according to the on-time setting unit 15 of the second configuration example, the offset of the on-time Ton caused by the circuit delay of the on-time comparator 156 is appropriately corrected by using the offset voltage Vofs proportional to the input voltage IN. Therefore, it is possible to suppress fluctuations in the switching frequency.

  FIG. 15 is a circuit diagram showing a detailed configuration of the on-time setting unit 15. Hereinafter, each circuit configuration and operation will be described in detail in the order of the voltage / current conversion unit 152, the voltage / voltage conversion unit 155, and the offset unit 157.

  Voltage / current conversion unit 152 includes an operational amplifier a1, an N-channel MOS field effect transistor a2, P-channel MOS field effect transistors a3 to a5, and resistors a6 to a8. The first end of the resistor a6 is connected to the application end of the input voltage IN. The second end of the resistor a6 and the first end of the resistor a7 are both connected to the non-inverting input terminal (+) of the operational amplifier a1. A second terminal of the resistor a7 is connected to the ground terminal. The inverting input terminal (−) of the operational amplifier a1 is connected to the source of the transistor a2 and the first terminal of the resistor a8. A second end of the resistor a8 is connected to the ground end. The output terminal of the operational amplifier a1 is connected to the gate of the transistor a2. The drain of the transistor a2 is connected to the drain of the transistor a3. The sources of the transistors a3 to a5 are all connected to the application terminal for the input voltage IN. The gates of the transistors a3 to a5 are all connected to the drain of the transistor a3. The drain of the transistor a5 corresponds to the first output terminal (the output terminal of the charging current Ia). The drain of the transistor a4 corresponds to the second output terminal (the output terminal of the offset adjustment current Ib).

  In the voltage / current converter 152 configured as described above, the operational amplifier a1 generates the gate voltage of the transistor a2 so that the voltages applied to the two input terminals thereof are equal to each other. Therefore, the divided voltage Vx of the input voltage IN is applied to the resistor a8, and the reference current Ix proportional to this flows. On the other hand, the transistors a3 to a5 forming the current mirror mirror the reference current Ix to generate the charging current Ia and the offset adjustment current Ib. Therefore, the charging current Ia and the offset adjustment current Ib are currents proportional to the reference current Ix (and thus the input voltage IN), respectively.

  The voltage / voltage conversion unit 155 includes an operational amplifier b1 and resistors b2 to b5. A first terminal of the resistor b2 is connected to an application terminal for the output voltage OUT. The second end of the resistor b2 and the first end of the resistor b3 are both connected to the non-inverting input terminal (+) of the operational amplifier b1. A second terminal of the resistor b3 is connected to the ground terminal. The output terminal of the operational amplifier b1 corresponds to the output terminal of the threshold voltage Vb, and is connected to the first terminal of the resistor b4. The inverting input terminal (−) of the operational amplifier b1 is connected to the second terminal of the resistor b4 and the first terminal of the resistor b5. The second end of the resistor b5 is connected to the ground end.

  In the voltage / voltage conversion unit 155 configured as described above, the operational amplifier b1 generates the threshold voltage Vb so that the voltages applied to the two input terminals thereof are equal to each other. That is, the operational amplifier b1 has a divided voltage Vy1 of the output voltage OUT (= α × OUT, where α is a voltage dividing ratio determined according to each resistance value of the resistors b2 and b3) and a divided voltage Vy2 ( = Β × Vb, where β is a threshold voltage Vb such that β is a voltage dividing ratio determined according to the resistance values of the resistors b4 and b5. Therefore, the threshold voltage Vb is a voltage (= (α / β) × OUT) proportional to the output voltage OUT.

  The offset unit 157 includes N-channel MOS field effect transistors c1 and c2 and a resistor c3 (resistance value: Rc3). The drain of the transistor c1 is connected to the second output terminal of the voltage / current converter 152 (the output terminal of the offset adjustment current Ib). The gates of the transistors c1 and c2 are both connected to the drain of the transistor c1. The sources of the transistors c1 and c2 are both connected to the ground terminal. The first end of the resistor c3 is connected to the output end of the voltage / voltage conversion unit 155 (the application end of the threshold voltage Vb). The second end of the resistor c3 and the drain of the transistor c2 are both connected to the inverting input end of the on-time comparator 156 (the application end of the threshold voltage Vb2 that has been offset adjusted).

  In the offset unit 157 configured as described above, the transistors c1 and c2 forming the current mirror are offset in a direction from the output terminal (application terminal of the threshold voltage Vb) of the voltage / voltage conversion unit 155 to the ground terminal via the resistor c3. The current direction of the offset adjustment current Ib is folded so that the adjustment current Ib flows. As a result, an offset voltage Vofs (= Ib × Rc3) proportional to the offset adjustment current Ib (and thus the input voltage IN) is generated between both ends of the resistor c3, and this offset voltage Vofs is subtracted from the threshold voltage Vb.

  However, the offset method of the threshold voltage Vb is not limited to this, and the input offset is applied between the non-inverting input terminal (+) and the inverting input terminal (−) of the on-time comparator 156. It doesn't matter.

<Application to electronic devices>
16 to 18 are external views showing examples of electronic devices (personal computer X, digital multi-function peripheral Y, and portable terminal (smart phone) Z) on which the above-described switching power supply device A is mounted. These illustrations are only examples, and the above-described switching power supply device A can be mounted on a wide variety of electronic devices.

<Other variations>
In the above-described embodiment, the configuration in which the present invention is applied to the synchronous rectification step-down switching power supply apparatus has been described as an example. However, the application target of the present invention is not limited thereto, and switching As the drive method, an asynchronous rectification method may be employed, and the output stage of the switching power supply device may be a boost type or a step-up / down type.

  As described above, the configuration of the present invention can be variously modified within the scope of the present invention in addition to the above-described embodiment. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The switching power supply device disclosed in the present specification can be used for, for example, a personal computer, a digital multifunction peripheral, a portable terminal (smart phone), and the like.

A Switching power supply device 1 Semiconductor device (switching power supply IC)
11 N-channel MOS field effect transistor (output transistor)
12 N-channel MOS field effect transistor (synchronous rectification transistor)
13 Error Amplifier 14 Main Comparator 15 ON Time Setting Unit 151 RS Flip-Flop 152 Voltage / Current Conversion Unit 153 Capacitor 154 N-channel MOS Field Effect Transistor (Discharge Transistor)
155 Voltage / Voltage Conversion Unit 156 On-Time Comparator 157 Offset Unit 16 Backflow Detection Unit 17 Driver 18 Ripple Injection Unit 19 Error Voltage Monitoring Unit (Comparator)
20-22 selector 23 clamper L1 inductor R1, R2 resistor C1, C2 capacitor T1-T5 external terminal a1 operational amplifier a2 N-channel MOS field effect transistor a3-a5 P-channel MOS field effect transistor a6-a8 resistor b1 operational amplifier b2-b5 Resistor c1, c2 N-channel MOS field effect transistor c3 Resistor X Personal computer Y Digital multifunction device Z Mobile terminal (smartphone)

Claims (12)

An error amplifier that generates an error voltage according to a difference between the feedback voltage generated from the output voltage and the first reference voltage;
A main comparator that compares the feedback voltage with the error voltage to generate a comparison signal;
An on-time setting unit for generating an on-time setting signal having a fixed pulse width according to the comparison signal;
A driver for generating the output voltage from an input voltage by performing ON / OFF control of the switching element in response to the on-time setting signal,
An error voltage monitoring unit that compares the error voltage with a second reference voltage to generate a lower limit detection signal;
A first selector that selectively outputs either the first voltage or the second voltage as the first reference voltage according to the lower limit detection signal;
A second selector that selectively outputs one of a third voltage and a fourth voltage as the second reference voltage according to the lower limit detection signal;
A switching power supply device comprising:   The second voltage according to claim 1, wherein the second voltage is higher than the first voltage, the third voltage is lower than the first voltage, and the fourth voltage is lower than the third voltage. Switching power supply. The first selector raises the first reference voltage from the first voltage to the second voltage when the error voltage falls below the fourth voltage, while the error voltage exceeds the third voltage. In order to lower the first reference voltage from the second voltage to the first voltage, a selection output of the first voltage and the second voltage is performed according to the lower limit detection signal,
The second selector raises the second reference voltage from the fourth voltage to the third voltage when the error voltage falls below the fourth voltage, while the error voltage exceeds the third voltage. 3. The selection output of the third voltage and the fourth voltage is performed according to the lower limit detection signal so as to lower the second reference voltage from the third voltage to the fourth voltage. The switching power supply device described in 1.   4. The switching power supply device according to claim 3, wherein the error amplifier is switched in accordance with the lower limit detection signal. The on-time setting unit
A capacitor that generates a sawtooth voltage by charging and discharging; and
A voltage / current converter that generates a charging current for the capacitor in accordance with the input voltage;
A charge / discharge switch for switching charge / discharge of the capacitor;
A voltage / voltage converter that generates a threshold voltage according to the output voltage;
An on-time comparator that compares the sawtooth voltage with the threshold voltage to generate a reset signal;
RS flip-flop for setting / resetting the on-time setting signal according to the comparison signal and the reset signal;
The switching power supply unit according to claim 1, wherein the switching power supply unit includes:   The switching power supply device according to claim 5, wherein the on-time setting unit further includes an offset unit that offsets the threshold voltage.   The switching power supply device according to claim 6, wherein the offset unit variably controls an offset amount of the threshold voltage according to the input voltage. The voltage / current conversion unit generates an offset adjustment current of a system different from the charging current of the capacitor according to the input voltage,
The switching power supply device according to claim 7, wherein the offset unit variably controls an offset amount of the threshold voltage according to the offset adjustment current. A backflow detection unit that detects a backflow current to the switch element and generates a backflow detection signal;
The switching power supply device according to any one of claims 1 to 8, wherein the driver forcibly turns off the switch element in accordance with the backflow detection signal.   The switching power supply device according to claim 1, further comprising a feedback voltage generation unit that divides the output voltage to generate the feedback voltage.   The switching power supply according to any one of claims 1 to 10, further comprising a ripple injection unit that injects a ripple component into the feedback voltage.   An electronic apparatus comprising the switching power supply device according to any one of claims 1 to 11.