JP2016032322A - Switching power source device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve high efficiency in light load and malfunction prevention at the time of operation mode switching.SOLUTION: A power supply control IC comprises: a reverse current detection circuit 18 for detecting a reverse current to a synchronous rectification transistor; and an overcurrent protection circuit 40 for performing an overcurrent protection operation when an output current exceeds a threshold value. The over current protection circuit 40 is turned ON/OFF depending of the detection result of the reverse current. The power supply control IC further includes: a sleep object circuit with an operation mode being switched to either one of a normal mode or a sleep mode according to a mode switching signal; and a mode switching control circuit for performing output mask on a sleep object circuit without delay at the time of shifting from the normal mode to the sleep mode, and releasing the output mask on the sleep object circuit with a predetermined delay at the time of returning from the sleep mode to the normal mode.SELECTED DRAWING: Figure 29

Description

  The present invention relates to a non-linear control type switching power supply apparatus.

  FIG. 41 is a circuit block diagram showing a conventional example of a switching power supply apparatus. A switching power supply 100 of a non-linear control method (for example, a fixed on-time method, a fixed off-time method, or a hysteresis window method) is a switching power supply device of a linear control method (for example, a voltage mode control method or a current mode control method). Compared to the above, it has a feature that a high load response characteristic can be obtained with a simple circuit configuration.

  As an example of the related art related to the above, Patent Document 1 by the applicant of the present application can be cited.

  Patent Document 1 discloses a switching power supply device having a sleep mode in which an on-time setting circuit and a backflow detection circuit of the switching power supply device are turned on / off as necessary.

JP 2014-87159 A

  Certainly, with the switching power supply device disclosed in Patent Document 1, the power consumption of the on-time setting circuit and the backflow detection circuit can be reduced by shifting to the sleep mode at the time of light load. It is possible to improve the efficiency.

  However, in the conventional switching power supply device, the safety priority is always given to the safety at the time of output ground fault, and the overcurrent protection circuit is always turned on even at light load, and the drive current is consumed not a little. For this reason, there remains room for further improvement in improving efficiency at light loads.

  In addition, when the operation mode is switched (when shifting from the normal mode to the sleep mode or when returning from the sleep mode to the normal mode), the drive current of the sleep target circuit varies greatly. For this reason, in the conventional switching power supply device, an unintended switching operation occurs due to the above-described current fluctuation, and there is a possibility that the output ripple is increased.

  In view of the above-described problems found by the inventors of the present application, the present invention uses a power supply control IC capable of realizing high efficiency at light load and prevention of malfunction during operation mode switching, and the same. An object of the present invention is to provide a switching power supply device and an electronic device.

  A power supply control IC disclosed in the present specification includes a gate driver circuit that drives an output transistor and a synchronous rectification transistor, a reverse current detection circuit that detects a reverse current to the synchronous rectification transistor, and an output current that exceeds a threshold value. An overcurrent protection circuit that performs an overcurrent protection operation when the current becomes larger, the overcurrent protection circuit being turned on / off according to the detection result of the backflow current (first configuration) It is said that.

  In the power supply control IC having the first configuration, the overcurrent protection circuit is turned off when the reverse current is detected, and is turned on when the reverse current is not detected. A configuration (second configuration) is preferable.

  In the power supply control IC having the first or second configuration, the overcurrent protection circuit latches the detection result of the backflow current every switching period and is turned on / off according to the latch output. (Third configuration) is preferable.

  The power supply control IC disclosed in the present specification includes a sleep target circuit whose operation mode is switched to one of a normal mode and a sleep mode in response to a mode switching signal; and from the normal mode to the sleep mode. A mode switching control circuit that performs output masking of the sleep target circuit without delay at the time of transition to, and cancels the output mask of the sleep target circuit with a predetermined delay when returning from the sleep mode to the normal mode; ; (Fourth configuration).

  The power supply control IC having the fourth configuration includes a gate driver circuit that drives the output transistor and the synchronous rectification transistor, and the mode switching control circuit sends the mode switching signal to the off timing of the synchronous rectification transistor. A configuration (fifth configuration) may be employed in which latching is performed and the output mask of the sleep target circuit is canceled using the latch output.

  The power supply control IC having the fifth configuration further includes a sub-comparator that performs an alternative operation when the main comparator forming the output feedback loop of the non-linear control system is in the sleep mode (sixth (6th). (Configuration).

  In the power supply control IC having the sixth configuration, the sub-comparator continues to operate even when the main comparator is in the normal mode as means for setting the maximum on-time of the output transistor. It is preferable to adopt a configuration (seventh configuration).

  The power control IC having the sixth or seventh configuration further includes a noise mask circuit that masks output noise of the sub-comparator when the normal mode is shifted to the sleep mode (eighth configuration). It is good to.

  The switching power supply disclosed in this specification includes a power supply control IC having any one of the first to eighth configurations, and a part or all of the power supply control IC is externally attached to output from an input voltage. And a switch output stage for generating a voltage (a ninth configuration).

  Further, the electronic device disclosed in the present specification has a configuration (tenth configuration) including a switching power supply device having the ninth configuration.

  According to the present invention, it is possible to provide a power supply control IC capable of realizing high efficiency at light load and prevention of malfunction during operation mode switching, and a switching power supply device and electronic equipment using the same. Become.

The block diagram which shows 1st Embodiment of a switching power supply device The figure which shows the 1st structural example of an ON time setting circuit. Time chart for explaining the on-time setting operation of the first configuration example The figure which shows the 2nd structural example of an ON time setting circuit. The figure which shows the modification of the ON time setting circuit of a 2nd structural example. Time chart for explaining power saving operation (backflow blocking operation) at light load Diagram showing one configuration example (feedback voltage side) of a ripple injection circuit The figure which shows the example of 1 structure of a reference voltage generation circuit The figure which shows the 1st structural example of a discharge control part. The figure which shows the 2nd structural example of a discharge control part. Time chart showing an example of ripple injection operation Comparison of old and new output behavior during input fluctuation Comparison of old and new output behavior during load fluctuation Old and new contrast diagram of transition behavior from light load to heavy load The block diagram which shows 2nd Embodiment of a switching power supply device Circuit diagram showing a configuration example of a silencer circuit and an on-time setting circuit Time chart showing an example of silent operation Time chart showing an example of silent operation when load is gradually increased Enlarged view of broken line area α Enlarged view of broken line area β Time chart showing an example of quiet operation stop cancellation Time chart for explaining the principle of overshoot The figure which shows the example of 1 structure of an overshoot suppression circuit Time chart for explaining the first overshoot suppression operation The figure which shows the example of 1 structure of a backflow detection circuit Time chart for explaining the overshoot second suppression operation The block diagram which shows 3rd Embodiment of a switching power supply device Time chart showing sleep operation of ON time setting circuit and backflow detection circuit The figure which shows one structural example of an overcurrent protection circuit Time chart showing sleep operation of overcurrent protection circuit The figure which shows the example of 1 structure of the semiconductor device provided with the mode switching control circuit Time chart showing an example of mode switching control operation Enlarged view of broken line area γ Enlarged view of broken line area δ The block diagram which shows 4th Embodiment of a switching power supply device Diagram showing one configuration example (reference voltage side) of a ripple injection circuit Time chart showing the first example of ripple injection operation Time chart showing a second example of ripple injection operation Block diagram showing a configuration example of a television equipped with a switching power supply device Front view of a TV equipped with a switching power supply Side view of a TV equipped with a switching power supply Rear view of a TV with a switching power supply Circuit block diagram showing a conventional example of a switching power supply device

<Switching power supply>
FIG. 1 is a block diagram showing a first embodiment of a switching power supply device. The switching power supply device 1 of the first embodiment is a step-down DC / DC converter that generates an output voltage Vout from an input voltage Vin by a non-linear control method (bottom detection on-time fixed method). The switching power supply device 1 includes a semiconductor device 10 and various discrete components externally attached to the semiconductor device 10 (N-channel MOS [metal oxide semiconductor] field effect transistors N1 and N2, a coil L1, a capacitor C1, and a resistor R1. And a switch output stage 20 formed by R2).

  The semiconductor device 10 is a main body (so-called power supply control IC) that comprehensively controls the entire operation of the switching power supply device 1. The semiconductor device 10 has external terminals T1 to T7 (upper gate terminal T1, lower gate terminal T2, switch terminal T3, feedback terminal T4, input voltage terminal T5 as means for establishing electrical connection with the outside of the device. , Output voltage terminal T6 and ground terminal T7). The external terminal T1 is connected to the gate of the transistor N1. The external terminal T2 is connected to the gate of the transistor N2. The external terminal T3 is connected to the application terminal of the switch voltage Vsw (a connection node between the source of the transistor N1 and the drain of the transistor N2). The external terminal T4 is connected to an application end (a connection node between the resistor R1 and the resistor R2) of the divided voltage Vdiv. The external terminal T5 is connected to the application terminal for the input voltage Vin. The external terminal T6 is connected to the application terminal for the output voltage Vout. The external terminal T7 is connected to the ground terminal.

  Next, the connection relationship of discrete components attached to the semiconductor device 10 will be described. The drain of the transistor N1 is connected to the application terminal for the input voltage Vin. The source of the transistor N2 is connected to the ground terminal. The source of the transistor N1 and the drain of the transistor N2 are both connected to the first end of the coil L1. The second end of the coil L1 and the first end of the capacitor C1 are both connected to the application terminal for the output voltage Vout. The second end of the capacitor C1 is connected to the ground end. The resistors R1 and R2 are connected in series between the application terminal of the output voltage Vout and the ground terminal.

  The transistor N1 is an output transistor that is on / off controlled according to the gate signal G1 input from the external terminal T1. The transistor N2 is a synchronous rectification transistor that is on / off controlled in accordance with the gate signal G2 input from the external terminal T2. As the rectifying element, a diode may be used instead of the transistor N2. The transistors N1 and N2 can also be built in the semiconductor device 10. The coil L1 and the capacitor C1 function as a rectifying / smoothing unit that rectifies and smoothes the rectangular-wave switch voltage Vsw appearing at the external terminal T3 to generate the output voltage Vout. The resistors R1 and R2 function as a divided voltage generation unit that divides the output voltage Vout to generate a divided voltage Vdiv.

  Next, the internal configuration of the semiconductor device 10 will be described. The semiconductor device 10 includes a ripple injection circuit 11, a reference voltage generation circuit 12, a main comparator 13, a one-shot pulse generation circuit 14, an RS flip-flop 15, an on time setting circuit 16, and a gate driver circuit 17. The backflow detection circuit 18 is integrated.

  The ripple injection circuit 11 adds a ripple voltage Vrpl (a pseudo ripple component simulating a coil current IL flowing through the coil L1) to the divided voltage Vdiv to generate a feedback voltage Vfb (= Vdiv + Vrpl). If such a ripple injection technique is introduced, stable switching control can be performed even if the ripple component of the output voltage Vout (and thus the divided voltage Vdiv) is not so large. A ceramic capacitor or the like can be used.

  The reference voltage generation circuit 12 generates a predetermined reference voltage Vref.

  The main comparator 13 compares the feedback voltage Vfb input to the inverting input terminal (−) and the reference voltage Vref input to the non-inverting input terminal (+) to generate the comparison signal S1. The comparison signal S1 is at a low level when the feedback voltage Vfb is higher than the reference voltage Vref, and is at a high level when the feedback voltage Vfb is lower than the reference voltage Vref.

  The one-shot pulse generation circuit 14 generates a one-shot pulse for the set signal S2 using the rising edge of the comparison signal S1 as a trigger.

  The RS flip-flop 15 sets the output signal S4 to a high level at the rising edge of the set signal S2 input to the set end (S), and the output signal at the rising edge of the reset signal S3 input to the reset end (R). S4 is reset to low level.

  The on-time setting circuit 16 sets the reset signal S3 to one after a predetermined on-time Ton has elapsed after the inverted output signal S4B of the RS flip-flop 15 (the logic inverted signal of the output signal S4) has fallen to a low level. Generate a shot pulse.

  The gate driver circuit 17 generates gate signals G1 and G2 according to the output signal S4 of the RS flip-flop 15, and performs switching control of the transistors N1 and N2 in a complementary (exclusive) manner. Note that the term “complementary (exclusive)” used in this specification refers to the transistors N1 and N2 from the viewpoint of preventing through-current in addition to the case where the on / off states of the transistors N1 and N2 are completely reversed. This includes a case where a delay is given to the on / off transition timing (when a simultaneous off period (dead time) is provided).

  The backflow detection circuit 18 monitors a backflow current to the transistor N2 (coil current IL flowing back from the coil L1 to the ground terminal via the transistor N2) and generates a backflow detection signal S5. The backflow detection signal S5 is latched at a high level (logic level at the time of backflow detection) when a backflow current to the transistor N2 is detected, and is at a low level (when no backflow is detected) at the rising edge of the gate signal G1 in the next cycle. (Logical level). As a method for monitoring the reverse current, for example, a zero cross point at which the switch voltage Vsw switches from negative to positive during the ON period of the transistor N2 may be detected. When the backflow detection signal S5 is at a high level, the gate driver circuit 17 generates the gate signal G2 so as to forcibly turn off the transistor N2 without depending on the output signal S4.

  The reference voltage generator 12, the main comparator 13, the one-shot pulse attitude circuit 14, the RS flip-flop 15, the on-time setting circuit 16, the gate driver circuit 17, and the backflow detection circuit 18 described above are connected to the feedback voltage Vfb and the reference voltage. Switching of the non-linear control method (in this configuration example, the bottom detection on-time fixed method) that generates the output voltage Vout from the input voltage Vin by performing on / off control of the transistors N1 and N2 according to the comparison result with the voltage Vref Functions as a control circuit.

<On-time setting circuit (first configuration example)>
FIG. 2 is a diagram illustrating a first configuration example of the on-time setting circuit 16. The on-time setting circuit 16X of the first configuration example includes a voltage / current conversion unit X1, a capacitor X2, an N-channel MOS field effect transistor X3, a comparator X4, and resistors X5 and X6.

  The voltage / current conversion unit X1 generates a charging current IX (= a × Vin) by performing voltage / current conversion on the input voltage Vin applied to the external terminal T5. The current value of the charging current IX varies according to the voltage value of the input voltage Vin. Specifically, the charging current IX increases as the input voltage Vin increases, and the charging current IX decreases as the input voltage Vin decreases.

  The 1st end of the capacitor | condenser X2 is connected to the voltage / current conversion part X1. The second end of the capacitor X2 is connected to the ground terminal. When the transistor X3 is off, the capacitor X2 is charged by the charging current IX, and the first voltage VX1 appearing at the first end of the capacitor X2 rises. On the other hand, when the transistor X3 is turned on, the capacitor X2 is discharged through the transistor X3, and the first voltage VX1 decreases.

  The transistor X3 is a charge / discharge switch that switches charge / discharge of the capacitor X2 in accordance with on / off control of the transistors N1 and N2. The drain of the transistor X3 is connected to the first end of the capacitor X2. The source of the transistor X3 is connected to the ground terminal. The gate of the transistor X3 is connected to the application terminal of the inverted output signal S4B.

  The voltage / current conversion unit X1, the capacitor X2, and the transistor X3 described above correspond to a first voltage generation circuit that generates the first voltage VX1 according to the charge / discharge operation of the capacitor X2.

  The comparator X4 generates the reset signal S3 by comparing the first voltage VX1 input to the non-inverting input terminal (+) and the second voltage VX2 input to the inverting input terminal (−). The reset signal S3 is at a high level when the first voltage VX1 is higher than the second voltage VX2, and is at a low level when the first voltage VX1 is lower than the second voltage VX2.

  A first end of the resistor X5 is connected to an external terminal T6 to which the output voltage Vout is applied. The second end of the resistor X5 is connected to the first end of the resistor X6. A second terminal of the resistor X6 is connected to the ground terminal. The resistors X5 and X6 correspond to a second voltage generation circuit that outputs a second voltage VX2 obtained by dividing the output voltage Vout from the connection node.

  FIG. 3 is a time chart for explaining the on-time setting operation of the first configuration example. In FIG. 3, the feedback voltage Vfb, the set signal S2, the inverted output signal S4B, the first voltage VX1, the reset signal S3, and the output signal S4 are depicted in order from the top.

  When the feedback voltage Vfb decreases to the reference voltage Vref during the off period of the transistor N1, the set signal S2 rises to a high level and the output signal S4 changes to a high level. Accordingly, the transistor N1 is turned on, and the feedback voltage Vfb starts to rise. At this time, the transistor X3 is turned off with the low level transition of the inverted output signal S4B, so that charging of the capacitor X2 with the charging current IX is started. As described above, the current value of the charging current IX varies according to the voltage value of the input voltage Vin. Therefore, the first voltage VX1 rises with a degree of increase (slope) corresponding to the input voltage Vin.

  Thereafter, when the first voltage VX1 rises to the second voltage VX2 (a divided voltage of the output voltage Vout), the reset signal S3 rises to a high level, and the output signal S4 changes to a low level. Therefore, the transistor N1 is turned off, and the feedback voltage Vfb starts to fall again. At this time, the transistor X3 is turned on with the high level transition of the inverted output signal S4B. Therefore, the capacitor X2 is quickly discharged through the transistor X3, and the first voltage VX1 is lowered to the low level.

  The gate driver circuit 17 generates gate signals G1 and G2 in accordance with the output signal S4, and performs on / off control of the transistors N1 and N2 using this. As a result, a rectangular waveform switch voltage Vsw appears at the external terminal T3. The switch voltage Vsw is rectified and smoothed by the coil L1 and the capacitor C1, and the output voltage Vout is generated. The output voltage Vout is divided by the resistors R1 and R2, and the divided voltage Vdiv (and thus the feedback voltage Vfb) is generated. With such output feedback control, the switching power supply device 1 generates the desired output voltage Vout from the input voltage Vin with a very simple configuration.

  Here, the on-time setting circuit 16X does not set the on-time Ton as a fixed value, but sets it as a fluctuation value according to the input voltage Vin and the output voltage Vout. Specifically, the on-time setting circuit 16X increases the degree of increase (slope) of the first voltage VX1 to shorten the on-time Ton as the input voltage Vin increases, and the first voltage VX1 as the input voltage Vin decreases. The on-time Ton is lengthened by reducing the degree of increase (inclination). The on-time setting circuit 16X decreases the second voltage VX2 to shorten the on-time Ton as the output voltage Vout decreases, and increases the second voltage VX2 to increase the on-time Ton as the output voltage Vout increases. In other words, the on-time setting circuit 16X sets the on-time Ton as a variation value that is inversely proportional to the input voltage Vin and proportional to the output voltage Vout.

  By adopting such a configuration, fluctuations in the switching frequency can be suppressed without impairing the advantages of the nonlinear control method. Accordingly, it is possible to improve output voltage accuracy and load regulation characteristics, or to facilitate measures against EMI (electromagnetic interference) and noise in set design. Further, the switching power supply device 1 can be applied without any problem as a power supply means for an application having a large input voltage fluctuation or an application that requires various output voltages.

<On-time setting circuit (second configuration example)>
FIG. 4 is a diagram illustrating a second configuration example of the on-time setting circuit 16. The on-time setting circuit 16Y of the second configuration example includes a voltage / current converter Y1, a capacitor Y2 (capacitance value CY2), an N-channel MOS field effect transistor Y3, a comparator Y4, a level shifter Y5, and a selector Y6. , Including a filter Y7. A feature of the second configuration example is that a level shifter Y5, a selector Y6, and a filter Y7 are provided instead of the resistors X5 and X6 of the first configuration example.

  The voltage / current conversion unit Y1 is a circuit block that generates a charging current IY (= a × Vin) by performing voltage / current conversion on the input voltage Vin applied to the external terminal T5, and includes resistors Y11 to Y13 (resistance values). : RY11-RY13), an operational amplifier Y14, an N-channel MOS field effect transistor Y15, and P-channel MOS field effect transistors Y16 and Y17.

  A first end of the resistor Y11 is connected to the external terminal T5. The second end of the resistor Y11 and the first end of the resistor Y12 are both connected to the non-inverting input terminal (+) of the operational amplifier Y14. The second end of the resistor Y12 is connected to the ground end. The inverting input terminal (−) of the operational amplifier Y14 is connected to the source of the transistor Y15 and the first terminal of the resistor Y13. A second end of the resistor Y13 is connected to the ground end. The output terminal of the operational amplifier Y14 is connected to the gate of the transistor Y15. The drain of the transistor Y15 is connected to the drain of the transistor Y16. The sources of the transistors Y16 and Y17 are both connected to the power supply terminal. The gates of the transistors Y16 and Y17 are both connected to the drain of the transistor Y16. The drain of the transistor Y17 is connected to the first terminal of the capacitor Y2 as the output terminal of the charging current IY.

  The charging current IY increases as the input voltage Vin increases and decreases as the input voltage Vin decreases, as represented by the following equation (1).

  A first end of the capacitor Y2 is connected to the voltage / current converter Y1. The second end of the capacitor Y2 is connected to the ground terminal. When the transistor Y3 is off, the capacitor Y2 is charged by the charging current IY, and the first voltage VY1 appearing at the first end of the capacitor Y2 rises. On the other hand, when the transistor Y3 is on, the capacitor Y2 is discharged through the transistor Y3, and the first voltage VY1 decreases.

  The transistor Y3 is a charge / discharge switch that switches charging / discharging of the capacitor Y2 in accordance with on / off control of the transistors N1 and N2. The drain of the transistor Y3 is connected to the first end of the capacitor Y2. The source of the transistor Y3 is connected to the ground terminal. The gate of the transistor Y3 is connected to the application terminal of the inverted output signal S4B.

  The voltage / current conversion unit Y1, the capacitor Y2, and the transistor Y3 described above correspond to a first voltage generation circuit that generates the first voltage VY1 according to the charge / discharge operation of the capacitor Y2.

  The comparator Y4 compares the first voltage VY1 input to the non-inverting input terminal (+) and the second voltage VY2 input to the inverting input terminal (−) to generate the reset signal S3. The reset signal S3 is at a high level when the first voltage VY1 is higher than the second voltage VY2, and is at a low level when the first voltage VY1 is lower than the second voltage VY2. Considering that the charging operation of the capacitor Y2 is started simultaneously with the turning on of the transistor N1 and the transistor N1 is turned off with the rising edge of the reset signal S3 as a trigger, the on time Ton is calculated by the following equation (2) Is done.

  The level shifter Y5 operates in response to the supply of the input voltage Vin and performs level shift processing of the gate signal G1. More specifically, the level shifter Y5 receives the gate signal G1 and outputs a voltage signal that is pulse-driven between the input voltage Vin and the ground voltage GND. The withstand voltage of the element forming the level shifter Y5 may be set as appropriate according to the voltage difference between the input voltage Vin and the ground voltage GND.

  The selector Y6 is a circuit block that selects and outputs the level-shifted gate signal G1 when no backflow current is detected according to the backflow detection signal S5, and selectively outputs the switch voltage Vsw when a backflow current is detected. And Y62. Note that at the time of detecting the reverse current, the transistors N1 and N2 are both turned off by a power saving operation (reverse current cut-off operation) at a light load described later, so that the switch voltage Vsw matches the output voltage Vout.

  The switch Y61 conducts / cuts off between the output terminal of the level shifter Y5 and the input terminal of the filter Y7 in accordance with the backflow detection signal S5. More specifically, the switch Y61 is turned on when the backflow detection signal S5 is at a low level (logic level when no backflow is detected), and the backflow detection signal S5 is at a high level (logic level when backflow is detected). It turns off when there is.

  On the other hand, the switch Y62 conducts / cuts off between the external terminal T3 and the input end of the filter Y7 in accordance with the backflow detection signal S5. More specifically, the switch Y62 is turned off when the backflow detection signal S5 is at a low level, and is turned on when the backflow detection signal S5 is at a high level.

  Note that if the switch voltage Vsw is supplied to the comparator Y4 via the filter Y7, ringing noise superimposed on the switch voltage Vsw can be removed by the filter Y7. However, the configuration of the on-time setting circuit 16Y is not limited to this. For example, the switch voltage Vsw may be directly supplied to the inverting input terminal (−) of the comparator Y4 when detecting the reverse current.

  The filter Y7 is a circuit block that generates the second voltage VY2 by smoothing the output of the selector Y6, and includes resistors Y71 to Y73 and capacitors Y74 and Y75. The first end of the resistor Y71 is connected to the output end of the selector Y6. The second end of the resistor Y71 is connected to the first end of the resistor Y72 and the first end of the capacitor Y74. The second end of the capacitor Y74 is connected to the ground terminal. The second end of the resistor Y72 is connected to the inverting input terminal (−) of the comparator Y4, the first end of the resistor Y73, and the first end of the capacitor Y75. The second end of the resistor Y73 and the second end of the capacitor Y75 are both connected to the ground terminal.

  Thus, the filter Y7 includes a CR filter circuit composed of resistors Y71 and Y72 and capacitors Y74 and Y75. Note that the number of stages of the CR filter circuit (two stages in FIG. 4) can be arbitrarily increased or decreased.

  The filter Y7 includes a resistor Y73 that forms a voltage dividing circuit together with resistors Y71 and Y72 that form a CR filter circuit. 4 exemplifies a configuration in which the connection node between the resistor Y72 and the resistor Y73 is the output end of the filter Y7, the configuration of the filter Y7 is not limited to this. For example, the configuration of the resistor Y71 By providing the resistor Y73 between the first end and the ground end, a connection node between the resistor Y71 and the resistor Y73 may be used as the input end of the filter Y7.

  The level shifter Y5, the selector Y6, and the filter Y7 generate the second voltage VY2 corresponding to the on-duty of the transistor N1 when the reverse current is not detected, while the switch voltage Vsw (and thus the output) when the reverse current is detected This corresponds to a second voltage generation circuit that generates the second voltage VY2 corresponding to the voltage Vout).

  The operation of the on-time setting circuit 16Y having the above-described configuration will be described in detail separately for a case in which no backflow current is detected (in current continuous mode) and a time in which backflow current is detected (in current discontinuous mode).

  First, a detailed description will be given of the case where no backflow current is detected (in the continuous current mode). When the backflow current is not detected (in the continuous current mode), the backflow detection signal S5 is at a low level, so the selector Y6 selectively outputs the level-shifted gate signal G1 to the filter Y7. The second voltage VY2 generated at this time is expressed by the following equation (3). In Equation (3), DUTY indicates the duty of the switch voltage Vsw, and RON indicates the on-resistance value of the transistor N1.

  Therefore, the on-time Ton can be calculated by the following equation (4) by substituting the equations (1) and (3) into the above equation (2).

  That is, when the backflow current is not detected (in the continuous current mode), the on-time Ton is set as a variation value corresponding to the on-duty (= (Vout + Iout × RON) / Vin) of the transistor N1.

  Next, a detailed description will be given of the detection of the backflow current (in the current discontinuous mode). At the time of detecting the reverse current (in the current discontinuous mode), the reverse current detection signal S5 is at the high level, so the selector Y6 selectively outputs the switch voltage Vsw (and thus the output voltage Vout) to the filter Y7. Therefore, the second voltage VY2 becomes the switch voltage Vsw (and thus the output voltage Vout) itself, and the on-time Ton is calculated by the following equation (5).

  That is, when the backflow current is detected (in the light load mode), the on-time Ton is set as a variation value corresponding to the input voltage Vin and the output voltage Vout. Such an on-time Ton setting operation is the same as in the first configuration example.

  As described above, the on-time setting circuit 16Y of the second configuration example generates the second voltage VY2 corresponding to the on-duty of the transistor N1 when the backflow current is not detected, while the switch voltage Vsw is detected when the backflow current is detected. The second voltage VY <b> 2 is generated according to (and thus the output voltage Vout).

  By adopting such a configuration, the same advantages as the first configuration example (switching frequency fluctuation suppression, output voltage accuracy, etc.) without being affected by the power saving operation (backflow blocking operation) at light load. It is possible to enjoy improved load regulation characteristics or ease of EMI countermeasures and noise countermeasures in set design.

  The on-time setting circuit 16Y of the second configuration example sets the on-time Ton by monitoring the switch voltage Vsw. Therefore, unlike the first configuration example, it is not necessary to separately provide the semiconductor device 10 with the external terminal T6 for monitoring the output voltage Vout.

  In FIG. 4, the configuration in which the gate signal G1 is input to the level shifter Y5 is taken as an example. However, the configuration of the on-time setting circuit 16Y is not limited to this. For example, as shown in FIG. The switch voltage Vsw may be input to Y5.

<Backflow detection circuit>
FIG. 6 is a time chart for explaining the power saving operation (backflow cut-off operation) at the time of light load by the backflow detection circuit 18, and in order from the top, the gate signals G1 and G2, the backflow detection signal S5, the coil current IL, In addition, the switch voltage Vsw is depicted.

  From time t1 to t2, since the gate signal G1 is at a high level and the gate signal G2 is at a low level, the transistor N1 is turned on and the transistor N2 is turned off. Accordingly, at time t1 to t2, the switch voltage Vsw rises to substantially the input voltage Vin, and the coil current IL increases.

  At time t2, when the gate signal G1 falls to the low level and the gate signal G2 rises to the high level, the transistor N1 is turned off and the transistor N2 is turned on. Therefore, the switch voltage Vsw decreases to a negative voltage (= GND−IL × RON), and the coil current IL starts to decrease.

  Here, when the output current Iout flowing through the load is a sufficiently large load, the energy stored in the coil L1 is large, so that the coil current IL has a zero value until time t4 when the gate signal G1 is raised to the high level again. The switch voltage Vsw is maintained at a negative voltage while continuing to flow toward the load without falling below. On the other hand, at the time of light load when the output current Iout flowing through the load is small, the energy stored in the coil L1 is small. Therefore, at time t3, the coil current IL falls below a zero value, and a backflow current to the transistor N2 is generated. The polarity of the switch voltage Vsw switches from negative to positive. In such a state, the electric charge stored in the capacitor C1 is thrown away to the ground terminal, which causes a reduction in efficiency at light loads.

  Therefore, the switching power supply device 1 uses the reverse current detection circuit 18 to detect the reverse current to the transistor N2 (polarity inversion of the switch voltage Vsw), and during the high level period (time t3 to t4) of the reverse current detection signal S5. The transistor N2 is forcibly turned off. With such a configuration, the backflow current to the transistor N2 can be promptly interrupted, so that it is possible to eliminate a decrease in efficiency at light loads.

<Ripple injection circuit (feedback voltage side)>
FIG. 7 is a diagram illustrating a configuration example of the ripple injection circuit 11. The ripple injection circuit 11 of this configuration example includes current sources 111 and 112, a charge / discharge switch 113, a capacitor 114, a terminal voltage application unit 115, a discharge switch 116, and a discharge control unit 117.

  The current source 111 is a first current source that generates a first current I1 (= α × Vin, where α is a proportional constant) corresponding to the input voltage Vin. The first end of the current source 111 is connected to the power supply end. The second end of the current source 111 is connected to the first end of the capacitor 114 (the output end of the feedback voltage Vfb) via the charge / discharge changeover switch 113.

  The current source 112 is a second current source that generates a second current I2 (= α × Vout) corresponding to the output voltage Vout. A first end of the current source 112 is connected to a first end of the capacitor 114 (an output end of the feedback voltage Vfb). The second end of the current source 112 is connected to the ground end. In the step-down type (Vin> Vout) switching power supply device 1, when the current source 111 and the current source 112 have the same proportionality constant α, I1> I2. Further, the current source 112 may be configured to generate the second current I2 in accordance with a voltage corresponding to the on-duty of the transistor N1 (for example, the second voltage VY2 in FIG. 4).

  The charge / discharge switching switch 113 is turned on / off according to the gate signal G1, thereby conducting / blocking between the second end of the current source 111 and the first end of the capacitor (output end of the feedback voltage Vfb). . More specifically, the charge / discharge switch 113 is turned on during the high level period of the gate signal G1 (the on period of the transistor N1) and turned off during the low level period of the gate signal G1 (the off period of the transistor N1). .

  The first end of the capacitor 114 is connected to the output end of the feedback voltage Vfb. A second end of the capacitor 114 is connected to the terminal voltage application unit 115. During the on period of the charge / discharge switch 113 (the on period of the transistor N1), the differential current (= I1-I2> 0) obtained by subtracting the second current I2 from the first current I1 flows into the capacitor 114. Therefore, the capacitor 114 is charged (the voltage across the capacitor 114 increases). On the other hand, since the first current I1 is cut off during the off period of the charge / discharge switch 113 (the transistor N1 is off), the second current I2 is drawn from the capacitor 114, so that the capacitor 114 is discharged. (The voltage across the capacitor 114 is lowered).

  The terminal voltage application unit 115 is a circuit block that applies the terminal voltage (source voltage Vs in this figure) of the capacitor 114 so that the voltage across the capacitor 114 is added to the divided voltage Vdiv as the ripple voltage Vrpl. Source 115a and P-channel MOS field effect transistor 115b. The current source 115a is connected between the power supply terminal and the source of the transistor 115b, and generates a predetermined third current I3 (operation current of the transistor 115b). The gate of the transistor 115b is connected to the application terminal of the divided voltage Vdiv. The drain of the transistor 115b is connected to the ground terminal. The source of the transistor 115 b is connected to the second end of the capacitor 114. The terminal voltage application unit 115 configured as described above functions as a source follower that applies a source voltage Vs (= Vdiv + Vth) higher than the divided voltage Vdiv by the on-threshold voltage Vth of the transistor 115 b to the second end of the capacitor 114. Accordingly, the feedback voltage Vfb output from the first end of the capacitor 114 has a voltage value (= Vdiv + Vth + Vrpl) obtained by adding the ripple voltage Vrpl to the source voltage Vs applied to the second end.

  The discharge switch 116 is connected in parallel with the capacitor 114 and is controlled to be turned on / off according to the discharge control signal Sx input from the discharge control unit 117. More specifically, the discharge switch 116 is turned on when the discharge control signal Sx is at a high level, and is turned off when the discharge control signal Sx is at a low level. When the discharge switch 116 is turned on, both ends of the capacitor 114 are short-circuited, so that the capacitor 114 is rapidly discharged and the ripple voltage Vrpl is reset to a zero value.

  The discharge control unit 117 generates the discharge control signal Sx so that the discharge switch 116 is turned on every time before the capacitor 114 starts to be charged. That is, the ripple voltage Vrpl is reset every time before charging of the capacitor 114 starts.

  The ripple injection circuit 11 having the above configuration simulates the coil current IL by charging and discharging the capacitor 114 using the first current I1 proportional to the input voltage Vin and the second current I2 proportional to the output current Vout. A ripple voltage Vrpl is generated and added to the divided voltage Vdiv to generate a feedback voltage Vfb.

<Reference voltage generation circuit>
FIG. 8 is a diagram illustrating a configuration example of the reference voltage generation circuit 12. The reference voltage generation circuit 12 of this configuration example includes a P-channel MOS field effect transistor 121 and current sources 122 and 123.

  The current source 122 is connected between the power supply terminal and the source of the transistor 121, and generates a predetermined third current I3 (the operating current of the transistor 121, which is the same value as the operating current of the transistor 115b described above). Generate. The gate of the transistor 121 is connected to the application end of the reference voltage Vref0. The drain of the transistor 121 is connected to the ground terminal. The source of the transistor 121 is connected to the output terminal of the reference voltage Vref.

  The reference voltage generation circuit 12 of this configuration example functions as a source follower that outputs a reference voltage Vref (= Vref0 + Vth) that is higher than the reference voltage Vref0 by the on-threshold voltage Vth of the transistor 121. Thus, by making the reference voltage generation circuit 12 the same source follower type as the terminal voltage application unit 115, the on-threshold voltage Vth of the transistor 115b included in the feedback voltage Vfb can be canceled.

  Further, the reference voltage generation circuit 12 of this configuration example has a second current I2 (same as that of the ripple injection circuit 11) corresponding to the output voltage Vout or the second voltage VY2 between the output terminal of the reference voltage Vref and the ground terminal. A current source 123 for generating a value). By adopting such a configuration, it becomes possible to cancel the temperature dependency and power supply dependency of the current source 112 that affect the feedback voltage Vfb.

<Discharge Control Unit (First Configuration Example)>
FIG. 9 is a diagram illustrating a first configuration example of the discharge control unit 117. The discharge control unit 117 of the first configuration example includes a one-shot pulse generation unit 117a and an RS flip-flop 117b.

  The one-shot pulse generator 117a generates a one-shot pulse for the fall detection signal Sf using the falling edge of the gate signal G2 as a trigger.

  The RS flip-flop 117b sets the discharge control signal Sx to a high level at the rising edge of the fall detection signal Sf input to the set end (S), and at the rising edge of the gate signal G1 input to the reset end (R). The discharge control signal Sx is reset to a low level.

  That is, the discharge controller 117 of the first configuration example turns on the discharge switch 116 every time the transistor N2 is turned off. With such a configuration, it is possible to reset the ripple voltage Vrpl to a zero value every time before charging of the capacitor 114 starts.

  Further, the discharge control unit 117 of the first configuration example keeps the discharge switch 116 turned on until the transistor N1 is turned on after the transistor N2 is turned off. That is, the reset state of the ripple voltage Vrpl is maintained during the switching drive dead time (the transistors N1 and N2 are simultaneously turned off). With such a configuration, the discharge period of the capacitor 114 can be earned without unnecessarily extending the high-level period of the one-shot pulse generated in the fall detection signal Sf, so the ripple voltage Vrpl can be more reliably reduced. It becomes possible to reset to zero value. Further, according to this configuration, it is possible to maintain the reset state of the ripple voltage Vrpl even in the simultaneous off period of the transistors N1 and N2 due to the power saving operation (backflow cut-off operation) at light load.

<Discharge control unit (second configuration example)>
FIG. 10 is a diagram illustrating a second configuration example of the discharge control unit 117. In the second configuration example, an OR gate 117c is used instead of the RS flip-flop 117b in the first configuration example. The OR gate 117c outputs a logical sum signal of the fall detection signal Sf and the backflow detection signal S5 as the discharge control signal Sx. By adopting such a configuration, it is possible to realize substantially the same operation as in the first configuration example. However, when this configuration example is employed, it is desirable to set the high level period of the one-shot pulse generated in the fall detection signal Sf sufficiently long.

<Ripple injection operation>
FIG. 11 is a time chart showing an example of ripple injection operation (current continuous mode at steady load), in which the behaviors of the gate signals G1 and G2, the feedback voltage Vfb, and the switch voltage Vsw are depicted in order from the top. ing.

  At time t11, when the feedback voltage Vfb falls below the reference voltage Vref and the gate signal G2 falls to the low level, the discharge switch 116 is turned on and the capacitor 114 is discharged. As a result, the ripple voltage Vrpl is reset to a zero value, and thus the feedback voltage Vfb is lowered until it becomes the same value as the divided voltage Vdiv.

  When the gate signal G1 rises to a high level at time t12, charging of the capacitor 114 by the above-described differential current (I1-I2) is started. As a result, the ripple voltage Vrpl starts to increase, and accordingly, the feedback voltage Vfb also increases.

  When a predetermined on-time Ton elapses from time t12 and the gate signal G1 falls to the low level at time t13, the discharge of the capacitor 114 by the second current I2 described above is started. As a result, the ripple voltage Vrpl starts to decrease, and accordingly, the feedback voltage Vfb also decreases.

  After the gate signal G2 is raised to the high level at time t14, when the feedback voltage Vfb falls below the reference voltage Vref and the gate signal G2 is lowered to the low level at time t15, the discharge switch 116 is turned on. The capacitor 114 is discharged. This operation is exactly the same as time t11, and the series of operations are repeated after time t15.

  As described above, when the ripple injection circuit 11 of this configuration example is used, the ripple voltage Vrpl that is reset for each cycle of the switching drive is added to the feedback voltage Vfb without using discrete components externally attached to the power supply control IC 10. can do.

<Contrast of old and new output behavior during input fluctuations>
FIG. 12 is an old and new comparison diagram of output behavior at the time of input fluctuation. The column (A) shows the behavior when the ripple injection circuit 11 of FIG. 7 is used, and the column (B) shows the behavior when the ripple injection circuit RPL of FIG. 41 is used. Yes.

  When the ripple injection circuit RPL of FIG. 41 is used, the output voltage OUT varies following the midpoint voltage FVOUT of the feedback voltage FB (corresponding to 1/2 of the amplitude voltage of the pseudo ripple component). Further, the pseudo ripple component superimposed on the feedback voltage FB increases and decreases depending on the input voltage IN. Accordingly, the output voltage OUT also deviates from the target value Vtarget with dependence on the input voltage IN. In order to prevent such a decrease in output accuracy, it is necessary to perform complicated correction processing using an operational amplifier or the like. Further, since the pseudo ripple component generated using the resistor Ra and the capacitors Ca and Cb inevitably has a dull waveform, the crossing angle between the feedback voltage FB and the reference voltage REF becomes shallow, and the jitter characteristics deteriorate.

  On the other hand, when the ripple injection circuit 11 of FIG. 7 is used, the feedback voltage Vfb is a voltage obtained by simply adding the ripple voltage Vrpl to the divided voltage Vdiv, and therefore, the amount corresponding to the bottom value of the feedback voltage Vfb. Output feedback control is performed so that the voltage Vdiv matches the reference voltage Vref. That is, the output voltage Vout is always adjusted to the desired target value Vtarget without depending on the magnitude of the pseudo ripple component, so that no complicated correction processing is required. In addition, since the ripple voltage Vrpl generated using the first current I1 and the second current I2 is difficult to dull, the crossing angle between the feedback voltage Vfb and the reference voltage Vref becomes deep, and the jitter characteristics can be improved. It becomes possible.

<Contrast between old and new output behavior during load fluctuations>
FIG. 13 is an old and new comparison diagram of output behavior at the time of load fluctuation. When the ripple injection circuit RPL of FIG. 41 is used, the output voltage OUT decreases as the load is lighter (see the broken line in the figure). Therefore, depending on the setting of the target value Vtarget, there may occur a situation where the output voltage OUT is insufficient at a light load.

  On the other hand, when the ripple injection circuit 11 of FIG. 7 is used, the output voltage Vout is always adjusted to the desired target value Vtarget without depending on the load fluctuation. Absent.

<Contrast of transition behavior from light load to heavy load>
FIG. 14 is an old and new comparison diagram of transition behavior from a light load to a heavy load. The column (A) shows the behavior when the ripple injection circuit 11 of FIG. 7 is used, and the column (B) shows the behavior when the ripple injection circuit RPL of FIG. 41 is used. .

  When the ripple injection circuit RPL of FIG. 41 is used, the current continuous mode and the current discontinuous mode are irregularly repeated at the transition from the light load to the heavy load, so that the ripple component of the output voltage OUT increases and the waveform is disturbed. . For example, in the column (B) of FIG. 14, a relatively long current discontinuous mode (simultaneous off of the transistors N1 and N2 by backflow detection) is performed after pulse generation in the continuous current mode is performed for two or three consecutive cycles. The behavior that only one cycle occurs is repeated. Such a behavior occurs because a pseudo ripple component is superimposed on the feedback voltage FB and the feedback voltage FB does not accurately represent the output voltage OUT even at a light load that does not require a ripple injection operation.

  On the other hand, when the ripple injection circuit 11 of FIG. 7 is used, the ripple injection operation is automatically stopped because the ripple voltage Vrpl is reset to zero in the current discontinuous mode. As a result, the current continuous mode and the current discontinuous mode are not repeated irregularly during the transition from the light load to the heavy load. For example, in the column (A) of FIG. 14, a current discontinuous mode having a length of ½ to ３ is generated every cycle as compared with the current discontinuous mode in the column (B). That is, in the column (A) in FIG. 14, the current discontinuous mode in the column (B), which occurred once every two to three cycles, is uniformly dispersed in each cycle. Note that the current discontinuous mode in the column (A) becomes shorter as the load becomes heavier, and switches to the current continuous mode in every cycle when the load becomes heavier. Such an operation makes it possible to realize a smooth transition from a light load to a heavy load.

<Silent function>
FIG. 15 is a block diagram showing a second embodiment (one configuration example of the semiconductor device 10 having a noise reduction function) of the switching power supply device. The semiconductor device 10 of this configuration example includes a noise reduction circuit 19 in addition to the circuit blocks 11 to 18 illustrated in FIG. Therefore, with respect to the same configuration as the above, the same reference numerals as those in FIG. 1 are assigned to omit redundant description, and hereinafter, the configuration and operation of the silencer circuit 19 will be described mainly.

  The silencer circuit 19 is a circuit block for suppressing the generation of audible noise by keeping the switching frequency Fsw at light load above a human audible range (for example, 30 kHz), and monitors the gate signals G1 and G2. A silence signal S6 is generated. The silence signal S6 is basically generated when a predetermined threshold time Tth (for example, 33 μs) elapses without the next on-timing from the on-timing of the transistor N1 (rising edge of the gate signal G1). When the transistor N2 is turned off (falling edge of the gate signal G2), the signal becomes low.

  The one-shot pulse generation circuit 14 receives inputs of the comparison signal S1 and the silence signal S6, and generates a one-shot pulse in the set signal S2 using one rising edge as a trigger. Therefore, even if the comparison signal S1 does not rise to the high level, if the silence signal S6 rises to the high level, the output signal S4 is set to the high level, so that the transistor N1 is turned on. That is, the silence signal S6 functions as a forced on signal for ignoring the comparison signal S1 and forcibly turning on the transistor N1.

  By adopting such a configuration, the switching frequency Fsw at the time of light load can be kept above the human audible range without unnecessarily discharging the capacitor C1, so that the efficiency during silent operation is improved compared to the conventional case. It becomes possible to do.

  However, if the transistor N1 is forcibly turned on when the comparison signal S1 has not yet risen to the high level (the feedback voltage Vfb has not yet fallen below the reference voltage Vref), the output voltage Vout rises unnecessarily. There is a risk that.

  Therefore, the on-time setting circuit 16 receives the input of the silence signal S6, and when the transistor N1 is forcibly turned on by the silence circuit 19, the on-time Ton of the transistor N1 is shortened as the output voltage Vout is higher. Thus, it has a function of suppressing an increase in output voltage Vout.

  With such a configuration, the output voltage Vout can be stabilized at about +1 to 2% of the target value Vtarget, and can be controlled so as not to become an overvoltage state beyond that.

  FIG. 16 is a circuit diagram showing a configuration example of the silencer circuit 19 and a third configuration example of the on-time setting circuit 16. The noise reduction circuit 19 of this configuration example includes one-shot pulse generation units 191 and 192, a timer unit 193, an RS flip-flop 194, a comparator 195, and a NOR gate 196.

  The one-shot pulse generator 191 generates a one-shot pulse for the signal Sa using the rising edge of the gate signal G1 as a trigger.

  The one-shot pulse generator 192 generates a one-shot pulse for the signal Sc using the falling edge of the gate signal G2 as a trigger.

  Upon receiving the one-shot pulse of the signal Sa, the timer unit 193 starts a counting operation for the threshold time Tth, and generates a one-shot pulse for the signal Sb when the counting operation for the threshold time Tth is completed. That is, the timer unit 193 generates the signal Sb obtained by delaying the signal Sa by the threshold time Tth. However, the count operation of the threshold time Tth is reset every time a one-shot pulse of the signal Sa is input. Therefore, if the one-shot pulse generation interval of the signal Sa (corresponding to the switching period of the transistor N1) is shorter than the threshold time Tth, no one-shot pulse is generated in the signal Sb. Note that either an analog timer or a digital timer may be used as the timer unit 193.

  The RS flip-flop 194 sets the signal Sd (inverted output signal) to a low level at the rising edge of the signal Sb input to the set end (S), and at the rising edge of the signal Sc input to the reset end (R). The signal Sd is reset to high level. Therefore, the signal Sd becomes a low level when the threshold time Tth elapses without the next on-timing from the on-timing of the transistor N1 (rising edge of the gate signal G1), and the off-timing of the transistor N2 It becomes high level when (falling edge of the gate signal G2) arrives.

  The comparator 195 compares the divided voltage Vdiv input to the non-inverting input terminal (+) with the threshold voltage V1 (corresponding to the upper limit value of the output voltage Vout) input to the inverting input terminal (−) to generate the signal Se. Is generated. The signal Se is at a high level when the divided voltage Vdiv is higher than the threshold voltage V1, and is at a low level when the divided voltage Vdiv is lower than the threshold voltage V1.

  The NOR gate 196 generates the silence signal S6 by performing a negative OR operation on the signal Sd and the signal Se. The silence signal S6 is at a low level when at least one of the signals Sd and Se is at a high level, and is at a high level when both the signals Sd and Se are at a low level. That is, when the signal Se is at a low level (logic level when no overvoltage is detected), a logic inversion signal of the signal Sd is output as the silence signal S6. On the other hand, when the signal Se is at a high level (logic level when an overvoltage is detected), the silence signal S6 is fixed at a low level without depending on the logic level of the signal Sd. Therefore, while the divided voltage Vdiv exceeds the threshold voltage V1, the forced on operation of the transistor N1 is stopped.

  For example, in a complete no-load state (Iout = 0A), the output voltage Vout reaches an overvoltage state by repeating the forced on operation of the transistor N1, no matter how much the on time Ton of the transistor N1 is shortened, and the divided voltage Vdiv Exceeds the threshold voltage V1. In such a case, the signal Sd is masked by the high-level signal Se, and the forced on operation of the transistor N1 is stopped, so that the overvoltage state of the output voltage Vout can be eliminated.

  The silence signal S6 is input to the one-shot pulse generation circuit 14 together with the comparison signal S1. The one-shot pulse generation circuit 14 includes an OR gate 141 at its input stage, and generates a one-shot pulse for the set signal S2 using one of the rising edges of the comparison signal S1 and the silence signal S6 as a trigger. Configure it.

  The on-time setting circuit 16Z of the third configuration example is based on the on-time setting circuit 16X (see FIG. 2) of the first configuration example, and as a component of the second voltage generation circuit, in addition to the resistors X5 and X6, A current output amplifier Z1, N-channel MOS field effect transistors Z2 and Z3, a capacitor Z4, resistors Z5 and Z6, an inverter Z7, and switches Z8 and Z9 are newly included. Therefore, the same components as those in the first configuration example are denoted by the same reference numerals as those in FIG. 2, and redundant description is omitted. In the following description, the second voltage is centered on the newly added components Z1 to Z9. The generation circuit will be described in detail.

  A first end of the resistor X5 is connected to an external terminal T6 to which the output voltage Vout is applied. The second end of the resistor X5 is connected to the first end of the resistor X6. A second terminal of the resistor X6 is connected to the ground terminal. The resistors X5 and X6 connected in this manner function as a first resistor ladder that outputs a first divided voltage VX2a obtained by dividing the output voltage Vout from the connection node. Therefore, the higher the output voltage Vout, the higher the first divided voltage VX2a.

  The first end of the resistor Z5 is connected to the external terminal T6 to which the output voltage Vout is applied. The second end of the resistor Z5 is connected to the resistor Z6 and the first end of the capacitor Z4. The second ends of the resistor Z6 and the capacitor Z4 are both connected to the ground end. The resistors Z5 and Z6 connected in this way function as a second resistor ladder that outputs a second divided voltage VX2b obtained by dividing the output voltage Vout from the connection node.

  The current output amplifier Z1 (gm amplifier or transconductance amplifier) has a difference between the divided voltage Vdiv input to the non-inverting input terminal (+) and the reference voltage V2 (<V1) input to the inverting input terminal (−). An offset current IZ according to the above is generated. Therefore, the offset current IZ increases as the divided voltage Vdiv (and thus the output voltage Vout) increases.

  The drain of the transistor Z2 is connected to the output terminal of the current output amplifier Z1. The gates of the transistors Z2 and Z3 are both connected to the drain of the transistor Z2. The sources of the transistors Z2 and Z3 are both connected to the ground terminal. The drain of the transistor Z3 is connected to a connection node (the output terminal of the second divided voltage VX2b) between the resistor Z5 and the resistor Z6. The transistors Z2 and Z3 connected in this way cause the second divided voltage VX2b by a voltage drop (= IZ × Z5) at the resistor Z5 by causing the offset current IZ to flow through the resistor Z5 forming the second resistor ladder. It functions as a current mirror that pulls down. Accordingly, the second divided voltage VX2b is lowered as the offset current IZ increases (and as the output voltage Vout increases).

  The switch Z8 is connected between the application terminal of the first divided voltage VX2a and the inverting input terminal (application terminal of the second voltage VX2) of the comparator X4, and is an inverted silencing signal input via the inverter Z7. It is turned on / off in response to S6B (logically inverted signal of the silence signal S6). The switch Z8 is turned on when the silencer circuit 19 is not operating (S6B = H), and is turned off when the silencer circuit 19 is operated (S6B = L). On the other hand, the switch Z9 is connected between the application terminal of the second divided voltage VX2b and the inverting input terminal (application terminal of the second voltage VX2) of the comparator X4, and is turned on / off according to the silence signal S6. Is done. The switch Z9 is turned off when the silencer circuit 19 is not operating (S6 = L), and turned on when the silencer circuit 19 is operated (S6 = H). The inverter Z7 and the switches Z8 and Z9 thus connected select the first divided voltage VX2a as the second voltage VX2 when the silencer circuit 19 is not operating (S6 = L, S6B = H). During the operation of the silencer circuit 19 (S6 = H, S6B = L), it functions as a selector that selects the second divided voltage VX2b as the second voltage VX2.

  As described above, the second voltage generation circuit selectively outputs the first divided voltage VX2a when the silencer circuit 19 is not in operation (S6 = L, S6B = H), so that the first configuration example ( As shown in FIG. 2), the second voltage VX2 is generated. When the silencer circuit 19 is in operation (S6 = H, S6B = L), the second divided voltage VX2b is selectively output by As the output voltage Vout is higher, the second voltage VX2 is lowered.

  FIG. 17 is a time chart showing an example of the silent operation. In order from the top, the output signal S4, the gate signals G1 and G2, the switch voltage Vsw, the coil current IL, the signals Sa to Sd, the silenced signal S6, and the on-state. The internal voltages of the time setting circuit 16Z (the first voltage VX1, the second voltage VX2, the first divided voltage VX2a, and the second divided voltage VX2b) are depicted. Note that, as a precondition in this figure, both the comparison signal S1 and the signal Se are always at a low level.

  Prior to time t20, the gate signals G1 and G2 are both set to the low level by the power saving operation (backflow blocking operation) at the time of light load, and the transistors N1 and N2 are simultaneously turned off.

  At time t20, when a one-shot pulse is generated in the signal Sb and the signal Sd is set to a low level, the silence signal S6 rises to a high level. As a result, since a one-shot pulse is generated in the set signal S2 (not shown), the output signal S4 is set to a high level. Note that when the output signal S4 rises to a high level, the first voltage VX1 starts to rise. Further, when the silence signal S6 rises to a high level, the second voltage VX2 is switched from the first divided voltage VX2a to the second divided voltage VX2b.

  When a predetermined simultaneous OFF time Td elapses from time t20, the gate signal G1 rises to a high level at time t21. As a result, since the transistor N1 is turned on, the switch voltage Vsw rises to almost the input voltage Vin, and the coil current IL starts to increase. At this time, the second voltage VX2 (= VX2b) decreases as the output voltage Vout (not shown) increases. Further, when the gate signal G1 rises to a high level, a one-shot pulse is generated in the signal Sa, so that the counting operation of the threshold time Tth is started.

  At time t22, when the first voltage VX1 becomes higher than the second voltage VX2 (= VX2b), the reset signal S3 (not shown) rises to a high level, so that the output signal S4 is reset to a low level and the gate signal G1 Falls to a low level. As a result, since the transistors N1 and N2 are simultaneously turned off, the switch voltage Vsw decreases to a negative voltage (= GND−Vf, where Vf is a forward voltage drop of a parasitic diode associated with the transistor N2), and the coil current IL starts to decrease.

  Note that the times t21 to t22 correspond to the on-time Ton of the transistor N1. As described above, the higher the output voltage Vout, the lower the second voltage VX2 (= VX2b), and the crossing timing between the first voltage VX1 and the second voltage VX2 (= VX2b) is advanced. That is, the higher the output voltage Vout, the shorter the on time Ton of the transistor N1. Accordingly, it is possible to appropriately suppress an increase in the output voltage Vout accompanying the forced on operation of the transistor N1.

  When a predetermined simultaneous OFF time Td elapses from time t22, the gate signal G2 rises to a high level at time t23. As a result, since the transistor N2 is turned on, the switching output stage 20 is switched from the diode rectification operation to the synchronous rectification operation, and the switch voltage Vsw rises to almost 0 V (= GND−IL × RON).

  At time t24, when the coil current IL falls below the zero value, a backflow current to the transistor N2 occurs, and the polarity of the switch voltage Vsw switches from negative to positive, the backflow detection signal S5 (not shown) rises to a high level. The gate signal G2 falls to the low level. As a result, the transistors N1 and N2 are turned off at the same time, so that the switch voltage Vsw settles to the output voltage Vout through the resonance state. Further, when the gate signal G2 falls to the low level, a one-shot pulse is generated in the signal Sc, so that the signal Sd is reset to the high level, and the silence signal S6 falls to the low level. As a result, the second voltage VX2 is switched from the second divided voltage VX2b to the first divided voltage VX2a.

  Thereafter, when the count operation of the threshold time Tth is completed without the high level timing of the gate signal G1 coming, a one-shot pulse is generated in the signal Sb at time t25. This situation is similar to the previous time t20, and the silent operation described above is repeated as long as the light load state continues after time t25.

  According to the silent operation described above, the switching frequency Fsw at light load can be kept above the human audible range while maintaining the output voltage Vout near the target value Vtarget without unnecessarily discharging the capacitor C1. Therefore, it is possible to improve the efficiency during the silent operation as compared with the conventional case. Further, unlike the conventional method in which the transistor N2 is forcibly turned on, the transistor N1 is not continuously turned on over a plurality of periods, so that further improvement in efficiency can be expected.

  FIG. 18 is a time chart showing an example of the silent operation when the load is gradually increased. From the top, the first voltage VX1 and the second divided voltage VX2b, the switch voltage Vsw, the coil current IL, and the output voltage Vout are depicted. Has been. FIGS. 19 and 20 are enlarged views of broken line areas α and β in FIG. 18, respectively.

  At a light load with a small output current Iout, the second divided voltage VX2b is greatly reduced to reduce the on-time Ton in order to suppress an increase in the output voltage Vout. On the other hand, as the output current Iout increases and the increase amount of the output voltage Vout decreases, the decrease amount of the second divided voltage VX2b also decreases, and the on-time Ton approaches the normal length.

  It should be noted that the timing at which the switching period of the transistor N1 becomes shorter than the threshold time Tth as the output current Iout increases (the timing at which the main comparator 13 starts to react normally), and the overvoltage state of the output voltage Vout is relaxed and turned on. As for the timing at which the time Ton returns to the normal state (the timing at which the lowering of the second divided voltage VX2b is finished), it is desirable that both are the same or the latter is earlier.

  FIG. 21 is a time chart showing an example of canceling the stop of the silent operation, in which the output current Iout, the output voltage Vout, the switching frequency Fsw, and the switch voltage Vsw are depicted in order from the top.

  As described above, for example, in a complete no-load state (Iout = 0A), the output voltage Vout becomes an overvoltage by repeating the forced on operation of the transistor N1 even if the on time Ton of the transistor N1 is shortened. Since this state is reached, the signal Se (not shown) generated by the comparator 195 rises to a high level, and the above-described silent operation (forced ON operation of the transistor N1) is stopped.

  However, when the output current Iout begins to increase and the overvoltage state of the output voltage Vout is resolved, the silent operation stop state is released without delay, and the switching frequency Fsw is maintained above the human audible range.

<Overshoot during sudden load reduction>
FIG. 22 is a time chart for explaining the principle that an overshoot of the output voltage Vout occurs when the load suddenly decreases (for example, −7 A@2.5 A / μs), and in order from the top, the comparison signal S1 and the feedback voltage Vfb , Source voltage Vs, reference voltage Vref, output voltage Vout, switch voltage Vsw, output current Iout, and coil current IL are depicted.

  When the output current Iout decreases rapidly, the output voltage Vout increases due to the excessive coil current IL. In particular, when the ripple injection circuit 11 of FIG. 7 is employed, overshoot of the output voltage Vout may be promoted due to the ripple generation operation. The reason will be described below with reference to FIG. 7 as appropriate.

  During steady load, the off period Toff of the transistor N1 (the low level period of the gate signal G1) is sufficiently short, so that the discharging operation of the capacitor 114 by the second current I2 is not continued until the ripple voltage Vrpl becomes negative. . Therefore, after the transistor N1 is turned on and the ripple voltage Vrpl is reset to the zero value, the ripple voltage Vrpl is always maintained positive until the transistor N1 is turned on again in the next cycle, so that the feedback voltage Vfb Is always kept higher than the source voltage Vs (corresponding to the divided voltage Vdiv before the ripple injection).

  On the other hand, when the load suddenly decreases, the off period Toff of the transistor N1 becomes longer, and thus the discharging operation of the capacitor 114 by the second current I2 may be continued until the ripple voltage Vrpl becomes negative. In such a situation, since the feedback voltage Vfb becomes lower than the source voltage Vs, the feedback voltage Vfb falls below the reference voltage Vref at a timing earlier than the original, and the comparison signal S1 rises to a high level. As a result, the transistor N1 is turned on unnecessarily (see the broken-line ellipse in the figure), and energy is recharged in the coil L1, so that overshoot of the output voltage Vout is promoted.

<Overshoot suppression circuit>
FIG. 23 is a diagram illustrating a configuration example of the overshoot suppression circuit 30. The overshoot suppressing circuit 30 of this configuration example includes a cross comparator 31 and monitors the polarity inversion timing (positive / negative inversion timing) of the ripple voltage Vrpl to suppress overshoot of the output voltage Vout.

  The cross comparator 31 has a feedback voltage Vfb (corresponding to the positive voltage of the capacitor 114) input to the inverting input terminal (−) and a source voltage Vs (corresponding to the negative voltage of the capacitor 114) input to the non-inverting input terminal (+). The polarity inversion detection signal S30 is generated. The polarity inversion detection signal S30 is at a low level when the feedback voltage Vfb is higher than the source voltage Vs, and is at a high level when the feedback voltage Vfb is lower than the source voltage Vs. That is, the polarity reversal detection signal S30 is at a low level when the ripple voltage Vrpl is positive, and is at a high level when the ripple voltage Vrpl is negative.

  As described above, the overshoot suppression circuit 30 of this configuration example has the ripple voltage Vrpl switched from positive to negative when the switching period of the transistor N1 does not expire before the polarity inversion timing of the ripple voltage Vrpl arrives. When the ON timing of the transistor N1 in the next cycle has not arrived at the time, the polarity inversion detection signal S30 is raised to a high level in order to activate the overshoot suppression function.

  Discharge control unit 117 further includes an OR gate 117d in addition to the components shown in FIG. The OR gate 117d generates a logical sum signal Sf2 of the fall detection signal Sf input from the one-shot pulse generation unit 117a and the polarity inversion detection signal S30 input from the overshoot suppression circuit 30, and the RS flip-flop 117 Output to the set end (S).

  The logical sum signal Sf2 is high when at least one of the fall detection signal Sf and the polarity inversion detection signal S30 is at a high level, and low when both the fall detection signal Sf and the polarity inversion detection signal S30 are at a low level. Become a level.

  Therefore, when the load is suddenly decreased, the discharging operation of the capacitor 114 continues, and the ripple voltage Vrpl is switched from positive to negative, and when the polarity inversion detection signal S30 rises to a high level, the logical sum signal Sf2 rises to a high level. As a result, the discharge control signal Sx is set to the high level without waiting for the one-shot pulse of the fall detection signal Sf, so that the discharge switch 116 is turned on and the ripple voltage Vrpl is reset.

  As described above, the discharge control unit 117 receives the input of the polarity inversion detection signal S30, and turns on the discharge switch 116 not only when the transistor N2 is turned off but also when the ripple voltage Vrpl is switched from positive to negative. The ripple voltage Vrpl is reset to zero.

  By adopting the above configuration, the ripple voltage Vrpl does not become negative even when the load is suddenly reduced, so that the feedback voltage Vfb does not fall below the reference voltage Vref at an earlier timing than the original. Accordingly, since the transistor N1 is not turned on unnecessarily, it is possible to suppress overshoot of the output voltage Vout, and thus, further reduction in the capacitance of the capacitor C1 can be realized.

  Note that in order to accurately detect the polarity inversion timing of the ripple voltage Vrpl, it is desirable to reduce the offset of the cross comparator 31 by trimming. In addition, an analog switch used in a switched capacitor or the like should be used as the switch 116 for short-circuiting both ends of the capacitor 114 so that spike noise generated when the ripple voltage Vrpl is reset is not superimposed on the feedback voltage Vfb. Is desirable.

  FIG. 24 is a time chart for specifically explaining the first overshoot suppression operation (reset operation of the ripple voltage Vrpl). In order from the top, the comparison signal S1, the polarity inversion detection signal S30, the feedback voltage Vfb, Source voltage Vs, reference voltage Vref, output voltage Vout, switch voltage Vsw, output current Iout, and coil current IL are depicted.

  As described above, when the output current Iout rapidly decreases, the output voltage Vout increases due to the surplus coil current IL, so that the source voltage Vs (corresponding to the divided voltage Vdiv before ripple injection) is the reference voltage. It becomes higher than Vref.

  Therefore, when the discharging operation of the capacitor 114 by the second current I2 continues when the load is suddenly reduced, the feedback voltage Vfb is lower than the source voltage Vs before being lower than the reference voltage Vref (see the small circle mark in the figure). At this time, since the polarity inversion detection signal S30 generated by the cross comparator 31 rises to a high level, both ends of the capacitor 114 are short-circuited so that the feedback voltage Vfb and the source voltage Vs are matched.

  As a result, since the timing when the feedback voltage Vfb falls below the reference voltage Vref can be delayed, the transistor N1 can be prevented from being turned on unnecessarily, and the overshoot of the output voltage Vout can be suppressed.

  FIG. 25 is a diagram illustrating a configuration example of the backflow detection circuit 18. The backflow detection circuit 18 of this configuration example includes a comparator 181, an AND gate 182, an RS flip-flop 183, and an OR gate 184.

  The comparator 181 compares the switch voltage Vsw input to the non-inverting input terminal (+) with the threshold voltage VZ (for example, −0.001 V) input to the inverting input terminal (−), and generates the zero-cross detection signal SA. Generate. The zero-cross detection signal SA is at a low level when the switch voltage Vsw is lower than the threshold voltage VZ, and is at a high level when the switch voltage Vsw is higher than the threshold voltage VZ. That is, the zero cross detection signal SA becomes low level when the coil current IL is flowing in the positive direction (the direction from the ground terminal to the coil L1 via the transistor N2), and the coil current IL is in the negative direction (from the coil L1 to the transistor). It goes high when the current flows in the direction toward the ground terminal via N2 (that is, when a backflow current flows in the transistor N2).

  The AND gate 182 generates a logical product signal SB of the zero cross detection signal SA and the gate signal G2, and outputs the logical product signal SB to the set end (S) of the RS flip-flop 183. The logical product signal SB becomes low level when either the zero cross detection signal SA or the gate signal G2 is low level, and becomes high level when both the zero cross detection signal SA and the gate signal G2 are high level. . That is, the zero cross detection signal SA is valid only during the high level period of the gate signal G2 (the on period of the transistor N2), and the zero cross detection signal SA is invalid during the low level period of the gate signal G2 (the off period of the transistor N2). Is done.

  The RS flip-flop 183 sets the backflow detection signal SC (corresponding to the backflow detection signal S5 in FIG. 1) to a high level at the rising edge of the logical product signal SB input to the set end (S), and the reset end (R). The backflow detection signal SC is reset to a low level at the rising edge of the gate signal G1 input to. That is, the backflow detection signal SC is latched at a high level (logic level at the time of backflow detection) when a backflow current is detected during the ON period of the transistor N2, and at a low level (backflow) at the ON timing of the transistor N1 in the next cycle. (Logic level when not detected).

  The OR gate 184 generates a synchronous rectification stop signal S5 ′ by performing a logical sum operation between the backflow detection signal SC input from the RS flip-flop 183 and the polarity inversion detection signal S30 input from the overshoot suppression circuit 30. To do. The synchronous rectification stop signal S5 ′ is at a high level when at least one of the backflow detection signal SC and the polarity inversion detection signal S30 is at a high level, and when both the backflow detection signal S5 and the polarity inversion detection signal S30 are at a low level. It becomes low level.

  The gate driver circuit 17 accepts the input of the synchronous rectification stop signal S5 ′ instead of the preceding backflow detection signal S5. When the synchronous rectification stop signal S5 ′ is at the high level, the transistor does not depend on the output signal S4. A gate signal G2 is generated so as to forcibly turn off N2. That is, the gate driver circuit 17 forcibly turns off the transistor N2 not only when the backflow current to the transistor N2 is detected but also when the ripple voltage Vrpl switches from positive to negative when the load suddenly decreases.

  FIG. 26 is a time chart for specifically explaining the second overshoot suppression operation (forced off operation of the transistor N2). In order from the top, the comparison signal S1, the polarity inversion detection signal S30, the feedback voltage Vfb, Source voltage Vs, reference voltage Vref, output voltage Vout, switch voltage Vsw, output current Iout, and coil current IL are depicted.

  As a result of the sudden decrease in the load current Iout, when the polarity inversion detection signal S30 rises to a high level at time t30, the transistor N2 is forcibly turned off, so that the transistors N1 and N2 are simultaneously turned off. That is, when the load suddenly decreases, the switching power supply device 1 is switched from the synchronous rectification state to the diode rectification state, and the switch voltage Vsw is reduced to a negative value.

  As a result, after time t30, the voltage applied to both ends of the coil L1 increases and the consumption of the coil current IL can be promoted, so that overshoot of the output voltage Vout can be suppressed.

<Sleep function>
FIG. 27 is a block diagram showing a third embodiment (one configuration example of the semiconductor device 10 having a sleep function) of the switching power supply device. The semiconductor device 10 of this configuration example includes an external terminal T8 for receiving an external input of the mode switching signal S7 in addition to the external terminals T1 to T7 shown in FIG. Therefore, with respect to the same configuration as above, the same reference numerals as those in FIG. 1 are assigned to omit redundant description, and the sleep function will be mainly described below.

  The semiconductor device 10 is externally input with a mode switching signal S7 for switching the operation mode of the sleep target circuit (in the example of this figure, the on-time setting circuit 16 and the backflow detection circuit 18). For example, when the mode switching signal S7 is at a low level, the sleep target circuit is switched to the normal mode. On the other hand, when the mode switching signal S7 is at a high level, the sleep target circuit has a more power saving sleep mode (an operation mode in which power consumption of the semiconductor device 10 is reduced by supplying power only to the minimum necessary circuit blocks). Can be switched to.

  The mode switching signal S7 is input to the on-time setting circuit 16 and the backflow detection circuit 18. When the mode switching signal S7 is at a low level, the on-time setting circuit 16 and the backflow detection circuit 18 are always turned on in order to give priority to improving the stability of the output feedback control. On the other hand, when the mode switching signal S7 is at a high level, the on-time setting circuit 16 and the backflow detection circuit 18 are on / off controlled as necessary in order to prioritize the improvement in efficiency at light load.

  FIG. 28 is a time chart showing the sleep operation (operation when the mode switching signal S7 is at a high level) of the on-time setting circuit 16 and the backflow detection circuit 18, and in order from the top, the feedback voltage Vfb, the reference voltage Vref, The set signal S2, the reset signal S3, the gate signals G1 and G2, the coil current IL, the switch voltage Vsw, the backflow detection signal S5, and the on / off states of the on-time setting circuit 16 and the backflow detection circuit 18 are depicted.

  At time t41, when the feedback voltage Vfb falls below the reference voltage Vref and a one-shot pulse is generated in the set signal S2, the gate signal G1 is raised to a high level and the transistor N1 is turned on. On the other hand, from time t41 to t42, the gate signal G2 is maintained at the low level, and the transistor N2 remains off. As a result, at times t41 to t42, the switch voltage Vsw rises substantially to the input voltage Vin, and the coil current IL increases.

  At time t41, the on-time setting circuit 16 and the backflow detection circuit 18 are turned on, triggered by the one-shot pulse of the set signal S2 (or the rising edge of the comparison signal S1). Therefore, the on-time setting circuit 16 can start measuring the on-time Ton immediately after the transistor N1 is turned on.

  At time t42, when the on-time setting circuit 16 counts the on-time Ton and a one-shot pulse is generated in the reset signal S3, the gate signal G1 falls to the low level and the gate signal G2 goes to the high level. Launched. As a result, the transistor N1 is turned off and the transistor N2 is turned on. At this time, an induced electric power is generated in the coil L1 so as to keep the coil current IL flowing in the same direction as before, so that the coil current IL flows into the coil L1 from the ground terminal via the transistor N2. Therefore, the switch voltage Vsw drops to a negative voltage value that is lower than the ground voltage GND by a voltage drop at the transistor N2.

  In FIG. 28, the on / off transition timings of the transistors N1 and N2 are completely the same. However, from the viewpoint of preventing through current, the transistors N1 and N2 are delayed by delaying the on / off transition timings of the transistors N1 and N2. N2 simultaneous off periods may be provided.

  Further, the on-time setting circuit 16 is turned off without delay when the counting of the on-time Ton is completed. More specifically, the on-time setting circuit 16 generates a one-shot pulse for the reset signal S3 and then shuts off the power supply path to itself. By performing such on / off control, it is possible to reduce the power consumption of the on-time setting circuit 16 and improve the efficiency at light load.

  Here, at the time of heavy load when the output current Iout flowing through the load is large, the energy stored in the coil L1 is large, so that the coil current IL is below the zero value until time t44 when the gate signal G1 is raised to the high level again. The switch voltage Vsw is kept at a negative voltage value while continuing to flow toward the load. On the other hand, when the output current Iout flowing through the load is small and the load is small, the energy stored in the coil L1 is small. Therefore, at time t43, the coil current IL falls below the zero value, and a reverse current flows to the transistor N2. The polarity of the voltage Vsw switches from negative to positive. In such a state, the electric charge stored in the capacitor C1 is thrown away to the ground terminal, which causes a reduction in efficiency at light loads.

  Therefore, the semiconductor device 10 generates a backflow detection signal S5 according to the presence or absence of a backflow current (polarity inversion of the switch voltage Vsw) using the backflow detection circuit 18, and the transistor N2 is forcibly turned off. With such a configuration, the backflow current to the transistor N2 can be promptly interrupted, so that it is possible to eliminate a decrease in efficiency at light loads.

  The backflow detection circuit 18 is turned off without delay when the backflow detection operation is completed. More specifically, the backflow detection circuit 18 cuts off the power supply path to itself after raising the backflow detection signal S5 to a high level. By performing such on / off control, it is possible to reduce the power consumption of the backflow detection circuit 16 and improve the efficiency at light load.

  After time t45, similarly to the above, switching stop processing at the time of backflow detection and on / off control of the on-time setting circuit 16 and the backflow detection circuit 18 are repeated. That is, the semiconductor device 10 in the sleep mode stops the switching operation of the transistors N1 and N2 while the output voltage Vout exceeds the reference voltage Vref, and then turns off the circuit blocks other than the main comparator 13 to Reduce current consumption as much as possible. Thereafter, when the main comparator 13 detects a decrease in the output voltage Vout, the circuit block that has been turned off is restored and the switching operation of the transistors N1 and N2 is resumed. With such a configuration, the average current consumption of the semiconductor device 10 can be reduced, so that it is possible to improve the efficiency at light loads.

<Overcurrent protection circuit>
Next, an overcurrent protection circuit having a sleep function will be described. FIG. 29 is a diagram illustrating a configuration example of an overcurrent protection circuit. The overcurrent protection circuit 40 of this configuration example includes a D flip-flop 41 and an overcurrent protection unit 42.

  The D flip-flop 41 uses the rising edge of the output signal S4 input to the clock end as a trigger to latch the backflow detection signal S5 input to the data end (D), and sleeps the latch output from the output end (Q). Output as signal SLP.

  The overcurrent protection unit 42 monitors the output current Iout flowing through the load, the coil current IL flowing through the coil L1, or the switch current flowing through the transistors N1 and N2, and generates an overcurrent protection signal S8. The overcurrent protection signal S8 is at a high level when the monitoring target current is larger than the threshold (when overcurrent is detected), and is at a low level when the monitoring target current is smaller than the threshold (when no overcurrent is detected).

  The overcurrent protection unit 42 is turned on / off according to the sleep signal SLP. More specifically, when the sleep signal SLP is at a high level, the overcurrent protection unit 42 is turned off, and the amount of drive current consumed is reduced. On the other hand, when the sleep signal SLP is at a low level, the overcurrent protection unit 42 is turned on and the overcurrent protection function is validated.

  The gate driver circuit 17 receives the input of the overcurrent protection signal S8, and when the overcurrent protection signal S8 is at a high level, the switching operation of the transistors N1 and N2 is forcibly stopped as the overcurrent protection operation.

  FIG. 30 is a time chart showing the sleep operation of the overcurrent protection circuit 40. In order from the top, the switch voltage Vsw, the output voltage Vout, the coil current IL, the output current Iout, the backflow detection signal S5, the sleep signal SLP, and An overcurrent protection signal S8 is depicted.

  At the time of a light load with a small output current Iout (before time t52), sufficient energy is not stored in the coil L1 even if the transistor N1 is turned on, so the coil current IL falls below the zero value every time (time t51). See). Therefore, the backflow detection signal S5 becomes high before the latch timing in the D flip-flop 41 at a light load unless an abnormality (such as a load short-circuit) that causes an overcurrent occurs. Always maintained at a high level. As a result, at the time of light load, the overcurrent protection unit 42 is basically turned off, and the amount of drive current consumed is reduced.

  The state in which the sleep signal SLP is at the high level, that is, the state in which the output current Iout is small and the necessity for the overcurrent protection operation is poor, so the overcurrent protection unit 42 is turned off. However, the safety of the switching power supply device 1 is not impaired.

  On the other hand, when the output current Iout increases (return from the sleep mode to the normal mode or the occurrence of an overcurrent due to a load short-circuit) at time t52, the coil current IL does not fall below the zero value, and the reverse current is detected. Since the signal S5 does not rise to the high level, the sleep signal SLP falls to the low level.

  A specific description will be given with reference to the example of FIG. At the latch timing (time t53) of the D flip-flop 41 that first arrives after the output current Iout suddenly increases at time t52, the backflow detection signal S5 is generated as the backflow current is detected in the immediately preceding switching cycle. Since it is at the high level, the sleep signal SLP latched is also kept at the high level.

  On the other hand, after the backflow detection signal S5 is reset to the low level at time t53, the coil current IL is no longer below the zero value at the second latch timing (time t54) that comes next, and the backflow detection signal S6 is Since it is maintained at the low level, the sleep signal SLP that latches it falls from the high level to the low level. As a result, the overcurrent protection unit 42 is turned on and the overcurrent protection operation is performed, so that an increase in the output current Iout can be suppressed.

  Even if the output current Iout increases rapidly, it takes a certain time until the coil L1 is charged with energy. Therefore, if the overcurrent protection unit 42 can be restored at the above timing, a sufficiently effective overcurrent protection operation can be performed.

  In the above description, the sleep release operation associated with the increase in the output current Iout has been described as an example. On the contrary, the sleep transition operation associated with the decrease in the output current Iout also follows the above description. Can be understood. That is, when the load becomes light and the coil current IL transitions from the continuous mode to the discontinuous mode, the sleep signal SLP rises from the low level to the high level at the second latch timing that arrives after the transition to the discontinuous mode. The protection unit 42 is turned off.

  As described above, the overcurrent protection circuit 40 of this configuration example latches the backflow detection signal S5 (backflow current detection result) at each switching period, and the overcurrent protection unit according to the sleep signal SLP that is the latch output. 40 on / off control is performed. More specifically, the overcurrent protection circuit 40 is turned off in response to the fact that a reverse current has been detected in the immediately preceding switching cycle, and is turned on in response to the fact that no reverse current has been detected in the immediately preceding switching cycle. It becomes.

  By adopting such a configuration, the overcurrent protection circuit 40 can be turned on / off depending on whether the current continuous mode or the current discontinuous mode is selected, thereby impairing the effectiveness of the overcurrent protection function. Therefore, it is possible to achieve high efficiency at light loads.

  Further, as with the previous on-time setting circuit 16 and the backflow detection circuit 18, the overcurrent protection circuit 40 can be included as a sleep target circuit that receives the input of the mode switching signal S7. In this case, for example, when the mode switching signal S7 is at the low level, the overcurrent protection circuit 40 is always turned on, and when the mode switching signal S7 is at the high level, the overcurrent protection circuit 40 is set to the reverse current detection signal. The on / off control may be performed in accordance with S5.

<Mode switching control circuit>
FIG. 31 is a diagram illustrating a configuration example of the semiconductor device 10 including the mode switching control circuit 60 (and its peripheral circuits). The semiconductor device 10 of this configuration example includes a sleep target circuit 50, a mode switching control circuit 60, a sleep non-target circuit 70, and a noise mask circuit 80.

  The sleep target circuit 50 is a circuit block whose operation mode is switched between the normal mode and the sleep mode in accordance with the mode switching signal S7. In the semiconductor device 10 of this configuration example, the main circuit 13 and the bias current generation circuit 51 are included in the sleep target circuit 50 in addition to the on-time setting circuit 16 and the backflow detection circuit 18 described above. For example, the main comparator 13 enters a sleep mode when the mode switching signal S7 is at a high level, and its drive current is zero (or almost zero).

  The mode switching control circuit 60 controls the output mask of the main comparator 13 and the switching control of the output feedback loop when the operation mode is switched (from the normal mode to the sleep mode or when the sleep mode returns to the normal mode). And includes D flip-flops 61 and 62, an OR gate 63, inverters 64 and 65, an AND gate 66, and an OR gate 67.

  The D flip-flop 61 uses the falling edge of the gate signal G2 input to the inverted clock terminal as a trigger to latch the mode switching signal S7 input to the data terminal (D), and outputs the latch output to the output terminal (Q). To the first latch signal S61.

  The D flip-flop 62 uses the falling edge of the gate signal G2 input to the inverted clock terminal as a trigger to latch the first latch signal S61 input to the data terminal (D), and outputs the latch output to the output terminal (Q To the second latch signal S62.

  Therefore, when the logic level of the mode switching signal S7 is switched, the logic level of the second latch signal S62 is switched when the falling edge of the gate signal G2 arrives twice thereafter. In the mode switching control circuit 60 of this configuration example, two stages of D flip-flops 61 and 62 are used. However, the number of D flip-flops may be one, or three or more. Also good.

  The OR gate 63 generates a logical sum signal S63 of the mode switching signal S7 and the second latch signal S62. The logical sum signal S63 is at a high level when at least one of the mode switching signal S7 and the second latch signal S62 is at a high level, and is at a low level when both the mode switching signal S7 and the second latch signal S62 are at a low level. Become a level. Therefore, the rising timing of the logical sum signal S63 coincides with the rising timing of the mode switching signal S7, but the falling timing of the logical sum signal S63 is not the falling timing of the mode switching signal S7 but the second latch signal S62. Is delayed until the fall timing of.

  The inverter 64 generates the output gate signal S64 by logically inverting the logical sum signal S63.

  The inverter 65 generates a noise mask control signal S65 by logically inverting the logical sum signal S63.

  The AND gate 66 generates a logical product signal S66 of the comparison signal S1 and the output gate signal S64. The output gate signal S66 becomes a low level when at least one of the comparison signal S1 and the output gate signal S64 is at a low level, and becomes a high level when both the comparison signal S1 and the output gate signal S64 are at a high level. Therefore, when the output gate signal S64 is at a high level, the comparison signal S1 is through-output as the logical product signal S66. However, when the output gate signal S64 is at a low level, it does not depend on the logical level of the comparison signal S1. The logical product signal S66 is fixed at a low level. That is, when the output gate signal S64 is at a low level, the output mask of the main comparator 13 is performed.

  The OR gate 67 generates a logical sum signal S67 of the logical product signal S66 and the sub comparison signal S71. The logical sum signal S67 is at a high level when at least one of the logical product signal S66 and the sub comparison signal S71 is at a high level, and is at a low level when both the logical product signal S66 and the sub comparison signal S71 are at a low level. Become. That is, when the output of the main comparator 13 is masked (S66 = L fixed), the sub comparison signal S71 is output through as the logical product signal S67.

  The mode switching control circuit 60 having the above configuration masks the output of the sleep target circuit 50 without delay when shifting from the normal mode to the sleep mode (S7 = L → H), and returns from the sleep mode to the normal mode. At the time (S7 = H → L), the output mask of the sleep target circuit 50 is canceled with a predetermined delay. At that time, the mode switching control circuit 60 latches the mode switching signal S7 at the falling edge of the gate signal G2 (off timing of the transistor N2), and cancels the output mask of the sleep target circuit 50 using the latch output.

  The sleep-excluded circuit 70 is a circuit block that always operates by receiving a supply of drive current without depending on the mode switching signal S7, and includes a sub-comparator 71 and switches 72 and 73. Although not explicitly shown in this figure, among the circuit blocks forming the output feedback loop, the reference voltage generation circuit 12, the one-shot pulse generation circuit 14, the RS flip-flop 15, the gate driver circuit 17, and the like also sleep. It is included in the non-target circuit 70.

  The sub-comparator 71 compares the divided voltage Vdiv before ripple injection input to the inverting input terminal (−) with the reference voltage Vref1 or Vref2 input to the non-inverting input terminal (+) to generate the sub comparison signal S71. Generate. The sub comparison signal S71 is at a low level when the divided voltage Vdiv is higher than the reference voltage Vref1 or Vref2, and is at a high level when the divided voltage Vdiv is lower than the reference voltage Vref1 or Vref2.

  The sub-comparator 71 maintains the formation of the output feedback loop by performing an alternative operation when the main comparator 13 is in the sleep mode. If the semiconductor device 10 is equipped with a max-on comparator for setting the maximum on-time of the transistor N1 when the output voltage Vout is too low, it is desirable to use this as the sub-comparator 71. By using such diversion, it is possible to realize power saving at light load without causing an unnecessary increase in circuit scale.

  Note that the sub-comparator 71 continues to operate as a max-on comparator not only when the main comparator 13 is in the sleep mode but also when the main comparator 13 is in the normal mode.

  The switch 72 is connected between the application terminal of the reference voltage Vref1 (for example, Vref1 = Vref) and the non-inverting input terminal (+) of the sub-comparator 71, and is turned on / off according to the logical sum signal S63. Specifically, the switch 72 is turned on when the logical sum signal S63 is at a high level, and turned off when the logical sum signal S63 is at a low level.

  The switch 73 is connected between the application terminal of the reference voltage Vref2 (for example, Vref2 = Vref × 0.99) and the non-inverting input terminal (+) of the sub-comparator 71, and the output gate signal S64 (logical sum signal S63). On / off in accordance with the logic inversion signal). More specifically, the switch 73 is turned on when the output gate signal S64 is at a high level, and turned off when the output gate signal S64 is at a low level.

  That is, the switches 72 and 73 function as selectors that switch the reference voltages Vref1 and Vref2 input to the non-inverting input terminal (+) of the sub-comparator 71 depending on whether or not the output mask of the main comparator 13 is performed. To do.

  More specifically, when the output of the main comparator 13 is masked, the reference voltage Vref1 equal to the reference voltage Vref is selected so that the sub-comparator 71 functions as an alternative to the main comparator 13. On the other hand, when the output mask of the main comparator 13 is released, the reference voltage Vref2 lower than the reference voltage Vref is selected so that the sub-comparator 71 functions as a max-on comparator.

  The noise mask circuit 80 is a circuit block that masks the output noise of the sub-comparator 71 during the transition from the normal mode to the sleep mode (S7 = L → H), and includes an OR gate 81, a signal delay unit 82, and an AND gate. 83.

  The OR gate 81 generates a logical sum signal S81 of the noise mask control signal S65 and the logical sum signal S67. The logical sum signal S81 is high when at least one of the noise mask control signal S65 and the logical sum signal S67 is at a high level, and low when both the noise mask control signal S65 and the logical sum signal S67 are at a low level. Become a level. That is, when the output of the main comparator 13 is masked (S65 = L), the logical sum signal S67 is output through as the logical sum signal S81, but when the output mask of the main comparator 13 is released (S65 = H), The logical sum signal S81 is fixed at the high level without depending on the logical level of the sum signal S67.

  The signal delay unit 82 delays the logical sum signal S81 by a predetermined delay time (for example, 1 μs) to generate a delay signal S82.

  The AND gate 83 generates a logical product signal S1 'of the logical sum signal S67 and the delay signal S82, and outputs this to the one-shot pulse generation circuit 14 as a substitute signal for the comparison signal S1. The logical product signal S1 ′ becomes a low level when at least one of the logical sum signal S67 and the delay signal S82 is at a low level, and becomes a high level when both the logical sum signal S67 and the delay signal S82 are at a high level. .

  Therefore, even when the output noise of the sub-comparator 71 occurs during the transition from the normal mode to the sleep mode (S7 = L → H), if the output noise converges within a predetermined delay time (within 1 μs). Since no output noise is superimposed on the logical product signal S1 ′, malfunction can be prevented.

  As described above, when the output mask of the main comparator 13 is released (S65 = H), the logical sum signal S81 is fixed to the high level, and hence the delay signal S82 is fixed to the high level. Is done. Therefore, the AND gate 83 is in a state of through-outputting the logical sum signal S67 (corresponding to the comparison signal S1) as the logical product signal S1 ', so that it is not necessary to delay the comparison signal S1 unnecessarily.

  FIG. 32 is a time chart showing an example of the mode switching control operation. From the top, the switch voltage Vsw, the output voltage Vout, the mode switching signal S7, the logical sum signal S63, the comparison signal S1, and the sub comparison signal S71 are sequentially displayed. It is depicted. 33 and 34 are enlarged views of broken line regions γ and δ in FIG. 32, respectively.

  First, switching operation from the normal mode to the sleep mode will be described. When the mode switching signal S7 is raised to a high level at time t61 in FIG. 33, the sleep target circuit 50 immediately shifts to the sleep mode. At this time, the mode switching control circuit 60 raises the logical sum signal S63 to the high level without delay in response to the mode switching signal S7 being raised to the high level, A switching process to the output feedback operation using the comparator 71 is performed. That is, at time t61, the switching operation according to the comparison signal S1 is switched to the switching operation according to the sub comparison signal S71.

  As described above, when the sleep target circuit 50 is in the sleep mode, the switching operation is performed using the sub-comparator 71 without using the main comparator 13, so that most of the circuits used in the normal mode (including the main comparator 13) are used. Since it is possible to turn off, it is possible to achieve high efficiency at light loads.

  Next, the switching operation from the sleep mode to the normal mode will be described. When the mode switching signal S7 falls to the low level at time t71 in FIG. 34, the sleep target circuit 50 immediately returns to the normal mode. However, immediately after returning to the normal mode (immediately after resuming the supply of drive current), the main comparator 13 does not operate correctly, and an erroneous pulse may be generated in the comparison signal S1 (see the comparison signal S1 at times t71 to t72). ).

  Therefore, the mode switching control circuit 60 maintains the logical sum signal S63 at the high level for a predetermined current recovery period (time t71 to t72) even after the mode switching signal S7 falls to the low level. 13 output mask processing and the output feedback operation using the sub-comparator 71 are continued. That is, at time t71, the current supply to the sleep target circuit 50 is restored, while the output feedback operation remains in the sleep mode.

  When the second falling edge arrives at the gate signal G2 at time t72 after the mode switching signal S7 falls to the low level, the mode switching control circuit 60 lowers the logical sum signal S63 to the low level. The output mask process of the comparator 13 is canceled. That is, the switching operation corresponding to the sub comparison signal S71 is switched to the switching operation corresponding to the comparison signal S1 with the time t72 as a boundary. Note that the return timing to the output feedback operation using the main comparator 13 always coincides with the off timing of the transistor N2.

  By performing such mode switching control, an unintended switching operation caused by an erroneous pulse of the comparison signal S1 does not occur when returning from the sleep mode to the normal mode, so that an increase in output ripple can be eliminated. Become.

<Ripple injection circuit (reference voltage side)>
FIG. 35 is a block diagram showing a fourth embodiment of the switching power supply device (one configuration example of the semiconductor device 10 including a ripple injection circuit on the reference voltage side). The semiconductor device 10 of this configuration example has basically the same configuration as that of FIG. 1, and instead of the ripple injection circuit 11 of FIG. 1, a coil is generated from a predetermined constant voltage Vref 0 (corresponding to the reference voltage Vref of FIG. 1). A ripple injection circuit 90 that generates a reference voltage Vref by subtracting a ripple voltage Vrpl simulating the current IL is provided.

  FIG. 36 is a diagram illustrating a configuration example of the ripple injection circuit 90. The ripple injection circuit 90 of this configuration example includes current sources 91a and 91b, current sources 92a and 92b, charge / discharge changeover switches 93a and 93b, a capacitor 94, a terminal voltage application unit 95, a discharge switch 96, a discharge switch 96, and a discharge switch 96. And a control unit 97.

  The current source 91a generates a current I91a (= α × Vout) corresponding to the output voltage Vout (or the second voltage VY2 corresponding to the on-duty of the transistor N1). The first end of the current source 91a is connected to the power supply end. The second end of the current source 91b is connected to the first end of the capacitor 94 (the output end of the reference voltage Vref).

  The current source 92a generates a current I92a (= α × Vin) corresponding to the input voltage Vin. The first end of the current source 92a is connected to the first end of the capacitor 94 (the output end of the reference voltage Vref) via the charge / discharge switch 93a. The second end of the current source 92a is connected to the ground end. In the step-down type (Vin> Vout) switching power supply 1, when the current source 91a and the current source 92a have the same proportionality constant α, I91a <I92a.

  The charge / discharge changeover switch 93a is turned on / off according to the gate signal G1, thereby conducting / blocking between the first end of the current source 92a and the first end of the capacitor (the output end of the reference voltage Vref). . More specifically, the charge / discharge switch 93a is turned on during the high level period of the gate signal G1 (the on period of the transistor N1) and turned off during the low level period of the gate signal G1 (the off period of the transistor N1). .

  The current source 91b generates a current I91b (= α × Vin) corresponding to the input voltage Vin. The first end of the current source 91b is connected to the power supply end. The second end of the current source 91b is connected to the second end of the capacitor 94 (the application end of the buffer voltage Vbuf) via the charge / discharge switch 93b.

  The current source 92b generates a current I92b (= α × Vout) corresponding to the output voltage Vout (or the second voltage VY2 corresponding to the on-duty of the transistor N1). The first end of the current source 92b is connected to the second end of the capacitor 94 (the application end of the buffer voltage Vbuf). The second end of the current source 92b is connected to the ground end. In the step-down type (Vin> Vout) switching power supply 1, when the current source 91b and the current source 92b have the same proportionality constant α, I91b> I92b.

  The charge / discharge changeover switch 93b is turned on / off according to the gate signal G1, thereby conducting / blocking between the second end of the current source 91b and the second end of the capacitor (application end of the buffer voltage Vbuf). . More specifically, the charge / discharge switch 93b is turned on during the high level period of the gate signal G1 (the on period of the transistor N1) and turned off during the low level period of the gate signal G1 (the off period of the transistor N1). .

  The first end of the capacitor 94 is connected to the output end of the reference voltage Vref. The second end of the capacitor 94 is connected to the terminal voltage application unit 95. During the on period of the charge / discharge switching switches 93a and 93b (the on period of the transistor N1), a differential current (= I92a−I91a> 0) obtained by subtracting the current I91a from the current I92a is extracted from the first end of the capacitor 94. Since the differential current (= I91b−I92b> 0) obtained by subtracting the current I92b from the current I91b flows into the second end of the capacitor 94, the capacitor 94 is charged (the voltage across the capacitor 94 increases). ). On the other hand, during the off period of the charge / discharge switch 93a and 93b (the off period of the transistor N1), the currents I92a and I91b are cut off, whereby the current I91a flows toward the first end of the capacitor 94 and the capacitor Since the current I92b is drawn from the second end of the capacitor 94, the capacitor 94 is discharged (the voltage across the capacitor 94 is lowered).

  The terminal voltage application unit 95 is a circuit block that applies the terminal voltage of the capacitor 94 (the buffer voltage Vbuf in this figure) so that the voltage across the capacitor 94 is subtracted from the constant voltage Vref0 as the ripple voltage Vrpl. 951, a buffer amplifier 952, resistors 953a and 953b, a capacitor 954, switches 955a and 955b, and an inverter 956.

  The non-inverting input terminal (+) of the error amplifier 951 is connected to the application terminal for the constant voltage Vref0. The inverting input terminal (−) of the error amplifier 951 is connected to the application terminal of the feedback voltage Vfb through the switch 955a, and is also connected to the output terminal of the error amplifier 951 through a negative feedback loop composed of the resistors 953a and 955b. Has been. The output terminal of the error amplifier 951 is connected to the input terminal of the buffer amplifier 952. A phase compensation resistor 953b and a capacitor 954 are connected in series between the output terminal of the error amplifier 951 and the ground terminal. The output terminal of the buffer amplifier 952 is connected to the second terminal of the capacitor 94. The control terminal of the switch 955a is connected to the output terminal of the inverter 956. The control end of the switch 955b and the input end of the inverter 956 are connected to the application end of the backflow detection signal S5.

  The switches 955a and 955b are turned on / off complementarily in response to the backflow detection signal S5. Specifically, when the backflow detection signal S5 is at a low level (logic level when no backflow is detected), the switch 955a is turned on and the switch 955b is turned off. Therefore, in the current continuous mode, the generation operation of the error voltage Verr is performed so that the constant voltage Vref0 and the feedback voltage Vfb are matched. On the other hand, when the backflow detection signal S5 is at a high level (logic level at the time of backflow detection), the switch 955a is turned off and the switch 955b is turned on. Therefore, in the current discontinuous mode, the error amplifier 951 functions as a buffer, and the error voltage Verr is fixed to a constant value that does not depend on the feedback voltage Vfb.

  The discharge switch 96 is connected in parallel with the capacitor 94 and is on / off controlled in accordance with a discharge control signal Sx input from the discharge control unit 97. Specifically, the discharge switch 96 is turned on when the discharge control signal Sx is at a high level, and is turned off when the discharge control signal Sx is at a low level. When the discharge switch 96 is turned on, both ends of the capacitor 94 are short-circuited, so that the capacitor 94 is rapidly discharged and the ripple voltage Vrpl is reset to a zero value.

  The discharge control unit 97 has a circuit configuration similar to that of the previous discharge control unit 117, and generates a discharge control signal Sx so that the discharge switch 96 is turned on every time before the capacitor 94 starts to be charged. That is, the ripple voltage Vrpl is reset every time before the capacitor 94 starts to be charged. Further, although not explicitly shown in the figure, it is desirable to introduce the above-described overshoot suppression circuit 30 (see FIG. 23) and perform resetting even when the polarity of the ripple voltage Vrpl is inverted.

  The ripple injection circuit 90 having the above-described configuration generates a ripple voltage Vrpl that simulates the coil current IL by charging and discharging the capacitor 94 using the currents I91a and I91b and the currents I92a and 92b, and this is used as the buffer voltage Vbuf ( = The reference voltage Vref (= Verr−Vrpl) is generated by subtracting from the error voltage Verr).

  FIGS. 37 and 38 are time charts showing a first example (C1: conductive polymer capacitor) and a second example (C1: ceramic capacitor) of the ripple injection operation, respectively, and the feedback voltage Vfb, The error voltage Verr, the reference voltage Vref, the comparison signal S1, the discharge control signal Sx, and the switch voltage Vsw are depicted.

  As shown in both figures, a sufficiently large pseudo-ripple component (ripple voltage Vrpl) is injected into the reference voltage Vref regardless of whether a conductive polymer capacitor or a ceramic capacitor is used as the capacitor C1. It is possible.

<Application to TV>
FIG. 39 is a block diagram illustrating a configuration example of a television equipped with the above switching power supply device. 40A to 40C are a front view, a side view, and a rear view of a television on which the above-described switching power supply device is mounted, respectively. The TV A in this configuration example includes a tuner unit A1, a decoder unit A2, a display unit A3, a speaker unit A4, an operation unit A5, an interface unit A6, a control unit A7, and a power supply unit A8. Have.

  The tuner unit A1 selects a broadcast signal of a desired channel from a reception signal received by an antenna A0 externally connected to the television A.

  The decoder unit A2 generates a video signal and an audio signal from the broadcast signal selected by the tuner A1. The decoder unit A2 also has a function of generating a video signal and an audio signal based on an external input signal from the interface unit A6.

  The display unit A3 outputs the video signal generated by the decoder unit A2 as a video.

  The speaker unit A4 outputs the audio signal generated by the decoder unit A2 as audio.

  The operation unit A5 is one of human interfaces that accept user operations. As the operation unit A5, a button, a switch, a remote controller, or the like can be used.

  The interface unit A6 is a front end that receives an external input signal from an external device (such as an optical disk player or a hard disk drive).

  The control unit A7 comprehensively controls the operations of the units A1 to A6. As the control unit A7, a CPU [central processing unit] or the like can be used.

  The power supply unit A8 supplies power to the units A1 to A7. As the power supply unit A8, the above-described switching power supply device 1 can be suitably used.

<Other variations>
In the above-described embodiment, the configuration in which the present invention is applied to the synchronous rectification step-down switching power supply apparatus has been described as an example. However, the application target of the present invention is not limited thereto, and switching As the drive method, an asynchronous rectification method may be employed, and the output stage of the switching power supply device may be a boost type or a step-up / down type.

  As described above, the configuration of the present invention can be variously modified within the scope of the present invention in addition to the above-described embodiment. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The switching power supply according to the present invention is a power supply (for example, an SOC requiring a high-speed response) mounted in various electronic devices such as a liquid crystal display, a plasma display, a BD recorder / player, a set top box, and a personal computer. It can be used as a power source for [system-on-chip] or peripheral equipment.

DESCRIPTION OF SYMBOLS 1 Switching power supply device 10 Semiconductor device (power supply control IC)
DESCRIPTION OF SYMBOLS 11 Ripple injection circuit 111,112 Current source 113 Charge / discharge switching switch 114 Capacitor 115 Terminal voltage application part 115a Current source 115b P channel type MOS field effect transistor 116 Discharge switch 117 Discharge control part 117a One-shot pulse generation part 117b RS flip-flop 117c OR gate 117d OR gate 12 reference voltage generation circuit 121 P-channel MOS field effect transistor 122, 123 current source 13 main comparator 14 one-shot pulse generation circuit 141 OR gate 15 RS flip-flop 16, 16X, 16Y, 16Z on-time setting circuit 17 Gate driver circuit 18 Backflow detection circuit 181 Comparator 182 AND gate 183 RS flip-flop 184 O Gate 19 Silencer 191, 192 One-shot pulse generator 193 Timer 194 RS flip-flop 195 Comparator 196 NOR gate 20 Switch output stage 30 Overshoot suppression circuit 31 Cross comparator 40 Overcurrent protection circuit 41 D flip-flop 42 Overcurrent protection Unit 50 Sleep target circuit 51 Bias current generation circuit 60 Mode switching control circuit 61, 62 D flip-flop 63 OR gate 64, 65 Inverter 66 AND gate 67 OR gate 70 Non-sleep target circuit 71 Sub-comparator 72, 73 Switch 80 Noise mask circuit 81 OR gate 82 Signal delay part 83 AND gate 90 Ripple injection circuit 91a, 91b, 92a, 92b Current source 93a, 93b Charge / Release Electric switch 94 Capacitor 95 Terminal voltage application unit 951 Error amplifier 952 Buffer amplifier 953a, 953b Resistor 954 Capacitor 955a, 955b Switch 956 Inverter 96 Discharge switch 97 Discharge controller N1 N-channel MOS field effect transistor (output transistor)
N2 N-channel MOS field effect transistor (synchronous rectification transistor)
L1 Coil R1, R2 Resistor C1 Capacitor T1-T8 External Terminal X1, Y1 Voltage / Current Converter X2, Y2 Capacitor X3, Y3 N-channel MOS Field Effect Transistor X4, Y4 Comparator X5, X6 Resistor Y5 Level Shifter Y6 Selector Y7 Filter ( CR filter)
Y11 to Z13 Resistor Y14 Operational Amplifier Y15 N-channel MOS Field Effect Transistor Y16, Y17 P-Channel MOS Field Effect Transistor Y61, Y62 Switch Y71-Y73 Resistor Y74, Y75 Capacitor Z1 Current Output Amplifier Z2, Z3 N-Channel MOS Field Effect Transistor Z4 Capacitor Z5, Z6 Resistance Z7 Inverter Z8, Z9 Switch A Television A0 Antenna A1 Tuner A2 Decoder A3 Display A4 Speaker A5 Operation A6 A6 Interface A7 Control A8 Power Supply

Claims (10)

A gate driver circuit for driving the output transistor and the synchronous rectification transistor;
A reverse current detection circuit for detecting a reverse current to the synchronous rectification transistor;
An overcurrent protection circuit that performs an overcurrent protection operation when the output current becomes larger than a threshold;
Have
The power supply control IC, wherein the overcurrent protection circuit is turned on / off according to a detection result of the backflow current.   2. The power supply control IC according to claim 1, wherein the overcurrent protection circuit is turned off when the reverse current is detected, and is turned on when the reverse current is not detected. .   3. The power supply control IC according to claim 1, wherein the overcurrent protection circuit latches the detection result of the backflow current for each switching period, and is turned on / off according to the latch output. . A sleep target circuit whose operation mode is switched between a normal mode and a sleep mode in response to a mode switching signal;
When shifting from the normal mode to the sleep mode, the output of the sleep target circuit is masked without delay, and when returning from the sleep mode to the normal mode, the output mask of the sleep target circuit is set with a predetermined delay. A mode switching control circuit to be released;
A power supply control IC comprising: A gate driver circuit for driving the output transistor and the synchronous rectification transistor;
5. The mode switching control circuit according to claim 4, wherein the mode switching control circuit latches the mode switching signal at an off timing of the synchronous rectification transistor, and cancels the output mask of the sleep target circuit using the latch output. Power control IC.   6. The power supply control IC according to claim 5, further comprising a sub-comparator that performs an alternative operation when a main comparator forming an output feedback loop of a nonlinear control system is in the sleep mode.   The power supply according to claim 6, wherein the sub-comparator continues to operate even when the main comparator is in the normal mode as means for setting a maximum on-time of the output transistor. Control IC.   8. The power supply control IC according to claim 6, further comprising a noise mask circuit that masks output noise of the sub-comparator during transition from the normal mode to the sleep mode. 9. The power supply control IC according to any one of claims 1 to 8,
A switch output stage that is externally or partially attached to the power supply control IC and generates an output voltage from an input voltage;
A switching power supply device comprising:   An electronic apparatus comprising the switching power supply device according to claim 9.