JP2018089419A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an interrupt prohibition period being processed in another area as short as possible, while outputting a condition device signal according to specifications.SOLUTION: A condition device signal causes a test device to output the information of a condition device determined in an internal lottery. The following two processes are written in another area: an output counter initialization process for setting an initial value of an output counter which sets an output time of the condition device signal; and a condition device signal output process for outputting the condition device signal to the test device till the value of the output counter satisfies an end condition, on the basis of the value of the output counter which is updated whenever executed. The following two processes are written in a use area: a process for calling the output counter initialization process; and a process for calling the condition device signal output process by a timer interruption process.SELECTED DRAWING: Figure 9

Description

  The present invention mainly relates to a game machine such as a revolving machine used in the business of pachinko shops in Article 2, Paragraph 1 of the Law Concerning Customs Business Regulations, etc. When taking a type test of a gaming machine at a designated testing organization of the National Public Safety Commission based on the provisions of Article 20, Paragraph 5 (General Safety Association, Safety Association), connect to the prescribed testing equipment. The present invention relates to a gaming machine that enables a test firing test.

  Patent Document 1 describes a prescribed test apparatus used for a type test of a spinning cylinder type gaming machine. This test apparatus has a general-purpose specification in which input / output signals to / from gaming machines are assigned to pin numbers of predetermined connectors and signal timings are standardized. Send a reel start switch signal to be substituted for the start lever operation signal or a stop button signal to be substituted for the stop button operation signal from the testing device to the gaming machine, and one or more determined by internal lottery from the gaming machine to the testing device The condition device operation information, that is, the condition device signal corresponding to the winning area number defined within the range that the random number for internal lottery can take is sent, and it is close to the actual game for a long time while minimizing the manual operation of the game A test fire test can be performed.

JP 2004-49670 A

  The processing program related to the test firing test performed between the gaming machine and the specified test device includes a ROM control area (4.5 KB, etc.) and a data area (3. 0KB, etc.) can be described in a separate area that is a storage area different from the used area within the specified capacity, and by doing this, it is preferable that the capacity for game control processing that can be described in the used area can be increased. Conceivable.

  However, when a test-related processing program is described in a separate area, it is imposed to ensure the fairness of the division of roles between the use area and the separate area. Due to the restriction that it is not possible, the interrupt process described in the use area cannot be executed by the timer interrupt during the execution of the program in another area, and it is necessary to disable the interrupt before executing the program in the other area. One output time of the conditional device signal composed of a plurality of time-division signals is standardized to be 20 ms or more and 30 ms or less, and it can be dealt with by providing a standby loop for time queuing in another area. Since it is in the interrupt disabled state, processing that should be originally performed for each timer interrupt of 1.49 ms, such as fraud monitoring processing, subcommand transmission processing, power interruption saving processing, etc. cannot be performed, and the reliability of the main controller is not necessarily guaranteed. Tests may be conducted in situations where this is not done, and the effectiveness of the test may be questioned.

  An object of the present invention is to provide a gaming machine that can output a conditional device signal according to the standard, can make the interruption prohibition period as short as possible, and can perform an interruption process that should be performed without any problem.

The reference numerals of the drawings are illustrated in parentheses for illustration.
A main CPU having a memory in which a use area describing a game control process for controlling the progress of a game and a different area describing another processing module other than the game control process are partitioned;
An internal lottery for determining whether or not the condition device corresponding to a plurality of types of roles defined in advance is activated in response to a start operation signal for rotating the reel,
It assumes a gaming machine that enables a test fire test with a specified test device (TD).
"Condition device" is a device whose operation is required to display a combination of symbols related to the operation of winning, re-playing, bonus or continuous action of bonus, It means that it operates when it wins a lottery (an electronic computer lottery performed in-flight) (Attachment Rules 2 of Article 6 (3) E).
“Prescribed test equipment” refers to equipment used when a designated test organization of the National Public Safety Commission conducts a test fire test in a type test of a gaming machine.

In the above gaming machines,
The initial value of the output counter that sets the output time of the condition device signal (condition device 1 to 8 signal) that causes the test device (TD) to output the information on the condition device determined by the internal lottery is set in the different area. Based on the output counter initialization process (E_SGLOT) and the value of the output counter updated at each execution, the condition device signal is sent to the test device (TD) until the value of the output counter satisfies an end condition. And condition device signal output processing (E_IPTPD) for outputting
In the use area, a process for calling the output counter initialization process (step S30) and a process for calling the conditional device signal output process by a timer interrupt process (step S17) are described.
The condition device signal is composed of a plurality of time-division signals (an accessory low-order signal, a non-substance low-order signal, an accessory high-order signal, a non-substance high-order signal),
The initial value of the output counter is a predetermined size (for example, 41H) updated to a corresponding value (for example, 40H, 30H, 20H, 10H, 00H) at the time of signal change that changes the time-division signal during the update. Set to
In the condition device signal output process, when the value of the output counter is updated to the corresponding value at the time of the signal change, the time division signal is changed and output, and the value of the output counter is the response at the time of the signal change. When the value is not updated, the specification is such that the time division signal is returned to the use area without being changed.

  As a result, in another area, the value of the output counter satisfies the end condition based on the process of setting the initial value of the output counter that sets the output time of the conditional device signal and the value of the output counter that is updated each time it is executed. Until this time, the process of outputting the condition device signal is a process that ends within an extremely short time. Therefore, the initial value of the output counter can output the conditional device signal at the standard time, but the period during which interruption is prohibited by processing in another area can be made as short as possible. Processing can be done without problems. Further, by updating the output counter, it is possible to appropriately send a conditional device signal composed of a plurality of time division signals to the test device.

The perspective view of this invention gaming machine. FIG. Combination list of each condition device and symbol. List of condition device signal information etc. corresponding to the winning area. List of stop operation information corresponding to the winning area. The block diagram of the control apparatus of a gaming machine. Main CPU memory map. Flow of timer interrupt processing and game main processing in the use area. Flow of output counter initialization processing and conditional device signal output processing in another area.

  FIG. 1 shows a swivel game machine to which the present invention is applied. The swivel type gaming machine is generally called a pachislot machine. In 1985, after revisions to the gaming machine rules, that is, the National Public Safety Commission Regulation No. 1 on January 30, 2004 (2004), 2 It is a slot machine that conforms to the National Public Safety Commission Regulation No. 4 “Rules for Game Machine Approval and Type Approval” on May 12. Hereinafter, terms and their technical contents are in accordance with the existing game machine rules.

  The gaming machine housing 8B includes a honeycomb rear cabinet 8R, a cabinet frame 8W, and door-shaped upper and lower front cabinets 8E and 8F. In the upper front cabinet 8E, an upper liquid crystal display device 71 that projects a moving image or the like in full color, a dot matrix display device 73 that imitates a searchlight, a reel panel 8, and an upper left movable lamp E1 having a set lamps e1 to e3 that can be unfolded and stored. , Upper right movable lamp E2 having the same set of lamps e4 to 6, lower left movable lamp E3 having the same set of lamps e7 to 9, lower right movable lamp E4 having the same set of lamps e10 to 12, upper left lamp E5, upper right lamp E6, reel Gate-type lamps E7 to E11 surrounding the panel 8 are provided. The lower front cabinet 8F has a lower liquid crystal display device 72 composed of a movable vision ATV that also functions as an operation unit 8S and a lower liquid crystal button AB for production and displays a moving image or the like in cooperation with the upper liquid crystal display device 71. Side lamps E12 and E13 are provided. Reference numerals 91 to 94 denote speakers for outputting BGM and various sound effects, 8M denotes a medal payout port, and 8G denotes a medal tray. Note that left and right mean left and right in the player's line of sight facing the gaming machine. The same applies hereinafter.

  Inside the transparent display window 80 of the reel panel 8 is provided a plurality of rotating cylinders, ie, a left reel 1L, a middle reel 1C, and a right reel 1R, which are variable display elements, on the outer periphery of each reel band 10L, 10C, 10R. Three consecutive frames are arranged through the window. Each symbol scrolls from top to bottom during normal forward rotation, including during steady rotation. A plurality of rows and a plurality of symbol display positions displayed through the window of the display window 80, that is, the three rows of the left, middle, and right reels 1L, 1C, and 1R and the upper, middle, and lower three rows respectively. At 3 × 3 = 9 symbol display positions specified by columns and stages, for example, only the middle line (left middle-middle middle-right middle) is the effective line. Note that two or more lines including other lines may be effective lines.

  The operation unit 8S has a medal slot 2i for inserting a game medal as a game medium, a start button bi, up / down / left / right movement buttons b1 to 4, and an end button bo, and selectively changes the volume, image brightness, BGM, character, and the like. A customizable button BT that can be used, an electromagnetic record of the storage device, that is, a bet button 3 that draws a prescribed number required for one game from a credit, for example, 3 bets (3 BETs), and the remaining number of medals in the medal tray 8G The adjustment button 4 to be dropped, the start lever 5 serving as a start switch for starting variable display (rotation) of each reel 1L, 1C, 1R, provided corresponding to each reel 1L, 1C, 1R, variable display (rotation) of the corresponding reel Left stop button 6L, middle stop button 6C, right stop, which are stop switches that individually stop Tan 6R, reject button 2R press when clogging medals downstream medal slot 2i, comprising a door key hole 8K.

  Also, a credit display DL1 for displaying the current number of credits, and a payout that also serves as a main monitor MA for displaying the AT instruction information when the assist time AT is activated to display the number of payout medals by winning and to notify suitable stop operation information. Display DL2, 1 to 3 lamps EL1 to 3 that are turned on each time one, two, or three medals are applied, a bet lamp ELb that is turned on when a receiving medal is accepted, and a start operation by the start lever 5 The game basic lamps 30 include a start lamp ELs that is turned on when possible and a replay lamp ELr that is turned on when a combination of symbols relating to replay is displayed.

  When the bet lamp ELb is lit, when one medal is inserted from the medal insertion slot 2i with the hanging medal being 0, the one lamp EL1 is lit, and when one is inserted, the two lamp EL2 is lit, and one more is inserted. The three-lamp lamp EL3 is lit and reaches the specified number. When the specified number of multiplying medals is reached, the start lamp ELs is turned on, and the start operation by the start lever 5 becomes possible. When a medal is further inserted into the medal insertion slot 2i without operating the start lever 5 from the state where the prescribed number has been reached, the counter of the credit indicator DL1 is advanced and can be stored up to a predetermined upper limit of 50 sheets. Up to 50 medals paid out by winning are added to the credit, and medals paid out exceeding 50 are received by the medal tray 8G from the medal payout opening 8M.

  As shown in FIG. 2, on the outer peripheral surface of each reel band 10L, 10C, 10R, there are 10 red, white 7, bar, watermelon 1, watermelon 2, bell 1, bell 2, cherry, replay and heart. The types of symbols are drawn by printing or the like according to the symbol numbers 0, 1 to 19 and according to a unique vertical arrangement. Each of the reels 1L, 1C, and 1R is a 20-frame reel that arranges all 20-frame symbols.

  For driving each reel 1L, 1C, 1R, a stepping motor having a specification in which one step angle for driving a standard 21-frame reel is about 1.43 degrees and rotates once in 504 steps by 1-2 phase excitation is used. . In the case of 21-frame reels, an equal number of steps of 504/21 = 24 steps can be assigned per symbol, but in the case of 20-frame reels, 504/20 = 25.2 does not result in an integer solution, so an uneven number of steps is assigned. ing. Symbol number 1,3,6,8,11,13,16 in which the remainder of the integer solution obtained by dividing 26 with the larger number of steps and 24 with the smaller number of steps and dividing symbol numbers 0 to 19 by 5 is odd. Assign the lesser 24 steps to 18 symbols, and assign the more 26 steps to the other symbols 0, 2, 4, 5, 7, 9, 10, 12, 14, 15, 17, 19 ing.

  FIG. 3 shows a combination of symbols on the effective line corresponding to the condition device related to the operation determined by the internal lottery, that is, the winning combination (winning flag). In order to facilitate winnings, the game is in the state of playing a role starting with the combination of the left symbol “red 7”, the middle symbol “white 7”, and the right symbol “heart”. It defines an accessory continuous activation device RBB related to a first-type special accessory that terminates its operation when the total number of acquired game media exceeds an upper limit, for example, 240.

  REP 1 to 10 are defined as re-playing roles for operating the re-game, and NML 1 to 27 are defined as winning combinations (small roles) that can acquire game medals. Among the small combinations, NML1 to NML4 are high payout combinations that can win 8 medals, the first high payout combination NML1 is in the upper row, the third high payout combination NML3 is in the upper right, and the fourth high payout combination NML4. , The second high payout combination NML2 arranges the bells 1 or 2 on the lower right. The NMLs 17 to 27 are medium payouts that can win three medals. The first middle payout NML17 arranges bells 1 or 2 in a small V-shape in the upper left, middle, middle, and upper right (small V), and the second The middle payout NML 18 arranges the bells 1 or 2 in the lower left-middle middle-lower right Oyama shape (Oyama). NML 5 to 16 are low payout combinations that can earn one medal, and are mainly duplicated with a high payout combination or a medium payout combination, and constitute an alternative combination with different payouts depending on the order of stop operations. There are those in which a plurality of symbols are listed in one column. For example, regarding REP3, the symbol on the left reel 1L means Bell 1 or Bell 2. In the remarks column, an example of display items in the display window 80 corresponding to the combination is shown.

  FIG. 4 shows the relationship between each winning area in the internal lottery and the operating condition device (winning combination), and the relationship between the condition device signal information output to the test device. The internal lottery is a random number extracted from a 2-byte counter, for example, which is updated at high speed on the RWM of the main controller MC when the start lever 5 is operated. The condition device related to the operation in the game, that is, the winning combination is determined depending on whether or not it belongs to the winning area, and the condition device signal information is specified.

  In the winning area, the number 0 is an unjustified (off), the number 1 small role ALL, the number 2 single role ALL, the number 3 to 26 high payout option, left middle right to right middle left 6 The upper bell 1 to the right down bell 12, numbers 27 to 38, in which a specific one of the street pushing orders is the correct pushing order in which 8 dividends can be obtained (the other is 1 coupon with a symbol drawing rate of 1/2). It is a medium dividend option, and a specific one of the six push orders is the correct push order that gives a three-piece payout (small V or Koyama) (the other is one payout with a symbol pull-in rate of 1/2) Small V Bell 1-Koyama Bell 8, Common 3 Bells 1 and 2 with Numbers 39 and 40, Weak Che with Number 41, Strong Che with Number 42, Middle Che with Number 43, Replay with Number 44, Freeze Lip with Number 45, No. 46-49 push order lip 1-4, No. 50 watermelon, No. 51 chan lip, No. 52 slipping chan Up, including the RBB of the number 53.

  RBB lottery "general medium", RBB winning combination action symbol combination cannot be displayed, RBB winning flag is carried over "inside medium", RBB symbol combination action symbol display The winning area to be drawn is determined according to the game state of “acting” of the character starting with (circles are drawn). If you win each winning area, you will win the listed condition device (role) alone or in duplicate. No fraud is provided in the “inside”. The small role ALL and the one-piece role ALL are drawn only in “in operation”. Of the conditional device signal information, the non-actual material information that is not a small character or a re-game corresponding character is composed of data representing the winning area number in 1 byte. The RBB winning game “general medium” or “inside medium” consists of 1-byte data in which 1 is set in the least significant bit and 0 is set in all other cases.

  As shown in FIG. 5, when the winning area of the 36-choice winning area of winning area numbers 3 to 38 is won, the solution obtained by “(the winning area number−the leading number 3) ÷ the remainder of the integer solution of 6 + 1” The instruction monitor numbers 1, 2, 3, 4, 5, and 6 are displayed on the instruction monitor MA. 1 corresponds to “middle left / right”, 2 corresponds to “middle left / right”, 3 corresponds to “middle left / right”, 4 corresponds to “middle right / left”, 5 corresponds to “middle right / left”, and 6 corresponds to “middle right / left”. In the command itself transmitted from the main controller MC to the peripheral controller SC, the winning area for the high payout winning combination is unified with No. 3, and the winning area for the medium payout winning combination is unified with No. 4. Based on the instruction monitor numbers 1, 2, 3, 4, 5 and 6 transmitted simultaneously, the upper liquid crystal display device 71 indicates that the stop buttons 6L, 6C and 6R are physically displayed when the correct answer push order is “left middle right”. If the correct push order is “left / right middle”, the button correspondence navigation “123” corresponding to the arrangement is “132”, and if the correct push order is “middle left / right”, “213” is the correct push order. "312" is displayed when the right is "middle right left", "231" is displayed when the right answer is "middle right", and "321" is displayed when the right answer is "right middle left". I try to let them.

  As shown in FIG. 6, the control device CN incorporated in the gaming machine housing 8B manages the progress of the game, and performs internal lottery, payout of medals by winning a prize, re-game operation, operation of accessory, assist time AT A main controller MC corresponding to a so-called main board for executing main game control related to the player's interest such as the operation of the player, and information transmitted from the main controller MC according to the one-way communication specification And a peripheral control device SC corresponding to a so-called sub-side peripheral substrate that executes effect control based on the items determined by the main control device MC. The one-way communication specification refers to a communication specification that satisfies “not capable of receiving a signal transmitted by a peripheral board” defined in the gaming machine rules for the main board.

  The main controller MC includes an 8-bit main CPU composed of a Z80 compatible chip incorporating a read-only read-only memory ROM and a readable / writable read / write memory RWM, and is used in a system clock operating environment of 12 MHz, for example. . The main CPU applies a predetermined extended specification for gaming machines to the basic Z80 specification.

  The input port I1 of the main CPU includes index sensors 11L, 11C, and 11R (IDs) of the reels 1L, 1C, and 1R, stop buttons 6L, 6C, and 6R, a bet button 3, a settlement button 4, a start lever 5, and a medal. An R chute that inherits medals from the medal insertion sensors SEN0 and medal passage sensors SEN1, 2 and the medal selector 2 provided in the medal selector 2 for selecting and detecting medals received from the insertion slot 2i and releases it to the hopper tank of the medal payout device HP. Each signal of the R chute sensor SEN3 provided in the medals and the medal payout sensor SEN4 provided at the exit of the medal payout device HP are input. Stepping motors 12L, 12C, and 12R for connecting the drive shafts SH to the reels 1L, 1C, and 1R via the motor driver Dr1 from the output port O1 through the built-in LEDs 61, 62, and 63 of the stop buttons 6L, 6C, and 6R. (SM), the blocker solenoid 28s for projecting the blocker claw 28 for releasing the game basic lamps 30 via the LED driver Dr2 and releasing the medal from the medal selector 2 via the solenoid driver Dr3 and returning it to the medal tray 8G, Each of the medal payout motors HPm of the medal payout device HP is controlled via the motor driver Dr4.

  Each index sensor IDs detects an on-edge and an off-edge of a semicircular belt-shaped index ID (1Li, 1Ci, 1Ri) attached to the inner side of each reel every half circle, and the first on-edge or off-edge is detected for each reel. After that, the stop buttons 6L, 6C, 6R can be accepted. Each stepping motor SM has a permanent magnet built-in type rotor Rm having a large number of rotor teeth on the outer periphery of the iron core, and a plurality of sets of magnetic poles having a plurality of stator teeth on the inner periphery of the magnetic pole. (A bar phase (inverted phase of A)) and D-phase (B bar phase (inverted phase of B)) windings, and a stator Sw. 1-phase excitation and 2-phase excitation for turning on one winding and other adjacent windings alternately by 1-2 phase excitation that repeats alternately every interrupt time, for example, t = 1.49 ms. The half step angle (one step angle by two-step update) is displaced by one step update, and one rotation is performed by step update 504. Further, forward rotation and reverse rotation are made possible by changing the step update direction of the excitation pulse.

  On the ROM of the main CPU, when the start lever 5 is operated, an internal lottery means for executing the internal lottery for determining whether or not the condition device corresponding to a plurality of types of roles defined in advance can be operated, that is, the winning area in FIG. K, each reel corresponds to the rotating device control means V1 that accelerates all the reels to the normal rotation side after the operation of the start lever 5 and 4.1 seconds have elapsed from the start of the previous game to reach the normal rotation speed Reel control means V including a rotation stop device control means V2 that allows the display of a combination of symbols corresponding to the winning combination on the active line by individually stopping by the operation of the stop button, and if the game result is a winning, a predetermined payout amount Medal payout means M for paying out medals, automatic medal insertion means N for automatically inserting medals for the next game in the same prescribed number if the game result is a re-game operation, Game state transition means J that shifts the game state if it is accompanied by a movement of an object, etc., and determination of whether or not a predetermined spinning effect is made to reversely rotate each reel with a predetermined probability determined for each winning combination by a predetermined freeze drawing Freezing lottery means W to perform, and a spinning effect execution means G to execute the spinning effect related to the winning are provided.

  Further, on the ROM of the main CPU, AT operation determining means H1 for determining the operation of the assist time AT under a predetermined operation condition associated with the internal winning combination, etc., the number of continuous games that will extend the operation of the assist time AT AT addition determination means H2 for determining the addition of the time etc. under a predetermined additional condition associated with the internal winning combination, etc., AT continuation management means H3 for managing the operation of the assist time AT from the end of the operation to the end of the operation, the correct answer push order for the choice combination AT instructions such as the upper liquid crystal display 71 managed by the peripheral control device SC and the AT instructions to be outputted to the main monitor MA constructed by borrowing the display function of the payout display DL2 managed by the main control device MC Information output means H4 is provided.

  A prescribed test apparatus TD can be connected to the main controller MC via the first interface board IF1 and the second interface board IF2 used during the test test. The first interface board IF1 is mounted with first, second and third connectors CN1, CN2 and CN3 having a predetermined standard, and the fourth connector CN4 having a predetermined standard is mounted on the second interface board IF2. Yes. Each of the connectors CN1 to CN4 has a total number of pins of 68, and a signal assigned to each pin has a general-purpose specification that matches the specification of the test apparatus TD.

  The first connector CN1 is used to input a signal from the main control device MC to the test device TD, and is based on condition device signal information composed of accessory information and non-object information corresponding to the winning area number determined by the internal lottery. Device 1-8 signal, reel index signal by each index sensor IDs, built-in LEDs 61, 62, 63 of each stop button 6L, 6C, 6R are changed from red display to blue lighting to stop each reel 1L, 1C, 1R. Various signals to be detected or determined by the main controller MC, such as a left / middle / right reel stop possible ramp signal to be enabled, a signal for identifying a gaming state such as the operation of an accessory, etc., are assigned to predetermined pin numbers. . The second connector CN2 is also used to input a signal from the main controller MC to the test apparatus TD, and assigns the excitation pulse signal of each stepping motor SM to a predetermined pin number.

  The third connector CN3 is used to input a signal output from the test device TD to the main control device MC. The third switch CN3 replaces the actual switch of the game medals with the input switch signal. The reel start switch signal replaces the operation signal of the start lever 5. The game operation signals by hand such as the stop switch signals corresponding to the left, middle, and right to be substituted for the operation signals of the stop buttons 6L, 6C, 6R are assigned to predetermined pin numbers. The operation signal of the start lever 5 or the reel start switch signal is generically called a reel start operation signal.

  The fourth connector CN4 is used to input a signal from the main control device MC to the test device TD, and is a signal indicating the order in which the stop buttons 6L, 6C, 6R are pressed and the pressing position (design to be aimed) based on the AT instruction information output means H4. Is assigned to the specified pin number. In addition, the second interface board IF2 includes the first interface within a predetermined time, for example, within 2 seconds from the turning on of the reel start operation signal (for example, falling from the high level to the low level) in accordance with the specifications of the test apparatus TD. The second and third reels to be stopped are identified as left, middle or right, respectively, and sent to the test apparatus TD in time series, or first, second and third. Equipped with a CPU that handles signal processing in accordance with a predetermined sequence, such as specifying the number of steps the stop button is pressed for the reel to be stopped from the reel index signal and sending it to the test device TD in time series ing.

  The peripheral control device SC includes a sub CPU composed of a read-only read-only memory ROM attached externally and a 32-bit RISC (Reduced Instruction Set Computer) chip microcomputer having a built-in and external read / write memory RWM. For example, it is used under a system clock operating environment of about 200 MHz. Under the control of the real-time operating system RTOS (Real-Time Operating System), the sub CPU controls the CPU time and priority assigned to tasks related to image production, audio production, etc., thereby performing appropriate and efficient parallel processing of tasks. It is possible.

  Transmission information from the main control device MC, signals for the actual machine customization button BT, and the attack button AB are input to the input port I2 of the sub CPU. Transmission information from the main control device MC, that is, reception information of the peripheral control device SC includes main-side initialization completion information, medal insertion information including operation information of the bet button 3, reel start information including operation information of the start lever 5, Winning flag information by internal lottery, operation information of stop buttons 6L, 6C, 6R, game result information, game state information, freeze and rotation effect information, AT operation information, AT instruction information, AT addition information, AT end information, error Various information such as information that is detected or determined or executed by the main controller MC is included.

  The sub CPU also functions as an I2C microcontroller, and connects the serial clock line SCL and serial data line SDA of the real-time clock RTC to the serial clock line SCL and serial data line SDA of the CPU built-in I2C. The serial clock line SCL and the serial data line SDA are each pulled up to the main operating potential vdd = 3.3V of the sub CPU via the resistor rp. The clock function of the real-time clock RTC is continuously maintained over a long period of time, for example, 10 years or longer by a backup power source Bt such as a secondary battery regardless of the power on / off of the gaming machine.

  On the ROM of the sub CPU, the navigation in accordance with the AT instruction information output from the AT instruction information output means H4 to the upper liquid crystal display device 71 based on the reception information from the main control device MC, for example, the correct push order is “middle left If “right”, the display navigation means X1 displays “123” or the like corresponding to the position of the stop button, and in conjunction with this display navigation, informs by voice whether the stop button to be operated from the speakers 91 to 94 is left, middle or right. Audio navigation means X2, image production means X3 for changing and displaying the moving image development displayed on the liquid crystal display devices 71 and 72 and the dot matrix display device 73 according to the gaming state, the spinning effect, the AT period, and the like. Lamp production means X4 for controlling the lighting and emission colors of the lamps E1 to E13, sound production means X5 for outputting sound effects and BGM from the speakers 91 to 94, movable Mechanical effect means for controlling the deployment and storage of the pump E1 to E4 X6, it is provided an oscillating effect means X7 for driving the lower liquid crystal buttons AB vibration generator 90 in conjunction with the pressing of.

  The I2C controller I2Cn is connected to the CPU built-in bus of the sub CPU, and the nine clocks facing the display window 80 of the serial clock line SCL and serial data line SDA of the I2C controller I2Cn are displayed on the reel bands 10L, 10C, 10R. LDE driver Dr5 for controlling reel back lamps BL1-9 illuminated from the back, LED driver Dr6 for controlling movable lamps E1-4, LED driver Dr7 for controlling lamps E5-11 provided on upper front cabinet 8E, lower front The LED driver Dr8 for controlling the lamps E12, 13 provided in the cabinet 8F is connected to each serial clock line SCL and serial data line SDA.

  The upper liquid crystal display device 71 and the lower liquid crystal display device 72 are controlled via a VDP (Video Display Processor), an output port O2, and LCD drivers Dr9 and Dr10. The dot matrix display device 73 is controlled via the output port O2 and the LED driver D11. The stepping motors m1 to m4 that drive the movable lamps E1 to E4 are controlled via the output port O2 and the motor driver Dr12. The vibration generator 90 is controlled via the output port O2 and the motor driver Dr13. Audio from the speakers 91 to 94 is controlled via the audio IC, the output port O2, and the power amplifier Dr14. The lower liquid crystal button locker AR that locks the lower liquid crystal button AB and prohibits the pressing thereof is controlled via the output port O2 and the solenoid driver Dr15.

  FIG. 7 shows a memory map of the ROM and RWM of the main CPU of the main controller MC. Internal lottery means K, reel control means V, medal payout means M, medal automatic insertion means N, game state transition means J, freeze lottery means W, spinning drum effect execution means G, AT operation determination means H1, AT addition determination means H2 The program instruction code of the game control process for controlling the progress of the game by causing the AT continuation management means H3 and the AT instruction information output means H4 to function is the address 0000H in the specified capacity (control area 4.5 KB) in the use area. 11FFH, and the program data of the game control process is described in addresses 1200H to 1DF3H in the specified capacity (data area 3.0 KB) in the used area.

  Separate processing other than game control processing responsible for security-related processing and test-related signal processing for trial firing test from the viewpoint of preventing unauthorized modification or other changes to the unused area, the comment area, and addresses 1F00H to 2FBFH Describes the module's program instruction code and data. A program management area, an area having no hardware area, an RWM of a use area is provided in 512 bytes of addresses F000H to F1FFH, and an RWM of another area is provided in 512 bytes of addresses F200H to F3FFH. F400H to FFFFH are areas having no hardware area. Note that the program instruction code of the game control process in the use area and the program instruction code of another process module in another area are described in an assembler language.

  Of the RWM in the used area, work areas such as timers, counters, and flags related to the used area program are secured in F000H to F13FH, and the used area stack area is secured in the F1C0H to F1FFH after the unused area. .

  Among the RWMs in another area, a work area such as a timer, a counter, a flag, etc. related to a program in another area is secured in F210H to F22FH after an unused area in F200H to F20FH, and a stack area in another area is allocated in F230H to F246H. Secured. F247H to F3FFH are unused, and F400H to FFFFH are areas where there is no area in terms of hardware.

  FIG. 8 shows a timer interrupt process and a game main process described in the use area. The timer interrupt process is executed every fixed time of 1.49 ms. When a timer interrupt occurs (step S00), all the internal registers of the main CPU used in the used area are saved and protected in the stack area of the used area (S01).

The internal registers of the main CPU to be protected are as follows.
1) Q register; 8-bit dedicated register with extended specifications for gaming machines. This is called a queue register.
The upper part is fixed to F0H, and is mainly used for RWM access from F000H to F0FFH by an extended data transfer instruction (LDQ; load Q).
2) I register: A dedicated register that stores the upper 8 bits of the interrupt destination address.
3) A register; 8-bit accumulator used for arithmetic processing and data transfer.

4) F register: 8-bit flag register that holds the results of various operations.
s (most significant bit) is a sign flag that is set to 1 when the operation result is negative.
z is a zero flag that is set to 1 when all bits are 0 as a result of operation.
tz is a specific bit flag of an extended specification for gaming machines that is set to 1 (changes in value) when all bits are 0 by execution of a data transfer instruction (LD; load). Called the Tizet flag. Also called a second zero flag.
h is a half-carry flag that a programmer cannot be involved in.
* Is undefined.
p / v is a parity overflow flag.
n is an addition / subtraction flag that the programmer cannot participate in.
c is a carry flag that is set to 1 when a carry or borrow occurs as a result of an operation.
Note that the F register constitutes an A register and a pair register AF.

5) B, C, D, E, H, L registers; 8-bit general purpose registers.
It becomes a 16-bit pair register of BC, DE, and HL.
6) IX and IY registers; 16-bit dedicated registers for index addressing.
IXh and IYh represent the upper 8 bits, and IXl and IYl represent the lower 8 bits.
When the back registers of the A, F, B, C, D, E, H, and L registers are used, the back registers are included in the internal registers of the main CPU to be protected.

  Subsequent to step S01, power interruption recovery processing including calculation of checksum (S02), input port I1 reading processing (S03), game basic lamps 30 lighting processing (S04), stepping motor SM motor control processing ( S05), output port O1 management processing (S06), subcommand transmission processing to be transmitted to the peripheral control device SC (S07), fraud monitoring processing (S08) for monitoring illegal insertion and fraud of game medals, and external terminal board External signal output processing for outputting a specific signal to the hall computer or the like (S09), monitoring processing of various sensors (S10), updating processing of various internal timers (S11), test signal processing with the test apparatus TD (S12) ) And the like are sequentially executed, all the registers saved in the stack area of the use area are restored (S13), and the interrupt is permitted (S1). ), Returns to interrupt the previous processing (S15).

  In the test signal processing in step S12, the conditional device signal output process E_IPTPD described in another area is called and executed by the CALL instruction via the test signal output process subroutine (S16) described in the use area (S17). After returning from the area, the process returns to the timer interrupt process (S18).

  In the game main process (S20) described in the use area, a game medal insertion process (S21), a reel start operation reception process (S22) for receiving a reel start operation signal, an internal lottery process (S23), and a freeze lottery process (S24). After that, the game interval timer of 4.1 seconds is confirmed (S25), waiting for the time-up (S26), the game interval timer is started again (S27), interrupt is prohibited (S28), and used. After the register is saved in the stack area of the use area and protected (S29), the output counter initialization process of another area is called and executed (S30), and after returning from the other area, the use register is restored (S31). Then, the interruption is permitted (S32), the rotation device rotation device control process (S33) for causing the rotation device rotation device control means V1 to function, and the rotation stop device control means V2 is made to function. One game is completed through the rolling stop device control process (S34) and the game result determination process (S35) that causes the medal payout means M, the medal automatic insertion means N, and the game state transition means J to function according to the game result ( S36).

  FIG. 9 shows an output counter initialization process E_SGLOT and a condition device signal output process E_IPTPD described in another area. When the output counter initialization process E_SGLOT is called from the use area (S40), after setting an initial value, for example, 41H (65 in decimal notation) in the hexadecimal notation, to the condition device signal output counter defined in the RWM in another area, It returns to the use area (S42). Since the condition device signal output counter is rewritten in another area, its initial value is set by a program in another area. The condition device signal output counter before setting the initial value 41H is 00H. The output counter initialization process E_SGLOT ends in about 10 μs, which is an extremely short time.

  As shown in the remarks column, the condition device signals (the lowest condition device 1 signal to the highest condition device 8 signal) are negative logic, that is, low level (0V) is on (ON) and high level (+ 5V) is off (OFF). 1 byte information. When the condition device 8 signal is turned on, it is identified that the information is an accessory information, and when the condition device 7 signal is turned on, it is identified that the information is a non-object information for winning or replaying. In the condition devices 1 to 6 signals, the inversion driver (74HC540F) that divides the accessory information and non-object information shown in FIG. 4 corresponding to the winning area number into 6 bits and is mounted on the first interface board IF1. Put the reversed information.

  The condition device signal is specified by an internal lottery triggered by the turning on of the reel start operation signal, and after the game interval timer is timed up, the first 6 outputs the condition device 8 signal turned on in the lower 6 bits of the accessory information Corresponding accessory low-order signal, the second output of the condition device 7 signal turned on. The non-object low-order signal corresponding to the lower 6 bits of the non-object information, the third output, the condition device 8 signal turned on The high-order 6 bits of the non-physical information (the real high-order signal corresponding to the high-order 6 bits (in this embodiment, high-order 2 bits in the present embodiment)) of the non-physical information with the condition device 7 signal turned on at the fourth output. In the embodiment, the unaccompanied lower signal corresponding to the upper 2 bits is sequentially sent to the test apparatus TD. The condition device signal is composed of four time-division signals, that is, an accessory subordinate signal, a non-subject subordinate signal, an accessory superordinate signal, and a non-subject superordinate signal.

  The initial value 41H (65) of the condition device signal output counter is a hexadecimal value 40H (decimal notation 64), 30H (48), which is a corresponding value at the time of signal change that changes four time-division signals during the update by countdown. ), 20H (32), 10H (16), and 00H (0). Each time division signal is changed at a multiple of 16. The output time of each time division signal is 1.49 ms × 16 = 23.84 ms, the output time of all four is 95.36 ms, and the reel start operation signal is turned on. Later, the reel acceleration time is about 105.79 ms, the stop prohibition period for improving the transient stability is about 61.09 ms, and the time required for detecting the earliest edge is added, that is, the reel stop stop lamp first. Until the signal is turned on and the stop operation can be accepted, all the output of the condition device signal is completed.

  When the conditional device signal output processing E_IPTPD is called during the timer interruption processing in the use area (S43), the conditional apparatus signal output counter is acquired from the RWM in another area (S44), and the value is 00H (0). Immediate return is made to return to the use area (YES in S45). This corresponds to the case where the initial value of the condition device signal output counter has not yet been set, or when the output of the condition device signal in one game has ended.

  If NO in step S45, the value of the conditional device signal output counter is updated by minus one (S46), and the updated value is a corresponding value at the time of signal change 40H (64), 30H (48), 20H (32 ) If it is not a multiple of 16 including 0, such as 10H (16) and 00H (0), the process returns to the use area (YES in S47). This corresponds to the case where any time division signal is in the middle of output.

  If NO in step S47, it is determined whether or not the conditional device signal output is cleared, that is, whether it is 00H (0) (S48). When cleared (NO in S48), the conditional device signal is all off (00000000B before inversion). (S49), an all-off condition device signal is output to the first interface board IF1 via the output port 6 which is, for example, the 6th 1-byte port in the output port O1 (S65), and is returned to the use area (S66). ). This is the case when the fourth output is completed.

  If YES in step S48, when the first output of the output counter is 40H (64) (NO in S50), the accessory information stored in the RWM in the use area is loaded into the A register for reference purposes. (S51), the lower 6 bits are extracted by ANDing with 00111111B (S52), and 1 byte is set to 1 which is a useful character in the 8th most significant bit and 0 which is not a non-useful character in the 7th bit. Are combined (S53), the condition device signal is set in the output port 6 (S65), and the service area is restored (S66). For example, in the case of inside, the accessory information is 00000001B, the accessory lower signal set to the output port 6 is 10000001B, the negative logic accessory lower signal output to the test device TD is 01111110B (0 is on, 1 is Off).

  In the case of YES in step S50, when the output of the output counter is 30H (48) at the second output start time (when the signal is changed for the first time) (NO in S54), the non-object information stored in the RWM of the use area Is loaded into the A register for reference purposes (S55), ANDed with 00111111B, and the lower 6 bits are extracted (S56). The highest 8 bits are not useful and 0 and 7 bits are non-useful. Each 1 is set to synthesize a 1-byte non-subordinate low-order signal (S57), the condition device signal is set in the output port 6 (S65), and the use area is restored (S66). For example, in the case of the strong check of winning area number 42, the non-actual material information is 00101010B, the non-actual low-order signal set to the output port 6 is 010101010B, and the negative logical character low-order signal output to the test apparatus TD is 10010101B. (0 is on, 1 is off).

  In the case of YES in step S54, when the output of the output counter is 20H (32) at the third output start (when the signal is changed for the second time) (NO in S58), the accessory information stored in the RWM of the use area is stored. Loaded into the A register for reference (S59), shifted to the right, that is, the lower 6 bits, and extracted the upper 2 bits of the accessory information (S60). Each set of 0, which is not a non-object, is combined to synthesize a 1-byte high-order signal (S61), the condition device signal is set in the output port 6 (S65), and the operating area is returned (S66). . For example, in the case of inside, the accessory information is 00000001B, the accessory upper signal set to the output port 6 is 10000000B, the negative logic accessory upper signal output to the test device TD is 01111111B (0 is on, 1 is Off).

  When the output of the output counter is 10H (16) at the time of the fourth output start (when the signal is changed with respect to the third time), which becomes YES in step S58, the non-object information stored in the RWM in the use area is A for reference purposes. Load into the register (S62), shift 6 bits to the right and extract the upper 2 bits of the non-essential information (S63). 1 is set to synthesize a 1-byte unaccompanied high-order signal (S64), the conditional device signal is set in the output port 6 (S65), and it is returned to the use area (S66). For example, in the case of strong Choi, the non-object information is 00101010B, the non-object high-order signal set to the output port 6 is 01000000B, the negative logic character low-order signal output to the test apparatus TD is 10111111B (0 is ON, 1 is off).

  In the conditional device signal output processing E_IPTPD, only the conditional device signal is changed and set to the output port 6, and no standby loop is provided to increase the output time. Prohibition does not last long.

  In the above, the conditional device signal output process E_IPTPD may be called by a timer interrupt process that is an integral multiple of 1.49 ms. For example, when calling every timer interrupt of 2.98 ms which is twice, the initial value of the output counter is 21H, and the timing at the time of signal change is 20H (32), 18H (24), 10H (16), 08H (8), 00H (0). In addition, the above is a method of outputting four time division signals of an accessory sub-signal, a non-substance sub-signal, an accessory high-order signal, and a non-substance high-order signal to the test apparatus TD. Two time-division signals of the non-object signal may be output to the test device TD, or time-division is performed by setting the object information in the upper 4 bits of the condition device signal and the non-object information in the lower 4 bits. Instead, a method of outputting to the test apparatus TD at a time may be adopted. In the above description, it goes without saying that specific numbers and the like are merely examples.

1L; left reel, 1C; middle reel, 1R; right reel 2i; medal slot, 2; medal selector 3; bet button, 4; checkout button 5; Liquid crystal display device 72; Lower liquid crystal display device 73; Dot matrix display device ATV; Movable vision 8; Reel panel 80; Display window 90; Vibration generator E1, E2, E3, E4; Movable lamp SEN1; Passing sensor 1, SEN2; Medal passing sensor 2
CN; control device, MC; main control device, SC; peripheral control device K; internal lottery means, V; reel control means V1; spinning cylinder rotation device control means, V2; rotation stop device control means M; medal payout means, N ; Automatic medal insertion means, J; Game state transition means W; Freeze lottery means, G; Spinning effect execution means H1; AT operation determination means, H2; AT addition determination means H3; AT continuation management means, H4; Output means X1; Display navigation means, X2; Voice navigation means, X3; Image effect means X4; Lamp effect means, X5; Sound effect means, X6; Mechanical effect means X7; Vibration effect means, TD; Test device IF1; Interface board, IF2; Second interface board

Claims (1)

A main CPU having a memory in which a use area describing a game control process for controlling the progress of a game and a different area describing another processing module other than the game control process are partitioned;
An internal lottery for determining whether or not the condition device corresponding to a plurality of types of roles defined in advance is activated in response to a start operation signal for rotating the reel,
In a gaming machine that enables a test firing test with a specified test device,
Output counter initialization processing for setting an initial value of an output counter that sets an output time of a condition device signal that causes the test device to output information on the condition device determined by the internal lottery in the separate area, and updated each time it is executed A condition device signal output process for outputting the condition device signal to the test device until the value of the output counter satisfies an end condition based on the value of the output counter.
In the use area, a process for calling the output counter initialization process and a process for calling the conditional device signal output process by a timer interrupt process are described.
The condition device signal consists of a plurality of time division signals,
The initial value of the output counter is set to a predetermined magnitude that is updated to a corresponding value at the time of signal change that changes the time division signal during the update,
In the condition device signal output process, when the value of the output counter is updated to the corresponding value at the time of the signal change, the time division signal is changed and output, and the value of the output counter is the response at the time of the signal change. A gaming machine characterized in that when it is not updated to a value, the time division signal is returned to the use area without being changed.

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