JP6543322B2 - Gaming machine - Google Patents

Description

  The present invention mainly relates to a gaming machine such as a coin-operated game machine, a pachinko game machine, etc. which is provided for the business of a pachinko parlor prescribed in Article 2, Paragraph 1 of the Act on Regulation of Sex Business etc. About.

  In Patent Document 1, it is checked whether the final storage content stored in the backup RAM area is normal or not based on the checksum stored in the backup RAM area when the power is turned off when the power is turned on. In this case, there is described a technique for performing control to restore the control state to the state before power-off based on the final stored content.

JP 2002-95840 A

  The checksum is not identical before and after the power is cut off, and there is a possibility that there may be an unauthorized action as well as a pure failure, and from the viewpoint of preventing unauthorized modification and other changes, checksum confirmation processing etc. The security related processing of this is basically the same as the test related signal processing specified by the game machine rules, the rule that the main board, that is, the control area (4.5 KB etc.) of the main controller and the data area (3.0 KB etc.) It can be described in another area which is a storage area different from the use area in the capacity, and in this way, it is considered preferable because the capacity for game control processing that can be described in the use area can be increased. In particular, with the transition to the main AT, where the main controller determines the operation of the assist time AT, which informs the pressing order of the correct answer etc. of the correct order for the pushing officer etc., which has been determined exclusively by the peripheral control device until now Further savings are required.

  An object of the present invention is to provide original game control such as security-related and test-related operations other than game control processing for controlling the progress of the game while securing clearness and fairness of role assignment of the use area and another area. Another object of the present invention is to provide a gaming machine which can appropriately describe a separate processing module provided for the purpose of optimization and the like, and can increase a capacity allocated to game control processing in a use area.

The reference numerals of the drawings are illustrated in parentheses.
A use area within a predetermined capacity that describes game control processing that controls the progress of a game, and another area that describes another processing module (for example, E_SAMP1) that performs processing related to security without describing the game control processing A gaming machine provided with a main CPU having a divided memory (ROM, RWM) is assumed. Here, the separate processing module may perform processing related to testing instead of, or in addition to processing related to security.

In the above gaming machines,
In the use area, internal registers (Q, I, AF, BC, DE, HL, IX, IY, AF ', BC', DE ') of the main CPU which prohibit interrupts and are used in the use area. , HL 'registers) are saved to the stack area (for example, RWM address F1C0H to F1FFH) of the use area, and then the separate processing module (E_SAMP1) described in the separate area is called and executed, and this separate process is performed Described is a processing procedure (for example, another area calling process 1) for restoring the internal register saved in the stack area of the use area and permitting an interrupt after returning from the module.
The internal register does not include the stack pointer SP and the program counter PC. Also, the R register (refresh register) is excluded from the fact that there is no need for protection.

  As a result, during execution of the separate processing module described in the separate area, the interrupt is prohibited, and therefore data of the use area is not rewritten from the separate area. Moreover, when calling another processing module, the internal register used in the used area is saved in the stack area of the used area, and after returning from the other processing module, the saved internal register is restored. Even if the contents (data) of the internal register are destroyed by execution, the sameness of the internal register is maintained before and after the execution of another processing module. Therefore, the game control process of the use area is not affected by the execution of the separate process module, and the separate process module other than the game control process can be secured while securing the clarity and fairness of the division of roles between the use area and the separate area. Can be appropriately described in another area, and the capacity allocated to game control processing in the use area can be appropriately increased.

  The table registers (each register of AF, BC, DE, and HL), and the table registers are stored in the internal registers which are saved in the stack area of the area used before calling the separate processing module (E_SAMP1). And data exchangeable back registers (AF ', BC', DE ', and HL' registers), and the back register is used as a save register of the front register at the time of interrupt processing in the use area. There is.

  As a result, when executing another processing module while being able to protect the internal register quickly with a small number of steps by saving the contents of the table register to the back register at the time of interrupt processing in the used area, including the back register Since the internal register used in the use area is saved and protected in the stack area of the use area, the execution of the separate processing module can surely eliminate the influence of the game control process in the use area, The purpose can be achieved effectively.

The perspective view of the gaming machine of the present invention. The block diagram of the control apparatus of a game machine. Memory map of main CPU. The program block diagram of a use area and another area.

  FIG. 1 shows a drum-type game machine to which the present invention is applied. Roll-down type gaming machines are generally called pachislo, and they have been revised in the gaming machine regulations, ie, the first public security commission rules of January 30, 2004 (1985) 2 It is a slot machine that conforms to the National Public Safety Commission Regulations No. 4 "Rules on Authorization and Type Verification of Gaming Machines, etc." Hereinafter, terms and technical contents thereof conform to the existing gaming machine regulations.

  The gaming machine case 8B includes a rear cabinet 8R, a cabinet frame 8W, and door-like upper and lower front cabinets 8E and 8F. In the upper front cabinet 8E, a liquid crystal display device 70 constituting the effect display device 7 for projecting moving images and predetermined information in full color, a reel panel 8, an upper decoration lamp 81, a left decoration lamp 82, a right decoration lamp 83, a liquid crystal display apparatus It has four accent decoration lamps 84 facing the corner of 70 and panel decoration lamps 85 facing the top, left and right of the reel panel 8. The lower front cabinet 8F includes an operation unit 8S, a lumbar panel 8P, a lower left decoration lamp 86, and a lower right decoration lamp 87. The decorative lamp 88 is referred to as a generic name of 81 to 87. Reference numerals 91 to 94 denote speakers for outputting BGM and various sound effects, 8M denotes a medal payout port, 8G denotes a medal receiver, and 8T denotes an ashtray. Note that left and right mean right and left in the player's line of sight facing the gaming machine. The same applies below.

  Inside the transparent display window 80 of the reel panel 8 are provided a plurality of variable display elements such as a left reel 1L, a middle reel 1C, and a right reel 1R, and a total of 21 on the outer periphery of each reel band 10L, 10C, 10R. Three consecutive tops of the symbols arranged in a top or 20 tops are exposed through the window. During normal rotation including steady rotation, each symbol scrolls from the top to the bottom. A plurality of columns and a plurality of columns of symbol display positions displayed over the display window 80, ie, three columns of left, middle and right reels 1L, 1C and 1R and three columns of top, middle and bottom respectively For example, only the middle row (left middle-middle middle-right middle) is set as the effective line at 3x3 = 9 symbol display positions specified by the row and the row. Note that two or more lines, including other lines, may be regarded as effective lines.

  The operation unit 8S includes a medal insertion slot 2 for inserting game medals as game media, a jog dial JD having a push button PB for making the player's operation involved in the effect and a dial DA, electromagnetic recording of the storage device, ie, one credit. A bet button 3 for drawing down the number of medals required for the game, for example 3 (3 BETs), a settlement button 4 for dropping the number of medals remaining on the credit to the medal receiver 8G, variable display (rotation) of each reel 1L, 1C, 1R Are provided corresponding to the start lever 5 serving as the start switch for starting the operation and each reel 1L, 1C, 1R, and the left stop button 6L serving as the stop switch for individually stopping the variable display (rotation) of the corresponding reel 6C, right stop button 6R, medal return button pressed when medals are clogged downstream of medal insertion slot 2 0, and a door key hole 8K.

  On the reel panel 8, a credit display DL1 for displaying the current number of credits, a payout display DL2 for displaying the number of medals paid out by winning, and 1 for lighting up every time one, two, or three medals are applied ~ 3 pieces of lamps EL1 to 3 3, bet lamp ELb lit when the hanging medal is acceptable, start lamp ELs lit when the start operation by the start lever 5 is possible, lit when a combination of symbols pertaining to replay is displayed The game basic lamps 30 including the replay lamp ELr to be played back are provided. Also, when the correct answer is made in the order of pressing the stop button 6L, 6C, 6R, the operation of the assist time AT that informs the order of the correct answer and the symbol to aim for the pressing small part paying out medals of high payout exceeding the number of inserted medals The game effect lamps 700 constituting the effect display device 70 including the left stop lamp 71, the middle stop lamp 72, and the right stop lamp 73 to be lighted together with the navigation notification in the liquid crystal display device 70 are provided.

  When the bet lamp ELb lights up, when one medal is inserted from the medal insertion slot 2 with the hanging medal being 0, the one lamp EL1 lights up, and when one more card is inserted, the two lamp EL2 lights up and one more card is inserted And the three-piece lamp EL3 lights up and reaches the specified number. When the specified number of medals are reached, the start lamp ELs is turned on, and the start operation by the start lever 5 becomes possible. If a medal is further inserted into the medal insertion slot 2 without operating the start lever 5 from the state of having reached the specified number, the counter of the credit display DL1 is advanced to store up to 50 sheets which is a predetermined upper limit. Up to 50 medals paid out by winning are also added to the credits, and medals paid out over 50 are received from the medal payout opening 8M by the medal receiver 8G.

  As shown in FIG. 2, the control device CN incorporated in the inside of the gaming machine case 8B manages the progress of the game, internal lottery, payout of medals by winning, operation of replay, operation of special effects, assist time AT The main control device MC corresponding to the main board in the gaming machine rule called the so-called main side that executes main game control related to the player's profit such as the operation of the game, and transmission from the main control device MC And a peripheral control device SC corresponding to a peripheral substrate in the gaming machine rule called a so-called sub-side which receives presentation information and executes effect control based on the determination in the main control device MC. The one-way communication specification refers to a communication specification that satisfies “the signal that the peripheral substrate can not receive can not be received” defined in the gaming machine rules regarding the main substrate.

  The main control unit MC includes an 8-bit main CPU consisting of a Z80 compatible chip with a read only read only memory ROM and a read / write read / write memory RWM built in, and used under a system clock operating environment of 12 MHz, for example . The main CPU applies a predetermined extension specification for a gaming machine to the basic Z80 specification.

  In the input port I1 of the main CPU, the index sensors 11L, 11C, 11R (IDs) of the reels 1L, 1C, 1R, the stop buttons 6L, 6C, 6R, the bet button 3, the settlement button 4, the start lever 5, medals The respective signals of the inserted medal sensor 21 provided downstream of the insertion slot 2 and the paid-out medal sensor 23 provided at the exit of the medal payout device HP incorporated in the gaming machine casing 8B are input. Respective stepping motors 12L, 12C, which connect the drive shaft SH to the respective reels 1L, 1C, 1R from the output port O1 via the motor driver circuit Dr1 with the built-in LEDs 61, 62, 63 of the stop buttons 6L, 6C, 6R. 12R (SM), the game basic lamps 30 via the LED driver circuit Dr2, the medal blocker 22 for dropping the medal added after the reel start via the solenoid driver circuit Dr3 to the medal receiver 8G, the motor driver circuit Dr4 Each of the medal payout motors 24 of the medal payout device HP is controlled via

  Each index sensor IDs detect the on-edge and off-edge of a semicircular band-shaped index ID (1Li, 1Ci, 1Ri) attached to the inner side of each reel every half turn, and detection of the first on-edge or off-edge is performed for all reels. After that, the reception of the stop button 6L, 6C, 6R is enabled. Each stepping motor SM includes a permanent magnet built-in type rotor Rm having a large number of small rotor teeth on the outer periphery of an iron core, and a plurality of sets of magnetic poles having a plurality of small stator teeth on the inner circumference of the magnetic pole. (A bar phase (A reverse phase)), D stator (B bar phase (B reverse phase)) and a stator Sw wound with a winding, and during steady rotation, one winding is turned on Exciting pulse by 1-2 phase excitation which alternately repeats one phase excitation and two phase excitation which turns on one winding and another adjacent winding every one interruption time, for example, t = 1.49 ms. The half step angle (one step angle by two step update) is displaced by one step update of and one rotation is performed by step update of 504. Further, by changing the step update direction of the excitation pulse, forward rotation and reverse rotation are enabled.

  On the ROM of the main CPU, for example, a random number value extracted from a 2-byte counter that is updated at high speed on hardware or software triggered by the operation of the start lever 5 is associated with a role within the possible 0-65535 range. According to which prize area they belong to, the internal lottery means K which determines the winning combination, the operation of re-playing, or any winning combination or wrongness relating to the operation of the bonus after operation of the start lever 5 And, after 4.1 seconds from the start of the previous game, the reel rotating device control means V1 for accelerating all reels to the normal rotation side to reach the steady rotation speed and stop each reel individually by the operation of the corresponding stop button Reel control means V including rotation stop device control means V2 which allows the display of a combination of symbols corresponding to winning combinations to the effective line, if the game result is a prize The medal payout means M pays out fixed number of medals, Automatic medal insertion means N for automatically inserting the hanging medals of the next game with the same specified number if the game result is the reworking, transition to the game result etc. Gaming state transition means J for transitioning the gaming state, freeze extraction means W for determining whether or not a predetermined revolving drum effect such as reverse rotation is performed to reverse each reel with a predetermined probability determined separately for each winning combination by predetermined freeze extraction, There is provided a rotating drum effect execution means G for executing a rotating drum effect relating to the touch.

  In addition, on the ROM of the main CPU, an AT operation determining means H1 which determines the operation of the assist time AT under a predetermined operating condition associated with the internal winning combination etc., and the number of continuing games to extend the operation of the assist time AT. AT addition determination means H2 to determine under the predetermined addition conditions associated with the internal winning combination etc., AT continuation management means H3 to manage from the operation decision of the assist time AT to the operation end, correct answer about push order small part The AT instruction information such as pressing order is output to the main monitor MA constructed by borrowing the display function of the payout display DL2 managed by the main controller MC, and is output to the liquid crystal display device 70 etc managed by the peripheral control device SC An instruction information output means H4 is provided.

  The peripheral control device SC includes a sub CPU consisting of a read only read only memory ROM externally attached and a 32-bit RISC (Reduced Instruction Set Computer) chip microcomputer having an internal and external read / write read / write memory RWM For example, it is used under a system clock operating environment of about 200 MHz. The sub CPU enables appropriate and efficient parallel processing of tasks by controlling the CPU time and priority assigned to tasks related to presentation display and voice under the control of a real-time operating system (RTOS). ing.

  The transmission information from the main control device MC and the signal of the jog dial JD are input to the input port I2 of the sub CPU. The transmission information from the main control device MC, that is, the reception information of the peripheral control device NC includes main side initialization completion information, medal insertion information including operation information of the bet button 3, reel start information including operation information of the start lever 5, Information of winning flag information by internal lottery, operation information of stop button 6L, 6C, 6R, game result information, game state information, freeze and turn drum effect information, AT operation information, AT instruction information, AT addition information, AT end information, error The information includes various information detected or determined or executed by the main control device MC.

  The sub CPU also functions as an I2C microcontroller, and connects the serial clock line SCL and the serial data line SDA of the real time clock RTC to the serial clock line SCL and the serial data line SDA of the CPU built-in I2C. The serial clock line SCL and the serial data line SDA are pulled up to the main operating potential vdd = 3.3 V of the sub CPU via the resistor rp, respectively.

  The time data of the real time clock RTC is the time of writing, for example, the time of writing according to the accurate current time based on the Japanese standard or the international standard clock radio at the time of production by a game machine manufacturer etc. It is written as 45 seconds. After that, the time is continuously updated based on the reference clock by the built-in crystal oscillator of the real time clock RTC. Corrections for the January 31 large month, January 30 or 28 small month, and the February 29th leap year, which is once every four years, are also performed automatically. The watch function of the real time clock RTC is continuously maintained for a long period of, for example, 10 years or more by the backup power supply BT such as a secondary battery regardless of the power on / off of the gaming machine.

  On the ROM of the sub CPU, based on the received information from the main control device MC, the navigation according to the AT instruction information output from the AT instruction information output means H4 to the liquid crystal display 70 etc. If "right", navigation means X1 to display "123" etc. corresponding to the stop button position, interlocked with the display of the navigation means X1, and voices whether the stop button to be operated from the speakers 91 to 94 is left, middle or right Voice navigation means X2 to notify, effect display means Y1 to change and display moving image development etc. displayed on the liquid crystal display device 70 according to the game state, turning drum effect, AT period, etc. A sound effect output means Y2 for outputting BGM is provided.

  The I2C controller I2Cn is connected to the CPU built-in bus of the sub CPU, and nine symbols facing the display window 80 of the I2C controller I2Cn serial clock line SCL and serial data line SDA are reel bands 10L, 10C, 10R The serial clock line SCL and serial data line SDA of the LED driver Dr6 connected to the serial clock line SCL and serial data line SDA of the LDE driver Dr5 that controls the reel back lamps BL1 to 9 that illuminate from the back, and the decoration lamp 88 The serial clock line SCL and the serial data line SDA of the LED driver Dr7 that connects and controls the game effect lamps 700 are connected. The task of these LED related I2C devices has higher priority than the real time clock RTC. The serial clock line SCL and the serial data line SDA are pulled up to the main operating potential vdd = 3.3 V of the sub CPU via the resistor rp, respectively. The liquid crystal display device 70 is controlled via a VDP (Video Display Processor), an output port O2, and an LCD driver circuit Dr8. The audio from the speakers 91 to 94 is controlled via an audio IC, an output port O2, and a power amplifier circuit Dr9.

  FIG. 3 shows a memory map of the ROM and RWM of the main CPU of the main control unit MC. Internal lottery means K, reel control means V, medal payout means M, medal automatic insertion means N, gaming state transition means J, freeze lottery means W, turning drum effect execution means G, AT operation determination means H1, AT addition determination means H2 , The program instruction code of the game control process for controlling the progress of the game by causing the AT continuation management means H3 and the AT instruction information output means H4 to function, the address 0000H to 0000H in the prescribed capacity (control area 4.5 KB) in the use area The program data of the game control process is described in 11FFH, and is described in addresses 1200H to 1DF3H in a prescribed capacity (data area 3.0 KB) in the use area.

  Unused area, behind the comment area, addresses 1F00H to 2FBFH, responsible for security related processing from the viewpoint of preventing unauthorized modification and other changes, test related signal processing specified in the gaming machine rules, etc., other than game control processing The program instruction code and data of the processing module are described. After the program management area and the area having no area in terms of hardware, the RWM of the used area is provided in 512 bytes of addresses F000H to F1FFH, and the RWM of another area is provided in 512 bytes of addresses F200H to F3FFH. F400H to FFFFH are areas having no area in terms of hardware. The program instruction code of the game control process in the use area and the program instruction code of another processing module in another area are described in the assembler language.

  Among the RWMs of the used area, work areas such as timers, counters, and flags related to the program of the used area are secured in F000H to F13FH, and the stack areas of the used area are secured in F1C0H to F1FFH behind the unused area. .

  Of the RWMs in the other areas, behind the unused areas of F200H to F20FH, F210H to F22FH secure work areas such as timers, counters, and flags related to the program of the other areas, and stack areas of other areas in F230H to F246H I have secured. F247H to F3FFH are unused, and F400H to FFFFH are areas having no area in terms of hardware.

  As shown in FIG. 4, in the game control process described in the use area, an interrupt process INT1 to be executed every one interrupt time, for example, t = 1.49 ms, comprehensively manage the respective means K to H4, and advance one game The game main process includes a plurality of different area calling processes 1, 2,... Which respectively call different area processes 1, 2. Although illustration is omitted, in the use area, initialization processing at power on, backup processing at power failure, etc. are also described. In the present embodiment, the external interrupt and the non-maskable interrupt NMI are unused.

The internal registers of the main CPU used in the used area are as follows.
1) Q register; 8-bit dedicated register for extended specifications for gaming machines. Called a queue register.
The upper rank is fixed to F0H and is used for RWM access from F000H to F0FFH.
2) I register: A dedicated register for storing the upper 8 bits of the interrupt destination address.
3) A register: 8-bit accumulator used for arithmetic processing and data transfer.

4) F register: 8-bit flag register for holding various operation results.
s (most significant bit) is a sign flag which is set to 1 when the operation result is negative.
z is a zero flag which is set to 1 when all bits are 0 as a result of operation.
tz is set to 1 when all bits are 0 (execution of a value) by execution of a data transfer instruction (LD; load). It is called the teasset flag. It is also called the second zero flag.
h is a half carry flag that the programmer can not participate.
* Undefined.
p / v is the parity overflow flag.
n is an addition / subtraction flag that the programmer can not participate.
c is a carry flag in which 1 is set when a carry or borrow occurs as a result of operation.
The F register constitutes a register pair AF with the A register.

5) B, C, D, E, H, L registers; 8-bit general purpose registers.
It becomes a 16-bit register pair of BC, DE and HL.
6) IX, IY register; 16-bit dedicated register for index addressing.
IXh and IYh indicate upper 8 bits, and IXl and IYl indicate lower 8 bits.
7) A ', F', B ', C', D ', E', H ', L'registers;
A, F, B, C, D, E, H, L Table registers and back registers that can exchange data by exchange instruction, A 'and F' for AF ', B' and C 'for BC', D It becomes the back register of each pair of DE 'by' and E 'and HL' by H 'and L'.

  In interrupt processing INT1, the data of table register AF is saved to the back register by exchange instruction EX (step t1), and the data of table registers BC, DE, HL is exchanged by back instruction BCX, DE, HL by exchange instruction EXX. After saving to '' (step t2), various interrupt processing is executed (step t3). Various interrupt processing includes reading processing to the input port I1, motor control processing of the stepping motor SM, output management processing to the output port O1, sub command transmission processing to the peripheral control device SC, monitoring processing of various sensors, and updating of various timers. Processing, including external signal output control processing to the gaming machine installation island side. After execution of various interrupt processing, the data saved in the back register BC ', DE', HL 'by the exchange instruction EXX is restored to the front register BC, DE, HL (step t4), and the back register AF' is made by the exchange instruction EX. The data which has been saved is restored to the table register AF (step t5), the interrupt is permitted (step t6), and the process returns from the interrupt processing (step t7).

  In SAMP1 of separate area call processing 1, interrupts are inhibited (step S1), and internal registers Q, I, A, F, B, C, D, E, H, L, IX used in the used area , IY are saved together from the bottom F1FFH of the stack area of the use area toward the smaller address (step S2) by an instruction defined in the extended specification for a gaming machine "PUSH ALL" (step S2), and the exchange instruction EX Switch AF and AF 'by step (step S3), switch BC and BC' by exchange command EXX, switch DE and DE 'by HL and HL' respectively (step S4), "PUSH GPR" In accordance with the instruction defined in step S2, the address is evacuated to a young address following the stuffing in step S2 (step S5).

  After step S5, another area processing 1 is called and executed by "CALL E_SAMP1" (step S6). By the execution of the CALL instruction, the upper 8 bits and the lower 8 bits of the return address, that is, the address of "POP GPR" next to the CALL instruction are recorded in the stack area of the used area.

  After returning from the separate area processing 1, the register holding the content of the back register stuffed in step S5 is restored at one time by the instruction defined in the expansion specification for the gaming machine "POP GPR" (step S7). The exchange instruction EXX exchanges BC 'and BC, DE' and DE, and HL 'and HL, respectively (step S8), and the exchange instruction EX interchanges AF' and AF (step S9), and calls another area processing 1 Return the contents of the previous back register, restore the table register packed in step S2 collectively by the instruction defined in the expansion specification for the gaming machine "POP ALL" (step S10), and permit the interrupt (Step S11).

  In E_SAMP1 of another area process 1 described in another area, predetermined another area process 1 is executed (step S12). In this separate area processing 1, backflow / dwelling / foreign matter detection processing at the time of medal insertion, backflow / dwelling / foreign object detection processing at the time of medal withdrawal, front door open detection processing, abnormality confirmation processing of internal lottery random number, winning of internal lottery Any one process or two or more combined processes of security related processes such as an abnormality confirmation process of a setting value which is a combination of probabilities, an RWM abnormality confirmation process, and a backup abnormality confirmation process are executed. In the separate area process 2 and subsequent steps, security related processes other than the separate area process 1 or test related signal output processes defined in the gaming machine rules are described. The separate area processing 2,... Is called from the separate area call processing 2,. After execution of the separate area process 1, the process returns to the use area by the "RET" instruction (step S13). The "RET" instruction returns to the return address stored in the stack area of the used area, the stack pointer SP pointing to the address of the stack area is incremented by 2, and "POP GPR" of step S7 is executed.

  The instruction code for different area call processing 1 described in the used area is “DI”, “EX”, “EXX”, “EI”, each 1 byte, “PUSH ALL”, “PUSH GPR”, “POP ALL”, When "POP GPR" is 2 bytes for each, 2 bytes for "CALL E_SAMP1" are 17 bytes in total, and another area processing 1 is described by an instruction exceeding 17 bytes, the capacity of the used area for the part exceeding 17 bytes Will save you The number of bytes saved in each process is at least a great saving effect on the total because the processing of the different area is not limited to one, and there are often a plurality of processes.

  In the above embodiment, although the reel-type gaming machine has been illustrated, the present invention is similarly applicable to a pachinko gaming machine. It is needless to say that the specific numbers, addresses, etc. in the above description are only one example.

1L; left reel, 1C; middle reel, 1R; right reel 2; medal insertion slot, 3; bet button, 4; settlement button 5; start lever, 6L, 6C, 6R; each stop switch 7; effect display device, 70 Liquid crystal display device 8; Reel panel, 80; Display window CN; Control device, MC; Main control device, SC; Peripheral control device K; Internal lottery means, V; Reel control means V1; Spindle rotating device control means, V2 ; Rotation stop device control means M; medal payout means, N: medal automatic insertion means, J; gaming state transition means W; freeze lottery means, G; spinning drum effect execution means H1; AT operation determination means, H2; Means H3; AT continuation management means, H4; AT instruction information output means X1; navigation means, X2; voice navigation means Y1; effect display means, Y2; sound effect output means

Claims (3)

It has a memory divided into a use area within a predetermined capacity that describes game control processing that controls the progress of a game, and another area that describes another processing module that performs processing related to security without describing the game control processing. In a gaming machine provided with a main CPU,
In the use area, after interrupts are prohibited and the internal register of the main CPU used in the use area is saved in the stack area of the use area, the other processing module described in the other area is called A game machine characterized in that a processing procedure for executing and returning the internal register saved in the stack area of the use area and permitting an interrupt after returning from the separate processing module is described. It has a memory divided into a use area within a predetermined capacity that describes game control processing that controls the progress of a game, and another area that describes another processing module that performs processing related to a test without describing the game control processing. In a gaming machine provided with a main CPU,
In the use area, after interrupts are prohibited and the internal register of the main CPU used in the use area is saved in the stack area of the use area, the other processing module described in the other area is called A game machine characterized in that a processing procedure for executing and returning the internal register saved in the stack area of the use area and permitting an interrupt after returning from the separate processing module is described.   The internal register saved in the stack area of the use area before calling the separate processing module includes a table register and a back register capable of exchanging data with the table register, and the back register is the area used in the use area. 3. A game machine according to claim 1, wherein said game machine is used as a save register of said table register at the time of interrupt processing of.

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