JP2018089100A - Microcomputer for controlling game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer for controlling a game machine in which it is not possible to erase data such as fraudulence monitoring information without depending on a regular procedure.SOLUTION: A microcomputer 10 for controlling a game machine mounted on a main control board 1 of a game machine is provided with a nonvolatile memory part 104 in which memory is retained even when power is cut off. A memory management part 103 capable of accessing the nonvolatile memory part 104 only accepts data writing and data reading input from a CPU part 101, data reading input from a memory reading device outside the game machine through a communication control part 105, and memory erasure and erasure history data reading so that data tallied by the CPU part 101 is appropriately retained even when a backup power source 2 is detached, and it is not possible to erase the tallied data written in the nonvolatile memory part 104 without depending on a regular memory reading device 200.SELECTED DRAWING: Figure 2

Description

  The present invention includes at least a ROM unit that stores a game machine control program, a CPU unit that controls a game machine based on the game machine control program stored in the ROM unit, and the CPU unit that stores the game machine control program. This invention relates to a one-chip gaming machine control microcomputer equipped with a RAM section that can be used as a work area when executing, and in particular, provides access to a non-volatile memory mounted to store abnormality monitoring related information. It relates to the technology to control.

  Pachislot machines such as pachinko machines and pachislot machines should not resonate with customers. For this reason, the range of the ratio of the number of payouts to the number of game medals or game balls (hereinafter referred to as “game medals”) (hereinafter referred to as “play rate”) is stipulated by law, and each machine manufacturer Must develop a gaming machine with a payout rate within an acceptable range.

  On the other hand, the gaming machine microcomputer mounted on the main control board that controls the gaming machine controls the progress of the game based on a lottery with a predetermined probability in order to ensure the fairness of the game. ing. Therefore, each gaming machine manufacturer develops a gaming machine by setting a lottery probability that does not deviate from the legally defined range as a specification of the gaming machine.

  However, even if the progress of the game in the game machine developed by the game machine manufacturer is correctly controlled, it is possible to pay out more game medals etc. than the original design value due to recent and diversified illegal acts. There is a case. For example, physically deforming nails and objects provided in gaming machines to limit the movement of game balls, or improperly crafting control circuits such as the main control board to induce malfunctions Thus, as the payout rate greatly exceeds the legally allowable range, a lot of game medals are paid out and illegal profits are obtained.

  Such a fraudulent act can be monitored by a gaming machine control microcomputer mounted on the main control board as a gaming medal payout abnormality or an insertion abnormality. However, in order to realize fraud monitoring by the gaming machine control microcomputer, the CPU resource of the gaming machine control microcomputer must be allocated to fraud monitoring, and the load on the gaming machine control microcomputer increases accordingly. Problems arise.

  Therefore, by arranging the control area, data area, and work area for the program for fraud monitoring in a different area from the control area of the program for controlling the progress of the game, etc. There has been proposed a gaming machine including a main control unit that suppresses an increase in control load of a program for controlling the progress as much as possible (see Patent Document 1).

  In addition, in order to be able to check what kind of fraud was done at what timing, we collected the number of game medals etc. inserted and paid out over a long period of time, and based on the collected information, the payout rate and the ratio of bonuses There has been proposed a slot machine including a main control board for deriving (the ratio of the number of payouts by an accessory) (see Patent Document 2).

JP 2009-136408 A Japanese Patent Laid-Open No. 2006-87235

  However, the gaming machine described in Patent Document 1 and the slot machine described in Patent Document 2 have a drawback that intentionally erased fraud monitoring information can be intentionally deleted. That is, since the number of game medals and the like inserted and paid out are stored in the work area on the RAM provided in the main control unit and the main control board, if the power supply to the RAM is cut off, the fraud monitoring information The contents of the work area in which is recorded are deleted.

  Even after the main power of the game machine or the slot machine is turned off, the RAM is supplied with power from the backup power source. Originally, the stored contents of the RAM are stored and retained. Is supplied from a power supply circuit arranged outside the main control unit or the main control board, the RAM data can be erased simply by unplugging the backup power supply connector.

  Therefore, in the gaming machine described in Patent Document 1 and the slot machine described in Patent Document 2, an actor who has performed an illegal act unplugs the backup power supply connector in order to avoid detection of the illegal act. The fraud monitoring information stored in the RAM can be deleted.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine control microcomputer in which data such as fraud monitoring information cannot be erased unless the proper procedure is followed.

  In order to solve the above-described problem, the invention according to claim 1 is directed to at least a ROM unit storing a game machine control program and a CPU for controlling the game machine based on the game machine control program of the ROM unit. A one-chip gaming machine control microcomputer having a CPU unit and a RAM unit that can be used as a work area when the CPU unit executes the gaming machine control program. Non-volatile memory unit for holding stored contents written during machine operation, memory management unit capable of writing and erasing to non-volatile memory unit, external device connected from outside of gaming machine, and memory management unit A communication control unit that relays communication with the external device and enables an external device to access the nonvolatile memory unit, and the memory management unit includes the CP When a write command is issued from the CPU unit, the data received from the CPU unit is written to the nonvolatile memory unit. When a read command is issued from the CPU unit, the data to be read is stored in the nonvolatile memory unit. When the memory clear command is issued from the external device via the communication control unit, the data is erased from the non-volatile memory unit, and the communication control unit When a read command is issued from an external device, the data to be read is read from the nonvolatile memory unit and passed to the external device.

  According to a second aspect of the present invention, in the gaming machine control microcomputer according to the first aspect, the memory management unit stores the memory clear command from the CPU unit in an unacceptable manner. According to the memory clear command issued based on the gaming machine control program, the data in the nonvolatile memory section cannot be cleared.

  The invention according to claim 3 is the gaming machine control microcomputer according to claim 2, wherein when the memory management unit receives the memory clear command, the transmission source of the memory clear command is the communication control unit. If not, it is characterized in that the data in the nonvolatile memory section cannot be cleared by not accepting this.

  According to a fourth aspect of the present invention, in the gaming machine control microcomputer according to the second aspect, the memory management unit includes a port for receiving commands and data from the CPU unit, and a communication control unit. A port for receiving commands and data is provided separately, and a memory clear command from the CPU unit cannot be accepted by not defining a memory clear command in the register of the port corresponding to the CPU unit. It is characterized by that.

  According to a fifth aspect of the present invention, in the gaming machine control microcomputer according to the second aspect, the transmission content is provided in a transmission path from the CPU unit to the memory management unit, and the transmission source is a CPU. A transmission source marking unit and / or a transmission source marking unit which is provided in a transmission path from the communication control unit to the memory management unit, and which adds to the transmission content that the transmission source is a communication control unit, The section is characterized by determining whether or not to accept the memory clear command based on the information of the transmission source marked in the memory clear command.

  According to a sixth aspect of the present invention, in the gaming machine control microcomputer according to any one of the first to fifth aspects of the present invention, the memory management unit is configured to store error detection information based on write data. A generation function is provided, and when a write command is received from the CPU unit, error detection information is written to the nonvolatile memory unit together with data for writing.

  According to a seventh aspect of the present invention, in the gaming machine control microcomputer according to the sixth aspect, the memory management unit has a data error detection function using error detection information, and the CPU unit or the external device When a read command is received from the non-volatile memory unit, error detection information is read from the nonvolatile memory unit together with the data to be read, and the presence or absence of a data error is detected based on the error detection information.

  The invention according to claim 8 is the gaming machine control microcomputer according to claim 7, wherein the memory management unit combines the error detection result of the data read from the nonvolatile memory unit with the read data. Thus, the read command is transmitted to the transmission source.

  The invention according to claim 9 is the gaming machine control microcomputer according to claim 7, wherein the memory management unit has an error detection result of data read from the nonvolatile memory unit. The data with the error is skipped, the next order data is read from the non-volatile memory section to detect the presence of data error, and only the data without data error is transmitted to the read command transmission source. It is characterized by.

According to a tenth aspect of the present invention, in the gaming machine control microcomputer according to any one of the first to fifth aspects, the nonvolatile memory unit stores data requested to be written by the CPU unit. A data area to be stored, and a management area for storing data used by the memory management unit for management of the nonvolatile memory unit; from an external device connected via the communication control unit, a memory clear command; In addition, the memory management unit that has received the unique identification information that can identify the device itself and the date / time information based on the clock / calendar function provided in the external device erases the contents of the data area in the nonvolatile memory unit, and also includes a memory clear command. The deletion history data including the identification information of the external device and the date / time information received together with the data is stored in the management area. The features.
According to an eleventh aspect of the present invention, in the gaming machine control microcomputer according to the tenth aspect, when the memory management unit issues an erase history read command from the external device via the communication control unit Is characterized in that the data to be read is read from the management area of the non-volatile memory unit and passed to the external device.

  The invention according to claim 12 is the gaming machine control microcomputer according to claim 10 or 11, wherein the memory management unit has a function of generating error detection information based on erasure history data, When a memory clear command is received from an external device, the error detection information is written in the management area of the nonvolatile memory unit together with the erase history data.

  According to a thirteenth aspect of the present invention, in the gaming machine control microcomputer according to the twelfth aspect, the memory management unit has a data error detection function using error detection information, and an erase history read command is sent from the external device. When received, the error detection information is read from the management area of the nonvolatile memory unit together with the data to be read, and the presence or absence of a data error is detected based on the error detection information.

  The invention according to claim 14 is the gaming machine control microcomputer according to claim 13, wherein the memory management unit reads the error detection result of the data read from the management area of the nonvolatile memory unit. The data is transmitted to an external device together with the data.

  The invention according to claim 15 is the gaming machine control microcomputer according to claim 13, wherein the memory management unit has an error detection result of data read from the nonvolatile memory unit. The data with the error is skipped, the next order data is read from the management area of the non-volatile memory unit to detect the presence or absence of data error, and only the data with no data error is transmitted to the external device. It is characterized by that.

  The invention according to claim 16 is the gaming machine control microcomputer according to any one of claims 1 to 15, wherein the chip ID is unique identification information for identifying the gaming machine control microcomputer itself. The memory management unit that has received the memory clear command from the external device connected via the communication control unit erases the data in the nonvolatile memory unit, and then the external device The chip ID stored in the chip ID storage unit is transmitted to the external device so that the ID can be stored as a memory clear history together with the date / time information.

  According to the gaming machine control microcomputer according to the present invention, fraud monitoring information or the like cannot be erased unless a clear command is transmitted from a legitimate external device. It becomes difficult and the effectiveness of fraud monitoring can be improved.

It is a schematic block diagram in which a memory reading device is connected to a gaming machine equipped with a gaming machine control microcomputer according to the present invention. It is a block diagram of the microcomputer for game machine control mounted in the main control board. (A) is a data structure figure totaled in a pachinko-type game machine, (b) is a data structure figure totaled in a swivel type game machine. It is a block diagram which shows the input / output related structure which paid its attention to CPU part, memory management part, non-volatile memory part, and communication control part. It is a block diagram which shows the input / output condition in case a CPU part writes data in a non-volatile memory part. It is a block diagram which shows the input / output situation in case a CPU part reads data from a non-volatile memory part. It is a block diagram which shows the input / output condition in case a communication control part reads data from a non-volatile memory by the instruction | indication from a memory reading device. It is a block diagram which shows the input / output condition in case a communication control part erases data per page from a non-volatile memory by the instruction | indication from a memory reading apparatus. It is a block diagram which shows the input / output condition in case a communication control part reads deletion history data from a non-volatile memory by the instruction | indication from a memory reading device.

  Embodiments of a gaming machine control microcomputer according to the present invention will be described below in detail with reference to the accompanying drawings.

  The gaming machine P shown in FIG. 1 is a pachinko gaming machine that can perform a ball game using a game ball. The main control board 1 responsible for controlling the main game progress in the gaming machine P has at least a backup power source 2 that can maintain power supply even after the main power source of the gaming machine P is turned off, and a role provided on the game board surface. Sensors, solenoids, motors, LEDs, and the like (hereinafter collectively referred to as gaming device 3) provided in the physical equipment and various winning awards, and a payout device 4 for paying out game balls are connected.

  The main control board 1 on which the gaming machine microcomputer 10 is mounted can be connected to a memory reading device 200 as an external device via a connection cable 300, and in accordance with an instruction from the memory reading device 200, Data in the computer 10 (for example, data including fraud monitoring information) can be transmitted to the memory reading device 200 or data in the gaming machine microcomputer 10 can be erased.

  FIG. 2 shows a schematic configuration of the gaming machine control microcomputer 10. Inside the gaming machine control microcomputer 10, there is a CPU unit 101 that reads and executes a gaming machine control program stored in the ROM unit 102a, and reads and writes data to and from the RAM unit 102b as needed.

  In the case of the pachinko gaming machine P, an example of the gaming operation by the gaming machine control program is as follows.

  The CPU unit 101 monitors an input signal from a game ball sensor, which is one of the game devices 3, via the input / output port 11 provided on the main control board 1. When the game ball winning is detected, The payout device 4 is instructed to pay out a predetermined number of game balls according to the type of mouth.

  When the winning opening where the game ball has been won is the starting opening, the special symbol apparatus produces an effect such as symbol variation and determines whether or not it is a big hit. The jackpot determination is made based on whether or not the random number value acquired at the timing when it is detected that the game ball has won the start opening matches a predetermined specific value. That is, when the random value acquired at the time of winning the start opening coincides with a specific value, this is determined as a big hit. This process is called an internal lottery of a pachinko game machine.

  The probability of the internal lottery is determined by the range of values that the random number can take and the number of random values that are determined to be a big hit. For example, if the range of values that can be taken by the random number is 0 to 199, and only one value of 7 is determined as the big hit random number value, the big hit probability is 1/200.

  As a jackpot gaming operation to be performed when it is determined that the jackpot is determined as described above, the CPU unit 101 drives the solenoid of the accessory device via the input / output port 11 to open the jackpot and win the prize. Allow game balls to win in the mouth. When the game ball sensor detects the winning of the game ball to the big winning opening via the input / output port 11, the payout device 4 is instructed to pay out the game ball every time a winning is made.

  When it is detected that a predetermined number or more of game balls have been won in the big prize opening, the big prize opening is once closed, but when the big prize opening has not reached the predetermined number of times, the big prize opening is opened again. It should be noted that the number of times that the big winning opening is opened at the time of the big hit is appropriately determined as a specification of the gaming machine together with the probability of the big hit.

  On the other hand, in the case of a revolving game machine, an example of the game operation by the game machine control program is as follows.

  The CPU unit 101 monitors an input signal from a game medal insertion sensor, which is one of the gaming devices 3, via the input / output port 11 mounted on the main control board 1, and confirms that a game medal has been inserted. Detect.

  When more game medals are inserted than the maximum number that can be inserted in one game, the excess game medals are stored inside and the stored number is updated. Note that when a game medal is not inserted but an insertion button is operated, it is considered that a stored game medal has been inserted, and the stored number is reduced and the inserted number is added.

  When the CPU unit 101 detects that the start lever of the rotation device has been operated via the input / output port 11, the CPU unit 101 acquires a random number at the timing when the start lever operation is detected, and uses the value of the random number to acquire the rotation number. When is stopped, it is determined which symbols can be aligned. This process is referred to as an internal lottery of a spinning cylinder type game machine. Here, when it is determined that a certain symbol may be arranged, it is expressed as “set a flag” for the symbol.

  In addition, the CPU unit 101 controls the rotating device by outputting a stepping motor pulse via the input / output port 11.

  When the CPU unit 101 detects that the stop button has been operated via the input / output port 11, the CPU unit 101 stops the rotating cylinder rotated by the rotating cylinder rotating device. If the symbol near the stop position of the rotator is a flagged symbol, the rotator rotation device is controlled so that the symbol stops at the stop position, and the flagged symbol is near the stop position. If not, the rotating device is controlled so that a specific symbol does not align with the stop position. In other words, the symbols are available on the spinning-type gaming machine because the flag is set for a specific symbol by the internal drawing of the spinning-type gaming machine, and the player operates the stop button at the timing when the symbol reaches the stop position. This is the case.

  When the symbols are aligned at the stop position, the CPU unit 101 instructs the payout device 4 to pay out the number of game medals corresponding to the aligned symbols, or increases the number of stored medals accordingly.

  As described above, in both the pachinko gaming machine and the revolving gaming machine, the CPU unit 101 performs all the control of the transition of the gaming state and the control of the insertion and payout of the game medal in each gaming state. The game history is totaled as game information. An example of the aggregation is shown in FIG.

  FIG. 3 (a) shows an example of tabulated data for pachinko machines. Number of shots, number of winning balls, number of starting ball prizes, number of winning mouth prize balls, number of ordinary electric power prize balls, special electric power prize Divide into the number of balls, and total each 2 bytes. FIG. 3 (b) shows an example of aggregated data for a spinning-reel game machine, which includes the number of inputs, the number of games, the number of re-games, the number of advantageous section games, the number of winnings paid out, the number of winnings out, and the number of consecutive winnings Divide and total by 2 bytes each.

  By using the aggregated data as described above, it is possible to determine the suitability according to legal standards or voluntarily defined standards for which gaming machines are not significantly intriguing for customers. As long as the gaming machine P is normally operated, the obtained total data does not deviate from those standards.

  However, when a fraudulent act is performed, the fraudulent act is performed for the purpose of obtaining a fraudulent profit. Therefore, the payout rate deviates from the design value, and such a state can be detected as an abnormality.

  For example, if the control circuit of the main control board 1 is improperly crafted and the internal lottery malfunctions, causing frequent big hits or lengthening the advantageous section, the player will obtain illegal profits. In this case, the payout rate becomes larger than the design value. On the other hand, if the number of winnings in the normal winning opening decreases by bending the pachinko game machine's nails, etc., the amusement hall side will gain unauthorized profits. It becomes smaller than the design value.

  The CPU unit 101 stores the game information in a work area in the RAM unit 102b. The power source of the RAM unit 102b is connected to the backup power source 2, and even if the main power source of the gaming machine P is turned off, game information and the like stored in the RAM unit 102b are not erased.

  However, the backup power source 2 and the main control board 1 are connected by a harness and a connector. If the connector is removed from the main control board 1, the power supply to the RAM unit 102b in the gaming machine control microcomputer 10 is cut off. The game information stored in the RAM unit 102b is erased. That is, if game information that can be used as fraud monitoring information is stored in the RAM unit 102b, there is a risk that game information may be easily deleted by an unauthorized person. This is not necessarily suitable for fraud monitoring.

  Therefore, the gaming machine control microcomputer 10 shown in the present embodiment passes the game information aggregated in the RAM unit 102b by the CPU unit 101 to the memory management unit 103 as aggregated data, and writes the aggregated data in the nonvolatile memory unit 104. The memory management unit 103 is instructed to hold the aggregated data in the nonvolatile memory unit 104 that retains the stored contents even when power is not supplied. In addition, when the memory management unit 103 receives a read command from the CPU unit 101, the memory management unit 103 can read the aggregated data stored in the nonvolatile memory unit 104 and transmit it to the CPU unit 101.

  The game machine control program operating on the CPU unit 101 stores game data in the work area in the RAM unit 102b in the format illustrated in FIG. 3 (in the pachinko game machine P, the data format shown in FIG. 3A). The totalized data is written into the non-volatile memory unit 104 every time an arbitrary timing, for example, 6,000 game balls are fired. Then, after writing the total data to the nonvolatile memory unit 104, the total data in the work area in the RAM 102b is cleared, and the subsequent total is continued.

  In this way, the non-volatile memory unit 104 accumulates game data (aggregated data) aggregated for every 6,000 game balls that have been launched. The accumulated data is read 10 times retroactively from the latest data, and the data for the latest 60,000 released game balls can be calculated by counting 10 times. it can. In the pachinko game machine, there are about 100 game balls that can be fired per minute, so the time to fire 6,000 game balls is about 1 hour, and in the case of 60,000, it is about 10 hours. .

  As described above, although the gaming machine P progresses based on a preset probability, even if it is a normal gaming machine, the short-term play rate varies greatly and is used as a criterion for judging whether there is fraud. Is not appropriate. The legal standards are also defined by the 1-hour and 10-hour payout rates, so aggregate data is stored in the non-volatile memory unit 104 every relatively short period, and a predetermined amount of aggregate data is accumulated. By the way, it is possible to check whether or not the gaming machine P satisfies the statutory standard by reading and counting the total data in a bundle.

  In addition, the nonvolatile memory unit 104 can not only read the stored content written but also erase it, but the memory reading device 200 is used to erase the data in the nonvolatile memory unit 104. There is a need. That is, only when the memory management unit 103 receives a memory clear command from the memory reading device 200 via the interface 12 and the communication control unit 105, the memory management unit 103 deletes data in the nonvolatile memory unit 104. It is executed.

  On the other hand, by not defining a clear command for erasing the stored contents of the nonvolatile memory unit 104 in the regular game machine control program, from the CPU unit 101 executing the regular game machine control program to the memory management unit 103 The memory clear command is not transmitted, and the data in the nonvolatile memory unit 104 is not erased by an instruction from the CPU unit 101 during normal operation. In addition, the memory management unit 103 does not accept the memory clear command from the CPU unit 101.

  In this way, an illegal memory clear command is transmitted from the CPU unit 101 to the memory management unit 103 or the program runs away due to noise or the like because the gaming machine control program stored in the ROM unit 102b is falsified. Even if the CPU unit 101 operates differently from the original game machine control program, the memory management unit 103 does not accept and execute the memory clear command from the CPU unit 101. Data in the nonvolatile memory unit 104 is not lost.

  A method for not allowing the memory management unit 103 to accept the memory clear command from the CPU unit 101 is not particularly limited. For example, when the memory management unit 103 receives a memory clear command, if the transmission source of the memory clear command is not the communication control unit 105, the memory management unit 103 does not accept the data so that the data in the nonvolatile memory unit 104 cannot be cleared. May be. Alternatively, the memory management unit 103 is provided with two physically different ports, and the memory clear command is not defined in the register of the port corresponding to the CPU unit 101, so that the memory from the CPU unit The clear command may not be accepted.

  Alternatively, a CPU-side transmission source marking unit 106 a is provided on the transmission path from the CPU unit 101 to the memory management unit 103, and a memory management unit-side transmission source marking unit 106 b is provided on the transmission path from the communication control unit 105 to the memory management unit 103. By marking the command transmitted from the CPU unit 101 to the memory management unit 103 with a marking indicating that the command has been transmitted from the CPU unit 101, the command transmitted from the communication control unit 105 to the memory management unit 103 is added. Is marked with a mark indicating that it has been transmitted from the communication control unit 105, so that the memory management 103 is information of the transmission source marked in the memory clear command (command from the CPU unit 101 or command from the communication control unit 105. ) To determine whether to accept the received memory clear command.

  The marking method performed by the CPU-side transmission source marking unit 106a or the memory management unit-side transmission source marking unit 106b may be appropriately adopted. For example, when a 1-byte command is transmitted through the transmission path from the CPU unit 101 to the memory management unit 103, a circuit that unconditionally performs a logical OR with “10000000” is used as the CPU-side transmission source marking unit 106a. Then, the most significant bit of the command accepted by the memory management unit 103 is always “1”. When a 1-byte command is transmitted on the transmission path from the communication control unit 105 to the memory management unit 103, a circuit that unconditionally ANDs “01111111” as the memory management unit side transmission source marking unit 106b. When used, the most significant bit of the command accepted by the memory management unit 103 is always “0”.

  That is, the most significant bit of the command that has reached the memory management unit 103 via the CPU side transmission source marking unit 106a is always “1”, and the command that has reached the memory management unit 103 via the memory management unit side transmission unit marking unit 106b. Since the most significant bit is always “0”, even if the transmission source of the memory clear command can be camouflaged, the transmission source can be reliably determined by whether the most significant bit is “0” or “1”. .

  Accordingly, the memory management unit 103 that has received the memory clear command does not clear the nonvolatile memory unit 104 when the most significant bit is “1”, and is non-volatile when the most significant bit is “0”. If it is set to execute clearing of the memory unit 104, a configuration in which the memory clear command from the CPU unit 101 is not accepted can be realized.

  Note that only one of the CPU-side transmission source marking unit 106a and the memory management unit-side transmission source marking unit 106b may be provided. For example, when only the CPU side sender marking unit 106a is provided, the memory management unit 103 may be set not to accept only when the most significant bit of the memory clear command is “1”. When only the part-side transmission source marking unit 106b is provided, the memory management unit 103 may accept only when the most significant bit of the memory clear command is “0”.

  On the other hand, when the gaming machine P is operated under a different operating condition after being operated under a normal operating condition, or as a result of the gaming machine P being distributed as a used machine, as in the operation test of the gaming machine P. It is necessary to erase the game information up to that time, such as when the game is started in a different game hall from the game hall that has been in operation, and in such a case, using the memory clear function of the memory reading device 200, Data in the nonvolatile memory unit 104 is erased.

  The memory reading device 200 reads from the clock / calendar function unit 201 capable of acquiring date / time information, the device ID storage unit 202 that stores a device ID that can identify the device itself, and the nonvolatile memory unit 104. A data storage unit 203 capable of storing the total data and the like, and a display unit 204 for visually displaying the data stored in the data storage unit 203.

  When erasing data in the nonvolatile memory unit 104 by the memory reading device 200, the memory reading device 200 is connected to the communication control unit 105 of the gaming machine microcomputer 10 via the interface 12, and a memory clear command is sent from the memory reading device 200. Is transmitted to the communication control unit 105, and the communication control unit 105 that has received the command transmits a memory clear command for erasing the contents of the nonvolatile memory unit 104 to the memory management unit 103, and receives the memory management. The unit 103 erases the contents of the nonvolatile memory unit 104.

  Also, the device ID and date / time information are included in the message of the memory clear command transmitted from the memory reading device 200 to the communication control unit 105, and the clear command and device ID from the memory reading device 200 are transmitted via the communication control unit 105. The memory management unit 103 that has received the date / time information erases the data area 104a of the non-volatile memory unit 104 and writes the device ID and date / time information in the management area 104b, thereby executing the memory clear unit and the execution date / time. It is possible to store history information (erase history data) including “” in the nonvolatile memory unit 104.

  After the memory clear execution to the data area 104a and the deletion history data to the management area 104b are completed, the memory management unit 103 transmits a memory erasure completion report to the communication control unit 105. The chip ID 106 is transmitted to the memory reading device 200 together with the erasure completion report. The chip ID is unique identification information that can identify the gaming machine control microcomputer 10 itself, and is stored in the chip ID storage unit 107.

  The memory reading device 200 that has received the memory erasure completion report from the communication control unit 105 stores the received chip ID and date / time information in the data storage unit 203. The date / time information stored together with the chip ID may be date / time information when the memory clear command is transmitted, or may be date / time information when the chip ID is received from the communication control unit 105.

  As described above, when erasing the contents of the non-volatile memory unit 104, it is important to record when and who performed it in order to determine whether it is an unauthorized operation. For this purpose, correct date and time information must be acquired. If the date and time information for that purpose is transmitted from the memory reading device 200, it is not necessary to provide a clock / calendar function inside the gaming machine control microcomputer 10, so that the deletion history data can be easily recorded.

  Next, details of commands and data performed between the CPU unit 101, the memory management unit 103, the nonvolatile memory unit 104, and the communication control unit 105 will be described. As shown in the block diagram of FIG. 4, the CPU unit 101 performs transmission / reception with the first input / output port 103a of the memory management unit 103 via an internal register, and the communication control unit 105 transmits via an internal register. The transmission / reception is performed with the second input / output port 103 b of the memory management unit 103. The memory management unit 103 performs transmission / reception with the data area 104a and the management area 104b of the nonvolatile memory unit 104 via the first input / output port 103a and the second input / output port 103b. Note that an input / output port dedicated to transmission / reception with the nonvolatile memory unit 104 may be separately provided in the memory management unit 103 so that reading / writing and erasing of the nonvolatile memory unit 104 can be performed from the dedicated input / output port.

  First, processing when the game information collected by the CPU unit 101 is written in the nonvolatile memory unit 104 will be described with reference to FIG.

  The CPU unit 101 writes data to be saved (aggregated data) to a data register provided in the first input / output port of the memory management unit 103, and a write command is provided in the first input / output port of the memory management unit 103. Write to the command register. When a write command is written to the command register, the memory management unit 103 starts processing to save the contents of the data register in the data area 104a of the nonvolatile memory unit 104.

  Note that the nonvolatile memory unit 104 used in the present embodiment is configured by, for example, a flash memory. The flash memory is a nonvolatile memory that can erase data in units of pages. The nonvolatile memory unit 104 in this configuration example includes four pages from page 0 to page 3, and page 0 and page 1 are allocated to the data area 104a, and page 2 and page 3 are allocated to the management area 104b. Can be used only by the memory management unit 103. In addition to the flash memory, MRAM, ReRAM, FeRAM, or the like may be used as the nonvolatile memory unit 104.

  The memory management unit 103 accesses the page by dividing it into a plurality of equal-sized blocks, and manages each block with a serial number that monotonously increases as a block number (for example, 2 bytes long).

  Further, in the flash memory, when data is erased in units of pages, the data read from each block is FFh. Therefore, if FFh or FFFFh is omitted from the block numbers, only written blocks can be searched. Since the maximum value of the block numbers of the written blocks obtained by the search indicates the last written block number, the newly written total data can be written in the next block. If no unwritten block remains in the page, the data of other pages can be erased (for example, page 1 can be erased when page 0 is full) and the subsequent data block can be written. .

  The memory management unit 103 adds the block number to the data (aggregated data) received from the CPU unit 101 in this way, and writes it to the data area 104a of the nonvolatile memory unit 104. Note that after the instructed total data is written in the data area 104 a of the nonvolatile memory unit 104, the completion of writing may be reported from the memory management unit 103 to the CPU unit 101.

  Next, processing when the CPU unit 101 reads the aggregated data from the nonvolatile memory unit 104 will be described with reference to FIG.

  When it is desired to read the total data stored in the nonvolatile memory unit 104, the CPU unit 101 writes a read command to a command register provided in the first input / output port 103a of the memory management unit 103. In this case, a numerical value for designating what block is read from the latest block is also designated.

  Upon receipt of the read command, the memory management unit 103 searches for the latest block from the block number, specifies the block in the range specified in the command register with reference to the latest block, and outputs the aggregated data to the first input / output The data is read into the data register of the port 103a and transmitted to the register of the CPU unit 101.

  The CPU unit 101 that has received the aggregated data for a plurality of blocks further aggregates them and processes them into game data that can determine whether there is fraud. For example, the display unit 13 provided on the exterior cover of the main control board 1 or the like. It may be displayed. In this way, a game clerk or the like of the game store can determine whether or not the gaming machine P is illegal by looking at the display content of the display 13. Alternatively, the game machine control program executed by the CPU unit 101 is provided with a function for determining whether or not the probability of fraud is high based on the game data, and the determination result (whether the probability of fraud is high is determined). (Determination result) may be displayed on the display 13.

  As described above, the CPU unit 101 can perform data writing to the nonvolatile memory unit 104 and data reading from the nonvolatile memory unit 104 via the memory management unit 103. Moreover, as described above, since no erase command is defined in the command register of the first input / output port 103a of the memory management unit 103, no matter what program is executed by the CPU unit 101, Since the memory management unit 103 does not accept a memory clear command for erasing the nonvolatile memory unit 104, data in the nonvolatile memory unit 104 is not erased by a command from the CPU unit 101.

  Next, processing when the communication control unit 105 reads aggregated data from the nonvolatile memory unit 104 according to an instruction from the memory reading device 200 will be described with reference to FIG.

  When the memory reading device 200 wants to read the total data stored in the non-volatile memory unit 104, when the memory reading device 200 transmits a read command to the communication control unit 105, the communication control unit 105 that has received the command The read command is written to the command register provided in the second input / output port 103b of the management unit 103. In this case, a numerical value for designating what block is read from the latest block is also designated.

  Upon receipt of the read command, the memory management unit 103 searches for the latest block from the block number, specifies the block in the range specified in the command register with the latest block as a reference, and outputs the aggregated data to the second input / output The data is read to the data register of the port 103b, transmitted to the register of the communication control unit 105, and further transmitted to the memory reading device 200.

  Note that the memory reading device 200 may further aggregate the received aggregated data for a plurality of blocks, process it into game data that can determine whether there is fraud, and display it on the display unit 204. In this way, an operator of the memory reading device 200 can determine whether or not the gaming machine P is illegal by looking at the display content of the display unit 204. Alternatively, the memory reading device 200 is provided with a function for determining whether or not the probability of fraud is high from the game data, and the determination result (the determination result whether or not the probability of fraud is high) is displayed on the display unit 204. It may be displayed.

  Next, processing when the communication control unit 105 deletes data from the nonvolatile memory unit 104 according to an instruction from the memory reading device 200 will be described with reference to FIG.

  Upon receiving the memory clear command, device ID, and date / time information from the memory reading device 200, the communication control unit 105 transfers the memory clear command, device ID, and date / time information to the command register provided in the second input / output port 103b of the memory management unit 103. Write.

  Receiving this, the memory management unit 103 erases the data of page 0 and page 1 which is the data area 104a of the nonvolatile memory unit 104, and erases the data to the unwritten block of page 2 or page 3 which is the management area 104b. Write data (device ID and execution date / time). The page and block management method in the management area 104b is the same as that in the data area 104a described above.

  Note that erasure of the data area 104a by the memory reading device 200 is not limited to erasing all pages, and only a specified specific page may be erased. Further, when page erasure is executed by the memory management unit 103, a memory erasure completion report is sent from the memory management unit 103 to the communication control unit 105. Accordingly, the communication control unit 105 sends a chip to the memory reading device 200. Send ID. In this way, after the memory reading device 200 transmits a memory clear command to the gaming machine control microcomputer 10 and erases the data in the nonvolatile memory portion, the memory reading device 200 stores the memory clear history (chip ID, date information). The data can be stored in the data storage unit 203, and the gaming machine control microcomputer 10 in which the memory is erased by the memory reading device 200 and the execution date and time can be recorded.

  Next, processing in the case where the communication control unit 105 reads erasure history data from the management area 104b of the nonvolatile memory unit 104 according to an instruction from the memory reading device 200 will be described with reference to FIG.

  The communication control unit 105 that has received the erase history read command from the memory reading device 200 writes the erase history read command to the command register provided in the second input / output port 103 b of the memory management unit 103. At this time, a numerical value for specifying how many blocks are read back from the latest block is also specified.

  Receiving this, the memory management unit 103 identifies the designated block from the management area 104b and reads the erase history data written in each block in the designated range as the second input, in the same way as when reading the aggregated data from the data area 104a. Reading to the data register of the output port 103b and notifying the communication control unit 105 of the completion of reading. Communication control unit 105 transmits the read erasure history data to memory reading device 200.

  Thus, in the gaming machine control microcomputer 10 according to the present embodiment, the memory management unit 103 clearly distinguishes the command from the CPU unit 101 and the command from the communication control unit 105. Regardless of whether or not there is, the CPU unit 101 cannot erase the aggregated data from the non-volatile memory unit 104, and the fictitious game data is non-volatile by communication from an external device such as the memory reading device 200. It is not added to the memory unit 104. Therefore, the aggregate data stored in the nonvolatile memory unit 104 can be used as highly reliable fraud monitoring information, and is suitable for determining whether the gaming machine P is fraudulent.

  In addition, when the memory management unit 103 receives the aggregated data from the CPU unit 101, the memory management unit 103 not only writes the data to the data area 104a of the nonvolatile memory unit 104 as it is, but also detects error detection information (error detection code or error correction code) based on the aggregated data. ) And the error detection information may be written in the same block together with the total data. In this way, when the memory management unit 103 receives a read command from the CPU unit 101 or the memory reading device 200, the error detection information is read from the corresponding block together with the total data, and the calculation is performed according to a certain procedure. It is possible to detect whether there is an error in the read aggregated data. Further, when an error correction code is used as error detection information, there is a possibility that errors in the read aggregated data can be corrected.

  As described above, if the memory management unit 103 has the error detection information generation function based on the write data and the data error detection function using the error detection information, the storage element of the nonvolatile memory unit 104 If the total data is not accurately stored in the data area 104a due to the failure of the memory, the memory management unit 103 can detect that there is an error in the total data. The reliability of the total data stored in the data area 104a can be ensured.

  For example, the error management result (presence / absence of error) performed by the memory management unit 103 on the total data read from the block of the data area 104a may be transmitted to the read command transmission source together with the read total data. good. In this way, it is possible to determine whether or not to use the aggregated data as fraud monitoring information from the error detection result in the CPU unit 101 or the memory reading device 200 that is the transmission source of the read command. When an error correction code is used as the error detection information, the error correction status (error repair is possible / impossible) for the read aggregated data may be transmitted together.

  Alternatively, if the error detection result performed by the memory management unit 103 on the aggregated data read from the block of the data area 104a is an error, the aggregated data with the error is used instead of transmitting the aggregated data with the error. May be skipped, and the read block may be traced back to the next order to read the total data, and only the total data with no error may be transmitted to the read command transmission source. In this way, only the aggregated data without error is transmitted to the CPU unit 101 or the memory reading device 200 that is the transmission source of the read command, and therefore the aggregated data received by the CPU unit 101 or the memory reading device 200 is illegal monitoring. Information can be treated as highly reliable.

  Also, when the memory management unit 103 receives a memory clear command from the memory reading device 200, the memory management unit 103 not only writes the erasure history data as it is to the management area 104b of the nonvolatile memory unit 104 but also detects an error based on the erasure history data. Information may be generated, and this error detection information may be written in the same block together with the erasure history data. In this way, when the memory management unit 103 receives an erase history read command from the memory reading device 200, the error detection information is read together with the erase history data of the designated block, and the calculation is performed according to a certain procedure. It is possible to detect whether there is an error in the erase history data. In addition, when an error correction code is used as error detection information, there is a possibility that an error in the read erasure history data can be corrected.

  Therefore, if the memory management unit 103 having a function of generating error detection information based on data for writing and a data error detection function using error detection information manages the writing / reading of erasure history data, the nonvolatile memory If the erasure history data is not accurately stored in the management area 104b due to a failure of the storage element of the volatile memory unit 104, the memory management unit 103 detects that the erasure history data is incorrect Therefore, the reliability of the erase history data stored in the management area 104b of the nonvolatile memory unit 104 can be ensured.

  For example, the error detection result (presence / absence of error) performed by the memory management unit 103 on the erase history data read from the block of the management area 104b is transmitted to the memory reading device 200 together with the read erase history data. May be. In this way, the memory reading device 200 can determine the reliability of the erase history data from the error detection result. When an error correction code is used as the error detection information, the error correction status (error repair is possible / not possible) for the read erasure history data may be transmitted together.

  Alternatively, if the error detection result that the memory management unit 103 has performed on the erase history data read from the block of the management area 104b has an error, the error exists instead of transmitting the erase history data with the error. The erasure history data may be skipped, the erasure history data may be read back to the next order in the read block, and only the erasure history data with no error may be transmitted to the memory reading device 200. In this way, since only the erasure history data without error is transmitted to the memory reading device 200, the erasing history data received by the memory reading device 200 can be treated as having high reliability.

  If there is an error in the data read from the block of the data area 104a or the management area 104b by the memory management unit 103, the data is managed as a closed block in which writing to the corresponding block is not performed. In such a case, for example, a memory warning signal is transmitted to the CPU unit 101 and displayed on the display unit 13 in order to notify the possibility that the lifetime due to deterioration of the nonvolatile memory unit 104 is approaching. Also good.

  As mentioned above, although embodiment of the microcomputer for game machines concerning this invention was described based on the accompanying drawing, this invention is not limited to this embodiment, The structure as described in a claim is not changed. In the range, it may be carried out by diverting known equivalent technical means.

DESCRIPTION OF SYMBOLS 1 Main control board 10 Microcomputer for game machine control 101 CPU part 102b RAM part 103 Memory management part 104 Non-volatile memory part 105 Communication control part 107 Chip ID memory | storage part 200 Memory reader

Claims (16)

At least a ROM unit that stores a game machine control program, a CPU unit that controls the gaming machine based on the game machine control program stored in the ROM unit, and the CPU unit that executes the game machine control program In a one-chip gaming machine control microcomputer comprising a RAM unit that can be used as a work area,
Even if the power supply is cut off, a nonvolatile memory unit that retains the memory content written during operation of the gaming machine,
A memory management unit capable of writing to and erasing the nonvolatile memory unit;
A communication control unit that relays communication between the external device connected from the outside of the gaming machine and the memory management unit, and allows the external device to access the nonvolatile memory unit;
With
The memory management unit
When a write command is issued from the CPU unit, the data received from the CPU unit is written to the nonvolatile memory unit,
When a read command is issued from the CPU unit, the data to be read is read from the non-volatile memory unit and passed to the CPU unit,
When a memory clear command is issued from the external device via the communication control unit, the data is erased from the nonvolatile memory unit,
When a read command is issued from the external device via the communication control unit, data to be read is read from the nonvolatile memory unit and passed to the external device.
A microcomputer for controlling a gaming machine, characterized by being configured as described above.   The memory management unit makes the memory clear command from the CPU unit unacceptable, and depending on the memory clear command issued based on the gaming machine control program stored in the ROM unit, the data in the nonvolatile memory unit The gaming machine control microcomputer according to claim 1, wherein the microcomputer cannot be cleared.   The memory management unit, when receiving a memory clear command, if the transmission source of the memory clear command is not a communication control unit, by not accepting it, the data in the nonvolatile memory unit cannot be cleared. The microcomputer for game machine control according to claim 2, characterized in that: The memory management unit
A port for receiving commands and data from the CPU unit and a port for receiving commands and data from the communication control unit are provided separately,
3. The gaming machine system according to claim 2, wherein a memory clear command from the CPU unit cannot be accepted by not defining a memory clear command in a register of a port corresponding to the CPU unit. Your microcomputer. Provided on the transmission path from the CPU section to the memory management section, and provided on the transmission path from the communication control section to the memory management section, and / or the transmission source marking section for attaching the transmission content to the CPU. Provided with a sender marking unit that attaches to the transmission content that the sender is a communication control unit,
3. The gaming machine control device according to claim 2, wherein the memory management unit determines whether or not to accept the memory clear command based on information of a transmission source marked in the memory clear command. Microcomputer.   The memory management unit has a function of generating error detection information based on write data. When a write command is received from the CPU unit, the memory management unit stores the error detection information together with the write data in the nonvolatile memory. The gaming machine control microcomputer according to any one of claims 1 to 5, characterized in that the microcomputer is written in the section.   The memory management unit has a data error detection function using error detection information. When a read command is received from the CPU unit or the external device, error detection information is read from the nonvolatile memory unit together with data to be read. 7. The gaming machine control microcomputer according to claim 6, wherein the microcomputer detects the presence or absence of a data error based on the read error detection information.   8. The gaming machine system according to claim 7, wherein the memory management unit transmits an error detection result of data read from the non-volatile memory unit together with the read data to a read command transmission source. Your microcomputer.   When the error detection result of the data read from the non-volatile memory unit has an error, the memory management unit skips the data with the error and reads the next order data from the non-volatile memory unit 8. The gaming machine control microcomputer according to claim 7, wherein presence or absence of an error is detected, and only data having no data error is transmitted to a read command transmission source. The non-volatile memory unit has a data area for storing data requested to be written by the CPU unit, and a management area for storing data used by the memory management unit for management of the non-volatile memory unit,
The memory management unit that has received the unique identification information that can identify the device itself and the date / time information based on the clock / calendar function of the external device, together with the memory clear command, from the external device connected via the communication control unit, The contents of the data area in the non-volatile memory unit are erased, and the erase history data including the identification information and date / time information of the external device received together with the memory clear command is stored in the management area. A microcomputer for gaming machine control according to any one of claims 1 to 9.   When an erase history read command is issued from the external device via the communication control unit, the memory management unit reads data to be read from the management area of the nonvolatile memory unit and passes the read data to the external device. 11. The gaming machine control microcomputer according to claim 10, characterized in that it is configured as described above.   The memory management unit has a function of generating error detection information based on erasure history data, and when receiving a memory clear command from the external device, the nonvolatile memory unit stores error detection information together with erasure history data. 12. The gaming machine control microcomputer according to claim 10, wherein the microcomputer is used for writing to the management area.   The memory management unit has a data error detection function using error detection information, and when an erase history read command is received from the external device, the error detection information together with the data to be read from the management area of the nonvolatile memory unit 13. The gaming machine control microcomputer according to claim 12, wherein the presence or absence of a data error is detected based on the error detection information.   14. The game according to claim 13, wherein the memory management unit transmits an error detection result of data read from the management area of the nonvolatile memory unit together with the read data to an external device. Microcomputer for machine control.   When the error detection result of the data read from the non-volatile memory unit has an error, the memory management unit skips the data with the error and reads the next rank data from the management area of the non-volatile memory unit. 14. The gaming machine control microcomputer according to claim 13, wherein the microcomputer is used to read and detect the presence or absence of a data error, and to transmit only data having no data error to an external device. A chip ID storage unit for storing a chip ID, which is unique identification information for identifying the gaming machine control microcomputer itself;
After the memory management unit receiving the memory clear command from the external device connected via the communication control unit erases the data in the nonvolatile memory unit, the external device uses the chip ID as the memory clear history together with the date / time information. The gaming machine control according to any one of claims 1 to 15, wherein the chip ID stored in the chip ID storage unit is transmitted to the external device so as to be stored. Microcomputer.

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