JP2018088300A5 - - Google Patents

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Publication number
JP2018088300A5
JP2018088300A5 JP2016231457A JP2016231457A JP2018088300A5 JP 2018088300 A5 JP2018088300 A5 JP 2018088300A5 JP 2016231457 A JP2016231457 A JP 2016231457A JP 2016231457 A JP2016231457 A JP 2016231457A JP 2018088300 A5 JP2018088300 A5 JP 2018088300A5
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JP
Japan
Prior art keywords
storage element
resistance change
complementary
change
writing
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JP2016231457A
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English (en)
Japanese (ja)
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JP6822657B2 (ja
JP2018088300A (ja
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Priority to JP2016231457A priority Critical patent/JP6822657B2/ja
Priority claimed from JP2016231457A external-priority patent/JP6822657B2/ja
Priority to US16/463,938 priority patent/US10896729B2/en
Priority to PCT/JP2017/039354 priority patent/WO2018100954A1/ja
Publication of JP2018088300A publication Critical patent/JP2018088300A/ja
Publication of JP2018088300A5 publication Critical patent/JP2018088300A5/ja
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Publication of JP6822657B2 publication Critical patent/JP6822657B2/ja
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JP2016231457A 2016-11-29 2016-11-29 抵抗変化型記憶素子のデータ書き込み装置 Active JP6822657B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2016231457A JP6822657B2 (ja) 2016-11-29 2016-11-29 抵抗変化型記憶素子のデータ書き込み装置
US16/463,938 US10896729B2 (en) 2016-11-29 2017-10-31 Data write circuit of resistive memory element
PCT/JP2017/039354 WO2018100954A1 (ja) 2016-11-29 2017-10-31 抵抗変化型記憶素子のデータ書き込み装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016231457A JP6822657B2 (ja) 2016-11-29 2016-11-29 抵抗変化型記憶素子のデータ書き込み装置

Publications (3)

Publication Number Publication Date
JP2018088300A JP2018088300A (ja) 2018-06-07
JP2018088300A5 true JP2018088300A5 (https=) 2020-01-16
JP6822657B2 JP6822657B2 (ja) 2021-01-27

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JP2016231457A Active JP6822657B2 (ja) 2016-11-29 2016-11-29 抵抗変化型記憶素子のデータ書き込み装置

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US (1) US10896729B2 (https=)
JP (1) JP6822657B2 (https=)
WO (1) WO2018100954A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9583187B2 (en) * 2015-03-28 2017-02-28 Intel Corporation Multistage set procedure for phase change memory
US10276794B1 (en) 2017-10-31 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and fabrication method thereof
KR102641097B1 (ko) * 2018-12-31 2024-02-27 삼성전자주식회사 저항성 메모리 장치 및 저항성 메모리 장치의 프로그램 방법
JP7000370B2 (ja) * 2019-03-13 2022-01-19 株式会社東芝 磁気記憶装置
JP7185748B1 (ja) * 2021-12-07 2022-12-07 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011192345A (ja) * 2010-03-15 2011-09-29 Fujitsu Ltd スピン注入型ｍｒａｍ、並びにその書き込み方法及び読み出し方法
JP2012203944A (ja) * 2011-03-24 2012-10-22 Toshiba Corp 抵抗変化型メモリ
JP5267626B2 (ja) * 2011-08-24 2013-08-21 凸版印刷株式会社 不揮発性メモリセルおよび不揮発性メモリ
US8995180B2 (en) * 2012-11-29 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Magnetoresistive random access memory (MRAM) differential bit cell and method of use
US9928906B2 (en) * 2014-03-24 2018-03-27 Tohoku University Data-write device for resistance-change memory element

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