JP2018061242A - Solid state image sensor, driving method of solid state image sensor, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image sensor, a driving method of solid state image sensor, and an electronic apparatus capable of preventing degradation of area efficiency on layout, while preventing complication of configuration.SOLUTION: A pixel portion 20 includes a first pixel array where the photoelectric conversion reading parts 211 of multiple first pixels 21 are arranged in matrix, a holding part array where the signal holding parts 212 of multiple first pixels 21 are arranged in matrix, and a second pixel array where the photoelectric conversion reading parts 221 of multiple second pixels 22 are arranged in matrix. At the time of rolling shutter mode, the read signals of the photoelectric conversion reading parts of first and second elements are outputted immediately to a first perpendicular signal line LSGN11 without following the bypass route, and at the time of global shutter mode, the holding signal of the signal holding part of the first pixel is outputted to the second perpendicular signal line LSGN12.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a solid-state imaging device, a driving method for the solid-state imaging device, and an electronic apparatus.

A CMOS (Complementary Metal Oxide Semiconductor) image sensor has been put to practical use as a solid-state imaging device (image sensor) using a photoelectric conversion element that detects light and generates charges.
CMOS image sensors are widely applied as a part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and mobile terminal devices (mobile devices) such as mobile phones. Yes.

  The CMOS image sensor has an FD amplifier having a photodiode (photoelectric conversion element) and a floating diffusion layer (FD: Floating Diffusion) for each pixel, and the readout selects one row in the pixel array. However, a column parallel output type in which these are simultaneously read in the column output direction is the mainstream.

By the way, in the CMOS image sensor, an operation of sequentially scanning and reading out the photoelectric charge generated and accumulated by the photodiode for each pixel or for each row is performed.
When this rolling scan, that is, when a rolling shutter is employed as an electronic shutter, the start time and end time of exposure for accumulating photocharges cannot be made to coincide for all pixels. Therefore, in the case of sequential scanning, there is a problem that a captured image is distorted when a moving subject is imaged.

  Therefore, in imaging applications where image distortion is unacceptable and imaging is performed at a high speed, or in sensing applications that require simultaneous image capture, exposure is started at the same timing for all pixels in the pixel array unit as an electronic shutter. A global shutter that executes the end of exposure is employed.

In a CMOS image sensor that employs a global shutter as an electronic shutter, for example, a signal holding unit that holds a signal read from a photoelectric conversion reading unit in a signal holding capacitor is provided in a pixel.
In a CMOS image sensor that employs a global shutter, electric charges from photodiodes are simultaneously accumulated as voltage signals in a signal holding capacitor of a signal holding unit, and then sequentially read out to ensure simultaneity of the entire image (for example, Non-Patent Document 1).
This CMOS image sensor has a bypass switch that bypasses the signal holding unit and transfers the output of the photoelectric conversion readout unit to the signal line, and has a rolling shutter function in addition to the global shutter function. Has been.

  The stacked CMOS image sensor described in Non-Patent Document 1 has a stacked structure in which a first substrate (Pixel die) and a second substrate (ASIC die) are connected through micro bumps (connecting portions). A photoelectric conversion readout unit for each pixel is formed on the first substrate, and a signal holding unit, a signal line, a vertical scanning circuit, a horizontal scanning circuit, a column readout circuit, etc. are formed on the second substrate. ing.

J. Aoki, et al., “A Rolling-Shutter Distortion-Free 3D Stacked Image Sensor with -160dB Parasitic Light Sensitivity In-Pixel Storage Node” ISSCC 2013 / SESSION 27 / IMAGE SENSORS / 27.3.

The conventional CMOS image sensor having the global shutter function described above shares a signal line with both the global shutter function and the rolling shutter function, and therefore holds a bypass switch that bypasses the signal holding unit and transfers it to the signal line. Since it is necessary to provide parallel to the part, there are the following disadvantages.
Since the multilayer CMOS image sensor having the conventional global shutter function described above includes a pixel and a global shutter signal holding capacitor in a pair on the first substrate (Pixel die) and the second substrate (ASIC die), The area required for the peripheral circuit on the second substrate (ASIC die) side becomes an overhead, and there is a problem that the area efficiency is low.
Further, in the above-described CMOS image sensor, the configuration on the signal holding unit side is complicated.

  An object of the present invention is to provide a solid-state imaging device, a driving method for the solid-state imaging device, and an electronic apparatus that can prevent a reduction in area efficiency in the layout while preventing complication of the configuration.

  In the solid-state imaging device according to the first aspect of the present invention, at least the first pixel is arranged among a first pixel including a photoelectric conversion readout unit and a signal holding unit and a second pixel including the photoelectric conversion readout unit. A pixel unit, a readout unit that reads out a pixel signal from the pixel unit, a first signal line that outputs a readout signal of the photoelectric conversion readout unit, and a holding signal of the signal holding unit And at least the photoelectric conversion readout unit of the first pixel includes an output node, a photoelectric conversion element that accumulates charges generated by photoelectric conversion in an accumulation period, and the photoelectric conversion element A transfer element capable of transferring the accumulated charge during a transfer period, a floating diffusion to which the charge accumulated in the photoelectric conversion element is transferred through the transfer element, and the floating diffusion A source follower element that converts the charge of the fusion into a voltage signal corresponding to the amount of charge, and outputs the converted signal to the output node; a reset element that resets the floating diffusion to a predetermined potential during a reset period; A selection element that electrically connects the output node to the first signal line in a period, and the signal holding unit outputs a signal output from the output node of the photoelectric conversion readout unit of the first pixel , A switch element that selectively connects the signal holding capacitor to the output node of the photoelectric conversion readout unit in the second period, and held in the signal holding capacitor in the second period. Including a source follower element that outputs the received signal according to the holding voltage, and selectively outputs the converted signal to the second signal line. It includes a part, a.

  According to a second aspect of the present invention, there is provided a first pixel including a photoelectric conversion readout unit and a signal holding unit, a pixel unit in which a second pixel including the photoelectric conversion readout unit is disposed, and a pixel signal from the pixel unit. A readout unit that performs readout, a first signal line that outputs a readout signal of the photoelectric conversion readout unit, and a second signal line that outputs a retention signal of the signal holding unit, and at least the The photoelectric conversion readout unit of the first pixel includes an output node, a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period, and a transfer that can transfer charges accumulated in the photoelectric conversion element during a transfer period. Element, a floating diffusion to which charges accumulated in the photoelectric conversion element are transferred through the transfer element, and a voltage signal corresponding to the charge amount of the charges in the floating diffusion A source follower element that converts and outputs the converted signal to the output node; a reset element that resets the floating diffusion to a predetermined potential in a reset period; and the output node in the first period as the first signal line. A signal holding capacitor capable of holding a signal output from an output node of the photoelectric conversion readout unit of the first pixel, and a second holding element. A switching element that selectively connects the signal holding capacitor to the output node of the photoelectric conversion readout unit during a period, and a source follower that outputs a signal held in the signal holding capacitor during the second period according to a holding voltage And an output unit that selectively outputs a converted signal to the second signal line. The pixel unit includes a plurality of the first signals. A first pixel array in which the photoelectric conversion readout units of the pixels are arranged in a matrix; a holding unit array in which the signal holding units of the plurality of first pixels are arranged in a matrix; and a plurality of the first pixels And a second pixel array in which the photoelectric conversion read-out units of the two pixels are arranged in a matrix, and in the first operation, the first of the first pixels The pixel signal is read by activating the second pixel array of the first pixel array and the second pixel, and the photoelectric conversion reading of the first pixel and the second pixel is performed during the second operation. The pixel signal is read by activating the first pixel array and the holding unit array of the first pixel in a state where the selection element in the unit is in a non-selected state.

  An electronic apparatus according to a third aspect of the present invention includes a solid-state imaging device and an optical system that forms a subject image on the solid-state imaging device. The solid-state imaging device includes a photoelectric conversion readout unit and a signal holding unit. Among the first pixel including the pixel and the second pixel including the photoelectric conversion readout unit, a pixel unit in which at least the first pixel is arranged, a readout unit that reads out a pixel signal from the pixel unit, and the photoelectric conversion unit A first signal line from which a read signal of the conversion read unit is output; and a second signal line from which the hold signal of the signal holding unit is output, and at least the photoelectric conversion reading of the first pixel. The unit includes an output node, a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period, a transfer element that can transfer charges accumulated in the photoelectric conversion element during a transfer period, and the photoelectric element through the transfer element. conversion A floating diffusion to which charges accumulated in the child are transferred, a source follower element that converts the charges of the floating diffusion into a voltage signal corresponding to the amount of charges, and outputs the converted signal to the output node; and A reset element that resets the floating diffusion to a predetermined potential; and a selection element that electrically connects the output node to the first signal line during a first period. A signal holding capacitor capable of holding a signal output from the output node of the photoelectric conversion readout unit of the pixel, and a switch for selectively connecting the signal holding capacitor to the output node of the photoelectric conversion readout unit in the second period The element and the signal held in the signal holding capacitor in the second period according to the holding voltage Includes a source follower device which outputs, including an output unit for outputting the selectively said second signal line the converted signal.

  ADVANTAGE OF THE INVENTION According to this invention, the fall of the area efficiency on a layout can be prevented, preventing complication of a structure.

1 is a block diagram illustrating a configuration example of a solid-state imaging device according to a first embodiment of the present invention. It is a circuit diagram showing an example of the 1st pixel and the 2nd pixel of the solid-state imaging device concerning a 1st embodiment of the present invention. It is a figure for demonstrating the pixel array in the pixel part of the solid-state imaging device which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the structural example of the read-out system of the column output of the pixel part of the solid-state imaging device which concerns on embodiment of this invention. It is a figure for demonstrating the laminated structure of the solid-state imaging device which concerns on the 1st embodiment. 6 is a timing chart for explaining a read operation in a global shutter mode of the solid-state imaging device according to the first embodiment. 6 is a timing chart for explaining a read operation in a rolling shutter mode of the solid-state imaging device according to the first embodiment. It is a figure for demonstrating the laminated structure of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. It is a figure for demonstrating the laminated structure of the solid-state imaging device which concerns on the 3rd Embodiment of this invention. It is a figure which shows the example of arrangement | positioning of the component of a vertical scanning circuit in the laminated structure of the solid-state imaging device which concerns on the 3rd Embodiment of this invention. It is a figure which shows the structural example of the electric charge reproduction | regeneration system which concerns on the 4th Embodiment of this invention. It is a figure for demonstrating operation | movement of the electric charge regeneration system which concerns on the 4th Embodiment of this invention. It is a figure which shows an example of a structure of the electronic device to which the solid-state imaging device which concerns on embodiment of this invention is applied.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging apparatus according to the first embodiment of the present invention.
In the present embodiment, the solid-state imaging device 10 is configured by, for example, a CMOS image sensor.

As shown in FIG. 1, the solid-state imaging device 10 includes a pixel unit 20 as an imaging unit, a vertical scanning circuit (row scanning circuit) 30, a readout circuit (column readout circuit) 40, and a horizontal scanning circuit (column scanning circuit) 50. , And a timing control circuit 60 as main components.
Among these components, for example, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60 constitute a pixel signal readout unit 70.

In the first embodiment, the solid-state imaging device 10 includes a first pixel including a photoelectric conversion readout unit and a signal holding unit as pixels, and a photoelectric conversion readout unit in the pixel unit 20, as will be described in detail later. For example, a stacked CMOS image sensor having both the operation functions of the rolling shutter as the first operation and the global shutter as the second operation is mixed.
In the solid-state imaging device 10 according to the first embodiment, the pixel unit 20 includes a first pixel array in which photoelectric conversion readout units of a plurality of first pixels are arranged in a matrix, and a plurality of first pixels. The signal holding units are configured to include a holding unit array in which the signal holding units are arranged in a matrix, and a second pixel array in which the photoelectric conversion readout units of the plurality of second pixels are arranged in a matrix.
In the rolling shutter mode, which is the first operation, the readout signals of the photoelectric conversion readout units of the first pixel and the second pixel are immediately output without following the bypass path to the first vertical signal line.
In the global shutter mode, which is the second operation, the holding signal of the signal holding unit of the first pixel is output to the second vertical signal line.

  Hereinafter, an outline of the configuration and functions of each unit of the solid-state imaging device 10, in particular, the configuration and function of the pixel unit 20, the readout process related to them, the stacked structure of the pixel unit 20 and the readout unit 70, etc. will be described in detail.

(Configuration of first pixel, second pixel, and pixel unit 20)
FIG. 2 is a circuit diagram illustrating an example of the first pixel and the second pixel of the solid-state imaging device 10 according to the first embodiment of the present invention.

The first pixel 21 arranged in the pixel unit 20 includes a photoelectric conversion readout unit 211 and a signal holding unit 212.
The second pixel 22 disposed in the pixel unit 20 includes a photoelectric conversion readout unit 221.

The photoelectric conversion readout unit 211 of the first pixel 21 includes a photodiode (photoelectric conversion element) and an in-pixel amplifier.
Specifically, the photoelectric conversion readout unit 211 includes a photodiode PD21 that is a photoelectric conversion element, for example.
For this photodiode PD21, a transfer transistor TG1-Tr as a transfer element, a reset transistor RST1-Tr as a reset element, a source follower transistor SF1-Tr as a source follower element, an output node ND21, and a selection element (selection switch) ) Each having one selection transistor SEL1-Tr.
As described above, the photoelectric conversion readout unit 211 of the first pixel 21 according to the first embodiment includes the transfer transistor TG1-Tr, the reset transistor RST1-Tr, the source follower transistor SF1-Tr, and the selection transistor SEL1-Tr. 4 transistors (4Tr) are included.

In the photoelectric conversion readout unit 211 according to the first embodiment, the output node ND21 is connected to the input unit of the signal holding unit 212 of the first pixel 21, and the first vertical signal line is connected via the selection transistors SEL1-Tr. It is connected to LSGN11.
The photoelectric conversion readout unit 211 outputs a readout voltage (signal voltage) (VRST1, VSIG1) to the first vertical signal line LSGN11 in the rolling shutter mode.
The photoelectric conversion readout unit 211 outputs a readout voltage (signal voltage) (VRST1, VSIG1) to the signal holding unit 212 in the global shutter mode.

In the first embodiment, the first vertical signal line LSGN11 is driven by the constant current source Ibias1 in the rolling shutter mode, and the second vertical signal line LSGN12 is driven by the constant current source Ibias1 in the global shutter mode.
The constant current source Ibias1 is shared by the rolling shutter mode and the global shutter mode.
As illustrated in FIG. 2, the constant current source Ibias1 is switched in connection destination according to the operation mode by the switch unit 410. In the rolling shutter mode, the first vertical signal line LSGN11 is connected to the constant current source Ibias1, and the second vertical signal line LSGN12 is connected to the reference potential VSS (for example, ground). On the other hand, in the global shutter mode, the second vertical signal line LSGN12 is connected to the constant current source Ibias1, and the first vertical signal line LSGN11 is connected to the reference potential VSS (for example, ground).

The photodiode PD21 generates and accumulates signal charges (here, electrons) corresponding to the amount of incident light.
Hereinafter, a case where the signal charge is an electron and each transistor is an n-type transistor will be described. However, the signal charge may be a hole or each transistor may be a p-type transistor.
The present embodiment is also effective when a plurality of photodiodes and transfer transistors share each transistor.

The transfer transistors TG1-Tr of the photoelectric conversion readout unit 211 are connected between the photodiode PD21 and the floating diffusion FD21, and are controlled by a control signal TG applied to the gate through the control line.
The transfer transistors TG1-Tr are in a conductive state when the control signal TG is selected during a transfer period in which the control signal TG is high (H), and transfer charges (electrons) photoelectrically converted and stored by the photodiode PD21 to the floating diffusion FD21.

The reset transistors RST1-Tr are connected between the power supply line Vdd of the power supply voltage VDD and the floating diffusion FD21, and are controlled by a control signal RST applied to the gate through the control line.
The reset transistors RST1-Tr are turned on when the control signal RST is selected during the H level reset period, and reset the floating diffusion FD21 to the potential of the power supply line Vdd of the power supply voltage VDD.

The source follower transistor SF1-Tr and the selection transistor SEL1-Tr are connected in series between the power supply line Vdd and the first vertical signal line LSGN11 driven by the constant current source Ibias1.
An output node ND21 is formed by a connection point between the source of the source follower transistor SF1-Tr and the drain of the selection transistor SEL1-Tr.
The signal line LSGN13 between the output node ND21 and the input unit of the signal holding unit 212 is driven by, for example, a constant current source Ibias3 arranged at the input unit of the signal holding unit 212.
The source follower transistors SF1-Tr output column output read voltages (VRST1, VSIG1) obtained by converting the charge of the floating diffusion FD21 into a voltage signal corresponding to the charge amount (potential) to the output node ND21.

A floating diffusion FD21 is connected to the gate of the source follower transistor SF1-Tr, and the selection transistors SEL1-Tr are controlled by a control signal SEL applied to the gate through a control line.
The selection transistors SEL1-Tr are turned on when the control signal SEL is selected during a selection period in which the control signal SEL is at the H level. As a result, the source follower transistor SF1-Tr outputs the column output read voltage (VRST1, VSIG1) obtained by converting the charge of the floating diffusion FD21 into a voltage signal corresponding to the charge amount (potential) to the first vertical signal line LSGN11. .

The signal holding unit 212 of the first pixel 21 basically includes an input unit 2121 to which the constant current source Ibias3 is connected, a sample hold unit 2122, an output unit 2123, and nodes ND22 to ND24.
Note that the node ND22 corresponds to an input node, the node ND23 corresponds to a first holding node, and the node ND24 corresponds to a second holding node.

  The constant current source Ibias3 is connected between the node ND22 and the reference potential VSS, and is controlled to be in an on state, for example, in a predetermined period during the global shutter period.

  Instead of the constant current source Ibias3, a switch element connected between the node ND22 and the reference potential VSS and controlled to be on during a predetermined period during the global shutter period may be provided.

The sample hold unit 2122 includes a first switch element SW21 that selectively connects the signal holding capacitor of the sample hold unit 2122 to the output node ND21 of the photoelectric conversion readout unit 211 in the global shutter period that is the second period. The pixel 21 has a first signal holding capacitor C21 and a second signal holding capacitor C22 that can hold a signal output from the output node ND21 of the photoelectric conversion readout unit 211, and a second switch element SW22.
The terminal a of the first switch element SW21 is connected to the input node ND22 connected to the third signal line LSGN13, and the terminal b is connected to the node ND23 connected to the sample hold unit 2122 side.
For example, the first switch element SW21 becomes conductive when the terminals a and b are connected while the signal sw1 is at a high level.
The first signal holding capacitor C21 is connected between the node ND23 that is the first holding node and the reference potential VSS.
The second signal holding capacitor C22 is connected between the node ND24, which is the second holding node, and the reference potential VSS.
The terminal a of the second switch element SW22 is connected to the node ND23, and the terminal b is connected to the node ND24.
The second switch element SW22 becomes conductive when the terminals a and b are connected, for example, while the signal SHRT is at a high level.

  The output unit 2123 includes a source follower transistor SF3-Tr that outputs the signal held in the signal holding capacitors C21 and C22 in accordance with the holding voltage during the global shutter period, which is the second period, and selectively holds the held signal. The signal is output to the second vertical signal line LSGN12 driven by the constant current source Ibias1 through the selection transistor SEL3-Tr.

  The source follower transistor SF3-Tr and the selection transistor SEL3-Tr are connected in series between the power supply line Vdd and the second vertical signal line LSGN12 driven by the constant current source Ibias1.

A node ND24 is connected to the gate of the source follower transistor SF3-Tr, and the selection transistor SEL3-Tr is controlled by a control signal SEL3 applied to the gate through a control line.
The selection transistors SEL3-Tr are turned on when the control signal SEL3 is selected during the selection period of the H level. As a result, the source follower transistor SF3-Tr outputs a column output read voltage (VRST, VSIG) corresponding to the holding voltage of the signal holding capacitors C21, C22 to the second vertical signal line LSGN12.

  Note that the configuration of the signal holding unit 212 described above is an example, and a function of holding the read voltage (signal voltage) (VRST1, VSIG1) output from the photoelectric conversion read unit 211 during the global shutter period that is the second period. Any circuit configuration may be used as long as the circuit is provided.

The second pixel 22 disposed in the pixel unit 20 includes a photoelectric conversion readout unit 221.
The photoelectric conversion readout unit 221 of the second pixel 22 has the same configuration as the photoelectric conversion readout unit 211 of the first pixel 21 described above.

That is, the photoelectric conversion readout unit 221 of the second pixel 22 includes a photodiode (photoelectric conversion element) and an in-pixel amplifier.
Specifically, the photoelectric conversion readout unit 221 includes a photodiode PD22 that is a photoelectric conversion element, for example.
For this photodiode PD22, a transfer transistor TG2-Tr as a transfer element, a reset transistor RST2-Tr as a reset element, a source follower transistor SF2-Tr as a source follower element, and a selection as a selection element (selection switch) Each has one transistor SEL2-Tr.
As described above, the photoelectric conversion readout unit 221 of the second pixel 22 according to the first embodiment includes the transfer transistor TG2-Tr, the reset transistor RST2-Tr, the source follower transistor SF2-Tr, and the selection transistor SEL2-Tr. 4 transistors (4Tr) are included.

  The photoelectric conversion readout unit 221 according to the first embodiment outputs a readout voltage (signal voltage) (VRST2, VSIG2) to the first vertical signal line LSGN11 in the rolling shutter mode.

The photodiode PD22 generates and accumulates signal charges (here, electrons) corresponding to the amount of incident light.
In the following description, the signal charge is an electron and each transistor is an n-type transistor. However, the signal charge may be a hole or each transistor may be a p-type transistor.
The present embodiment is also effective when a plurality of photodiodes and transfer transistors share each transistor.

The transfer transistor TG2-Tr of the photoelectric conversion readout unit 221 is connected between the photodiode PD22 and the floating diffusion FD22, and is controlled by a control signal TG applied to the gate through the control line.
The transfer transistors TG2-Tr are in a conductive state when the control signal TG is selected during the H level transfer period, and transfer the charges (electrons) photoelectrically converted and accumulated by the photodiode PD22 to the floating diffusion FD22.

The reset transistor RST2-Tr is connected between the power supply line Vdd of the power supply voltage VDD and the floating diffusion FD22, and is controlled by a control signal RST applied to the gate through the control line.
The reset transistor RST2-Tr is turned on when the control signal RST is selected during the reset period when the H level is reset, and resets the floating diffusion FD22 to the potential of the power supply line Vdd of the power supply voltage VDD.

  The source follower transistor SF2-Tr and the selection transistor SEL2-Tr are connected in series between the power supply line Vdd and the first vertical signal line LSGN11 driven by the constant current source Ibias1.

A floating diffusion FD22 is connected to the gate of the source follower transistor SF2-Tr, and the selection transistor SEL2-Tr is controlled by a control signal SEL applied to the gate through a control line.
The selection transistors SEL2-Tr are turned on when the control signal SEL is selected during the selection period of the H level. As a result, the source follower transistor SF2-Tr outputs the column output read voltage (VRST2, VSIG2) obtained by converting the charge of the floating diffusion FD22 into a voltage signal corresponding to the charge amount (potential) to the first vertical signal line LSGN11. .

  In the pixel unit 20 according to the first embodiment, a first pixel 21 and a second pixel 22 having the above-described configuration are arranged as a pixel array, for example, as shown in FIG. An array is combined.

  FIG. 3 is a diagram for explaining a pixel array in the pixel unit 20 of the solid-state imaging device 10 according to the first embodiment of the present invention.

  The pixel unit 20 of the solid-state imaging device 10 according to the first embodiment includes a first pixel array 230, a holding unit array 240, an upper (for example, one side) second pixel array 250-1, and a lower side (the other). Side) second pixel array 250-2.

In the first pixel array 230, the photoelectric conversion readout units 211 of the plurality of first pixels 21 are arranged in a two-dimensional matrix (matrix) of N rows × M columns.
In the first pixel array 230, for example, the photoelectric conversion readout unit 211 of the plurality of first pixels 21 is in a two-dimensional matrix form of N rows × M columns so that an image with an aspect ratio of 16: 9 can be output. Arranged in a matrix).

In the holding unit array 240, the signal holding units 212 of the plurality of first pixels 21 are arranged in a two-dimensional matrix (matrix) of N rows × M columns corresponding to the first pixel array 230. .
Similarly to the first pixel array 230, the holding unit array 240 includes N rows × M columns of signal holding units 212 for the plurality of first pixels 21 so that an image with an aspect ratio of, for example, 16: 9 can be output. Are arranged in a two-dimensional matrix (matrix).

  In the upper second pixel array 250-1, the photoelectric conversion readout units 221 of the plurality of second pixels 22 are arranged in a two-dimensional matrix (matrix) of P (P <N) rows × M columns. Yes.

  Similarly, in the second pixel array 250-2 on the lower side, the photoelectric conversion readout unit 221 of the plurality of second pixels 22 has a two-dimensional matrix shape (matrix shape) of P (P <N) rows × M columns. Is arranged.

  In the example of FIG. 3, the second pixel arrays 250-1 and 250-2 are arranged on both sides (upper and lower sides) of the first vertical signal line LSGN 11 of the first pixel array 230 in the wiring direction. . Note that the second pixel array 250 may be disposed on at least one side of both sides of the first vertical signal line LSGN11 in the wiring direction of the first pixel array 230.

  The second pixel arrays 250-1 and 250-2 are activated together with the first pixel array 230 in the rolling shutter mode, and a plurality of second pixel arrays 250-1 and 250-2 can output an image having an aspect ratio of 1: 1 as a whole. The photoelectric conversion readout units 221 of the second pixels 22 are arranged in a two-dimensional matrix (matrix) of P (P <N) rows × M columns. The aspect ratio may be an arbitrary ratio such as 4: 3.

As described above, in the present embodiment, the readout unit 70 can output an image having an aspect ratio corresponding to the aspect ratio of the first pixel array 230 in the global shutter mode that is the second operation. More specifically, the readout unit 70 can output an image having an arbitrary aspect ratio that can be formed in the first pixel array 230 in the global shutter mode that is the second operation.
Further, the reading unit 70 can be formed in a composite pixel array formed by the first pixel array 230 and the second pixel array 250 (−1, −2) in the rolling shutter mode that is the first operation. An image with an aspect ratio of can be output.

  In the rolling shutter mode, the first pixel array 230 may be used as an area for electronic camera shake correction to output an image with an aspect ratio of 16: 9.

  In addition, the photoelectric conversion readout units 211 in the same column of the first pixel array 230 and the second pixel arrays 250-1 and 250-2 are connected to the common first vertical signal line LSGN11.

  As will be described later, when the solid-state imaging device 10 has a laminated structure of a first substrate (upper substrate) and a second substrate (lower substrate), the first pixel array 230 and the second substrate are formed on the first substrate. Pixel arrays 250-1 and 250-2 are formed, and a holding unit array 240 is formed on the second substrate so as to face the first pixel array 230.

  The pixel unit 20 activates the first pixel array 230 and the second pixel arrays 250-1 and 250-2 in the rolling shutter mode, which is the first operation under the control of the reading unit 70, so that the pixels are sequentially arranged. The pixel signal is read out and accessed in units of rows.

  Further, the pixel unit 20 controls the photoelectric conversion readout unit of the first pixel array 230 and the second pixel arrays 250-1 and 250-2 in the global shutter mode which is the second operation under the control of the readout unit 70. 211, 221 and select transistors SEL1-Tr. In a state where SEL2-Tr is in a non-selected state (the signal SEL is at a low level), the first pixel array 230 and the holding unit array 240 are activated and pixel signals are read out.

  In the pixel unit 20, for example, the gates of the transfer transistor TG-Tr, the reset transistor RST-Tr, and the selection transistor SEL-Tr are connected in units of rows. Is called.

Since the pixels are arranged in (N + 2P) rows × M columns in the pixel unit 20, each of the control lines LSEL, LRST, and LTG has (N + 2P) lines, the first vertical signal line LSGN11, and the second vertical signal line. There are M LSGNs 12 each.
In FIG. 1, each row control line is represented as one row scanning control line. Similarly, each vertical signal line LSGN11, LSGN12 is represented as one vertical signal line.

The vertical scanning circuit 30 controls the photoelectric conversion readout unit 211 and the signal holding unit 212 of the first pixel 21 and the second pixel 22 through the row scanning control line in the shutter row and readout row according to the control of the timing control circuit 60. The photoelectric conversion readout unit 221 is driven.
Further, the vertical scanning circuit 30 outputs a row selection signal of a row address of a read row that reads out the signal and a shutter row that resets the charge accumulated in the photodiode PD in accordance with the address signal.

  The column readout circuit 40 includes a plurality of column signal processing circuits (not shown) arranged corresponding to the respective column outputs of the pixel unit 20, and is configured to allow column parallel processing by the plurality of column signal processing circuits. Also good.

  The column readout circuit 40 according to the first embodiment includes a correlated double sampling (CDS) circuit, an ADC (analog / digital converter; AD converter), an amplifier (AMP), a sample hold (S / S). H) It can be configured including a circuit or the like.

As described above, the column readout circuit 40 may be configured to include the ADC 41 that converts the readout signal VSL output from each column of the pixel unit 20 into a digital signal, as shown in FIG. 4A, for example.
Alternatively, the column readout circuit 40 may be provided with an amplifier (AMP) 42 that amplifies the readout signal of each column output of the pixel unit 20 as shown in FIG. 4B, for example.
Further, the column readout circuit 40 may be provided with a sample hold (S / H) circuit 43 that samples and holds the readout signal VSL output from each column of the pixel unit 20 as shown in FIG. 4C, for example. .

  In the first embodiment, the column readout circuit 40 sends, for example, a signal transmitted through the first vertical signal line LSGN11 and a signal transmitted through the second vertical signal line LSGN12 to the column signal processing circuit of each column. A circuit for selectively inputting according to the operation mode is arranged.

  The horizontal scanning circuit 50 scans a signal processed by a plurality of column signal processing circuits such as an ADC of the reading circuit 40, transfers it in the horizontal direction, and outputs it to a signal processing circuit (not shown).

  The timing control circuit 60 generates timing signals necessary for signal processing of the pixel unit 20, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the like.

  In the rolling shutter mode, which is the first operation, the reading unit 70 activates the first pixel array 230 and the second pixel arrays 250-1 and 250-2 to sequentially access the pixels to read out pixel signals. Do it line by line.

  In the global shutter mode, which is the second operation, the readout unit 70 selects the selection transistors SEL1-Tr. In the photoelectric conversion readout unit 221 of the first pixel array 230 and the second pixel arrays 250-1 and 250-2. In a state where SEL2-Tr is in a non-selected state (the signal SEL is at a low level), the first pixel array 230 and the holding unit array 240 are activated to read out pixel signals.

(Laminated structure of the solid-state imaging device 10)
Next, a stacked structure of the solid-state imaging device 10 according to the first embodiment will be described.

  FIG. 5 is a diagram for explaining a stacked structure of the solid-state imaging device 10 according to the first embodiment.

The solid-state imaging device 10 according to the first embodiment has a stacked structure of a first substrate (upper substrate) 110 and a second substrate (lower substrate) 120.
The solid-state imaging device 10 is formed as an imaging device having a laminated structure that is bonded at a wafer level and cut out by dicing, for example.
In this example, the first substrate 110 is stacked on the second substrate 120.

On the first substrate 110, a first pixel array 230 is formed in which the photoelectric conversion read-out portions 211 of the first pixels 21 of the pixel unit 20 are arranged around the central portion thereof, and the first pixel array 230 is formed. Second pixel arrays 250-1 and 250-2 are formed on both sides (upper side and lower side) of the first vertical signal line LSGN 11 in the wiring direction.
A first vertical signal line LSGN11 is formed on the first substrate 110.

  As described above, in the first embodiment, the photoelectric conversion readout unit 211 of the first pixel 21 and the photoelectric conversion readout unit 221 of the second pixel 22 are formed in a matrix on the first substrate 110. ing.

In the second substrate 120, the signal holding units 212 of the first pixels 21 connected to the output nodes ND21 of the photoelectric conversion readout units 211 of the first pixel array 230 centering on the center are arranged in a matrix. The arranged holding unit array 240 (region 121) and the second vertical signal line LSGN12 are formed.
Then, in the example of FIG. 5 around the holding unit array 240, regions 122 and 123 for the column readout circuit 40 are formed on the upper side and the lower side in the drawing. Note that the column readout circuit 40 may be configured to be disposed on either the upper side or the lower side of the region 121 of the holding unit array 240.
Further, a region 124 for the vertical scanning circuit 30 and a digital system or output system region 125 are formed on the side of the holding unit array 240.
Further, the vertical scanning circuit 30, the horizontal scanning circuit 50, and the timing control circuit 60 may also be formed on the second substrate 120.

In such a stacked structure, the input node ND21 of each photoelectric conversion readout unit 211 of the first pixel array 230 of the first substrate 110 and the input of the signal holding unit 212 of each first pixel 21 of the second substrate 120 are used. For example, as shown in FIG. 2, the node ND <b> 22 is electrically connected using vias (Die-to-Die Via), micro bumps, or the like.
Further, the first vertical signal line LSGN11 of the first substrate 110 and the input portion of the column readout circuit 40 of the second substrate 120 are respectively connected to vias (Die-to-Die Via) as shown in FIG. Electrical connection is made using micro bumps or the like.

(Reading operation of the solid-state imaging device 10)
The characteristic configuration and function of each part of the solid-state imaging device 10 have been described above.
Next, a read operation and the like in the global shutter mode and the rolling shutter mode of the solid-state imaging device 10 according to the first embodiment will be described in detail.

(Reading operation in global shutter mode)
First, the reading operation in the global shutter mode will be described.
6A to 6H are timing charts for explaining a read operation in the global shutter mode of the solid-state imaging device according to the first embodiment.

FIG. 6A shows a reading operation process in the global shutter mode. FIG. 6B shows control signals SEL for the selection transistors SEL1-Tr and SEL2-Tr of the photoelectric conversion readout unit 211 of the first pixel 21 and the photoelectric conversion readout unit 221 of the second pixel 22. FIG. 6C shows control signals RST of the reset transistors RST1-Tr and RST2-Tr of the photoelectric conversion readout unit 211 of the first pixel 21 and the photoelectric conversion readout unit 221 of the second pixel 22. FIG. 6D shows control signals TG for the transfer transistors TG1-Tr and TG2-Tr of the photoelectric conversion readout unit 211 of the first pixel 21 and the photoelectric conversion readout unit 221 of the second pixel 22.
FIG. 6E shows the control signal sw <b> 1 of the switch element SW <b> 21 of the signal holding unit 212 of the first pixel 21. FIG. 6F shows the control signal SHRT of the switch element SW22 of the signal holding unit 212 of the first pixel 21. FIG. 6G shows the control signal SEL3 of the selection transistors SEL3-Tr of the signal holding unit 212 of the first pixel 21. FIG. 6H shows a driving state (on / off state) of the constant current source Ibias3 arranged in the signal holding unit 212 of the first pixel 21. FIG.

In the global shutter mode, as shown in FIG. 6B, control of the selection transistors SEL1-Tr and SEL2-Tr of the photoelectric conversion readout unit 211 of the first pixel 21 and the photoelectric conversion readout unit 221 of the second pixel 22 is performed. The signal SEL is set to the low level (L) during the entire period of the global shutter mode.
This suppresses (stops) the output of voltage signals from the first pixel array 230 and the second pixel arrays 250-1 and 250-2 to the first vertical signal line LSGN11 during the entire period of the global shutter mode. .
Therefore, the second pixel arrays 250-1 and 250-2 are controlled to be inactive.
Further, the first pixel array 230 is in an active state, and is in a state in which a voltage signal from the output node ND21 can be output to the signal holding unit 212.
That is, in the global shutter mode, only the first pixel array 230 is in the active state among the first pixel array 230 and the second pixel arrays 250-1 and 250-2. The ratio image is ready to be output.

  6B to 6H, times t1 to t2 are reset periods of the photodiodes PD21 and the floating diffusion FD21 in all the photoelectric conversion readout units 211 of the first pixel array 230.

  In this reset period, the control signal sw1 for the switch element SW21, the control signal SHRT for controlling the switch element SW22, and the selection transistors SEL3-Tr for controlling the driving of all the signal holding units 212 of the holding unit array 240 are controlled. The control signal SEL3 to be set is set to L level, the switch element SW21, the switch element SW22, and the selection transistor SEL3-Tr are controlled to be in a non-conductive state, and the constant current source Ibias3 is controlled to be in an off state.

In such a state, in the reset period, the reset transistors RST1-Tr are selected during the period in which the control signal RST is at the H level and become conductive.
Then, during the period when the control signal RST is at the H level, the transfer transistors TG1-Tr are selected during the period when the control signal TG is at the H level and become conductive, and the charge (electrons) accumulated by the photoelectric conversion by the photodiode PD21 is stored. The storage node becomes conductive with the floating diffusion FD21, and the photodiode PD21 and the floating diffusion FD21 are reset to the potential of the power supply line Vdd.

After the reset of the photodiode PD21, the control signal TG of the transfer transistor TG1-Tr is switched to the L level, the transfer transistor TG1-Tr is turned off, and the photodiode PD21 starts accumulating the photoelectrically converted charge.
At this time, the control signal RST of the reset transistors RST1-Tr is kept at the H level, and the floating diffusion FD21 is kept reset to the potential of the power supply line Vdd.
Then, because the reset period ends, the control signal RST of the reset transistor RST1-Tr is switched to the L level, and the reset transistor RST1-Tr is turned off.

  Next, from time t2 to time t3, the pixel signal in the reset state is read, and the read reset signal VRST is held in the signal holding capacitor C22 of the signal holding unit 212.

  In each photoelectric conversion read-out unit 211, the charge of the floating diffusion FD21 is converted into a voltage signal by a source follower transistor SF1-Tr with a gain corresponding to the amount of charge (potential), and is output from the output node ND21 as a column output read reset signal VRST. Is output.

In the photoelectric conversion readout unit 211, in parallel with the timing at which the control signals RST of the reset transistors RST1-Tr are switched to the L level, the following control is performed in all the signal holding units 212 of the holding unit array 240.
In the signal holding unit 212, the control signal sw1 is switched to the H level, the switch element SW21 is turned on, the control signal SHRT is switched to the H level, the switch element SW22 is turned on, and the constant current source Ibias3 is turned on. It is controlled to become.

  Thereby, at time t2, the read reset signal VRST output from the output node ND21 of each photoelectric conversion read unit 211 is transmitted to the corresponding signal holding unit 212 through the third signal line LSGN13, and the switch element SW21 and the switch SW22. Through the signal holding capacitor C22.

  Next, in a state where the control signal sw1 is at the H level and the switch element SW21 is held in the conductive state, and the constant current source Ibias3 is held in the on state, the control signal SHRT is switched to the L level and the switch element SW22 is in the nonconductive state. It becomes.

Here, a predetermined period including time t3 is a transfer period.
In the transfer period, in each photoelectric conversion readout unit 211, the transfer transistors TG1-Tr are selected when the control signal TG is at the H level and become conductive, and the electric charges (electrons) that are photoelectrically converted and accumulated by the photodiode PD21. Is transferred to the floating diffusion FD21.
When the transfer period ends, the control signal TG of the transfer transistors TG1-Tr is switched to the L level, and the transfer transistors TG1-Tr are turned off.

  In this state, at time t4, in each photoelectric conversion readout unit 211, the source follower transistors SF1-Tr convert the charge of the floating diffusion FD11 into a voltage signal with a gain corresponding to the amount of charge (potential), and a column output readout signal Output from the output node ND21 as VSIG.

  At time t4, the readout signal VSIG output from the output node ND21 of each photoelectric conversion readout unit 211 is transmitted to the corresponding signal holding unit 212 through the third signal line LSGN13, and the signal holding capacitor C21 through the switch element SW21. Retained.

  After the read signal VSIG is held in the signal holding capacitor C21, the control signal sw1 is switched to the L level, the switch element SW21 is turned off, and then the constant current source Ibias3 is switched to the off state.

In order to read out the signal held in this state, in order to select a certain row in the holding unit array 240, the control signal SEL3 of each selection transistor SEL3-Tr in the selected row is set to the H level, The select transistor SEL3-Tr is turned on.
At time t5, the read reset signal VRST held in the signal holding capacitor C22 is read.
At this time, in each signal holding unit 212, a column output read reset signal is generated by the source follower transistor SF3-Tr whose gate is connected to the node ND24 according to the holding voltage of the signal holding capacitor C22 connected to the node ND24. It is output to the second vertical signal line LSGN12 as VRST, supplied to the column readout circuit 40, and held, for example.

Next, the control signal SHRT is held at the H level for a predetermined period including the time t6, and the switch element SW22 is held in the conductive state.
At time t6, the combined signal of the read signal VSIG held in the signal holding capacitor C21 and the read reset signal VRST held in the signal holding capacitor C22 is read.
The combined signal CMS can be expressed by the following equation.

[Equation 1]
CMS
= {(C1 / (C1 + C2)). VSIG + (C2 / (C1 + C2)). VRST}
Here, C1 represents the capacitance of the signal holding capacitor C21, and C2 represents the capacitance of the signal holding capacitor C22.

  At this time, in each signal holding unit 212, a signal follower capacitor C21 connected to the node ND23 and a signal hold capacitor connected to the node ND24 by a source follower transistor SF3-Tr whose gates are connected to the nodes ND23 and ND24. In response to the holding voltage of C22, it is output to the second vertical signal line LSGN12 as a column output read composite signal CMS, supplied to the column read circuit 40, and held, for example.

  For example, in the readout circuit 40 constituting a part of the readout unit 70, a difference (VRST−CMS) between the readout reset signal VRST read out at time t5 and the combined signal CMS read out at time t6 is taken. CDS processing is performed.

[Equation 2]
VRST-CMS = VRST-
{(C1 / (C1 + C2)). VSIG + (C2 / (C1 + C2)). VRST}
= (C1 / (C1 + C2)). (VRST-VSIG)

(Reading operation in rolling shutter mode)
Next, a reading operation in the rolling shutter mode will be described.
FIG. 7A to FIG. 7D are timing charts for explaining the reading operation in the rolling shutter mode of the solid-state imaging device according to the first embodiment.

FIG. 7A shows control signals SEL of the selection transistors SEL1-Tr and SEL2-Tr of the photoelectric conversion readout unit 211 of the first pixel 21 and the photoelectric conversion readout unit 221 of the second pixel 22. FIG. 7B shows control signals RST of the reset transistors RST1-Tr and RST2-Tr of the photoelectric conversion readout unit 211 of the first pixel 21 and the photoelectric conversion readout unit 221 of the second pixel 22. FIG. 7C shows control signals TG for the transfer transistors TG1-Tr and TG2-Tr of the photoelectric conversion readout unit 211 of the first pixel 21 and the photoelectric conversion readout unit 221 of the second pixel 22.
FIG. 7D shows the control signal sw1 of the switch element SW21 of the signal holding unit 212 of the first pixel 21, the control signal SHRT of the switch element SW22, and the control signal SEL3 of the selection transistors SEL3-Tr.

  In this rolling shutter mode period, the control signal sw1 for the switch element SW21, the control signal SHRT for controlling the switch element SW22, and the selection transistor SEL3-Tr for controlling the driving of all the signal holding parts 212 of the holding part array 240. The control signal SEL3 for controlling is set to L level, and the switch element SW21, the switch element SW22, and the selection transistor SEL3-Tr are controlled to be in a non-conductive state.

That is, in the rolling shutter mode period, all the signal holding units 212 of the holding unit array 240 formed on the second substrate 120 are not accessed.
In the rolling shutter mode period, the first pixel array 230 and the second pixel arrays 250-1 and 250-2 formed on the first substrate 110 are sequentially accessed in units of rows.
That is, in the rolling shutter mode, since the first pixel array 230 and the second pixel arrays 250-1 and 250-2 are in an active state, for example, 1: 1 or 4 different from 16: 9 or 16: 9. : An image with an aspect ratio of 3 or the like can be output.

  In the rolling shutter mode period, as shown in FIG. 7A, in order to select one row in the first pixel array 230 or the second pixel array 250-1, 250-2, the selected row is selected. The control signal SEL for controlling (driving) each photoelectric conversion readout unit 211 of the first pixel array 230 in the row or the photoelectric conversion readout unit 221 of the second pixel arrays 250-1 and 250-2 is set to the H level. Thus, the selection transistor SEL2-Tr (or SEL1-Tr) of the pixel is turned on.

In this selected state, the reset transistor RST2-Tr (or RST1-Tr) is selected during the reset period PR while the control line RST is selected during the H level, and the floating diffusion FD22 (or FD21) is connected to the power supply line Vdd. Reset to potential.
After this reset period PR has passed (the reset transistor RST2-Tr or RST1-Tr is in a non-conductive state), the period including the time t11 until the transfer period PT is started is the first to read out the pixel signal in the reset state. It becomes a reading period.

  At time t11, the source follower transistor SF2-Tr (or SF1-Tr) in the selected row converts the charge of the floating diffusion FD22 (or FD21) into a voltage signal with a gain corresponding to the amount of charge (potential), and the column An output read reset signal VRST is immediately output to the first vertical signal line LSGN11 and supplied to the column read circuit 40, for example, held therein.

Here, the first read period ends and the transfer period PT begins.
During the transfer period PT, the transfer transistors TG2-Tr (or TG1-Tr) are selected during the period when the control signal TG is at the high level (H) and become conductive, and are photoelectrically converted and accumulated by the photodiode PD22 (or PD21). Charges (electrons) are transferred to the floating diffusion FD22 (or FD21).
After the transfer period PT elapses (the transfer transistor TG2-Tr or TG1-Tr is in a non-conductive state), it includes a time t12 when the photodiode PD22 (or PD21) reads out a pixel signal corresponding to the charge accumulated by photoelectric conversion. The second readout period is entered.

  At time t12 when the second read period starts, the source follower transistor SF2-Tr (or SF1-Tr) of the selected row gains the charge of the floating diffusion FD22 (or FD21) according to the charge amount (potential). And is immediately output to the first vertical signal line LSGN11 as a column output read signal VSIG, supplied to the column read circuit 40, for example, held therein.

  Then, for example, in the read circuit 40 constituting a part of the read unit 70, the difference {VRST−VSIG} between the read reset signal VRST and the read signal VSIG is taken, and the CDS process is performed.

  As described above, in the rolling shutter mode period, the first pixel array 230 and the second pixel arrays 250-1 and 250-2 formed on the first substrate 110 are sequentially accessed in units of rows. The read operations are sequentially performed.

As described above, according to the first embodiment, the solid-state imaging device 10 includes the first pixel 21 including the photoelectric conversion readout unit and the signal holding unit as the pixels, and the photoelectric conversion readout unit in the pixel unit 20. And a second pixel 22 including the first and second pixels 22 are mixed and configured as, for example, a stacked CMOS image sensor having both a rolling shutter function as a first operation and a global shutter function as a second operation.
In the solid-state imaging device 10 according to the first embodiment, the pixel unit 20 includes a first pixel array 230 in which the photoelectric conversion readout units 211 of the plurality of first pixels 21 are arranged in a matrix, and a plurality of first pixels. A holding unit array 240 in which signal holding units 212 of one pixel 21 are arranged in a matrix, and a second pixel array 250-1 in which photoelectric conversion readout units 221 of a plurality of second pixels are arranged in a matrix. 250-2.
Then, in the rolling shutter mode as the first operation, the readout signals of the photoelectric conversion readout units 211 and 221 of the first pixel 21 and the second pixel 22 do not follow the bypass path to the first vertical signal line LSGN11. Output immediately. In the global shutter mode, which is the second operation, the holding signal of the signal holding unit 212 of the first pixel is output to the second vertical signal line LSGN12.

  Therefore, according to the solid-state imaging device 10 of the first embodiment, it is possible to prevent a reduction in area efficiency on the layout while preventing the configuration from becoming complicated.

  Moreover, according to the solid-state imaging device 10 of the first embodiment, an image signal having a desired aspect ratio can be obtained according to the operation mode.

The solid-state imaging device 10 according to the first embodiment has a stacked structure of a first substrate (upper substrate) 110 and a second substrate (lower substrate) 120.
On the first substrate 110, a first pixel array 230 is formed in which the photoelectric conversion read-out portions 211 of the first pixels 21 of the pixel unit 20 are arranged around the central portion thereof, and the first pixel array 230 is formed. Second pixel arrays 250-1 and 250-2 are formed on both sides (upper side and lower side) of the first vertical signal line LSGN 11 in the wiring direction.
A first vertical signal line LSGN11 is formed on the first substrate 110.
In the second substrate 120, the signal holding units 212 of the first pixels 21 connected to the output nodes ND21 of the photoelectric conversion readout units 211 of the first pixel array 230 centering on the center are arranged in a matrix. The arranged holding unit array 240 (region 121) and the second vertical signal line LSGN12 are formed.
Then, areas 122 and 123 for the column readout circuit 40 are formed around the holding unit array 240.

  Therefore, in the first embodiment, the first substrate 110 side is basically formed of only NMOS elements, and effective pixels are formed by the pixels of the first pixel array and the second pixel array. By maximizing the area, the value per cost can be maximized.

(Second Embodiment)
FIG. 8 is a diagram for explaining a stacked structure of a solid-state imaging device according to the second embodiment of the present invention.

The laminated structure of the second embodiment is different from the laminated structure of the first embodiment as follows.
In the stacked structure of the second embodiment, the region 124 of the vertical scanning circuit (Row Decoder) 30 and the regions 122 and 123 for the column readout circuit system (Column Signal Chain) provided on the second substrate 120A are smaller than the pixel pitch. Arranged at the pitch.
In addition, the wiring pitch is matched to the pixel pitch of the first substrate 110A by securing the routing regions 126 to 128 at the peripheral edge of the second substrate 120A.

Further, in the stacked structure of the second embodiment, the second pixel arrays 250-3 and 250-4 for the rolling shutter are arranged on the first substrate 110A, and the first pixel array 230 and the second pixel array. It is formed on both sides of 250-1 and 250-2.
As a result, it is possible to output image signals having the same or an arbitrary aspect ratio during the rolling shutter mode operation and the global shutter mode operation.

(Third embodiment)
FIG. 9 is a diagram for explaining a stacked structure of a solid-state imaging device according to the third embodiment of the present invention.
FIG. 10A and FIG. 10B are diagrams showing examples of arrangement of components of the vertical scanning circuit in the stacked structure of the solid-state imaging device according to the third embodiment of the present invention.

The laminated structure of the third embodiment is different from the laminated structure of the first embodiment as follows.
In the stacked structure of the third embodiment, a part of the region 124 of the vertical scanning circuit (Row Decoder) provided on the second substrate 120B is formed as the region 111 on the first substrate 110B, and a part of the component parts is formed. Arranged in the region 111 of the first substrate 110B.

In the example of FIG. 10A, the power stabilization capacitor C30 of the vertical scanning circuit (Row Decoder) 30 is arranged in the region 111 of the first substrate 110B.
As a result, it is possible to effectively use the empty area of the first substrate 110B in which only the pixel system is basically formed, and the number of external parts can be reduced by incorporating the stabilization capacitor C30. .

In the example of FIG. 10B, the PMOS transistor PT is the second of the CMOS p-channel MOS (PMOS) transistor PT and n-channel MOS (NMOS) transistor NT constituting the driver of the vertical scanning circuit (Row Decoder) 30. The NMOS transistor NT is disposed on the first substrate 110B.
As a result, the NMOS transistor NT is basically formed on the first substrate 110B formed of an NMOS element, thereby facilitating design and manufacturing, and effective use of the empty area of the first substrate 110B. be able to.

(Fourth embodiment)
FIG. 11 is a diagram illustrating a configuration example of a charge regeneration system according to the fourth embodiment of the present invention.

  The solid-state imaging device 10 according to the fourth embodiment is provided with a charge regeneration (charge recycling) system 80 in addition to the configurations of the first to third embodiments.

The charge regeneration system 80 as a charge recycle unit includes an external capacitor Cext, a signal holding unit 212C, an overcharge regulation circuit 810, and regulators 820 and 830.
The overcharge regulation circuit 810 and the regulators 820 and 830 constitute a power supply circuit unit.

  In the signal holding unit 212C of FIG. 11, the third switch element SW23 is arranged instead of the constant current source Ibias3, and the selection transistor is provided as the switch element SW25. However, the switch element SW24 as the external connection switch element is provided. The functions are the same as those of the signal holding unit 212 in FIG.

The charge regeneration system 80 includes an external capacitor Cext having a large external capacity, a first signal holding capacitor (sampling capacity) CS21 and a second signal holding capacitor (sampling capacity) of the signal holding unit 212C of all the first pixels 21. The charge accumulated in CS 22 is transferred and reused as a power source for the digital circuit of the own chip.
Thereby, the power consumption of the chip can be reduced.

  The switch element SW24 as an external connection switch element is connected between the node ND23 which is the first holding node of the signal holding unit 212C and the node ND80 connected to the input / output terminal TI / O, and is turned on by the control signal sw4. The state is controlled.

The external capacitor Cext has a capacitance set to about 10 μF.
The external capacitor Cext may be on-chip. For example, it may be formed on the first substrate 110C. Thereby, it is possible to effectively use the empty area of the first substrate 110C.

<Example of Calculation of Capacity of External Capacitor Cext>
CS = 10 fF,
N = 2M pixel,
Ctot = 2 * CS * N = 40 nF,
Then,
Cext is determined so as to satisfy the following equation (in order to suppress ripple to 1/100).
Cext> 100 * Ctot

The overcharge regulation circuit 810 uses a current clamp circuit 811, a hysteresis comparator 812, and a low-pass filter (LPF) 813 to suppress voltage ripple and regulate voltage with low power consumption.
A discharge path that does not affect the circuit by flowing a charge to another ground (GNDCR) is created to suppress power supply noise during charge transfer.

<Set value of reference voltage VREF of hysteresis comparator 812>
The reference voltage VREF of the hysteresis comparator 812 is set to a low voltage (for example, ˜0.5 V) so that almost all of the charge of the signal holding capacitor CS can be transferred.
If it is too low, a large capacity is required.
If it is too high, the amount of charge that can be recycled decreases.
Therefore, considering the voltage when reusing, about 0.5V is good.

The regulator 820 is configured by on-chip a boost circuit 821 that boosts from a low voltage to a high voltage and an LDO regulator 822.
The regulator 830 is configured by on-chip a boost circuit 831 for boosting from a low voltage to a high voltage and an LDO regulator 832.

The regulators 820 and 830 are boosted to 0.5 V-> 1.2 V (DVDD) or 1.8 V (DVDDIO) by the boost circuits 821, 831, and mainly include a digital circuit (vertical scanning circuit (Row Decoder) 30). ) Power supply voltage.
Any number of regulators may be used.

In the charge regeneration system 80, the charges accumulated in the signal holding capacitors (sampling capacitors) CS21 and CS22 of the signal holding units 212C of all the first pixels 21 are transferred to an external capacitor Cext having a large external capacity, and the digital of the own chip is transferred. Reuse as circuit power.
The signal holding unit 212C of the first pixel 21 performs a so-called global sampling operation after the sampling circuit finally resets the residual charge with a clean ground (GNDPIX).

  FIGS. 12A to 12J are diagrams for explaining the operation of the charge regeneration system according to the fourth embodiment of the present invention.

FIG. 12A shows the control signal RST of the reset transistors RST 1 -Tr of the photoelectric conversion readout unit 211 of the first pixel 21. FIG. 12B shows a control signal TG for the transfer transistors TG 1 -Tr of the photoelectric conversion readout unit 211 of the first pixel 21.
FIG. 12C shows the control signal sw1 of the first switch element SW21 of the signal holding unit 212C of the first pixel 21. FIG. 12D shows the control signal sw2 (SHRT) of the second switch element SW22 of the signal holding unit 212C of the first pixel 21. FIG. 12E shows the control signal sw3 of the third switch element SW23 of the signal holding unit 212C of the first pixel 21. FIG. 12F shows the control signal sw4 of the switch element SW24 as the external connection switch element of the signal holding unit 212C of the first pixel 21. FIG. 12G shows the control signal sw5 (SEL3) of the switch element SW25 of the signal holding unit 212C of the first pixel 21.
FIG. 12H shows the potential Vfd of the floating diffusion FD21 of the photoelectric conversion readout unit 211 of the first pixel 21. FIG. 12I shows the potential Vx of the node ND23 of the signal holding unit 212C of the first pixel 21. FIG. 12J shows the potential Vy of the node ND80 of the charge regeneration system 80.

12A to 12J, t21 indicates the start time of the global sampling period.
At time t21, the control signal RST is set to H level, and the reset transistors RST1-Tr are turned on. As a result, the floating diffusion FD21 is reset to the potential of the power supply line Vdd.
Further, the control signal sw2 is set to H level, the switch element SW22 is turned on (on state), and the first signal holding capacitor CS21 and the second signal holding capacitor CS22 are short-circuited (connected). In parallel with this, the control signal sw3 is set to H level, and the switch element SW23 is turned on (on state). As a result, the first signal holding capacitor CS21 and the second signal holding capacitor CS22 are connected to the ground GNDPIX, and the residual charge is removed.

12A to 12J, t22 indicates the sampling start time of the reset voltage VRST.
At time t22, the control signal sw1 is set to the H level, the switch element SW21 is turned on (on state), and the output node ND21 of the photoelectric conversion readout unit 211 on the first substrate 110C side of the first pixel 21 The node ND23 of the sample hold unit of the signal hold unit 212C on the second substrate 120C side is connected.
Then, the first signal holding capacitor CS21 and the second signal holding capacitor CS22 serve as a load capacitor and a dynamic first pixel amplifier driving current source, and the potential Vx of the node ND23 rises to VRST.
Thereafter, the control signal sw2 is set to L level, the switch element SW22 is turned off (off state), and the reset voltage VRST is sampled in the signal holding capacitor CS22.

12A to 12J, t23 indicates the first charge recycling start time.
At time t23, the control signal sw4 is set to H level, the switch element SW24 is turned on (on state), the signal holding capacitor CS21 is connected to the external capacitor Cext, and charge transfer is performed.
As a result, the potential Vx of the node ND23 of the signal holding unit 212C becomes VREF.

12A to 12J, t24 indicates the sampling preparation period of the signal voltage VSIG.
At time t24, the control signal sw3 is set to H level, and the switch element SW23 is turned on (on state). As a result, the signal holding capacitor CS21 is connected to the ground GNDPIX, and the residual charge is removed.

12A to 12J, t25 indicates the optical signal charge transfer period.
At time t25, the control signal TG is set to H level, the transfer transistors TG1-Tr are turned on, and the photoelectric charges (electrons) photoelectrically converted and accumulated by the photodiode PD21 are transferred to the floating diffusion FD21.
As a result, the voltage Vfd of the floating diffusion FD21 decreases in proportion to the amount of charge.

12A to 12J, t26 indicates the start time of the optical signal voltage VSIG sampling period.
At time t26, the control signal sw1 is set to H level, the switch element SW21 is turned on (on state), and the output node ND21 of the photoelectric conversion readout unit 211 on the first substrate 110C side of the first pixel 21 The node ND23 of the sample holding unit of the signal holding unit 212C on the second substrate 120C side is connected again.
As a result, the potential Vx of the node ND23 rises to VSIG.

12A to 12J, t27 indicates the readout period start time.
At time t27, the control signal sw5 is set to the H level, the switch element SW25 is turned on (on state), and the output unit of the signal holding unit 212C and the second vertical signal line LSGN12 are connected.
As a result, a voltage proportional to the voltage sampled in the signal holding capacitor CS22 appears on the second vertical signal line LSGN12.

12A to 12J, t28 indicates the sampled optical signal readout start time.
At time t28, the control signal sw2 is set to H level, the switch element SW22 is turned on (on state), and the first signal holding capacitor CS21 and the second signal holding capacitor CS22 are short-circuited (connected).
As a result, as described above, the potential Vx of the node ND23 changes according to the sampling voltage and the capacitance value of the signal holding capacitors CS21 and CS22 (normally, both are designed to have the same value). Since the control signal sw5 is at the H level, a voltage proportional to the potential Vx of the node ND23 appears on the second vertical signal line LSGN12.

12A to 12J, t29 indicates the second charge recycle start time.
At time t29, the control signal sw2 is at the H level, the control signal sw4 is set to the H level, the switch element SW24 is turned on (on state), and the signal holding capacitors CS21 and CS22 are connected to the external capacitor Cext. The
As a result, the charges used for the read operation and accumulated in the signal holding capacitors CS21 and CS22 are transferred to the external capacitor Cext and become charges for reuse.
Further, the potential Vx of the node ND23 is VREF.

As described above, the charge regeneration system 80 transfers the charge accumulated in the signal holding capacitors (sampling capacitors) CS21 and CS22 of the signal holding units 212C of all the first pixels 21 to the external capacitor Cext having a large external capacity. Reuse it as a power source for its own chip digital circuit.
Thereby, the power consumption of the chip can be reduced.

  The solid-state imaging device 10 described above can be applied as an imaging device to an electronic apparatus such as a digital camera, a video camera, a portable terminal, a monitoring camera, or a medical endoscope camera.

  FIG. 13 is a diagram illustrating an example of the configuration of an electronic apparatus equipped with a camera system to which the solid-state imaging device according to the embodiment of the present invention is applied.

As shown in FIG. 13, the electronic apparatus 300 includes a CMOS image sensor 310 to which the solid-state imaging device 10 according to the present embodiment can be applied.
Furthermore, the electronic apparatus 300 includes an optical system (lens or the like) 320 that guides incident light (forms a subject image) to the pixel region of the CMOS image sensor 310.
The electronic device 300 includes a signal processing circuit (PRC) 330 that processes an output signal of the CMOS image sensor 310.

The signal processing circuit 330 performs predetermined signal processing on the output signal of the CMOS image sensor 310.
The image signal processed by the signal processing circuit 330 can be displayed as a moving image on a monitor composed of a liquid crystal display or the like, or output to a printer, or directly recorded on a recording medium such as a memory card. Is possible.

As described above, by mounting the above-described solid-state imaging device 10 as the CMOS image sensor 310, it is possible to provide a high performance, small size, and low cost camera system.
Electronic devices such as surveillance cameras and medical endoscope cameras are used for applications where the camera installation requirements include restrictions such as mounting size, number of connectable cables, cable length, and installation height. Can be realized.

  DESCRIPTION OF SYMBOLS 10 ... Solid-state imaging device, 20 ... Pixel part, PD21, PD22 ... Photodiode, TG1-Tr, TG2-Tr ... Transfer transistor, RST1-Tr, RST2-Tr ... Reset transistor, SF1-Tr, SF2-Tr, SF3-Tr ... source follower transistor, SEL1-Tr, SEL2-Tr, SEL3-Tr ... selection transistor, FD21, FD22 ... floating diffusion, 21 ... first , 211... Photoelectric conversion readout unit, 212... Signal holding unit, 22... Second pixel, 221... Photoelectric conversion readout unit, 30. Read circuit (column read circuit), 50... Horizontal scanning circuit, 60... Timing control circuit, 70. 80 ... Charge regeneration system, Cext ... External capacitor, SW24 ... Switch element, 810 ... Overcharge regulation circuit, 820,830 ... Regulator, 300 ... Electronic equipment, 210. ..CMOS image sensor 320 ... optical system 330 ... signal processing circuit (PRC)

Claims (20)

Of a first pixel including a photoelectric conversion readout unit and a signal holding unit and a second pixel including the photoelectric conversion readout unit, a pixel unit in which at least the first pixel is disposed;
A readout unit that reads out a pixel signal from the pixel unit;
A first signal line from which a readout signal of the photoelectric conversion readout unit is output;
A second signal line from which a holding signal of the signal holding unit is output,
At least the photoelectric conversion readout unit of the first pixel is
An output node;
A photoelectric conversion element for accumulating charges generated by photoelectric conversion during the accumulation period;
A transfer element capable of transferring charges accumulated in the photoelectric conversion element during a transfer period;
Floating diffusion to which the charge accumulated in the photoelectric conversion element is transferred through the transfer element;
A source follower element that converts the charge of the floating diffusion into a voltage signal corresponding to a charge amount, and outputs the converted signal to the output node;
A reset element for resetting the floating diffusion to a predetermined potential during a reset period;
A selection element that electrically connects the output node to the first signal line in a first period;
The signal holding unit is
A signal holding capacitor capable of holding a signal output from an output node of the photoelectric conversion readout unit of the first pixel;
A switch element that selectively connects the signal holding capacitor to an output node of the photoelectric conversion readout unit in a second period;
An output unit that includes a source follower element that outputs a signal held in the signal holding capacitor in the second period according to a holding voltage, and selectively outputs the converted signal to the second signal line; Includes solid-state imaging device. The pixel unit is at least
A first pixel array in which the photoelectric conversion readout sections of the plurality of first pixels are arranged in a matrix;
The solid-state imaging device according to claim 1, further comprising: a holding unit array in which the signal holding units of the plurality of first pixels are arranged in a matrix. The pixel portion is
The photoelectric conversion readout unit of the plurality of second pixels has a second pixel array arranged in a matrix,
The photoelectric conversion readout unit of the second pixel is
A photoelectric conversion element for accumulating charges generated by photoelectric conversion during the accumulation period;
A transfer element capable of transferring charges accumulated in the photoelectric conversion element during a transfer period;
Floating diffusion to which the charge accumulated in the photoelectric conversion element is transferred through the transfer element;
A source follower element that converts the charge of the floating diffusion into a voltage signal corresponding to the amount of charge;
A reset element for resetting the floating diffusion to a predetermined potential during a reset period;
The solid-state imaging device according to claim 2, further comprising: a selection element that electrically connects an output line of a voltage signal from the source follower element to the first signal line in a first period. The second pixel array is:
The solid-state imaging device according to claim 3, wherein the solid-state imaging device is disposed on at least one side of at least both sides of the first signal line in the wiring direction of the first pixel array. The second pixel array is:
The solid-state imaging device according to claim 3, wherein the solid-state imaging device is disposed on at least one side of both sides of the first pixel array in a direction orthogonal to a wiring direction of the first signal line. The reading unit
6. The pixel signal is read out by activating the first pixel array of the first pixel and the second pixel array of the second pixel during a first operation. 7. The solid-state imaging device described in 1. The reading unit
In the second operation, the first pixel array of the first pixel and the first pixel array in the state where the selection element in the photoelectric conversion readout unit of the first pixel and the second pixel is in a non-selected state The solid-state imaging device according to claim 3, wherein the pixel signal is read by activating the holding unit array. The reading unit
During the first operation, the first pixel array of the first pixel and the second pixel array of the second pixel are activated to read out pixel signals,
In the second operation, the first pixel array of the first pixel and the first pixel array in the state where the selection element in the photoelectric conversion readout unit of the first pixel and the second pixel is in a non-selected state The solid-state imaging device according to claim 3, wherein the pixel signal is read by activating the holding unit array. The reading unit
During the second operation, an image having an arbitrary aspect ratio that can be formed in the first pixel array can be output.
9. The solid-state imaging device according to claim 8, wherein an image having an arbitrary aspect ratio that can be formed in a composite pixel array formed by the first pixel array and the second pixel array can be output during the first operation. . The pixel signal read from the photoelectric conversion readout unit of the first pixel includes at least a reset readout signal and a readout signal,
The signal holding unit is
A first holding node;
A second holding node;
A first signal holding capacitor connected to the first holding node and capable of holding a signal output from an output node of the photoelectric conversion readout unit of the first pixel;
A second signal holding capacitor connected to the second holding node and capable of holding a signal output from an output node of the photoelectric conversion readout unit of the first pixel;
A first switching element that selectively connects the first holding node to which the first signal holding capacitor is connected in a second period to an output node of the photoelectric conversion readout unit;
A second switch element that selectively connects the first holding node and the second holding node in the second period;
In the second period, a signal held in the second signal holding capacitor connected to at least the second holding node among the first holding node and the second holding node is set according to a holding voltage. 10. A solid-state imaging device according to claim 1, further comprising: an output unit that selectively outputs a converted signal to the second signal line. The reading unit
Read the reset read signal as the pixel signal from the photoelectric conversion read unit of the first pixel, and then read the read signal,
When the reset read signal is read as the pixel signal, the first switch element and the second switch element of the signal holding unit are turned on for a predetermined period, and the read reset signal is supplied to the second signal holding capacitor. Holding the second switch element in a non-conductive state;
When reading the readout signal as the pixel signal, the second switch element of the signal holding unit is held in a non-conductive state, the first switch element is made conductive, and the read signal is sent to the first signal. Holding the first switch element in a non-conductive state by holding the signal holding capacitor;
In a state where the first switch element and the second switch element are held in a non-conductive state, a conversion signal corresponding to a reset read signal held in the second signal holding capacitor is sent to the second signal line. Output to
The reset read signal and the first signal held in the second signal holding capacitor in a state where the first switch element is held in a non-conductive state and the second switch element is held in a conductive state. The solid-state imaging device according to claim 10, wherein a conversion signal corresponding to a combined signal of the readout signals held in the capacitor is output to the second signal line. A first substrate;
A second substrate,
The first substrate and the second substrate have a laminated structure connected through a connection portion,
The first substrate includes
At least the photoelectric conversion readout unit of the first pixel and the first signal line are formed,
The second substrate includes
The solid-state imaging device according to claim 1, wherein at least a part of the signal holding unit, the second signal line, and the reading unit of the first pixel is formed. A first substrate;
A second substrate,
The first substrate and the second substrate have a laminated structure connected through a connection portion,
The first substrate includes
At least a part of the first pixel array, the second pixel array, the first signal line, and the readout unit is formed,
The second substrate includes
The solid-state imaging device according to claim 1, wherein at least a part of the signal holding unit, the second signal line, and the reading unit of the first pixel is formed. 2. A charge recycling unit that transfers charges held in the signal holding capacitors of the signal holding units of the plurality of first pixels to an external capacitor and reuses them as a power source for a digital circuit of the chip. The solid-state imaging device according to any one of 13. The charge recycling unit includes:
The external capacitor capable of storing the charge held in the signal holding capacitor of the signal holding unit of the plurality of first pixels;
The solid-state imaging device according to claim 14, further comprising: a power supply circuit unit capable of supplying processing power generated using the electric charge held in the external capacitor to a processing system circuit. The pixel signal read from the photoelectric conversion readout unit of the first pixel includes at least a reset readout signal and a readout signal,
The signal holding unit is
A first holding node;
A second holding node;
A first signal holding capacitor connected to the first holding node and capable of holding a signal output from an output node of the photoelectric conversion readout unit of the first pixel;
A second signal holding capacitor connected to the second holding node and capable of holding a signal output from an output node of the photoelectric conversion readout unit of the first pixel;
A first switching element that selectively connects the first holding node to which the first signal holding capacitor is connected in a second period to an output node of the photoelectric conversion readout unit;
A second switch element that selectively connects the first holding node and the second holding node in the second period;
An external connection switching element for connecting the first holding node to the external capacitor during a charge recycling period;
In the second period, a signal held in the second signal holding capacitor connected to at least the second holding node among the first holding node and the second holding node is set according to a holding voltage. The solid-state imaging device according to claim 15, further comprising: an output unit that includes a source follower element that outputs the converted signal and selectively outputs the converted signal to the second signal line. The reading unit
Read the reset read signal as the pixel signal from the photoelectric conversion read unit of the first pixel, and then read the read signal,
When the reset read signal is read as the pixel signal, the first switch element and the second switch element of the signal holding unit are turned on for a predetermined period, and the read reset signal is supplied to the second signal holding capacitor. Holding the second switch element and the first switch element in a non-conductive state;
The external connection switch element is turned on for a predetermined period, the charge of the first signal holding capacitor is transferred to the external capacitor, and a first charge recycling is performed.
When reading the readout signal as the pixel signal, the second switch element of the signal holding unit is held in a non-conductive state, the first switch element is made conductive, and the read signal is sent to the first signal. Holding the first switch element in a non-conductive state by holding the signal holding capacitor;
In a state where the first switch element and the second switch element are held in a non-conductive state, a conversion signal corresponding to a reset read signal held in the second signal holding capacitor is sent to the second signal line. Output to
The reset read signal and the first signal held in the second signal holding capacitor in a state where the first switch element is held in a non-conductive state and the second switch element is held in a conductive state. A conversion signal corresponding to a composite signal of the read signal held in the capacitor is output to the second signal line;
With the first switch element held in a non-conductive state and the second switch element held in a conductive state, the external connection switch element is turned on for a predetermined period, and the first signal holding capacitor and the The solid-state imaging device according to claim 16, wherein the charge of the second signal holding capacitor is transferred to the external capacitor and second charge recycling is performed. The signal holding unit is
A third switch element that selectively connects the first holding node and a predetermined reference potential in the second period;
The reading unit
Before reading the reset read signal, the second switch element and the third switch element are held in a conductive state, and the residual charges of the first signal holding capacitor and the second signal holding capacitor are reduced. Remove,
18. The residual charge of the first signal holding capacitor is removed by holding the third switch element in a conductive state before reading the read signal after the first charge recycling process. Solid-state imaging device. A pixel unit in which a first pixel including a photoelectric conversion readout unit and a signal holding unit and a second pixel including the photoelectric conversion readout unit are disposed;
A readout unit that reads out a pixel signal from the pixel unit;
A first signal line from which a readout signal of the photoelectric conversion readout unit is output;
A second signal line from which a holding signal of the signal holding unit is output,
At least the photoelectric conversion readout unit of the first pixel is
An output node;
A photoelectric conversion element for accumulating charges generated by photoelectric conversion during the accumulation period;
A transfer element capable of transferring charges accumulated in the photoelectric conversion element during a transfer period;
Floating diffusion to which the charge accumulated in the photoelectric conversion element is transferred through the transfer element;
A source follower element that converts the charge of the floating diffusion into a voltage signal corresponding to a charge amount, and outputs the converted signal to the output node;
A reset element for resetting the floating diffusion to a predetermined potential during a reset period;
A selection element that electrically connects the output node to the first signal line in a first period;
The signal holding unit is
A signal holding capacitor capable of holding a signal output from an output node of the photoelectric conversion readout unit of the first pixel;
A switch element that selectively connects the signal holding capacitor to an output node of the photoelectric conversion readout unit in a second period;
An output unit that includes a source follower element that outputs a signal held in the signal holding capacitor in the second period according to a holding voltage, and selectively outputs the converted signal to the second signal line; Including
The pixel portion is
A first pixel array in which the photoelectric conversion readout sections of the plurality of first pixels are arranged in a matrix;
A holding unit array in which the signal holding units of the plurality of first pixels are arranged in a matrix;
A second pixel array in which the photoelectric conversion readout units of the plurality of second pixels are arranged in a matrix,
A method for driving a solid-state imaging device,
During the first operation, the first pixel array of the first pixel and the second pixel array of the second pixel are activated to read out pixel signals,
In the second operation, the first pixel array of the first pixel and the first pixel array in the state where the selection element in the photoelectric conversion readout unit of the first pixel and the second pixel is in a non-selected state A driving method of a solid-state imaging device that reads out pixel signals by activating a holding unit array. A solid-state imaging device;
An optical system that forms a subject image on the solid-state imaging device,
The solid-state imaging device
Of a first pixel including a photoelectric conversion readout unit and a signal holding unit and a second pixel including the photoelectric conversion readout unit, a pixel unit in which at least the first pixel is disposed;
A readout unit that reads out a pixel signal from the pixel unit;
A first signal line from which a readout signal of the photoelectric conversion readout unit is output;
A second signal line from which a holding signal of the signal holding unit is output,
At least the photoelectric conversion readout unit of the first pixel is
An output node;
A photoelectric conversion element for accumulating charges generated by photoelectric conversion during the accumulation period;
A transfer element capable of transferring charges accumulated in the photoelectric conversion element during a transfer period;
Floating diffusion to which the charge accumulated in the photoelectric conversion element is transferred through the transfer element;
A source follower element that converts the charge of the floating diffusion into a voltage signal corresponding to a charge amount, and outputs the converted signal to the output node;
A reset element for resetting the floating diffusion to a predetermined potential during a reset period;
A selection element that electrically connects the output node to the first signal line in a first period;
The signal holding unit is
A signal holding capacitor capable of holding a signal output from an output node of the photoelectric conversion readout unit of the first pixel;
A switch element that selectively connects the signal holding capacitor to an output node of the photoelectric conversion readout unit in a second period;
An output unit that includes a source follower element that outputs a signal held in the signal holding capacitor in the second period according to a holding voltage, and selectively outputs the converted signal to the second signal line; Including electronic equipment.

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