JP6995550B2 - Solid-state image sensor, solid-state image sensor driving method, and electronic equipment - Google Patents

Description

The present invention relates to a solid-state image sensor, a method for driving the solid-state image sensor, and an electronic device.

A CMOS (Complementary Metal Oxide Semiconductor) image sensor is put into practical use as a solid-state image sensor (image sensor) using a photoelectric conversion element that detects light and generates electric charges.
CMOS image sensors are widely applied as part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and mobile terminal devices (mobile devices) such as mobile phones. There is.

The CMOS image sensor has an FD amplifier having a photodiode (photoelectric conversion element) and a floating diffusion layer (FD) for each pixel, and its readout selects a certain line in the pixel array. However, the column parallel output type that reads them out in the column output direction at the same time is the mainstream.

Further, various kinds of pixel signal readout (output) circuits of the column parallel output type CMOS image sensor have been proposed.
Among them, one of the most advanced circuits is a circuit equipped with an analog-to-digital converter (ADC (Analog digital converter)) for each column and extracting a pixel signal as a digital signal (for example, Patent Document). See 1 and 2).

In this column-parallel ADC-equipped CMOS image sensor (column AD method CMOS image sensor), the comparator (comparator) compares the so-called RAMP wave and the pixel signal, and performs AD conversion by performing digital CDS with the counter in the subsequent stage. ..

However, although this type of CMOS image sensor is capable of high - speed signal transfer, it has the disadvantage of not being able to read out the global shutter.

On the other hand, an ADC (furthermore, a memory unit) including a comparator is arranged in each pixel, and a global shutter that executes exposure start and exposure end at the same timing for all pixels in the pixel array unit is provided. A digital pixel sensor has been proposed (see, for example, Patent Documents 3 and 4).

Japanese Unexamined Patent Publication No. 2005-278135 Japanese Unexamined Patent Publication No. 2005-295346 US 7164114 B2 FIG, 4 US 2010/0181464 A1

However, although the CMOS image sensor equipped with the above-mentioned conventional digital pixel sensor can realize the global shutter function, for example, the charge overflowing from the photodiode during the storage period is not used in real time. There is a limit to wide dynamic range and high frame rate.

Random noise is an important performance index of CMOS image sensors, and it is known that pixels and AD converters are the main sources of random noise.
Generally, as a random noise reduction method, flicker noise is reduced by increasing the transistor size, or a capacitance is added to the comparator output and the band is reduced to reduce the noise filter effect by CDS. The method of aiming is known.
However, each method has the disadvantages that the inversion delay of the comparator deteriorates due to the increase in area and capacity, and the frame rate of the image sensor cannot be increased.

Further, an n-bit memory such as 8-bit or 12-bit is required as a memory unit for storing the data after the AD conversion process, but when reading the pixel signal in a plurality of stages such as two stages, the total is A capacity such as 2n bits is required.
Further, when considering the digital CDS, a larger capacity such as 4n bits is required.
Therefore, efficient access to the memory according to the AD conversion process is required.

Further, since the ADC (furthermore, the memory unit) including the comparator is arranged in each pixel, it is difficult to maximize the effective pixel area, and it is difficult to maximize the value per cost. ..

The present invention provides a solid-state image sensor, a method for driving a solid-state image sensor, and an electronic device that can realize a substantially wide dynamic range and a high frame rate and can efficiently access a memory. To do.
In addition, the present invention can substantially realize a wide dynamic range and a high frame rate, enable efficient access to the memory, reduce noise, and maximize the effective pixel area. It is an object of the present invention to provide a solid-state image sensor, a method for driving a solid-state image sensor, and an electronic device that can be expanded to the maximum and can maximize the value per cost.

The solid-state imaging device according to the first aspect of the present invention has a pixel unit in which pixels for photoelectric conversion are arranged and a readout unit for reading a pixel signal from the pixel of the pixel unit, and the pixels are stored. A photoelectric conversion element that stores the charge generated by photoelectric conversion during the period, a transfer element that can transfer the charge accumulated in the photoelectric conversion element to the transfer period after the storage period, and the photoelectric conversion element through the transfer element. Refer to the output node to which the accumulated charge is transferred, the output buffer unit that converts the charge of the output node into a voltage signal according to the amount of charge, and outputs the converted voltage signal, and the voltage signal by the output buffer unit. A comparison device that compares the voltage and outputs a digitized comparison result signal, a memory unit that can store data corresponding to the comparison result signal of the comparison device, and a comparison result signal of the comparison device. The comparator includes a memory control unit that controls access to the memory unit according to a state, and the comparator overflows from the photoelectric conversion element to the output node during the storage period under the control of the readout unit. The first comparison process that outputs a digitized first comparison result signal for the voltage signal according to the overflow charge, and the accumulation of the photoelectric conversion element transferred to the output node during the transfer period after the accumulation period. It is possible to perform a second comparison process for outputting a second digitized comparison result signal with respect to the voltage signal according to the charge, and the memory control unit may perform the first comparison process according to the first comparison process. Depending on the state of the comparison result signal, it is controlled whether or not to write the data corresponding to the second comparison result signal to the memory unit by the second comparison process.

A second aspect of the present invention includes a pixel unit in which pixels for photoelectric conversion are arranged and a readout unit for reading a pixel signal from the pixel of the pixel unit, and the pixel is photoelectrically converted during the accumulation period. A photoelectric conversion element that stores the charge generated by the above, a transfer element that can transfer the charge accumulated in the photoelectric conversion element to a transfer period after the storage period, and a charge accumulated in the photoelectric conversion element through the transfer element. Compare the output node to which the output node is transferred, the output buffer unit that converts the charge of the output node into a voltage signal according to the amount of charge, and outputs the converted voltage signal, and the voltage signal and reference voltage by the output buffer unit. A method of driving a solid-state imaging device, comprising: a comparer that performs a comparison process that outputs a digitized comparison result signal, and a memory unit that stores data corresponding to the comparison result signal of the comparer. When reading out the pixel signal of the pixel, in the comparator, under the control of the reading unit, the digitized first voltage signal according to the overflow charge overflowing from the photoelectric conversion element to the output node during the storage period. The first comparison process for outputting the comparison result signal of 1 and the digitized second for the voltage signal according to the stored charge of the photoelectric conversion element transferred to the output node during the transfer period after the storage period. It is possible to perform the second comparison process of outputting the comparison result signal of the above, and the second comparison process of the second comparison process is performed according to the state of the first comparison result signal of the first comparison process. It controls whether or not to write the data according to the comparison result signal of 2 to the memory unit, and controls the access to the memory unit according to the state of the comparison result signal of the comparer.

The electronic device according to the third aspect of the present invention includes a solid-state image pickup device and an optical system for forming a subject image on the solid-state image pickup device, and the solid-state image pickup device is provided with pixels for photoelectric conversion. It has a pixel unit and a readout unit that reads a pixel signal from the pixel of the pixel unit, and the pixel is a photoelectric conversion element that stores the charge generated by photoelectric conversion during the accumulation period, and the photoelectric conversion element. A transfer element capable of transferring the stored charge during the transfer period after the accumulation period, an output node to which the charge accumulated by the photoelectric conversion element is transferred through the transfer element, and the charge of the output node as the amount of charge. A comparator that performs comparison processing that compares the output buffer unit that converts to the corresponding voltage signal and outputs the converted voltage signal, the voltage signal by the output buffer unit and the reference voltage, and outputs the digitized comparison result signal. A memory unit that can store data corresponding to the comparison result signal of the comparer, and a memory control unit that controls access to the memory unit according to the state of the comparison result signal of the comparer. Under the control of the readout unit, the comparator outputs a digitized first comparison result signal for the voltage signal according to the overflow charge overflowing from the photoelectric conversion element to the output node during the accumulation period. A first comparison process and a second comparison result signal digitized with respect to the voltage signal according to the stored charge of the photoelectric conversion element transferred to the output node during the transfer period after the storage period are output. It is possible to perform the comparison process of 2, and the memory control unit performs the second comparison process according to the state of the first comparison result signal by the first comparison process. It controls whether or not to write the data according to the comparison result signal to the memory unit.

According to the present invention, it is possible to substantially realize a wide dynamic range and a high frame rate, and it is possible to efficiently access the memory.
Further, according to the present invention, it is possible to realize a substantially wide dynamic range and a high frame rate, efficiently access the memory, reduce noise, and maximize the effective pixel area. It can be expanded to the limit and the value per cost can be maximized.

It is a block diagram which shows the structural example of the solid-state image sensor which concerns on 1st Embodiment of this invention. It is a figure which shows an example of the digital pixel array of the pixel part of the solid-state image pickup apparatus which concerns on 1st Embodiment of this invention. It is a circuit diagram which shows an example of the pixel of the solid-state image pickup apparatus which concerns on 1st Embodiment of this invention. It is a simplified cross-sectional view which shows the structural example of the charge accumulation transfer system which is the main part of the digital pixel which concerns on 1st Embodiment of this invention, and is the potential figure at the time of overflow. It is a figure for demonstrating the 1st comparison process of the comparator which concerns on this embodiment. It is a figure for demonstrating the 1st comparison process of the comparator which concerns on this embodiment, and is a figure for demonstrating another pattern example of a reference voltage. It is a figure which shows the state of the optical time conversion when various reference voltages are input to the comparator which concerns on this embodiment. It is a figure which shows the optical response coverage in the digital pixel which concerns on 1st Embodiment of this invention. It is a figure which shows the structural example of the memory part and the output circuit which concerns on 1st Embodiment of this invention. It is a figure which shows an example of the frame reading sequence in the solid-state image pickup apparatus which concerns on 1st Embodiment of this invention. It is a figure for demonstrating the configuration example of the memory control part 240 which concerns on 1st Embodiment of this invention. This is a timing chart for explaining the operation of the memory control unit when the output of the comparator is inverted in the time stamp ADC mode. This is a timing chart for explaining the operation of the memory control unit when the output of the comparator is not inverted in the time stamp ADC mode. It is a schematic diagram for demonstrating the laminated structure of the solid-state image pickup apparatus which concerns on this 1st Embodiment. It is a simplified sectional view for demonstrating the laminated structure of the solid-state image pickup apparatus which concerns on this 1st Embodiment. It is a timing chart for demonstrating the reading operation mainly in the pixel part in the predetermined shutter mode of the solid-state image pickup apparatus which concerns on this 1st Embodiment. It is a figure which shows the operation sequence and the potential transition for explaining the reading operation mainly in a pixel part in the predetermined shutter mode of the solid-state image pickup apparatus which concerns on this 1st Embodiment. It is a figure for demonstrating the structural example of the memory control part which concerns on 2nd Embodiment of this invention. It is a timing chart for demonstrating the operation of the memory control part of FIG. 18 when the output of a comparator is inverted in the time stamp ADC mode. It is a timing chart for demonstrating the operation of the memory control part of FIG. 18 when the output of a comparator is not inverted in the time stamp ADC mode. It is a figure for demonstrating the solid-state image pickup apparatus which concerns on 3rd Embodiment of this invention, and is the figure which shows an example of the selection process of time stamp ADC mode operation and linear ADC mode operation. It is a circuit diagram which shows an example of the pixel of the solid-state image sensor which concerns on 4th Embodiment of this invention. It is a figure which shows an example of the structure of the electronic device to which the solid-state image sensor which concerns on embodiment of this invention is applied.

Hereinafter, embodiments of the present invention will be described in association with the drawings.

(First Embodiment)
FIG. 1 is a block diagram showing a configuration example of a solid-state image sensor according to the first embodiment of the present invention.
In the present embodiment, the solid-state image sensor 10 is configured by, for example, a CMOS image sensor including digital pixels (Digital Pixel) as pixels.

As shown in FIG. 1, the solid-state image sensor 10 has a pixel unit 20 as an image pickup unit, a vertical scanning circuit (row scanning circuit) 30, an output circuit 40, and a timing control circuit 50 as main components. ..
Among these components, for example, the vertical scanning circuit 30, the output circuit 40, and the timing control circuit 50 constitute a pixel signal reading unit 60.

In the first embodiment, the solid-state image sensor 10 includes a photoelectric conversion reading unit, an AD (analog-digital) conversion unit, and a memory unit as digital pixels in the pixel unit 20, and has, for example, a global shutter operation function. It is configured as a stacked CMOS image sensor.
In the solid-state imaging device 10 according to the first embodiment, as will be described in detail later, each digital pixel DP has an AD conversion function, and the AD conversion unit is a voltage signal read by a photoelectric conversion reading unit. It has a comparator (comparator) that performs a comparison process that compares the voltage with the reference voltage and outputs a digitized comparison result signal.
Under the control of the readout unit 60, the comparator outputs a digitized first comparison result signal for the voltage signal corresponding to the overflow charge overflowing from the photoelectric conversion element to the output node (floating diffusion) during the storage period. The comparison process of 1 and the second comparison process of outputting a second digitized comparison result signal for the voltage signal corresponding to the accumulated charge of the photoelectric conversion element transferred to the output node during the transfer period after the accumulation period. I do.

Further, the solid-state image sensor 10 has a memory control unit that controls access to the memory unit according to the state (level in this embodiment) of the comparison result signal of the comparator.
Then, does the memory control unit write data to the memory unit according to the second comparison result signal by the second comparison process according to the state of the first comparison result signal by the first comparison process? Control whether or not.
Specifically, when the level of the first comparison result signal by the first comparison processing changes from the first level to the second level during the first comparison processing period, the memory control unit receives a second. Writing of the data corresponding to the second comparison result signal by the comparison process to the memory unit is prohibited.
On the other hand, when the level of the first comparison result signal by the first comparison processing does not change at the first level during the first comparison processing period, the memory control unit performs a second comparison processing. Allows writing of data to the memory unit according to the comparison result signal of.

Hereinafter, the outline of the configuration and function of each part of the solid-state image sensor 10, particularly the configuration and function of the pixel unit 20 and the digital pixel, the readout processing related to them, the laminated structure of the pixel portion 20 and the readout unit 60, and the like are described in detail. Describe.

(Structure of pixel unit 20 and digital pixel 200)
FIG. 2 is a diagram showing an example of a digital pixel array of the pixel portion of the solid-state image sensor 10 according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram showing an example of pixels of the solid-state image sensor 10 according to the first embodiment of the present invention.

As shown in FIG. 2, the pixel unit 20 has a plurality of digital pixels 200 arranged in a matrix of N rows and M columns.
Note that FIG. 2 shows an example in which nine digital pixels 200 are arranged in a matrix of 3 rows and 3 columns (matrix of M = 3 and N = 3) for the sake of simplification of the drawing. ..

The digital pixel 200 according to the first embodiment has a photoelectric conversion readout unit (denoted as PD in FIG. 2) 210, an AD conversion unit (denoted as ADC in FIG. 2) 220, and a memory unit (denoted as MEM in FIG. 2). It includes 230 and a memory control unit (denoted as MCT in FIG. 2) 240.
As will be described in detail later, the pixel unit 20 of the first embodiment is configured as a laminated CMOS image sensor of the first substrate 110 and the second substrate 120, but in this example, FIG. 3 As shown in the above, a photoelectric conversion reading unit 210 is formed on the first substrate 110, and an AD conversion unit 220, a memory unit 230, and a memory control unit 240 are formed on the second substrate 120.

The photoelectric conversion reading unit 210 of the digital pixel 200 includes a photodiode (photoelectric conversion element) and an in-pixel amplifier.
Specifically, the photoelectric conversion reading unit 210 has, for example, a photodiode PD1 which is a photoelectric conversion element.
For this photodiode PD1, a transfer transistor TG1-Tr as a transfer element, a reset transistor RST1-Tr as a reset element, a source follower transistor SF1-Tr as a source follower element, and a current transistor IC1-Tr as a current source element. , It has one floating diffusion FD1 as an output node ND1 and one read node ND2.
As described above, the photoelectric conversion reading unit 210 of the digital pixel 200 according to the first embodiment has four transistors of the transfer transistor TG1-Tr, the reset transistor RST1-Tr, the source follower transistor SF1-Tr, and the current transistor IC1-Tr. It is configured to include (4Tr).

In the first embodiment, the output buffer unit 211 includes the source follower transistor SF1-Tr, the current transistor IC1-Tr, and the read node ND2.

In the photoelectric conversion reading unit 210 according to the first embodiment, the reading node ND2 of the output buffer unit 211 is connected to the input unit of the AD conversion unit 220.
The photoelectric conversion reading unit 210 converts the charge of the floating diffusion FD1 as an output node into a voltage signal according to the amount of charge, and outputs the converted voltage signal VSL to the AD conversion unit 220.

More specifically, in the first comparison processing period PCMP1 of the AD conversion unit 220, the photoelectric conversion reading unit 210 overflows from the photodiode PD1 which is a photoelectric conversion element to the floating diffusion FD1 as an output node during the storage period PI. The voltage signal VSL corresponding to the overflow charge is output.

Further, the photoelectric conversion reading unit 210 is used to charge the product of the photodiode PD1 transferred to the floating diffusion FD1 as an output node during the transfer period PT after the storage period PI in the second comparison processing period PCMP2 of the AD conversion unit 220. The corresponding voltage signal VSL is output.
The photoelectric conversion reading unit 210 outputs a reading reset signal (signal voltage) (VRST) and a reading signal (signal voltage) (VSIG) as pixel signals to the AD conversion unit 220 in the second comparison processing period PCMP2.

The photodiode PD1 generates and accumulates a signal charge (here, an electron) in an amount corresponding to the amount of incident light.
Hereinafter, the case where the signal charge is an electron and each transistor is an n-type transistor will be described, but the signal charge may be a hole or each transistor may be a p-type transistor.
The present embodiment is also effective when each transistor is shared between a plurality of photodiodes and transfer transistors.

In each digital pixel 200, an embedded photodiode (PPD) is used as the photodiode (PD).
Since surface levels due to defects such as dangling bonds exist on the surface of the substrate forming the photodiode (PD), a large amount of electric charge (dark current) is generated by the thermal energy, and the correct signal cannot be read.
In the embedded photodiode (PPD), by embedding the charge storage portion of the photodiode (PD) in the substrate, it is possible to reduce the mixing of dark current into the signal.

The transfer transistor TG1-Tr of the photoelectric conversion readout unit 210 is connected between the photodiode PD1 and the floating diffusion FD1 and is controlled by the control signal TG applied to the gate through the control line.
In the transfer transistor TG1-Tr, the control signal TG is selected for the high (H) level transfer period PT and becomes conductive, and the charge (electrons) photoelectrically converted and accumulated by the photodiode PD1 is transferred to the floating diffusion FD1.
After the photodiode PD1 and the floating diffusion FD1 are reset to a predetermined reset potential, the transfer transistor TG1-Tr is in a non-conducting state in which the control signal TG is at the low (L) level, and the photodiode PD1 has a storage period PI. However, at this time, if the intensity (amount) of the incident light is very high, the charge exceeding the saturated charge amount overflows into the floating diffusion FD1 as an overflow charge through the overflow path under the transfer transistor TG1-Tr.

The reset transistor RST1-Tr is connected between the power supply line Vdd of the power supply voltage VDD and the floating diffusion FD1 and is controlled by the control signal RST applied to the gate through the control line.
The reset transistor RST1-Tr is selected for the control signal RST during the H level reset period to be in a conductive state, and resets the floating diffusion FD1 to the potential of the power supply line Vdd of the power supply voltage VDD.

In the source follower transistor SF1-Tr as the source follower element, the source is connected to the read node ND2, the drain side is connected to the power supply line Vdd, and the gate is connected to the floating diffusion FD1.
The drain and source of the current transistor IC1-Tr as a current source element are connected between the read node ND2 and the reference potential VSS (for example, GND). The gate of the current transistor IC1-Tr is connected to the supply line of the control signal VBNPIX.
Then, the signal line LSGN1 between the read node ND2 and the input unit of the AD conversion unit 220 is driven by the current transistor IC1-Tr as a current source element.

4 (A) and 4 (B) are a simplified cross-sectional view showing a configuration example of a charge storage transfer system which is a main part of a digital pixel according to the first embodiment of the present invention, and a potential diagram at the time of overflow.

Each digital pixel cell PXLC has a substrate having a first substrate surface 1101 side (for example, a back surface side) irradiated with light L and a second substrate surface 1102 side facing the first substrate surface 1101 side (this). In the example, it is formed on the first substrate 110) and separated by the separation layer SPL.
The digital pixel cell PXL C in FIG. 4 includes a photodiode PD1 forming a photoelectric conversion readout unit 210, a transfer transistor TG1-Tr, a floating diffusion FD1, a reset transistor RST1-Tr, a separation layer SPL, and a color (not shown). It is configured to include a filter unit and a microlens.

(Polydiode configuration)
The photodiode PD1 is a first conductive type (this) formed so as to be embedded in a semiconductor substrate having a first substrate surface 1101 side and a second substrate surface 1102 side opposite to the first substrate surface 1101 side. In the embodiment, the n-type) semiconductor layer (n-layer in the present embodiment) 2101 is included, and is formed so as to have a photoelectric conversion function and a charge storage function of the received light.
A second conductive type (p type in this embodiment) separation layer SPL is formed on a side portion of the photodiode PD1 in a direction (X direction) orthogonal to the normal of the substrate.

As described above, in the present embodiment, the embedded photodiode (PPD) is used as the photodiode (PD) in each digital pixel cell PXLC.
Since surface levels due to defects such as dangling bonds exist on the surface of the substrate forming the photodiode (PD), a large amount of electric charge (dark current) is generated by the thermal energy, and the correct signal cannot be read.
In the embedded photodiode (PPD), by embedding the charge storage portion of the photodiode (PD) in the substrate, it is possible to reduce the mixing of dark current into the signal.

In the photodiode PD1 of FIG. 4, the n-layer (first conductive semiconductor layer) 2101 is configured to have a two-layer structure in the normal direction of the substrate 110 (Z direction of the Cartesian coordinate system in the figure). There is.
In this example, the n-layer 2102 is formed on the first substrate surface 1101 side, the n-layer 2103 is formed on the second substrate surface 1102 side of the n-layer 2102, and the second substrate surface 1102 of the n-layer 2103 is formed. A p + layer 2104 and a p layer 2105 are formed on the side.
Further, the p + layer 2106 is formed on the first substrate surface 1101 side of the n− layer 2102.
The p + layer 2106 is uniformly formed not only over the photodiode PD1 but also over the separation layer SPL and further other digital pixel cells PXLC.

A color filter portion is formed on the light incident side of the P + layer 2106, and further, the micro is on the light incident emitting side of the color filter portion so as to correspond to a part of the photodiode PD1 and the separation layer SPL. The lens is formed.

These configurations are examples, and may be a single-layer structure, or may be a laminated structure of three layers, four layers or more.

(Structure of separation layer in X direction (column direction))
In the p-type separation layer SPL in the X direction (column direction) of FIG. 4, the direction on the side in contact with the n-layer 2102 of the photodiode PD1 and orthogonal to the normal of the substrate (X direction of the orthogonal coordinate system in the figure). ), A first p layer (second conductive semiconductor layer) 2107 is formed.
Further, in the p-type separation layer SPL, the second p-layer (second conductive semiconductor layer) 2108 is located on the right side of the first p-layer 2107 in the X direction in the normal direction of the substrate 110 (orthogonal in the figure). It is configured to have a two-layer structure (in the Z direction of the coordinate system).
In this example, in the second p-layer 2108, the p-layer 2109 is formed on the first substrate surface 1101 side, and the p-layer 2110 is formed on the second substrate surface 1102 side of the p-layer 2109.

These configurations are examples, and may be a single-layer structure, or may be a laminated structure of three layers, four layers or more.

A p + layer 2106 similar to the photodiode 2110 is formed on the first substrate surface 1101 side of the first p-layer 2107 and the second p-layer 2109 of the p-type separation layer SPL.

The n-layer 2103 is formed so as to extend so that an overflow path OVP is formed over a part of the first p-layer 2107 of the p-type separation layer SPL on the second substrate surface 1102 side.
Then, the gate electrode 2111 of the transfer transistor TG1-Tr is formed on the p layer 2105 on the second substrate surface 1102 side of the n layer 2103 via the gate insulating film.
Further, an n + layer 2112 serving as a floating diffusion FD1 is formed on the second substrate surface 1102 side of the first p layer 2107 of the p-type separation layer SPL, and the channel of the reset transistor RST1-Tr is adjacent to the n + layer 2112. The n + layer 2114 is formed adjacent to the p layer 2113 and the p layer 2113 which are the formation regions.
Then, a gate electrode 2115 is formed on the p layer 2113 via a gate insulating film.

In such a structure, when the intensity (amount) of the incident light is very high, the charge exceeding the saturated charge amount overflows to the floating diffusion FD1 as an overflow charge through the overflow path OVP under the transfer transistor TG1-Tr.

The AD conversion unit 220 of the digital pixel 200 compares the analog voltage signal VSL output by the photoelectric conversion reading unit 210 with a lamp waveform or a fixed voltage reference voltage VREF changed with a predetermined inclination. It has a function to convert to a digital signal.

As shown in FIG. 3, the AD conversion unit 220 includes a comparator (COMP) 221, a counter (CNT) 222, an input side coupling capacitor C221, an output side load capacitor C222, and a reset switch SW-RST. ing.

In the comparator 221, the voltage signal VSL output to the signal line LSGN1 from the output buffer unit 211 of the photoelectric conversion reading unit 210 is supplied to the inverting input terminal (-) as the first input terminal, and the second input terminal. The reference voltage VREF is supplied to the non-inverting input terminal (+), and the voltage signal VST and the reference voltage VREF are compared, and a comparison process is performed to output a digitized comparison result signal SCMP.

In the comparator 221, the coupling capacitor C221 is connected to the inverting input terminal (-) as the first input terminal, and the output buffer unit 211 and the second substrate of the photoelectric conversion reading unit 210 on the first substrate 110 side. By AC-coupling the input unit of the comparator 221 of the AD conversion unit 220 on the 1120 side, noise reduction is achieved and a high SNR can be realized at low illuminance.

Further, in the comparator 221, the reset switch SW-RST is connected between the output terminal and the inverting input terminal (-) as the first input terminal, and the load capacitor C222 is connected between the output terminal and the reference potential VSS. It is connected.

Basically, in the AD conversion unit 220, the analog signal (potential VSL) read from the output buffer unit 211 of the photoelectric conversion reading unit 210 to the signal line LSGN1 has a reference voltage VREF, for example, a certain inclination in the comparator 221. It is compared with the ramp signal RAMP, which is a linearly changing slope waveform.
At this time, the counter 222 arranged for each column is operating as in the comparator 221, and the voltage signal VSL is digitally changed by changing the counter value with the lamp signal RAMP having the lamp waveform while maintaining a one-to-one correspondence. Convert to a signal.
Basically, the AD conversion unit 220 converts a change in the reference voltage VREF (for example, a lamp signal RAMP) into a change in voltage into a change in time, and counts the time in a certain period (clock) to obtain a digital value. Convert to.
Then, when the analog signal VSL and the lamp signal RAMP (reference voltage VREF) intersect, the output of the comparator 221 is inverted and the input clock of the counter 222 is stopped, or the clock at which the input is stopped is transferred to the counter 222. The input is input, and the value (data) of the counter 222 at that time is stored in the memory unit 230 to complete the AD conversion.
After the end of the above AD conversion period, the data (signal) stored in the memory unit 230 of each digital pixel 200 is output from the output circuit 40 to a signal processing circuit (not shown), and a two-dimensional image is generated by a predetermined signal processing. ..

(First comparison process and second comparison process in the comparator 221)
Then, the comparator 221 of the AD conversion unit 220 of the first embodiment is driven by the readout unit 60 so as to perform the following two first comparison processing and the second comparison processing during the pixel signal readout period. Be controlled.

In the first comparison processing CMPR1, the comparator 221 responds to the overflow charge overflowing from the photodiode PD1 which is a photoelectric conversion element to the floating fusion FD1 which is an output node during the accumulation period PI under the control of the readout unit 60. The first digitized comparison result signal SCMP1 with respect to the voltage signal VSL1 is output.
The operation of the first comparison process CMPR1 is also referred to as an operation of the time stamp ADC mode.

In the second comparison process CMPR2, the comparator 221 responds to the stored charge of the photodiode PD1 transferred to the floating fusion FD1 which is an output node during the transfer period PT after the storage period PI under the control of the readout unit 60. The second comparison result signal SCMP2 digitized with respect to the voltage signal VSL2 (VSIG) is output.
Actually, in the second comparison processing CMPR2, before the digitization of the voltage signal VSL2 (VSIG) according to the accumulated charge, the digital of the voltage signal VSL2 (VRRT) corresponding to the reset voltage of the floating diffusion FD1 at the time of reset is performed. To be reset.
The operation of the second comparison process CMPR2 is also referred to as an operation of the linear ADC mode.

In the present embodiment, basically, in the accumulation period PI, after the photodiode PD1 and the floating diffusion FD1 are reset to the reset level, the transfer transistor TG1-Tr is switched to the conduction state and the transfer period PT is started. It is a period until it is reset.
The period PCMPR1 of the first comparison process CMPR1 is the period from when the photodiode PD1 and the floating diffusion FD1 are reset to the reset level until the floating diffusion FD1 is reset to the reset level before the transfer period PT is started. Is.
The period PCMPR2 of the second comparison process CMPR2 is a period after the floating diffusion FD1 is reset to the reset level, and is a period including a period after the transfer period PT.

Here, the first comparative processing CMPR1 will be described in more detail.
FIG. 5 is a diagram for explaining the first comparison processing CMPR1 of the comparator 221 according to the present embodiment.
In FIG. 5, the horizontal axis represents time and the vertical axis represents the voltage level VFD of the floating diffusion FD1 which is an output node.

The voltage level VFD of the floating diffusion FD1 has the smallest charge amount at the reset level, and the voltage level VFD has the highest level VFDini.
On the other hand, in the saturated state, the amount of charge is large, and the voltage level VFD becomes a low level VFD sat.
According to such a condition, the reference voltage VREF1 of the comparator 221 is set to the voltage VREFsat fixed to the level in the unsaturated state before the saturation state, or from the voltage level VREFrst at the reset level to the voltage level VREFsat. Set the lamp voltage to VREFlamp.

When such a reference voltage VREF1 is set to VREFat or VREFramp in the first comparison process CMPR1, as shown in FIG. 5, the charge amount is larger when the intensity of the incident light is higher and the illuminance is higher. The time for the output of the device 221 to flip (reverse) is fast.
Example of the highest illuminance In the case of EXP1, the output of the comparator 221 immediately flips (inverts) from the first level (eg, low level) to the second level (high level) at time t1.
Example Example of illuminance lower than EXP1 In the case of EXP2, the output of the comparator 221 flips (inverts) from the first level (for example, low level) to the second level (high level) at time t2 later than time t1. ..
Example Example of illuminance lower than EXP2 In the case of EXP3, the output of the comparator 221 flips (inverts) from the first level (for example, low level) to the second level (high level) at time t3 later than time t2. ..

As described above, in the first comparison processing CMPR1, the comparator 221 has a first comparison result signal corresponding to a time corresponding to the amount of overflow charge from the photodiode PD1 to the floating diffusion FD1 during a predetermined period of the accumulation period PI. Output SCMP1.

More specifically, the comparator 221 corresponds to a predetermined threshold value of the photodiode PD1 at the maximum sampling time at which the overflow charge starts to overflow from the photodiode PD1 to the floating diffusion FD1 which is an output node in the first comparison process CMPR1. It is possible to perform comparison processing with the optical level from the signal level to the signal level obtained in the minimum sampling time.

As described above, the photo conversion operation in the time stamp ADC mode is performed with the light to time conversion in the storage period PI.
As shown in FIG. 5, under very bright light, the output state of the comparator 221 is inverted from the first level (eg low level) to the second level (high level) immediately after the reset activation period. , Its light level corresponds to the saturation signal (well capacitance) described in the following time.

((FD saturation amount x accumulation time) / sampling period) + PD saturation amount For example, FD saturation: 8Ke @ 150uV / e to FD capacity 1.1fF, minimum sampling time: 15nsec, accumulation time: 3msec:
Suppose that.

In this time stamp ADC operation mode, as described above, the minimum sampling time from the signal level corresponding to the predetermined threshold value of the photodiode PD1 at the maximum sampling time at which the overflow charge starts to overflow from the photodiode PD1 to the floating diffusion FD1 which is the output node. It is possible to cover the optical level up to the signal level obtained in.

FIG. 6 is a diagram for explaining the first comparison processing CMPR1 of the comparator 221 according to the present embodiment, and is a diagram for explaining another pattern example of the reference voltage.

The reference voltage VREF may be a lamp waveform (signal) RAMP changed with a predetermined slope shown in FIG. 6 in FIG. 6 or a fixed voltage DC shown in FIG. 6 in (2). , The log (log) shown in (3) in FIG. 6 and the voltage signal having an exponential value shown in (4) in FIG. 6 may be present.

FIG. 7 is a diagram showing a state of optical time conversion when various reference voltages VREF are input to the comparator according to the present embodiment.
In FIG. 7, the horizontal axis shows the sampling time, and the vertical axis shows the estimated signal in the overflow signal. The overflow signal here is estimated under the condition that the transfer transistor TG1-Tr is in a conductive state and the photodiode PD1 is not charged (non-overflow).

FIG. 7 shows the sampling time in which the comparator 221 corresponds to the overflow charge (signal) due to the nature (suitability) of the applied light.
FIG. 7 shows various fixed reference voltages DC1, DC2, DC3 and sampling times that are inverted with respect to the lamp reference voltage VRAMP. Here, a linear reference lamp is used.

When the operation of the time stamp ADC mode for performing the first comparison process CMPR1 for the saturated overflow charge is completed, the floating diffusion FD1 and the comparator 221 are reset, and then the second comparison process CMPR2 for the unsaturated charge is performed linearly. The operation shifts to the ADC mode.

FIG. 8 is a diagram showing optical response coverage in a digital pixel according to the first embodiment of the present invention.
In FIG. 8, A shows a signal by the time stamp ADC mode operation, and B shows a signal by the linear ADC mode operation.

Since the time stamp ADC mode can have an optical response to very bright light, the linear ADC mode can have an optical response from a dark level. For example, a dynamic range performance of 120 dB can be realized.
For example, as described above, the saturation signal in the optical conversion range corresponds to 900 Ke.
Since the linear ADC mode operates in the normal read mode to which the ADC is applied, it can cover from the noise level of 2e to the saturation of the photodiode PD1 of 8 Ke and the floating diffusion FD1.
The coverage of the linear ADC mode can be extended to 30 Ke with additional switches and capacities.

FIG. 9 is a diagram showing a configuration example of a memory unit and an output circuit according to the first embodiment of the present invention.

In the comparator 221, the first comparison result signal SCMP1 in which the voltage signal corresponding to the overflow charge of the floating diffusion FD1 is digitized by the first comparison processing CMPR1 and the storage of the photodiode PD1 by the second comparison processing CMPR2. The second comparison result signal SCMP2 in which the charge is digitized is associated and stored as digital data in the n-bit memory 231.
The memory 231 capable of sample-holding n-bit data of the memory unit 230 is composed of an SRAM, a DRAM, or the like, and is supplied with, for example, a digitally converted signal, corresponds to a photo conversion code, and is an output circuit 40 around a pixel array. It can be read by the external IO buffer 41.

The memory 231 is accessed by the output signal B of the memory control unit 240 according to the state (level in this embodiment) of the comparison result signal of the comparator 221. Specifically, whether or not to write (overwrite). Is controlled.
When the signal B corresponding to the first comparison result signal SCMP1 by the first comparison processing CMPR1 is supplied to the memory 231 at the first level (low level), writing (overwriting) is prohibited and the memory 231 is prohibited from writing (overwriting) to the second level. Writing (overwriting) is allowed when supplied at (high level).

FIG. 10 is a diagram showing an example of a frame readout sequence in the solid-state image sensor 10 according to the first embodiment of the present invention.
Here, an example of the frame readout method in the solid-state image sensor 10 will be described.
In FIG. 10, TS indicates the processing period of the time stamp ADC, and Lin indicates the processing period of the linear ADC.

As mentioned above, the overflow charge is accumulated in the floating diffusion FD1 during the accumulation period PI. The time stamp ADC mode operates during the accumulation time PI.
In practice, the time stamp ADC mode operates during the accumulation period PI until the floating diffusion FD1 is reset.
When the operation of the time stamp ADC mode is completed, the mode shifts to the linear ADC mode, the signal (VRST) at the time of resetting the floating diffusion FD1 is read, and the digital signal is converted to be stored in the memory unit 230.
Further, after the end of the storage period PI, in the linear ADC mode, the signal (VSIG) corresponding to the stored charge of the photodiode PD1 is read and converted so that the digital signal is stored in the memory unit 230.
The read frame is executed by reading digital signal data from the memory node and has such a MIMO data format, eg, through the IO buffer 41 (FIG. 9) of the output circuit 40, the solid-state image sensor 10 (image). It is sent to the outside of the sensor). This operation can be performed globally for all pixel arrays.

Further, in the pixel unit 20, the photodiode PD1 is reset by using the reset transistor RST1-Tr and the transfer transistor TG1-Tr at the same time for all the pixels, so that the exposure for all the pixels is started simultaneously in parallel. Further, after the predetermined exposure period (accumulation period PI) is completed, the output signal from the photoelectric conversion reading unit is sampled by the AD conversion unit 220 and the memory unit 230 using the transfer transistor TG1-Tr, so that all pixels can be simultaneously sampled. The exposure is finished in parallel. As a result, complete shutter operation is electronically realized.

(Configuration and function of memory control unit 240)
The solid-state image sensor 10 of the present embodiment further includes a memory control unit 240 that controls access to the memory unit according to the state (level in the present embodiment) of the comparison result signal of the comparator 221.
The memory control unit 240 is a memory of data corresponding to the second comparison result signal SCMP2 by the second comparison processing CMPR2 according to the state (output level) of the first comparison result signal SCMP1 by the first comparison processing CMPR1. It controls whether or not to write to the unit 230.
Specifically, in the memory control unit 240, during the first comparison processing period PSMPR1, the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 is changed from the first level (for example, low level) to the second level. When the level (high level) is changed, the writing of the data corresponding to the second comparison result signal SCMP2 by the second comparison processing CMPR2 to the memory unit 230 is prohibited.
On the other hand, when the memory control unit 240 does not change the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 during the first comparison processing period CMPR1 as the first level (low level). Second comparison processing Allows the CMPR2 to write data corresponding to the second comparison result signal SCMP2 to the memory unit 230.

The reason for providing the memory control unit 240 will be described below.
In the time stamp ADC mode, during the first comparison processing period PSMPR1, the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 changes from the first level (for example, low level) to the second level (high level). ) Means the following.
That is, in this case, very (extremely) high illuminance (bright) light is applied to the photodiode PD1, and the photoelectrically converted charge overflows from the photodiode PD1 to the floating diffusion FD1 as an overflow charge. It means that the read signal of the linear ADC mode of is not necessary.
Therefore, in this case, the memory control unit 240 prohibits the writing (overwriting) of the data corresponding to the second comparison result signal SCMP2 by the second comparison processing CMPR2 to the memory unit 230.

On the other hand, in the time stamp ADC mode, during the first comparison processing period PSMPR1, the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 changes from the first level (for example, low level) to the second level (for example, low level). Not changing to high level) means the following.
That is, in this case, there is an extremely high probability that the photodiode PD1 is irradiated with light having a normal illuminance of dark to medium brightness, and the photoelectrically converted charge overflows from the photodiode PD1 to the floating diffusion FD1 as overflow charge. The low value means that a subsequent linear ADC mode read signal is necessary.
Therefore, in this case, the memory control unit 240 allows the data to be written (overwritten) to the memory unit 230 according to the second comparison result signal SCMP2 by the second comparison process CMPR2.

FIG. 11 is a diagram for explaining a configuration example of the memory control unit 240 according to the first embodiment of the present invention.
FIG. 12 is a timing chart for explaining the operation of the memory control unit when the output of the comparator is inverted in the time stamp ADC mode.
FIG. 13 is a timing chart for explaining the operation of the memory control unit when the output of the comparator is not inverted in the time stamp ADC mode.

The memory control unit 240 of FIG. 11 includes a flag bit memory cell (Flag) 241 and a NOR circuit 242 as a gate circuit.

The flag bit memory cell 241 is a flag sampling signal FLG. SAMP, the first comparison result signal SCMP1 by the first comparison processing CMPR1 is supplied.
The flag bit memory cell 241 receives the flag sampling signal FLG after the end of the first comparison processing period PCMPR1. When the SAMP is supplied, a signal indicating that the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 changes from the first level (low level) to the second level (high level). A is set to the second level (high level) and output to the NOR circuit 242.
The flag bit memory cell 241 receives the flag sampling signal FLG after the end of the first comparison processing period PCMPR1. When SAMP is supplied, the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 has not changed from the first level (low level) to the second level (high level), signal A. Is set to the first level (low level) and output to the NOR circuit 242.

The NOR circuit 242 is supplied with the output signal A of the flag bit memory cell 241 and the first comparison result signal SCMP1 by the first comparison processing CMPR1.
The NOR circuit 242 outputs the signal A in a state where the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 is changed from the first level (low level) to the second level (high level). When input at the second level (high level), the signal B is set to the first level (low level) and output to the memory unit 230 to prohibit writing (overwriting).
The NOR circuit 242 outputs the signal A in a state where the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 has not changed from the first level (low level) to the second level (high level). When inputting at the first level (low level), the signal B is set to the second level (high level) and output to the memory unit 230 to allow writing (overwriting).

Since the flag bit memory cell 241 is a part of the ADC memory 231, there is no layout-like overhead and the area efficiency is good.
Further, since the NOR circuit 242 can be configured with 4 transistors (4T) in the minimum size, the overhead on the area can be minimized.
By providing the memory control unit 240, only one ADC memory is required even though the two-step comparison process is performed.

In the memory control unit 240, as shown in FIG. 12, the flag sampling signal FLG is performed after the end of the first comparison processing period PCMPR1. When the SAMP is supplied, it is flagged that the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 has changed from the first level (low level) to the second level (high level). The output signal A of the bit memory cell 241 is input to the NOR circuit 242 at the second level (high level). In response to this, the signal B is set to the first level (low level) from the NOR circuit 242 and output to the memory unit 230, and writing (overwriting) is prohibited.

In the memory control unit 240, as shown in FIG. 13, the flag sampling signal FLG is performed after the end of the first comparison processing period PCMPR1. When the SAMP is supplied, if the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 remains at the first level (low level) and does not change, the output signal of the flag bit memory cell 241 A is input to the NOR circuit 242 at the first level (low level). In response to this, the signal B is set to the second level (high-low level) from the NOR circuit 242 and output to the memory unit 230, and writing (overwriting) is permitted.

The flag bit memory cell 241 and the NOR circuit 242 have a clear signal FLG after the end of the second comparison processing period PCMPR2 in the linear ADC mode. Cleared to work status by CLR.

The vertical scanning circuit 30 drives the photoelectric conversion reading unit 210 of the digital pixel 200 through the row scanning control line in the shutter row and the readout row according to the control of the timing control circuit 50.
The vertical scanning circuit 30 has a reference voltage VREF1 set according to the first comparison processing CMPR1 and the second comparison processing CMPR2 for the comparator 221 of each digital pixel 200 according to the control of the timing control circuit 50. , VREF2 is supplied.
Further, the vertical scanning circuit 30 outputs a row selection signal of the row address of the read row that reads out the signal and the row row of the shutter row that resets the charge accumulated in the photodiode PD according to the address signal.

As shown in FIG. 9, the output circuit 40 includes an IO buffer 41 arranged corresponding to the memory output of each digital pixel 200 of the pixel unit 20, and outputs digital data read from each digital pixel 200 to the outside. do.

The timing control circuit 50 generates a timing signal necessary for signal processing of the pixel unit 20, the vertical scanning circuit 30, the output circuit 40, and the like.

In the first embodiment, the reading unit 60 controls to read the pixel signal from the digital pixel 200, for example, in the global shutter mode.

(Laminate structure of solid-state image sensor 10)
Next, the laminated structure of the solid-state image pickup device 10 according to the first embodiment will be described.

14 (A) and 14 (B) are schematic views for explaining the laminated structure of the solid-state image pickup device 10 according to the first embodiment.
FIG. 15 is a simplified cross-sectional view for explaining the laminated structure of the solid-state image sensor 10 according to the first embodiment.

The solid-state image sensor 10 according to the first embodiment has a laminated structure of a first substrate (upper substrate) 110 and a second substrate (lower substrate) 120.
The solid-state image pickup device 10 is formed as an image pickup device having a laminated structure cut out by dicing after bonding at a wafer level, for example.
In this example, it has a structure in which the first substrate 110 and the second substrate 120 are laminated.

The first substrate 110 is formed with a photoelectric conversion reading unit 210 of each digital pixel 200 of the pixel unit 20 centered on the central portion thereof.
A photodiode PD is formed on the first surface 111 side where the light L of the first substrate 110 is the incident side, and a microlens MCL and a color filter are formed on the light incident side thereof.
A transfer transistor TG1-Tr, a reset transistor RST1-Tr, a source follower transistor SF1-Tr, and a current transistor IC1-Tr are formed on the second surface side of the first substrate 110.

As described above, in the first embodiment, the photoelectric conversion reading unit 210 of the digital pixel 200 is basically formed in a matrix on the first substrate 110.

The AD conversion unit 220, the memory unit 230, and the memory control unit 240 of each digital pixel 200 are formed in a matrix on the second substrate 120.
Further, the vertical scanning circuit 30, the output circuit 40, and the timing control circuit 50 may also be formed on the second substrate 120.

In such a laminated structure, for example, the readout node ND2 of each photoelectric conversion readout unit 210 of the first substrate 110 and the inverting input terminal (-) of the comparator 221 of each digital pixel 200 of the second substrate 120 are shown in FIG. As shown in 3, electrical connection is made using a signal line LSGN1, a microbump BMP, a via (Die-to-Die Via), or the like, respectively.
Further, in the present embodiment, the readout node ND2 of each photoelectric conversion readout unit 210 of the first substrate 110 and the inverting input terminal (-) of the comparator 221 of each digital pixel 200 of the second substrate 120 are coupled capacitors. It is AC-coupled by C221.

(Reading operation of the solid-state image sensor 10)
The characteristic configurations and functions of each part of the solid-state image sensor 10 have been described above.
Next, the operation of reading out the pixel signal of the digital pixel 200 of the solid-state image sensor 10 according to the first embodiment will be described in detail.

FIG. 16 is a timing chart for explaining a readout operation mainly in the pixel portion in a predetermined shutter mode of the solid-state image sensor according to the first embodiment.
17 (A) to 17 (D) are diagrams showing an operation sequence and potential transition for explaining a readout operation mainly in a pixel portion in a predetermined shutter mode of the solid-state image sensor according to the first embodiment.

First, at the start of the read operation, as shown in FIGS. 16 and 17A, a global reset is performed to reset the photodiode PD1 and the floating diffusion FD1 of each digital pixel 200.
In the global reset, the reset transistor RST1-Tr and the transfer transistor TG1-Tr are held in a conductive state for a predetermined period at the same time for all pixels, and the photodiode PD1 and the floating diffusion FD1 are reset. Then, the reset transistor RST1-Tr and the transfer transistor TG1-Tr are switched to the non-conducting state at the same time for all the pixels, and the exposure, that is, the accumulation of electric charge is started in parallel for all the pixels.

Then, as shown in FIGS. 16 and 17 (B), the operation of the time stamp (TS) ADC mode for the overflow charge is started.
The overflow charge is accumulated in the floating diffusion FD1 during the accumulation period PI. The time stamp ADC mode operates during the accumulation time PI, specifically, during the accumulation period PI, until the floating diffusion FD1 is reset.

In the time stamp (TS) ADC mode, in the photoelectric conversion reading unit 210, the photodiode PD1 is changed to the floating diffusion FD1 as an output node in the storage period PI corresponding to the first comparison processing period PCMP1 of the AD conversion unit 220. The voltage signal VSL1 corresponding to the overflow charge is output.
Then, in the comparator 221 of the AD conversion unit 220, the first comparison processing CMPR1 is performed. In the comparator 221, under the control of the readout unit 60, the overflow charge overflowing from the photodiode PD1 to the floating fusion FD1 which is an output node during the accumulation period PI until the floating diffusion FD1 is reset. The digitized first comparison result signal SCMP1 with respect to the corresponding voltage signal VSL1 is output, and the digital data corresponding to the first comparison result signal SOCM1 is stored in the memory 231 of the memory unit 230.

Next, as shown in FIGS. 16 and 17 (C), the operation of the time stamp (TS) ADC mode for the overflow charge is terminated, the mode is changed to the linear ADC mode, and the reset period PR2 of the floating diffusion FD1 is started.
In the reset period PR2, the reset transistor RST1-Tr is held in the conduction state for a predetermined period, and the floating diffusion FD1 is reset. The signal (VRST) at the time of resetting the floating diffusion FD1 is read out, and the digital signal is stored in the memory 232 of the memory unit 230.
Then, the reset transistor RST1-Tr is switched to the non-conducting state. In this case, the accumulation period PI is continued.

Next, as shown in FIGS. 16 and 17 (D), the accumulation period PI ends, and the transfer period PT is entered.
In the transfer period PT, the transfer transistors TG1-Tr are held in a conductive state for a predetermined period, and the accumulated charge of the photodiode PD1 is transferred to the floating diffusion FD1.

In the linear (Lin) ADC mode, in the photoelectric conversion reading unit 210, the floating diffusion FD1 as an output node from the photodiode PD1 after the storage period PI ends corresponding to the second comparison processing period PCMP2 of the AD conversion unit 220. The voltage signal VSL2 corresponding to the stored charge transferred to is output.
Then, in the comparator 221 of the AD conversion unit 220, the second comparison processing CMPR2 is performed. In the comparator 221, under the control of the readout unit 60, after the storage period PI, the second comparison result digitized with respect to the voltage signal VSL2 according to the stored charge transferred from the photodiode PD1 to the floating fusion FD1 which is the output node. The signal SMP2 is output, and the digital data corresponding to the second comparison result signal SMP2 is stored in the memory 232 of the memory unit 230.

During the above processing, the memory control unit 240 sends the second comparison result signal SCMP2 by the second comparison processing CMPR2 according to the state (output level) of the first comparison result signal SCMP1 by the first comparison processing CMPR1. Whether or not to write the corresponding data to the memory unit 230 is controlled.
Specifically, in the memory control unit 240, the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 is changed from the first level (for example, low level) to the second level in the first comparison processing period PSMPR1. When the level (high level) is changed, the writing of the data corresponding to the second comparison result signal SCMP2 by the second comparison processing CMPR2 to the memory unit 230 is prohibited.
On the other hand, in the memory control unit 240, when the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 does not change at the first level (low level) during the first comparison processing period CMPR1. , The writing of the data corresponding to the second comparison result signal SCMP2 by the second comparison process CMPR2 to the memory unit 230 is permitted.

The signal read to the memory unit 230 is executed by reading digital signal data from the memory node, and has such a MIMO data format, for example, through the IO buffer 41 of the output circuit 40, the solid-state imaging device 10 (image). It is sent to the outside of the sensor). This operation is performed globally for all pixel arrays.

As described above, according to the first embodiment, the solid-state image sensor 10 includes a photoelectric conversion reading unit 210, an AD conversion unit 220, and a memory unit 230 as digital pixels in the pixel unit 20, and is a global shutter. It is configured as, for example, a stacked CMOS image sensor having the operation function of.
In the solid-state imaging device 10 according to the first embodiment, each digital pixel 200 has an AD conversion function, and the AD conversion unit 220 compares the voltage signal read by the photoelectric conversion reading unit 210 with the reference voltage. It also has a comparator 221 that performs a comparison process to output a digitized comparison result signal.
Then, under the control of the readout unit 60, the comparator 221 digitizes the first comparison result signal for the voltage signal corresponding to the overflow charge overflowing from the photodiode PD1 to the output node (floating diffusion) FD1 during the storage period. The first comparison process CMPR1 that outputs SMPP1 and the second digitized comparison result for the voltage signal corresponding to the stored charge of the photodiode PD1 transferred to the floating node FD1 (output node) during the transfer period after the storage period. The second comparison process CMPR2, which outputs the signal SCMP2, is performed.

Further, the solid-state image sensor 10 has a memory control unit 240 that controls access to the memory unit according to the state (level in this embodiment) of the comparison result signal of the comparator 221.
Then, the memory control unit 240 receives data according to the second comparison result signal SCMP2 by the second comparison processing CMPR2 according to the state (output level) of the first comparison result signal SCMP1 by the first comparison processing CMPR1. Controls whether or not to write to the memory unit 230.
Specifically, in the memory control unit 240, during the first comparison processing period PSMPR1, the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 is changed from the first level (for example, low level) to the second level. When the level (high level) is changed, the writing of the data corresponding to the second comparison result signal SCMP2 by the second comparison processing CMPR2 to the memory unit 230 is prohibited.
On the other hand, when the memory control unit 240 does not change the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 during the first comparison processing period CMPR1 as the first level (low level). Second comparison processing Allows the CMPR2 to write data corresponding to the second comparison result signal SCMP2 to the memory unit 230.

Therefore, according to the solid-state image sensor 10 of the first embodiment, since the electric charge overflowing from the photodiode during the storage period is used in real time, it is possible to realize a wide dynamic range and a high frame rate. Moreover, efficient access to the memory is possible.
Further, according to the first embodiment , it is possible to realize a substantially wide dynamic range and a high frame rate, efficient access to the memory is possible, and noise can be reduced, which is effective. The pixel area can be expanded to the maximum, and the value per cost can be maximized.

Further, according to the solid-state image sensor 10 of the first embodiment, it is possible to prevent a decrease in area efficiency in layout while preventing a complicated configuration.

Further, the solid-state image sensor 10 according to the first embodiment has a laminated structure of a first substrate (upper substrate) 110 and a second substrate (lower substrate) 120.
Therefore, in the first embodiment, the cost is obtained by basically forming the first substrate 110 side only with the µ-based elements and maximizing the effective pixel area by the pixel array. You can maximize the value per hit.

(Second embodiment)
FIG. 18 is a diagram for explaining a configuration example of the memory control unit 240A according to the second embodiment of the present invention.
FIG. 19 is a timing chart for explaining the operation of the memory control unit of FIG. 18 when the output of the comparator is inverted in the time stamp ADC mode.
FIG. 20 is a timing chart for explaining the operation of the memory control unit of FIG. 18 when the output of the comparator is not inverted in the time stamp ADC mode.

The memory control unit 240A according to the second embodiment is, for example, an n-bit connected in series between a power supply potential VDD and a reference potential VSS, in this example, eight p-channel MOSs corresponding to the eighth bit (8-position bit). It is composed of a CMOS buffer BF1 composed of a ProLiant) PT0 to PT7, a polyclonal transistor PT8, and an n-channel MOS (NMOS) NT1.

The gates of the polyclonal transistors PT0 to PT7 are connected to the bit cells BC0 to BC7 of the memory 231.
The gates of the polyclonal transistor PT8 and the nanotube transistor NT1 are the control signal EVA as a sampling signal. TS ADC It is connected to the supply line of B, and a signal OUT (a signal corresponding to the signal B of the NOR circuit in FIG. 11) is output to the memory 231 from the connection node of the drain city.

In the memory control unit 240A of the second embodiment, as shown in FIG. 19, the first comparison processing period PCWhen the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 changes from the first level (for example, low level) to the second level (high level) in MPR1, the ADC code ADC CODE <N- 1> is not 0.
Therefore, each bit cell BC0 to BC7 is at a high level, and the polyclonal transistors PT0 to PT7 are held in a non-conducting state. At this time, the control signal EVATS ADC B isYesSince it is a level, the output node of the buffer BF1 becomes the reference potential VSS level, and the signal OUT is output at the first level (low level). As a result, writing of data corresponding to the second comparison result signal SCMP2 by the second comparison process CMPR2 to the memory unit 230 is prohibited.

On the other hand, in the memory control unit 240A, as shown in FIG. 20, the level of the first comparison result signal SCMP1 by the first comparison processing CMPR1 is the first level (low level) in the first comparison processing period CMPR1. If it remains unchanged, the ADC code ADC CODE <N-1> is 0.
Therefore, each bit cell BC0 to BC7 is at a low level, and the polyclonal transistors PT0 to PT7 are held in a conductive state. At this time, the control signal EVA TS ADC Since B is at a low level, the output node of the buffer BF1 has a power supply potential VDD level, and the signal OUT is output at the second level (high level). As a result, writing of data corresponding to the second comparison result signal SCMP2 by the second comparison process CMPR2 to the memory unit 230 is permitted.

According to the second embodiment, it is possible not only to obtain the same effect as the effect of the first embodiment described above, but also to speed up the reading process and reduce the power consumption.

(Third embodiment)
FIG. 21 is a diagram for explaining a solid-state image sensor according to a third embodiment of the present invention, and is a diagram showing an example of selection processing of time stamp ADC mode operation and linear ADC mode operation.

The solid-state image sensor 10B according to the third embodiment is different from the solid-state image sensor 10 according to the first embodiment described above as follows.
In the solid-state image sensor 10 according to the first embodiment, the time stamp (TS) ADC mode operation and the linear (Lin) ADC mode operation are continuously performed.

On the other hand, in the solid-state image sensor 10B according to the second embodiment, the time stamp (TS) ADC mode operation and the linear (Lin) ADC mode operation can be selectively performed according to the illuminance.

In the example of FIG. 21, when the illuminance is normal (ST1), the time stamp ADC mode operation and the linear ADC mode operation are continuously performed (ST2).
In the case of extremely (extremely) high illuminance (ST1, ST3) instead of normal illuminance, there is a high probability that the charge will overflow from the photodiode PD1 to the floating diffusion FD1, so only the time stamp ADC mode operation is performed (ST4). ,
In the case of very (extremely) low illuminance (ST1, ST3, ST5), which is neither normal illuminance nor very (extremely) high illuminance, the probability that the charge overflows from the photodiode PD1 to the floating diffusion FD1 is extremely low. Therefore, only linear ADC mode operation is performed (ST6),

According to the third embodiment, it is possible not only to obtain the same effect as the effect of the first embodiment described above, but also to speed up the reading process and reduce the power consumption.

(Fourth Embodiment)
FIG. 22 is a diagram showing a configuration example of pixels of the solid-state image sensor according to the fourth embodiment of the present invention.

The solid-state image sensor 10C according to the fourth embodiment is different from the solid-state image sensor 10 according to the first embodiment described above as follows.
In the solid-state image sensor 10C according to the fourth embodiment, the current transistor IC1-Tr as a current source is arranged not on the first substrate 110 side but on the input side of the AD conversion unit 220 on the second substrate 120 side, for example. Has been done.

According to the fourth embodiment, the same effect as that of the first embodiment described above can be obtained.

The solid-state image pickup devices 10, 10A, 10B, and 10C described above can be applied as an image pickup device to electronic devices such as digital cameras, video cameras, mobile terminals, surveillance cameras, and medical endoscope cameras. ..

FIG. 23 is a diagram showing an example of the configuration of an electronic device equipped with a camera system to which the solid-state image sensor according to the embodiment of the present invention is applied.

As shown in FIG. 23, the electronic device 300 has a CMOS image sensor 310 to which the solid-state image sensor 10 according to the present embodiment can be applied.
Further, the electronic device 300 has an optical system (lens or the like) 320 that guides incident light to the pixel region of the CMOS image sensor 310 (to form an image of a subject image).
The electronic device 300 has a signal processing circuit (PRC) 330 that processes the output signal of the CMOS image sensor 310.

The signal processing circuit 330 performs predetermined signal processing on the output signal of the CMOS image sensor 310.
The image signal processed by the signal processing circuit 330 can be displayed as a moving image on a monitor including a liquid crystal display or output to a printer, and can be directly recorded on a recording medium such as a memory card. Is possible.

As described above, by mounting the above-mentioned solid-state image sensors 10, 10A, 10B, and 10C as the CMOS image sensor 310, it is possible to provide a high-performance, compact, and low-cost camera system.
Electronic devices such as surveillance cameras and medical endoscope cameras are used in applications where there are restrictions on camera installation requirements such as mounting size, number of connectable cables, cable length, and installation height. Can be realized.

10, 10A, 10B, 10C ... Solid image pickup device, 20 ... Pixel part, PD1 ... Photodiode, TG1-Tr ... Transfer transistor, RST1-Tr ... Reset transistor, SF1-Tr ... Source follower transistor, IC1-Tr ... current transistor, FD1 ... floating diffusion, 200 ... digital pixel, 210 ... photoelectric conversion readout unit, 211 ... output buffer unit, 220 ... AD conversion unit, 221 ... comparator, 222 ... counter, 230 ... memory unit, 231 ... memory, 240, 240A ... memory control unit, 30 ... vertical scanning circuit, 40.・ ・ Output circuit, 50 ・ ・ ・ Timing control circuit, 60 ・ ・ ・ Read unit, 300 ・ ・ ・ Electronic device, 310 ・ ・ ・ CMOS image sensor, 320 ・ ・ ・ Optical system, 330 ・ ・ ・ Signal processing circuit ( PRC).

Claims (8)

The pixel part where the pixels that perform photoelectric conversion are arranged, and
It has a reading unit that reads a pixel signal from the pixel of the pixel unit.
The pixel is
A photoelectric conversion element that stores the electric charge generated by photoelectric conversion during the storage period, and
A transfer element capable of transferring the electric charge accumulated in the photoelectric conversion element during the transfer period after the accumulation period, and a transfer element.
An output node to which the electric charge accumulated in the photoelectric conversion element is transferred through the transfer element, and
An output buffer unit that converts the electric charge of the output node into a voltage signal according to the amount of electric charge and outputs the converted voltage signal.
A comparator that compares the voltage signal by the output buffer unit with the reference voltage and outputs a digitized comparison result signal, and a comparator that performs comparison processing.
A memory unit that can store data according to the comparison result signal of the comparator, and
A memory control unit that controls access to the memory unit according to the state of the comparison result signal of the comparator is included.
The comparator is under the control of the readout unit.
A first comparison process for outputting a first digitized comparison result signal for the voltage signal according to the overflow charge overflowing from the photoelectric conversion element to the output node during the accumulation period.
A second comparison process for outputting a second digitized comparison result signal for the voltage signal according to the stored charge of the photoelectric conversion element transferred to the output node during the transfer period after the storage period. Can be done,
The reading unit is
In the first comparison process, after obtaining a digitized first comparison result signal for the voltage signal corresponding to the overflow charge overflowing to the output node, the second comparison process is performed.
The memory control unit
Whether or not to write data according to the second comparison result signal by the second comparison process to the memory unit according to the state of the first comparison result signal by the first comparison process. A solid-state image sensor that controls. The memory control unit
When the level of the first comparison result signal by the first comparison process changes from the first level to the second level during the first comparison process, the second level by the second comparison process is performed. The solid-state image sensor according to claim 1, which prohibits writing of data corresponding to the comparison result signal to the memory unit. The memory control unit
When the level of the first comparison result signal by the first comparison processing does not change at the first level during the first comparison processing period, the second comparison result by the second comparison processing The solid-state image sensor according to claim 1 or 2, which allows writing of data according to a signal to the memory unit. The memory part is
Writing is prohibited when the signal corresponding to the first comparison result signal by the first comparison processing is supplied at the first level, and writing is permitted when the signal corresponding to the first comparison result signal is supplied at the second level.
The memory control unit
When the sampling signal is supplied after the end of the first comparison processing period, the level of the first comparison result signal by the first comparison processing changes from the first level to the second level. Then, a signal corresponding to the first comparison result signal is supplied to the memory unit at the first level.
When the sampling signal is supplied after the end of the first comparison processing period, if the level of the first comparison result signal by the first comparison processing does not change at the first level, the memory. The solid-state image pickup device according to claim 2 or 3, wherein a signal corresponding to the first comparison result signal is supplied to a unit at a second level. The first board and
Including the second substrate,
The first substrate and the second substrate have a laminated structure connected through a connecting portion.
On the first substrate,
At least, the photoelectric conversion element, the transfer element, the output node, and the output buffer portion of the pixel are formed.
On the second substrate,
The solid-state image sensor according to any one of claims 1 to 4, wherein at least a part of the comparator, the memory unit, the memory control unit, and the reading unit is formed. The pixel is
Floating diffusion as the output node and
Includes a reset element that resets the floating diffusion to a predetermined potential during the reset period.
The output buffer unit is
A source follower element that converts the charge of the floating diffusion into a voltage signal according to the amount of charge and outputs the converted signal.
Including a current source connected to the source of the source follower element.
The floating diffusion, the reset element, and the source follower element are formed on the first substrate.
The solid-state image sensor according to claim 5, wherein the current source is formed on the first substrate or the second substrate. The pixel part where the pixels that perform photoelectric conversion are arranged, and
It has a reading unit that reads a pixel signal from the pixel of the pixel unit.
The pixel is
A photoelectric conversion element that stores the electric charge generated by photoelectric conversion during the storage period, and
A transfer element capable of transferring the electric charge accumulated in the photoelectric conversion element during the transfer period after the accumulation period, and a transfer element.
An output node to which the electric charge accumulated in the photoelectric conversion element is transferred through the transfer element, and
An output buffer unit that converts the electric charge of the output node into a voltage signal according to the amount of electric charge and outputs the converted voltage signal.
A comparator that compares the voltage signal by the output buffer unit with the reference voltage and outputs a digitized comparison result signal, and a comparator that performs comparison processing.
A method for driving a solid-state image sensor, including a memory unit that stores data corresponding to a comparison result signal of the comparator.
When reading out the pixel signal of the pixel, in the comparator,
Under the control of the reading unit
A first comparison process is performed to output a first digitized comparison result signal for the voltage signal corresponding to the overflow charge overflowing from the photoelectric conversion element to the output node during the accumulation period.
In the first comparison process, after obtaining a digitized first comparison result signal for the voltage signal corresponding to the overflow charge overflowing to the output node,
A second comparison process for outputting a second digitized comparison result signal to the voltage signal according to the stored charge of the photoelectric conversion element transferred to the output node during the transfer period after the storage period is performed .
Whether or not to write data according to the second comparison result signal by the second comparison process to the memory unit according to the state of the first comparison result signal by the first comparison process. A method for driving a solid-state image sensor that controls access to the memory unit according to the state of the comparison result signal of the comparator. With a solid-state image sensor,
The solid-state image sensor has an optical system for forming a subject image, and the solid-state image sensor has an optical system.
The solid-state image sensor
The pixel part where the pixels that perform photoelectric conversion are arranged, and
It has a reading unit that reads a pixel signal from the pixel of the pixel unit.
The pixel is
A photoelectric conversion element that stores the electric charge generated by photoelectric conversion during the storage period, and
A transfer element capable of transferring the electric charge accumulated in the photoelectric conversion element during the transfer period after the accumulation period, and a transfer element.
An output node to which the electric charge accumulated in the photoelectric conversion element is transferred through the transfer element, and
An output buffer unit that converts the electric charge of the output node into a voltage signal according to the amount of electric charge and outputs the converted voltage signal.
A comparator that compares the voltage signal by the output buffer unit with the reference voltage and outputs a digitized comparison result signal, and a comparator that performs comparison processing.
A memory unit that can store data according to the comparison result signal of the comparator, and
A memory control unit that controls access to the memory unit according to the state of the comparison result signal of the comparator is included.
The comparator is under the control of the readout unit.
A first comparison process for outputting a first digitized comparison result signal for the voltage signal according to the overflow charge overflowing from the photoelectric conversion element to the output node during the accumulation period.
A second comparison process for outputting a second digitized comparison result signal for the voltage signal according to the stored charge of the photoelectric conversion element transferred to the output node during the transfer period after the storage period. Can be done,
The reading unit is
In the first comparison process, after obtaining a digitized first comparison result signal for the voltage signal corresponding to the overflow charge overflowing to the output node, the second comparison process is performed.
The memory control unit
Whether or not to write data according to the second comparison result signal by the second comparison process to the memory unit according to the state of the first comparison result signal by the first comparison process. An electronic device that controls.

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