JP2020136858A - Solid state image pickup device, driving method of the solid state image pickup device, and electronic apparatus - Google Patents

Abstract

To provide a solid state image pickup device capable of preventing a FD level from fluctuating even if an irregular strength light is entered into a photoelectric conversion element during a comparison processing of an AD converter, and achieving a normal AD conversion processing, a driving method of the solid state image pickup device, and an electronic apparatus.SOLUTION: A comparator 221 performs: a first comparison processing that outputs a first comparison result signal obtained by digitalizing a voltage signal in accordance with an over-flow electric charge leaked from a photodiode PD1 to a floating defusion FD1 in an accumulation period under a control of a reading part 60; and a second comparison processing that outputs a second comparison result signal obtained by digitalizing the voltage signal in accordance with an accumulation electric charge of the PD1 transferred to the FD1 in a transferring period after the accumulation period. A photoelectric conversion reading out part 210 contains an electric charge discharging part 212 which can discharge an unnecessary electric charge to an output node region from the PD1 when an irregular strength light is entered to the PD1 in the second comparison processing.SELECTED DRAWING: Figure 3

Description

The present invention relates to a solid-state image sensor, a method for driving the solid-state image sensor, and an electronic device.

A CMOS (Complementary Metal Oxide Semiconductor) image sensor is put into practical use as a solid-state image sensor (image sensor) using a photoelectric conversion element that detects light and generates an electric charge.
CMOS image sensors are widely applied as part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and mobile terminal devices (mobile devices) such as mobile phones. There is.

The CMOS image sensor has an FD amplifier having a photodiode (photoelectric conversion element) and a floating diffusion layer (FD) for each pixel, and its reading selects a certain line in the pixel array. However, the column parallel output type that reads them out in the column output direction at the same time is the mainstream.

Further, various kinds of pixel signal readout (output) circuits of the column parallel output type CMOS image sensor have been proposed.
Among them, one of the most advanced circuits is a circuit equipped with an analog-to-digital converter (ADC (Analog digital converter)) for each column and extracting a pixel signal as a digital signal (for example, Patent Documents). See 1 and 2).

In this column-parallel ADC-equipped CMOS image sensor (column AD system CMOS image sensor), the comparator (comparator) compares the so-called RAMP wave and the pixel signal, and performs AD conversion by performing digital CDS with the counter in the subsequent stage. ..

However, although this type of CMOS image sensor is capable of high-speed signal transfer, it has the disadvantage of not being able to read the global shutter.

On the other hand, an ADC (furthermore, a memory unit) including a comparator is arranged in each pixel, and a global shutter that executes exposure start and exposure end at the same timing for all pixels in the pixel array unit is provided. Digital pixel sensors have been proposed (see, for example, Patent Documents 3 and 4).

Japanese Unexamined Patent Publication No. 2005-278135 Japanese Unexamined Patent Publication No. 2005-295346 US 7164114 B2 FIG, 4 US 2010/0181464 A1

However, in the conventional digital pixel sensor described above, when irregular strong light is incident on the photodiode PD during the AD conversion comparison process, the charge overflows from the photodiode PD to the floating diffusion FD, which is a floating output node. The level of the diffusion FD fluctuates, and there is a possibility that normal AD conversion processing cannot be realized.

Further, although it is possible to realize the global shutter function in the CMOS image sensor equipped with the above-mentioned conventional digital pixel sensor, for example, since the charge overflowing from the photodiode during the storage period is not used in real time, it is possible to realize the global shutter function. There is a limit to wide dynamic range and high frame rate.

Random noise is an important performance index of CMOS image sensors, and it is known that pixels and AD converters are the main sources of random noise.
Generally, as a random noise reduction method, the flicker noise is reduced by increasing the transistor size, or a capacitance is added to the comparator output to reduce the band to reduce the noise filtering effect by CDS. The method of aiming is known.
However, each method has a disadvantage that the inversion delay of the comparator deteriorates due to the increase in area and capacity, and the frame rate of the image sensor cannot be increased.

Further, since the ADC (furthermore, the memory unit) including the comparator is arranged in each pixel, it is difficult to maximize the effective pixel area, and it is difficult to maximize the value per cost. ..

The present invention prevents the FD level from fluctuating even if irregular strong light is incident on the photoelectric conversion element during the AD conversion comparison process, and solid-state imaging capable of realizing a normal AD conversion process. The purpose of the present invention is to provide an apparatus, a method for driving a solid-state image sensor, and an electronic device.
Further, the present invention can substantially realize a wide dynamic range and a high frame rate, can reduce noise, can maximize the effective pixel area, and is value per cost. It is an object of the present invention to provide a solid-state image sensor, a method for driving the solid-state image sensor, and an electronic device capable of maximizing the above.

The solid-state imaging device according to the first aspect of the present invention includes a pixel unit in which pixels for photoelectric conversion are arranged and a readout unit for reading a pixel signal from the pixel of the pixel unit, and the pixel has an accumulation period. A photoelectric conversion element that stores the charge generated by the photoelectric conversion, a transfer element that can transfer the charge accumulated in the photoelectric conversion element to the transfer period after the storage period, and the photoelectric conversion element that stores the charge accumulated in the photoelectric conversion element through the transfer element. An output node to which the transferred charge is transferred, an output buffer unit that converts the charge of the output node into a voltage signal according to the amount of charge and outputs the converted voltage signal, and a voltage signal and a reference voltage by the output buffer unit. The comparer includes a comparer that performs a comparison process that compares with and outputs a digitized comparison result signal, and a memory unit that stores data corresponding to the comparison result signal of the comparer. Under the control of the unit, a first comparison process for outputting a digitized first comparison result signal for the voltage signal corresponding to the overflow charge overflowing from the photoelectric conversion element to the output node during the storage period, and A second comparison process for outputting a second digitized comparison result signal with respect to the voltage signal corresponding to the accumulated charge of the photoelectric conversion element transferred to the output node during the transfer period after the storage period. This includes a charge emitting unit capable of discharging unnecessary charge from the photoelectric conversion element to the outside of the output node region when irregularly strong light is incident on the photoelectric conversion element during the second comparison process.

A second aspect of the present invention includes a pixel unit in which pixels for performing photoelectric conversion are arranged, and a reading unit for reading a pixel signal from the pixels of the pixel unit, and the pixels are photoelectrically converted during the storage period. A photoelectric conversion element that accumulates the charge generated by the above, a transfer element that can transfer the charge accumulated in the photoelectric conversion element to a transfer period after the accumulation period, and a charge accumulated in the photoelectric conversion element through the transfer element. Compare the output node to which is transferred, the output buffer unit that converts the charge of the output node into a voltage signal according to the amount of charge, and outputs the converted voltage signal, and the voltage signal and reference voltage by the output buffer unit. A method of driving a solid-state imaging device that includes a comparer that performs a comparison process that outputs a digitized comparison result signal. When the pixel signal of the pixel is read out, the comparer controls the reading unit. Under the above, a first comparison process for outputting a digitized first comparison result signal with respect to the voltage signal corresponding to the overflow charge overflowing from the photoelectric conversion element to the output node during the storage period is performed, and the storage is performed. During the transfer period after the period, a second comparison process for outputting a digitized second comparison result signal with respect to the voltage signal corresponding to the accumulated charge of the photoelectric conversion element transferred to the output node is performed, and the first comparison process is performed. When irregular strong light is incident on the photoelectric conversion element during the comparison process of No. 2, unnecessary charge is emitted from the photoelectric conversion element to the outside of the output node region.

The electronic device according to the third aspect of the present invention includes a solid-state imaging device and an optical system for forming a subject image on the solid-state imaging device, and the solid-state imaging device is provided with pixels for photoelectric conversion. A photoelectric conversion element that stores a charge generated by photoelectric conversion during the storage period and a photoelectric conversion element that stores the charge generated by the photoelectric conversion are included in the pixel unit and a read unit that reads a pixel signal from the pixel of the pixel unit. A transfer element capable of transferring the charged charge during the transfer period after the accumulation period, an output node to which the charge accumulated by the photoelectric conversion element is transferred through the transfer element, and a charge of the output node according to the amount of charge. An output buffer unit that converts to a voltage signal and outputs the converted voltage signal, and a comparer that compares the voltage signal by the output buffer unit with the reference voltage and outputs a digitized comparison result signal. , The comparer, under the control of the readout unit, digitizes the first comparison result for the voltage signal according to the overflow charge overflowing from the photoelectric conversion element to the output node during the storage period. A first comparison process for outputting a signal and a second digitized comparison result signal for the voltage signal according to the accumulated charge of the photoelectric conversion element transferred to the output node during the transfer period after the accumulation period. When an irregular strong light is incident on the photoelectric conversion element during the second comparison processing, an unnecessary charge is removed from the photoelectric conversion element outside the output node region. Includes a charge release unit that can be released into.

According to the present invention, it is possible to prevent the FD level from fluctuating even if irregular strong light is incident on the photoelectric conversion element during the AD conversion comparison process, and to realize a normal AD conversion process. Become.
Further, according to the present invention, it is possible to substantially realize a wide dynamic range and a high frame rate, reduce noise, maximize the effective pixel area, and per cost. It is possible to maximize the value of.

It is a block diagram which shows the structural example of the solid-state image sensor which concerns on 1st Embodiment of this invention. It is a figure which shows an example of the digital pixel array of the pixel part of the solid-state image sensor which concerns on 1st Embodiment of this invention. It is a circuit diagram which shows an example of the pixel of the solid-state image sensor which concerns on 1st Embodiment of this invention. A simplified cross-sectional view showing a configuration example of a charge storage transfer system having a charge emission section which is a main part of a digital pixel according to the first embodiment of the present invention, and a configuration of a charge storage transfer system of a comparative example having no charge release section. It is a simplified sectional view which shows an example. It is a simplified top view of the configuration example of the charge storage transfer system including the storage capacitor which is the main part of the digital pixel which concerns on 1st Embodiment of this invention. It is a figure for demonstrating the management state of the potential of the transfer transistor and the shutter gate transistor in the photoelectric conversion reading part of this 1st Embodiment. It is a figure for demonstrating the 1st comparison process of the comparator which concerns on this embodiment. It is a figure for demonstrating the 1st comparison process of the comparator which concerns on this Embodiment, and is the figure for demonstrating another pattern example of a reference voltage. It is a figure which shows the state of the optical time conversion when various reference voltages are input to the comparator which concerns on this embodiment. It is a figure which shows the optical response coverage in the digital pixel which concerns on 1st Embodiment of this invention. It is a figure which shows the normal operation of the 2nd comparison process at the time of not having a shutter gate transistor which is a charge emitting part, and the operation state at the time of the incident of irregular strong light. It is a figure which shows the operation state when the irregular strong light of the 2nd comparison process is incident with the case which does not have a shutter gate transistor which is a charge emitting part, and has. It is a figure which shows the structural example of the memory part and the output circuit which concerns on 1st Embodiment of this invention. It is a figure which shows an example of the frame reading sequence in the solid-state image sensor which concerns on 1st Embodiment of this invention. It is a schematic diagram for demonstrating the laminated structure of the solid-state image pickup apparatus which concerns on this 1st Embodiment. It is a simplified sectional view for demonstrating the laminated structure of the solid-state image pickup apparatus which concerns on this 1st Embodiment. It is a timing chart for demonstrating the reading operation mainly in the pixel part in the predetermined shutter mode of the solid-state image sensor which concerns on this 1st Embodiment. It is a figure which shows the operation sequence and the potential transition for demonstrating the reading operation mainly in the pixel part in the predetermined shutter mode of the solid-state image pickup apparatus which concerns on this 1st Embodiment. It is a figure for demonstrating the solid-state image sensor which concerns on 2nd Embodiment of this invention, and is the figure which shows an example of the selection process of time stamp ADC mode operation and linear ADC mode operation. It is a figure which shows an example of the frame reading sequence in the solid-state image sensor which concerns on 3rd Embodiment of this invention. It is a figure which shows the state of the optical time conversion when the reference voltage is input to the comparator which concerns on this 3rd Embodiment. It is a figure which shows the relationship between the digital code and the charge amount by light conversion in this 3rd Embodiment. It is a circuit diagram which shows an example of the pixel of the solid-state image sensor which concerns on 4th Embodiment of this invention. It is a figure which shows an example of the structure of the electronic device to which the solid-state image sensor which concerns on embodiment of this invention are applied.

Hereinafter, embodiments of the present invention will be described in association with the drawings.

(First Embodiment)
FIG. 1 is a block diagram showing a configuration example of a solid-state image sensor according to the first embodiment of the present invention.
In the present embodiment, the solid-state image sensor 10 is composed of, for example, a CMOS image sensor including digital pixels (Digital Pixel) as pixels.

As shown in FIG. 1, the solid-state image sensor 10 has a pixel unit 20 as an image pickup unit, a vertical scanning circuit (row scanning circuit) 30, an output circuit 40, and a timing control circuit 50 as main components. ..
Among these components, for example, the vertical scanning circuit 30, the output circuit 40, and the timing control circuit 50 constitute a pixel signal reading unit 60.

In the first embodiment, the solid-state image sensor 10 includes a photoelectric conversion reading unit, an AD (analog-digital) conversion unit, and a memory unit as digital pixels in the pixel unit 20, and has a global shutter operation function, for example. It is configured as a stacked CMOS image sensor.
In the solid-state imaging device 10 according to the first embodiment, as will be described in detail later, each digital pixel DP has an AD conversion function, and the AD conversion unit is a voltage signal read by a photoelectric conversion reading unit. It has a comparator (comparator) that performs comparison processing that compares the voltage with the reference voltage and outputs a digitized comparison result signal.
Under the control of the reading unit 60, the comparator outputs a digitized first comparison result signal for the voltage signal corresponding to the overflow charge overflowing from the photoelectric conversion element to the output node (floating diffusion) during the storage period. The comparison process of 1 and the second comparison process of outputting a digitized second comparison result signal with respect to the voltage signal corresponding to the accumulated charge of the photoelectric conversion element transferred to the output node in the transfer period after the accumulation period. I do.

Then, in the present embodiment, even if irregular strong light is incident on the photoelectric conversion element during the second comparison process, unnecessary charges are emitted from the photoelectric conversion element to the outside of the floating diffusion FD region, and the photoelectric conversion element is used. It has a shutter gate (SG) that prevents the charge from overflowing into the floating diffusion FD and fluctuating the FD level.
As a result, even if irregularly strong light is incident on the photoelectric conversion element during the second comparison processing, the FD level is prevented from fluctuating, and a normal AD conversion processing can be realized.

Hereinafter, the outline of the configuration and function of each part of the solid-state image sensor 10, particularly the configuration and function of the pixel unit 20 and the digital pixel, the readout processing related thereto, the laminated structure of the pixel portion 20 and the readout unit 60, and the like will be described in detail. Describe.

(Structure of pixel unit 20 and digital pixel 200)
FIG. 2 is a diagram showing an example of a digital pixel array of the pixel portion of the solid-state image sensor 10 according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram showing an example of pixels of the solid-state image sensor 10 according to the first embodiment of the present invention.

As shown in FIG. 2, the pixel unit 20 has a plurality of digital pixels 200 arranged in a matrix of N rows and M columns.
Note that FIG. 2 shows an example in which nine digital pixels 200 are arranged in a matrix of 3 rows and 3 columns (matrix of M = 3 and N = 3) for simplification of the drawing. ..

The digital pixel 200 according to the first embodiment has a photoelectric conversion reading unit (denoted as PD in FIG. 2) 210, an AD conversion unit (denoted as ADC in FIG. 2) 220, and a memory unit (denoted as MEM in FIG. 2). ) 230 is included.
As will be described in detail later, the pixel portion 20 of the first embodiment is configured as a laminated CMOS image sensor of the first substrate 110 and the second substrate 120, but in this example, FIG. As shown in the above, a photoelectric conversion reading unit 210 is formed on the first substrate 110, and an AD conversion unit 220 and a memory unit 230 are formed on the second substrate 120.

The photoelectric conversion reading unit 210 of the digital pixel 200 includes a photodiode (photoelectric conversion element) and an in-pixel amplifier.
Specifically, the photoelectric conversion reading unit 210 includes, for example, a photodiode PD1 which is a photoelectric conversion element.
For this photodiode PD1, a transfer transistor TG1-Tr as a transfer element, a reset transistor RST1-Tr as a reset element, a source follower transistor SF1-Tr as a source follower element, and a current transistor IC1-Tr as a current source element , A shutter gate transistor SG1-Tr as a shutter gate element, a floating diffusion FD1 as an output node ND1, and a read node ND2, respectively.
As described above, the photoelectric conversion reading unit 210 of the digital pixel 200 according to the first embodiment includes the transfer transistor TG1-Tr, the reset transistor RST1-Tr, the source follower transistor SF1-Tr, the current transistor IC1-Tr, and the shutter gate. It is configured to include 5 transistors (5Tr) of transistors SG1-Tr.

Then, in the first embodiment, the output buffer unit 211 includes the source follower transistor SF1-Tr, the current transistor IC1-Tr, and the read node ND2.

In the photoelectric conversion reading unit 210 according to the first embodiment, the reading node ND2 of the output buffer unit 211 is connected to the input unit of the AD conversion unit 220.
The photoelectric conversion reading unit 210 converts the electric charge of the floating diffusion FD1 as an output node into a voltage signal according to the amount of electric charge, and outputs the converted voltage signal VSL to the AD conversion unit 220.

More specifically, in the first comparison processing period PCMP1 of the AD conversion unit 220, the photoelectric conversion reading unit 210 overflows from the photodiode PD1 which is a photoelectric conversion element to the floating diffusion FD1 as an output node during the storage period PI. The voltage signal VSL corresponding to the overflow charge is output.

Further, the photoelectric conversion reading unit 210 uses the product charge of the photodiode PD1 transferred to the floating diffusion FD1 as an output node during the transfer period PT after the storage period PI in the second comparison processing period PCMP2 of the AD conversion unit 220. The corresponding voltage signal VSL is output.
The photoelectric conversion reading unit 210 outputs a reading reset signal (signal voltage) (VRST) and a reading signal (signal voltage) (VSIG) as pixel signals to the AD conversion unit 220 in the second comparison processing period PCMP2.

The photodiode PD1 generates and accumulates a signal charge (here, an electron) in an amount corresponding to the amount of incident light.
Hereinafter, the case where the signal charge is an electron and each transistor is an n-type transistor will be described, but the signal charge may be a hole or each transistor may be a p-type transistor.
The present embodiment is also effective when each transistor is shared between a plurality of photodiodes and transfer transistors.

In each digital pixel 200, an embedded photodiode (PPD) is used as the photodiode (PD).
Since surface levels due to defects such as dangling bonds exist on the surface of the substrate on which the photodiode (PD) is formed, a large amount of electric charge (dark current) is generated by the thermal energy, and the correct signal cannot be read.
In the embedded photodiode (PPD), by embedding the charge storage portion of the photodiode (PD) in the substrate, it is possible to reduce the mixing of dark current into the signal.

The transfer transistor TG1-Tr of the photoelectric conversion reading unit 210 is connected between the photodiode PD1 and the floating diffusion FD1 and is controlled by the control signal TG applied to the gate through the control line.
In the transfer transistor TG1-Tr, the control signal TG is selected for the high (H) level transfer period PT and becomes conductive, and the electric charge (electrons) converted by photoelectric conversion by the photodiode PD1 and accumulated is transferred to the floating diffusion FD1.
After the photodiode PD1 and the floating diffusion FD1 are reset to a predetermined reset potential, the control signal TG of the transfer transistor TG1-Tr becomes a low (L) level non-conducting state, and the photodiode PD1 has a storage period PI. However, at this time, if the intensity (amount) of the incident light is very high, the charge exceeding the saturated charge amount overflows into the floating diffusion FD1 as an overflow charge through the overflow path under the transfer transistor TG1-Tr.

The reset transistor RST1-Tr is connected between the power supply line Vdd of the power supply voltage (sometimes referred to as the power supply potential) VDD and the floating diffusion FD1, and is controlled by the control signal RST applied to the gate through the control line.
In the reset transistor RST1-Tr, the control signal RST is selected during the H level reset period and becomes conductive, and the floating diffusion FD1 is reset to the potential of the power supply line Vdd of the power supply voltage VDD.

In the source follower transistor SF1-Tr as the source follower element, the source is connected to the read node ND2, the drain side is connected to the power supply line Vdd, and the gate is connected to the floating diffusion FD1.
The drain and source of the current transistor IC1-Tr as a current source element are connected between the read node ND2 and the reference potential VSS (for example, GND). The gate of the current transistor IC1-Tr is connected to the supply line of the control signal VBNPIX.
Then, the signal line LSGN1 between the read node ND2 and the input unit of the AD conversion unit 220 is driven by the current transistor IC1-Tr as a current source element.

The shutter gate transistor SG1-Tr as a shutter gate element uses an unnecessary charge from the photodiode PD1 as an output node when irregular strong light is incident on the photodiode PD1 during the second comparison process PCMP2 of AD conversion. It is shown as a form of a charge emitting unit 212 capable of discharging outside the floating diffusion FD1 region of the above.

The shutter gate transistor SG1-Tr has a source and a drain connected to a charge storage portion of the photodiode PD1 and a predetermined fixed potential VAAPIX, and is controlled by a control signal SG applied to the gate through a control line.
The shutter gate transistor SG1-Tr is in a conductive state when the control signal SG is selected during the H level period, and forms an emitter flow as an anti-blooming path between the charge storage portion of the photodiode PD1 and the predetermined fixed potential VAAPIXA. Unwanted charge is released to the fixed potential VAAPIX.

FIG. 4 is a simplified cross-sectional view showing a configuration example of a charge storage transfer system having a charge emission part which is a main part of a digital pixel according to the first embodiment of the present invention, and a charge storage of a comparative example having no charge emission part. It is a simplified sectional view which shows the structural example of the transfer system.
FIG. 4 (A) is a simplified cross-sectional view showing a configuration example of a charge storage transfer system having a charge emission portion which is a main portion of the digital pixel according to the present embodiment, and FIG. 4 (B) does not have a charge emission portion. It is a simplified cross-sectional view which shows the structural example of the charge accumulation transfer system of the comparative example.
FIG. 5 is a simplified top view of a configuration example of a charge storage transfer system including a storage capacitor, which is a main part of a digital pixel according to the first embodiment of the present invention.

Each digital pixel cell PXLC has a substrate (this) having a first substrate surface 1101 side (for example, the back surface side) irradiated with light L and a second substrate surface 1102 side facing the first substrate surface 1101 side. In the example, it is formed on the first substrate 110) and separated by the separation layer SPL.
The digital pixel cell PLXC according to the present embodiment of FIG. 4A has a photodiode PD1 forming a photoelectric conversion reading unit 210, a transfer transistor TG1-Tr, a floating diffusion FD1, a shutter gate transistor SG1-Tr, and a separation layer. It is configured to include an SPL, a color filter unit (not shown), and a microlens.

Although the digital pixel in FIG. 4 shows a back-illuminated type as an example, the present invention may be a front-illuminated type.

(Photodiode configuration)
The photodiode PD1 is an epitaxial of a second conductive type (p type in this embodiment) of a semiconductor substrate having a first substrate surface 1101 side and a second substrate surface 1102 side facing the first substrate surface 1101 side. A first conductive type (n type in this embodiment) semiconductor layer (n layer in this embodiment) 2102 formed so as to be embedded in a layer (p-epi) 2101 is included, and a photoelectric conversion function of received light and a photoelectric conversion function It is formed so as to have a charge storage function.
On the side portion of the photodiode PD1 in the direction orthogonal to the normal of the substrate (X direction), on both sides in the drawing, a second conductive type (this embodiment) is provided via an epitaxial layer (p-epi) 2101R and 2101L. In the form, a p-type) separation layer SPL is formed.

As described above, in the present embodiment, the embedded photodiode (PPD) is used as the photodiode (PD) in each digital pixel cell PXLC.
Since surface levels due to defects such as dangling bonds exist on the surface of the substrate on which the photodiode (PD) is formed, a large amount of electric charge (dark current) is generated by the thermal energy, and the correct signal cannot be read.
In the embedded photodiode (PPD), by embedding the charge storage portion of the photodiode (PD) in the substrate, it is possible to reduce the mixing of dark current into the signal.

In the photodiode PD1 of FIG. 4, the p + layer 2103 is formed on the second substrate surface 1102 side of the n layer (first conductive semiconductor layer) 2102.
A color filter portion is formed on the light incident side of the epitaxial layer (p-epi) 2101, and further corresponds to a part of the photodiode PD1 and the separation layer SPL on the light incident side of the color filter portion. The microlens is formed so as to do so.

(Structure of separation layer in X direction (column direction))
An n + layer 2105 serving as a floating diffusion FD1 is formed on the second substrate surface 1102 side of the p-type separation layer 2104 (SPL1) on the right side in the X direction (column direction) of FIG. 4, and is formed on the left side in the X direction (column direction) of FIG. On the second substrate surface 1102 side of the p-type separation layer 2106 (SPL2) in the above, an n + layer 2107 that serves as a drain of the shutter gate transients TSG1-Tr is formed.
Then, the gate electrode 2108 of the transfer transistor TG1-Tr is formed on the epitaxial layer (p-epi) 2101R on the second substrate surface 1102 side via the gate insulating film.
An overflow path OVP from the photodiode PD1 to the floating diffusion FD1 is formed under the transfer transistor TG1-Tr.
On the other hand, the gate electrode 2109 of the shutter gate transistor SG1-Tr is formed on the epitaxial layer (p-epi) 2101L on the second substrate surface 1102 side via the gate insulating film.
An emitter flow path EFP from the photodiode PD1 to the + layer 2107 is formed under the shutter gate transistor SG1-Tr.

In such a structure, when the intensity (amount) of the incident light is very high, the charge exceeding the saturated charge amount overflows to the floating diffusion FD1 as an overflow charge through the overflow path OVP under the transfer transistor TG1-Tr.
The overflow charge is used in the first comparison process CMPR1 of the comparator 221.

On the other hand, when irregular strong light is incident on the photodiode PD1 during the second comparison process of the AD conversion, the electric charge overflows from the photodiode PD to the floating diffusion FD1 of the floating diffusion FD which is the output node. The level may fluctuate and normal AD conversion processing may not be realized.
Therefore, in the present embodiment, even if irregular strong light is incident on the photodiode PD1 during the second comparison process, unnecessary charges are emitted from the photodiode PD1 to the outside of the floating diffusion FD region, and the photodiode PD1 It has a shutter gate transistor SG1-Tr that prevents the charge from overflowing to the floating diffusion FD1 and fluctuating the FD level.
As a result, even if irregular strong light is incident on the photodiode PD1 during the second comparison process, the FD level is prevented from fluctuating, and a normal AD conversion process can be realized.

In the present embodiment, under the control of the reading unit 60, the potentials of the transfer transistor TG1-Tr and the shutter gate transistor SG1-Tr are set to the following based on the situation of the first comparison processing CMPR1 and the second comparison processing CMPR2. It is managed like this.

6 (A) to 6 (C) are diagrams for explaining a management state of the potentials of the transfer transistor TG1-Tr and the shutter gate transistor SG1-Tr in the photoelectric conversion reading unit of the first embodiment.
FIG. 6 (A) shows the potential state when the overflow charge is used, FIG. 6 (B) shows the potential state when the charge is released by the shutter gate transistor SG1-Tr, and FIG. 6 (C) shows the transfer transistor. The state of the potential when the accumulated charge is transferred by TG1-Tr is shown.

When the overflow charge is used, both the transfer transistor TG1-Tr and the shutter gate transistor SG1-Tr are held at the potential where the gate potential becomes non-conducting (off).
At this time, in order to guarantee the first comparison process, the off potential of the shutter gate transistor SG1-Tr is set lower than the off potential of the transfer transistor TG1-Tr.

When the charge is released by the shutter gate transistor SG1-Tr, the gate potential is held at the potential where the shutter gate transistor SG1-Tr is in a conductive state (on) and the transfer transistor TG1-Tr is in a non-conducting state (off).

When the accumulated charge is transferred by the transfer transistor TG1-Tr, the gate potential is held at the potential where the transfer transistor TG1-Tr is in a conductive state (on) and the shutter gate transistor SG1-Tr is in a non-conducting state (off).

In the present embodiment, under the control of the reading unit 60, in the second comparison process CMPR2, the transfer transistor TG1-Tr is held in a conductive state and the shutter gate transistor SG1-Tr is held in a non-conducting state during the transfer period. The shutter gate transistor SG1-Tr is held in the conductive state for a predetermined period after the transfer period in which the transfer transistor TG1-Tr is switched to the non-conducting state at the end of the transfer period.

The AD conversion unit 220 of the digital pixel 200 compares the analog voltage signal VSL output by the photoelectric conversion reading unit 210 with a lamp waveform or a fixed voltage reference voltage VREF changed with a predetermined inclination. Functions to convert to a digital signal.

As shown in FIG. 3, the AD conversion unit 220 includes a comparator (COMP) 221 and a counter (CNT) 222, an input side coupling capacitor C221, an output side load capacitor C222, and a reset switch SW-RST. ing.

In the comparator 221, the voltage signal VSL output from the output buffer unit 211 of the photoelectric conversion reading unit 210 to the signal line LSGN1 is supplied to the inverting input terminal (-) as the first input terminal, and the second input terminal. The reference voltage VREF is supplied to the non-inverting input terminal (+), and the voltage signal VST and the reference voltage VREF are compared, and a comparison process is performed to output a digitized comparison result signal SCMP.

In the comparator 221, the coupling capacitor C221 is connected to the inverting input terminal (-) as the first input terminal, and the output buffer unit 211 and the second substrate of the photoelectric conversion reading unit 210 on the first substrate 110 side. By AC-coupling the input unit of the comparator 221 of the AD conversion unit 220 on the 120 side, noise reduction is achieved and a high SNR can be realized at low illuminance.

Further, in the comparator 221, a reset switch SW-RST is connected between the output terminal and the inverting input terminal (-) as the first input terminal, and a load capacitor C222 is provided between the output terminal and the reference potential VSS. It is connected.

Basically, in the AD conversion unit 220, the analog signal (potential VSL) read from the output buffer unit 211 of the photoelectric conversion reading unit 210 to the signal line LSGN1 has a reference voltage VREF, for example, a certain slope in the comparator 221. It is compared with the ramp signal RAMP, which is a linearly changing slope waveform.
At this time, the counter 222 arranged for each row is operating as in the comparator 221, and the voltage signal VSL is digitally changed by changing the lamp signal RAMP with the lamp waveform and the counter value while maintaining a one-to-one correspondence. Convert to a signal.
Basically, the AD conversion unit 220 converts a change in the reference voltage VREF (for example, a lamp signal RAMP) into a change in voltage into a change in time, and counts the time in a certain period (clock) to obtain a digital value. Convert to.
Then, when the analog signal VSL and the lamp signal RAMP (reference voltage VREF) intersect, the output of the comparator 221 is inverted and the input clock of the counter 222 is stopped, or the clock at which the input is stopped is changed to the counter 222. The input is input, and the value (data) of the counter 222 at that time is stored in the memory unit 230 to complete the AD conversion.
After the end of the above AD conversion period, the data (signal) stored in the memory unit 230 of each digital pixel 200 is output from the output circuit 40 to a signal processing circuit (not shown), and a two-dimensional image is generated by a predetermined signal processing. ..

(First comparison process and second comparison process in the comparator 221)
Then, the comparator 221 of the AD conversion unit 220 of the first embodiment is driven by the reading unit 60 so as to perform the following two first comparison processing and the second comparison processing during the pixel signal reading period. Be controlled.

In the first comparison process CMPR1, the comparator 221 responds to the overflow charge overflowing from the photodiode PD1 which is a photoelectric conversion element to the floating fusion FD1 which is an output node during the accumulation period PI under the control of the readout unit 60. The first digitized comparison result signal SCMP1 with respect to the voltage signal VSL1 is output.
The operation of the first comparison process CMPR1 is also referred to as the operation of the time stamp ADC mode.

In the second comparison process CMPR2, the comparator 221 responds to the accumulated charge of the photodiode PD1 transferred to the floating fusion FD1 which is the output node during the transfer period PT after the accumulation period PI under the control of the readout unit 60. A second digitized comparison result signal SCMP2 with respect to the voltage signal VSL2 (VSIG) is output.
Actually, in the second comparison processing CMPR2, before digitizing the voltage signal VSL2 (VSIG) according to the accumulated charge, digitalizing the voltage signal VSL2 (VRST) corresponding to the reset voltage of the floating diffusion FD1 at the time of reset. To reset.
The operation of the second comparison process CMPR2 is also referred to as an operation in the linear ADC mode.

In the present embodiment, basically, in the storage period PI, after the photodiode PD1 and the floating diffusion FD1 are reset to the reset level, the transfer transistor TG1-Tr is switched to the conductive state and the transfer period PT is started. It is the period until the end.
The period PCMPR1 of the first comparison process CMPR1 is the period from when the photodiode PD1 and the floating diffusion FD1 are reset to the reset level until the floating diffusion FD1 is reset to the reset level before the transfer period PT is started. Is.
The period PCMPR2 of the second comparison process CMPR2 is a period after the floating diffusion FD1 is reset to the reset level, and is a period including a period after the transfer period PT.

Here, the first comparison process CMPR1 will be described in more detail.
FIG. 7 is a diagram for explaining the first comparison processing CMPR1 of the comparator 221 according to the present embodiment.
In FIG. 7, the horizontal axis represents time and the vertical axis represents the voltage level VFD of the floating diffusion FD1 which is an output node.

The voltage level VFD of the floating diffusion FD1 has the smallest amount of charge at the reset level, and the voltage level VFD has the highest level VFDini.
On the other hand, in the saturated state, the amount of charge is large, and the voltage level VFD becomes a low level VFD sat.
According to such a condition, the reference voltage VREF1 of the comparator 221 is set to the voltage VREFsat fixed to the level in the unsaturated state before the saturation state, or the voltage level VREFrst at the reset level is changed to the voltage level VREFsat. Set the lamp voltage to VREFlamp.

When such a reference voltage VREF1 is set to VREFat or VREFramp in the first comparison process CMPR1, as shown in FIG. 7, the higher the intensity of the incident light and the higher the illuminance, the larger the charge amount, so that the comparison is made. The time for the output of the device 221 to flip (invert) is fast.
Example of the highest illuminance In the case of EXP1, the output of the comparator 221 immediately flips at time t1.
In the case of Example EXP2 having an illuminance lower than that of Example EXP1, the output of the comparator 221 flips (inverts) to time t2 later than time t1.
In the case of Example EXP3 having an illuminance lower than that of Example EXP2, the output of the comparator 221 flips (inverts) to time t3 later than time t2.

As described above, in the first comparison processing CMPR1, the comparator 221 has a first comparison result signal corresponding to a time corresponding to the amount of overflow charge from the photodiode PD1 to the floating diffusion FD1 during a predetermined period of the accumulation period PI. Output SCMP1.

More specifically, the comparator 221 corresponds to a predetermined threshold value of the photodiode PD1 at the maximum sampling time at which the overflow charge starts to overflow from the photodiode PD1 to the floating diffusion FD1 which is an output node in the first comparison processing CMPR1. It is possible to perform comparison processing with the optical level from the signal level to the signal level obtained in the minimum sampling time.

As described above, the photo conversion operation in the time stamp ADC mode is performed with the light to time conversion in the storage period PI.
As shown in FIG. 7, under very bright light, the output state of the comparator 221 is inverted immediately after the reset activation period, and the light level is the saturation signal (well capacitance) described in the following time. Corresponds to.

((FD saturation amount x accumulation time) / sampling period) + PD saturation amount For example, FD saturation: 8Ke @ 150uV / e to FD capacity 1.1fF, minimum sampling time: 15nsec, accumulation time: 3msec:
Is assumed to be.

In this time stamp ADC operation mode, as described above, the minimum sampling time from the signal level corresponding to the predetermined threshold value of the photodiode PD1 at the maximum sampling time at which the overflow charge starts to overflow from the photodiode PD1 to the floating diffusion FD1 which is the output node. It is possible to cover the light level up to the signal level obtained in.

FIG. 8 is a diagram for explaining the first comparison processing CMPR1 of the comparator 221 according to the present embodiment, and is a diagram for explaining another pattern example of the reference voltage.

The reference voltage VREF may be a lamp waveform (signal) RAMP changed with a predetermined inclination shown in FIG. 8 or a fixed voltage DC shown in FIG. 8 (2). , There may be a log (log) shown in (3) in FIG. 8 or a voltage signal having an exponential value shown in (4) in FIG.

FIG. 9 is a diagram showing a state of optical time conversion when various reference voltages VREF are input to the comparator according to the present embodiment.
In FIG. 9, the horizontal axis shows the sampling time, and the vertical axis shows the estimated signal in the overflow signal.

FIG. 9 shows the sampling time in which the comparator 221 corresponds to the overflow charge (signal) due to the nature (suitability) of the applied light.
FIG. 9 shows sampling times that are inverted with respect to various fixed reference voltages DC1, DC2, DC3 and the lamp reference voltage VRAMP. Here, a linear reference lamp is used.

When the operation of the time stamp ADC mode for performing the first comparison processing CMPR1 for the saturated overflow charge is completed, the floating diffusion FD1 and the comparator 221 are reset, and then the second comparison processing CMPR2 for the unsaturated charge is performed. The operation shifts to the ADC mode.

FIG. 10 is a diagram showing optical response coverage in a digital pixel according to the first embodiment of the present invention.
In FIG. 10, A indicates a signal due to time stamp ADC mode operation, and B indicates a signal due to linear ADC mode operation.

Since the time stamp ADC mode can have an optical response to very bright light, the linear ADC mode can have an optical response from a dark level. For example, a dynamic range performance of 120 dB can be realized.
For example, as described above, the saturation signal in the optical conversion range is 900 Ke.
Since the linear ADC mode operates in the normal read mode to which the ADC is applied, it can cover from the noise level of 2e to the saturation of the photodiode PD1 of 8Ke and the floating diffusion FD1.
Coverage in linear ADC mode can be extended to 30 Ke with additional switches and capacities.

(Correspondence when irregular strong light is incident during the second comparison process)
Next, regarding the response to the case where irregularly strong light is incident on the photodiode PD1 during the second comparison process CMPR2, the case where the shutter gate transistor SG1-Tr, which is the charge emitting unit 212, is not provided and the case where the shutter gate transistor SG1-Tr is provided is compared To do.

11 (A) and 11 (B) show the normal operation of the second comparison process when the shutter gate transistor SG1-Tr, which is the charge emitting unit, is not provided, and the operating state when irregular strong light is incident. It is a figure.
12 (A) and 12 (B) show the operating state when the shutter gate transistor SG1-Tr, which is the charge emitting portion, is not provided and when irregular strong light of the second comparison process is incident. It is a figure.

When irregular strong light is incident on the photodiode PD1 during the second comparison process of the AD conversion, FIGS. 11 (B) and 12 (A) when the shutter gate transistor SG1-Tr, which is a charge emitting portion, is not provided. ), The charge overflows from the photodiode PD1 to the floating diffusion FD1 and the level of the floating diffusion FD, which is an output node, fluctuates, and there is a possibility that normal AD conversion processing cannot be realized.

On the other hand, in the present embodiment, even if irregular strong light is incident on the photodiode PD1 during the second comparison process CMPR2, unnecessary charges are emitted from the photodiode PD1 to the outside of the floating diffusion FD1 region. It has a shutter gate transistor SG1-Tr that prevents the charge from overflowing from the photodiode PD1 to the floating diffusion FD1 and fluctuating the FD level.
As a result, as shown in FIG. 12B, it is possible to prevent the FD level from fluctuating even if irregular strong light is incident on the photodiode PD1 during the second comparison processing CMPR2, and normal AD conversion is performed. Processing is feasible.

In the present embodiment, under the control of the reading unit 60, in the second comparison processing CMPR2, as shown in FIG. 12B, the transfer transistor TG1-Tr is held in a conductive state during the transfer period TR, and the shutter gate The transistor SG1-Tr is held in the non-conducting state, and the shutter gate transistor SG1-Tr is held in the non-conducting state for a predetermined period after the transfer period in which the transfer transistor TG1-Tr is switched to the non-conducting state at the end of the transfer period.

FIG. 13 is a diagram showing a configuration example of a memory unit and an output circuit according to the first embodiment of the present invention.

In the comparator 221, the first comparison result signal SCMP1 in which the voltage signal corresponding to the overflow charge of the floating diffusion FD1 is digitized by the first comparison processing CMPR1 and the photodiode PD1 are accumulated by the second comparison processing CMPR2. The second comparison result signal SCMP2 in which the charge is digitized is associated and stored as digital data in the memories 231,232.
The memory unit 230 is composed of SRAM and DRAM, is supplied with a digitally converted signal, corresponds to a photo conversion code, and can be read out by an external IO buffer 41 of an output circuit 40 around a pixel array.

FIG. 14 is a diagram showing an example of a frame readout sequence in the solid-state image sensor 10 according to the first embodiment of the present invention.
Here, an example of the frame readout method in the solid-state image sensor 10 will be described.
In FIG. 14, TS indicates the processing period of the time stamp ADC, and Lin indicates the processing period of the linear ADC.

As mentioned above, the overflow charge is accumulated in the floating diffusion FD1 during the accumulation period PI. The time stamp ADC mode operates during the accumulation time PI.
In practice, the time stamp ADC mode operates during the accumulation period PI until the floating diffusion FD1 is reset.
When the operation of the time stamp ADC mode is completed, the mode shifts to the linear ADC mode, the signal (VRST) at the time of resetting the floating diffusion FD1 is read, and the digital signal is converted to be stored in the memory unit 230.
Further, after the end of the storage period PI, in the linear ADC mode, the signal (VSIG) corresponding to the stored charge of the photodiode PD1 is read and converted so that the digital signal is stored in the memory unit 230.
The read frame is executed by reading digital signal data from the memory node and has such a MIPI data format, eg, through the IO buffer 41 (FIG. 13) of the output circuit 40, the solid-state image sensor 10 (image). It is sent to the outside of the sensor). This operation can be performed globally for all pixel arrays.

Further, in the pixel unit 20, the photodiode PD1 is reset by using the reset transistor RST1-Tr and the transfer transistor TG1-Tr at the same time for all the pixels, so that the exposure is started in parallel for all the pixels. Further, after the predetermined exposure period (accumulation feedback PI) is completed, the output signal from the photoelectric conversion / reading unit is sampled by the AD conversion unit 220 and the memory unit 230 using the transfer transistor TG1-Tr, so that all pixels can be simultaneously displayed. The exposure is finished in parallel. As a result, a complete shutter operation is electronically realized.

The vertical scanning circuit 30 drives the photoelectric conversion reading unit 210 of the digital pixel 200 through the line scanning control line in the shutter line and the reading line according to the control of the timing control circuit 50.
The vertical scanning circuit 30 has a reference voltage VREF1 set according to the first comparison processing CMPR1 and the second comparison processing CMPR2 for the comparator 221 of each digital pixel 200 according to the control of the timing control circuit 50. , VREF2 is supplied.
Further, the vertical scanning circuit 30 outputs a row selection signal of the row address of the read row for reading the signal and the row address of the shutter row for resetting the charge accumulated in the photodiode PD according to the address signal.

As shown in FIG. 13, the output circuit 40 includes an IO buffer 41 arranged corresponding to the memory output of each digital pixel 200 of the pixel unit 20, and outputs digital data read from each digital pixel 200 to the outside. To do.

The timing control circuit 50 generates a timing signal necessary for signal processing of the pixel unit 20, the vertical scanning circuit 30, the output circuit 40, and the like.

In the first embodiment, the reading unit 60 controls reading the pixel signal from the digital pixel 200, for example, in the global shutter mode.

(Laminate structure of solid-state image sensor 10)
Next, the laminated structure of the solid-state image sensor 10 according to the first embodiment will be described.

15 (A) and 15 (B) are schematic views for explaining the laminated structure of the solid-state image sensor 10 according to the first embodiment.
FIG. 16 is a simplified cross-sectional view for explaining the laminated structure of the solid-state image sensor 10 according to the first embodiment.

The solid-state image sensor 10 according to the first embodiment has a laminated structure of a first substrate (upper substrate) 110 and a second substrate (lower substrate) 120.
The solid-state image sensor 10 is formed as, for example, an image sensor having a laminated structure cut out by dicing after being bonded at a wafer level.
In this example, it has a structure in which the first substrate 110 and the second substrate 120 are laminated.

On the first substrate 110, a photoelectric conversion reading unit 210 of each digital pixel 200 of the pixel unit 20 is formed around the central portion thereof.
A photodiode PD is formed on the first surface 111 side on which the light L of the first substrate 110 is on the incident side, and a microlens MCL and a color filter are formed on the light incident side.
A transfer transistor TG1-Tr, a reset transistor RST1-Tr, a source follower transistor SF1-Tr, a current transistor IC1-Tr, and a shutter gate transistor SG1-Tr are formed on the second surface side of the first substrate 110.

As described above, in the first embodiment, the photoelectric conversion reading unit 210 of the digital pixel 200 is basically formed in a matrix on the first substrate 110.

The AD conversion unit 220 and the memory unit 230 of each digital pixel 200 are formed in a matrix on the second substrate 120.
Further, the vertical scanning circuit 30, the output circuit 40, and the timing control circuit 50 may also be formed on the second substrate 120.

In such a laminated structure, the read node ND2 of each photoelectric conversion reading unit 210 of the first board 110 and the inverting input terminal (-) of the comparator 221 of each digital pixel 200 of the second board 120 are shown in FIG. As shown in 3, electrical connections are made using signal lines LSGN1, microbump BMP, vias (Die-to-Die Via), and the like, respectively.
Further, in the present embodiment, the read node ND2 of each photoelectric conversion read unit 210 of the first board 110 and the inverting input terminal (-) of the comparator 221 of each digital pixel 200 of the second board 120 are coupled capacitors. It is AC-coupled by C221.

(Reading operation of the solid-state image sensor 10)
The characteristic configurations and functions of each part of the solid-state image sensor 10 have been described above.
Next, the pixel signal reading operation of the digital pixel 200 of the solid-state image sensor 10 according to the first embodiment will be described in detail.

FIG. 17 is a timing chart for explaining a readout operation mainly in the pixel portion in a predetermined shutter mode of the solid-state image sensor according to the first embodiment.
18 (A) to 18 (D) are diagrams showing an operation sequence and potential transition for explaining a readout operation mainly in a pixel portion in a predetermined shutter mode of the solid-state image sensor according to the first embodiment.

First, when starting the read operation, as shown in FIGS. 17 and 18 (A), a global reset is performed to reset the photodiode PD1 and the floating diffusion FD1 of each digital pixel 200.
In the global reset, the reset transistor RST1-Tr and the transfer transistor TG1-Tr are held in a conductive state for a predetermined period at the same time for all pixels, and the photodiode PD1 and the floating diffusion FD1 are reset. Then, the reset transistor RST1-Tr and the transfer transistor TG1-Tr are switched to the non-conducting state at the same time for all the pixels, and the exposure, that is, the accumulation of electric charges is started in parallel for all the pixels.

Then, as shown in FIGS. 17 and 18 (B), the operation of the time stamp (TS) ADC mode for the overflow charge is started.
The overflow charge is accumulated in the floating diffusion FD1 during the accumulation period PI. The time stamp ADC mode operates during the accumulation time PI, specifically, during the accumulation period PI, until the floating diffusion FD1 is reset.

In the time stamp (TS) ADC mode, in the photoelectric conversion reading unit 210, the photodiode PD1 is changed to the floating diffusion FD1 as an output node in the storage period PI corresponding to the first comparison processing period PCMP1 of the AD conversion unit 220. The voltage signal VSL1 corresponding to the overflow charge is output.
Then, in the comparator 221 of the AD conversion unit 220, the first comparison processing CMPR1 is performed. In the comparator 221, under the control of the reading unit 60, the overflow charge overflowing from the photodiode PD1 to the floating fusion FD1 which is an output node during the accumulation period PI until the floating diffusion FD1 is reset. The digitized first comparison result signal SMP1 with respect to the corresponding voltage signal VSL1 is output, and the digital data corresponding to the first comparison result signal SMP1 is stored in the memory 231 of the memory unit 230.

Next, as shown in FIGS. 17 and 18 (C), the operation of the time stamp (TS) ADC mode for the overflow charge is completed, the mode is changed to the linear ADC mode, and the reset period PR2 of the floating diffusion FD1 is started.
In the reset period PR2, the reset transistor RST1-Tr is held in the conductive state for a predetermined period, and the floating diffusion FD1 is reset. The signal (VRST) at the time of resetting the floating diffusion FD1 is read out, and the digital signal is stored in the memory 232 of the memory unit 230.
Then, the reset transistor RST1-Tr is switched to the non-conducting state. In this case, the accumulation period PI is continued.

Next, as shown in FIGS. 17 and 18 (D), the accumulation period PI ends and the transfer period PT shifts.
In the transfer period PT, the transfer transistors TG1-Tr are held in a conductive state for a predetermined period, and the accumulated charge of the photodiode PD1 is transferred to the floating diffusion FD1. At this time, the shutter gate transistor SG1-Tr is held in a non-conducting state.
Then, the shutter gate transistor SG1-Tr is held in the conductive state for a predetermined period after the transfer period in which the transfer transistor TG1-Tr is switched to the non-conducting state at the end of the transfer period.

In the linear (Lin) ADC mode, the photoelectric conversion / reading unit 210 corresponds to the second comparison processing period PCMP2 of the AD conversion unit 220, and after the accumulation period PI ends, the photodiode PD1 to the floating diffusion FD1 as an output node. The voltage signal VSL2 corresponding to the accumulated charge transferred to is output.
Then, the second comparison process CMPR2 is performed in the comparator 221 of the AD conversion unit 220. In the comparator 221, under the control of the readout unit 60, after the storage period PI, the second comparison result digitized with respect to the voltage signal VSL2 according to the stored charge transferred from the photodiode PD1 to the floating fusion FD1 which is the output node. The signal SMP2 is output, and the digital data corresponding to the second comparison result signal SMP2 is stored in the memory 232 of the memory unit 230.

Even if irregular strong light is incident on the photodiode PD1 during the second comparison processing CMPR2, unnecessary charges are emitted from the photodiode PD1 through the shutter gate transistor SG1-Tr to the outside of the floating diffusion FD1 region, and the photo It is possible to prevent the charge from overflowing from the diode PD1 to the floating diffusion FD1 and fluctuating the FD level.
As a result, even if irregular strong light is incident on the photodiode PD1 during the second comparison process CMPR2, the FD level is prevented from fluctuating, and a normal AD conversion process is realized.

The signal read into the memory unit 230 is executed by reading the digital signal data from the memory node, and has such a MIMO data format, for example, through the IO buffer 41 of the output circuit 40, the solid-state image sensor 10 (image). It is sent to the outside of the sensor). This operation is performed globally for all pixel arrays.

As described above, according to the first embodiment, the solid-state image sensor 10 includes a photoelectric conversion reading unit 210, an AD conversion unit 220, and a memory unit 230 as digital pixels in the pixel unit 20, and is a global shutter. It is configured as, for example, a stacked CMOS image sensor having the operation function of.
In the solid-state imaging device 10 according to the first embodiment, each digital pixel 200 has an AD conversion function, and the AD conversion unit 220 compares the voltage signal read by the photoelectric conversion reading unit 210 with the reference voltage. It also has a comparator 221 that performs a comparison process that outputs a digitized comparison result signal.
Then, the comparator 221 digitizes the first comparison result signal with respect to the voltage signal corresponding to the overflow charge overflowing from the photodiode PD1 to the output node (floating diffusion) FD1 during the storage period under the control of the readout unit 60. The first comparison process CMPR1 that outputs SCMP1 and the second digitized comparison result for the voltage signal corresponding to the accumulated charge of the photodiode PD1 transferred to the floating node FD1 (output node) during the transfer period after the accumulation period. The second comparison process CMPR2, which outputs the signal SCMP2, is performed.
Then, in the first embodiment, even if irregular strong light is incident on the photodiode PD1 during the second comparison process, unnecessary charges are emitted from the photodiode PD1 to the outside of the floating diffusion FD region. It has a shutter gate transistor SG1-Tr that prevents the charge from overflowing from the photodiode PD1 to the floating diffusion FD and fluctuating the FD level.

Therefore, according to the solid-state image sensor 10 of the first embodiment, it is possible to prevent the FD level from fluctuating even if irregular strong light is incident on the photoelectric conversion element during the second comparison process, and it is normal. AD conversion processing can be realized.

Further, according to the solid-state image sensor 10 of the first embodiment, since the electric charge overflowing from the photodiode during the storage period is used in real time, it is possible to realize a wide dynamic range and a high frame rate. Become.
Further, according to the first embodiment, it is possible to substantially realize a wide dynamic range and a high frame rate, reduce noise, and expand the effective pixel area to the maximum. It is possible to maximize the value per cost.

Further, according to the solid-state image sensor 10 of the first embodiment, it is possible to prevent a decrease in area efficiency in layout while preventing a complicated configuration.

Further, the solid-state image sensor 10 according to the first embodiment has a laminated structure of a first substrate (upper substrate) 110 and a second substrate (lower substrate) 120.
Therefore, in the first embodiment, the cost is obtained by basically forming the first substrate 110 side only with the MOSFET-based elements and maximizing the effective pixel area by the pixel array. You can maximize the value per hit.

(Second Embodiment)
FIG. 19 is a diagram for explaining a solid-state image sensor according to a second embodiment of the present invention, and is a diagram showing an example of selection processing of time stamp ADC mode operation and linear ADC mode operation.

The solid-state image sensor 10A according to the second embodiment is different from the solid-state image sensor 10 according to the first embodiment described above as follows.
In the solid-state image sensor 10 according to the first embodiment, the time stun (TS) ADC mode operation and the linear (Lin) ADC mode operation are continuously performed.

On the other hand, in the solid-state image sensor 10A according to the second embodiment, the time stamp (TS) ADC mode operation and the linear (Lin) ADC mode operation can be selectively performed according to the illuminance.

In the example of FIG. 19, when the illuminance is normal (ST1), the time stamp ADC mode operation and the linear ADC mode operation are continuously performed (ST2).
In the case of extremely (extremely) high illuminance (ST1, ST3) instead of the normal illuminance, there is a high probability that the electric charge overflows from the photodiode PD1 to the floating diffusion FD1, so only the time stamp ADC mode operation is performed (ST4). ,
In the case of very (extremely) low illuminance (ST1, ST3, ST5), which is neither normal illuminance nor very (extremely) high illuminance, the probability that the charge overflows from the photodiode PD1 to the floating diffusion FD1 is extremely low. From, only linear ADC mode operation is performed (ST6),

According to the second embodiment, it is possible not only to obtain the same effect as the effect of the first embodiment described above, but also to speed up the reading process and reduce the power consumption.

(Third Embodiment)
FIG. 20 is a diagram showing an example of a frame readout sequence in the solid-state image sensor 10B according to the third embodiment of the present invention.
FIG. 21 is a diagram showing a state of optical time conversion when a reference voltage is input to the comparator according to the third embodiment.
In FIG. 21, the horizontal axis shows the sampling time, and the vertical axis shows the estimated signal in the overflow signal. The overflow signal here is estimated under the condition that the transfer transistor TG1-Tr is in a conductive state and the photodiode PD1 is not charged (non-overflow).
FIG. 21 shows the sampling time in which the comparator 221 corresponds to the non-overflow charge (signal) due to the nature (suitability) of the applied light.
22 (A) and 22 (B) are diagrams showing the relationship between the digital code and the amount of electric charge due to optical conversion in the third embodiment. FIG. 22 (A) shows the characteristics when a linear lamp signal is used, and FIG. 22 (B) shows the characteristics when a log signal is used.

In the third embodiment, the reading unit 60 causes the comparator 221 to perform the first comparison processing CMPR1 even when the photodiode PD1 does not overflow from the photodiode PD1 to the floating diffusion FD1 which is an output node during the storage period. Therefore, it is controlled to output the digitized first comparison result signal SCMP1 with respect to the voltage signal VSL according to the electric charge.

In the third embodiment, good conversion processing can be realized, and in some cases, a dynamic range performance of 86 dB can be realized.

(Fourth Embodiment)
FIG. 23 is a diagram showing a configuration example of pixels of the solid-state image sensor according to the fourth embodiment of the present invention.

The solid-state image sensor 10C according to the fourth embodiment is different from the solid-state image sensor 10 according to the first embodiment described above as follows.
In the solid-state image sensor 10B according to the fourth embodiment, the current transistor IC1-Tr as a current source is arranged not on the first substrate 110 side but on the input side of the AD conversion unit 220 on the second substrate 120 side, for example. Has been done.

According to the fourth embodiment, the same effect as that of the first embodiment described above can be obtained.

The solid-state imaging devices 10, 10A, 10B, and 10C described above can be applied as imaging devices to electronic devices such as digital cameras, video cameras, mobile terminals, surveillance cameras, and medical endoscope cameras. ..

FIG. 24 is a diagram showing an example of the configuration of an electronic device equipped with a camera system to which the solid-state image sensor according to the embodiment of the present invention is applied.

As shown in FIG. 24, the electronic device 300 has a CMOS image sensor 310 to which the solid-state image sensor 10 according to the present embodiment can be applied.
Further, the electronic device 300 has an optical system (lens or the like) 320 that guides incident light (imaging a subject image) to the pixel region of the CMOS image sensor 310.
The electronic device 300 includes a signal processing circuit (PRC) 330 that processes the output signal of the CMOS image sensor 310.

The signal processing circuit 330 performs predetermined signal processing on the output signal of the CMOS image sensor 310.
The image signal processed by the signal processing circuit 330 can be displayed as a moving image on a monitor including a liquid crystal display or output to a printer, and can be directly recorded on a recording medium such as a memory card. Is possible.

As described above, by mounting the above-mentioned solid-state image sensors 10, 10A, 10B, and 10C as the CMOS image sensor 310, it is possible to provide a high-performance, compact, and low-cost camera system.
Then, it is used in applications where there are restrictions such as mounting size, number of cables that can be connected, cable length, and installation height in the camera installation requirements, for example, electronic devices such as surveillance cameras and medical endoscope cameras. Can be realized.

10, 10A, 10B, 10C ... Solid-state imaging device, 20 ... Pixel part, PD1 ... Photodiode, TG1-Tr ... Transfer transistor, RST1-Tr ... Reset transistor, SF1-Tr ... Source follower transistor, IC1-Tr ... current transistor, SG1-Tr ... shutter gate transistor, FD1 ... floating diffusion, 200 ... digital pixel, 210 ... photoelectric conversion readout unit, 211. Output buffer unit, 212 ... Charge discharge unit, 220 ... AD conversion unit, 221 ... Comparator, 222 ... Counter, 230 ... Memory unit, 30 ... Vertical scanning circuit, 40 ... Output circuit, 50 ... Timing control circuit, 60 ... Read unit, 300 ... Electronic equipment, 310 ... CMOS image sensor, 320 ... Optical system, 330 ... Signal processing Circuit (PRC).

Claims (20)

The pixel part where the pixels that perform photoelectric conversion are arranged and
It has a reading unit that reads a pixel signal from the pixel of the pixel unit.
The pixel is
A photoelectric conversion element that accumulates the electric charge generated by photoelectric conversion during the storage period,
A transfer element capable of transferring the electric charge accumulated in the photoelectric conversion element during the transfer period after the accumulation period, and
An output node to which the electric charge accumulated in the photoelectric conversion element is transferred through the transfer element, and
An output buffer unit that converts the electric charge of the output node into a voltage signal according to the amount of electric charge and outputs the converted voltage signal.
A comparator that compares the voltage signal by the output buffer unit with the reference voltage and outputs a digitized comparison result signal is included.
The comparator is under the control of the reading unit.
A first comparison process for outputting a digitized first comparison result signal with respect to the voltage signal corresponding to the overflow charge overflowing from the photoelectric conversion element to the output node during the storage period.
A second comparison process for outputting a second digitized comparison result signal with respect to the voltage signal according to the accumulated charge of the photoelectric conversion element transferred to the output node during the transfer period after the storage period. Do,
A solid-state imaging device including a charge emitting unit capable of discharging unnecessary charges from the photoelectric conversion element to the outside of the output node region when irregular strong light is incident on the photoelectric conversion element during the second comparison process. The charge emitting part is
The solid-state imaging device according to claim 1, wherein a shutter gate element capable of forming an emitter flow path from the photoelectric conversion element to the outside of the output node region is formed. The transfer element is formed by a transfer transistor.
The shutter gate element is formed by a shutter gate transistor.
The reading unit is
The solid-state image sensor according to claim 2, wherein the off potential of the shutter gate transistor is set lower than the off potential of the transfer transistor in order to guarantee the first comparison process. The reading unit is used in the second comparison process.
During the transfer period, the transfer transistor is held in a conductive state, and the shutter gate transistor is held in a non-conducting state.
The solid-state image sensor according to claim 3, wherein the shutter gate transistor is held in the conductive state for a predetermined period after the transfer period in which the transfer transistor is switched to the non-conducting state at the end of the transfer period. The solid according to any one of claims 2 to 4, wherein in the case of irregular strong exposure due to charge overflow from the photoelectric conversion element, the output node level is maintained at a level at which the comparison process is normally performed by the shutter gate operation. Image sensor. The comparator is used in the first comparison process.
The solid-state image sensor according to any one of claims 1 to 5, which outputs the first comparison result signal corresponding to the time corresponding to the amount of the overflow charge. The comparator is used in the first comparison process.
The solid according to claim 6, wherein the overflow charge can correspond to an optical level from the signal level of the photoelectric conversion element to the signal level obtained in the minimum sampling time at the maximum sampling time when the photoelectric conversion element starts to overflow from the photoelectric conversion element to the output node. Image sensor. The accumulation period is
This is the period from when the photoelectric conversion element and the output node are reset to the reset level until the transfer element is switched to the conductive state and the transfer period is started.
The period of the first comparison process is
The period from when the photoelectric conversion element and the output node are reset to the reset level until the output node is reset to the reset level before the transfer period is started.
The period of the second comparison process is
The solid-state image sensor according to any one of claims 1 to 7, which is a period after the output node is reset to the reset level and includes a period after the transfer period. The reading unit is
The solid-state image sensor according to any one of claims 1 to 7, wherein the first comparison process and the second comparison process are controlled so as to be selectively performed according to the illuminance. The reading unit is
The solid-state image sensor according to claim 9, wherein the first comparison process and the second comparison process are controlled to be performed in the case of normal illuminance. The reading unit is
The solid-state image sensor according to claim 9 or 10, wherein when the illuminance is higher than the normal illuminance, the first comparison process is controlled to be performed. The reading unit is
The solid-state image sensor according to any one of claims 8 to 11, wherein when the illuminance is lower than the normal illuminance, the second comparison process is controlled to be performed. The reading unit is
Even when the photoelectric conversion element does not overflow to the output node during the storage period with respect to the comparator, the first digitized voltage signal according to the charge is digitized by the first comparison process. The solid-state imaging device according to any one of claims 1 to 12, which controls to output a comparison result signal. The pixel is
Floating diffusion as the output node and
Includes a reset element that resets the floating diffusion to a predetermined potential during the reset period.
The output buffer unit
A source follower element that converts the charge of the floating diffusion into a voltage signal according to the amount of charge and outputs the converted signal.
The solid-state imaging device according to any one of claims 1 to 13, further comprising a current source connected to a source of the source follower element. The comparator
The voltage signal from the output buffer unit is supplied to the first input terminal,
The reference voltage is supplied to the second input terminal, and the reference voltage is supplied.
The solid-state image sensor according to any one of claims 1 to 14, wherein a coupling capacitor is connected to the supply line of the voltage signal to the first input terminal. The comparator
A reset switch is connected between the output terminal and the first input terminal.
The solid-state image sensor according to any one of claims 1 to 15, wherein a load capacitor is connected to the output terminal side. The first board and
Including the second substrate,
The first substrate and the second substrate have a laminated structure connected through a connecting portion.
The pixel is
A memory unit for storing data corresponding to the comparison result signal of the comparator is included.
On the first substrate,
At least the photoelectric conversion element, the transfer element, the output node, and the output buffer portion of the pixel are formed.
On the second substrate,
The solid-state imaging device according to any one of claims 1 to 16, wherein at least a part of the comparator, the memory unit, and the reading unit is formed. The pixel is
Floating diffusion as the output node and
Includes a reset element that resets the floating diffusion to a predetermined potential during the reset period.
The output buffer unit
A source follower element that converts the charge of the floating diffusion into a voltage signal according to the amount of charge and outputs the converted signal.
Including a current source connected to the source of the source follower element.
The floating diffusion, the reset element, and the source follower element are formed on the first substrate.
The solid-state image sensor according to claim 17, wherein the current source is formed on the first substrate or the second substrate. The pixel part where the pixels that perform photoelectric conversion are arranged and
It has a reading unit that reads a pixel signal from the pixel of the pixel unit.
The pixel is
A photoelectric conversion element that accumulates the electric charge generated by photoelectric conversion during the storage period,
A transfer element capable of transferring the electric charge accumulated in the photoelectric conversion element during the transfer period after the accumulation period, and
An output node to which the electric charge accumulated in the photoelectric conversion element is transferred through the transfer element, and
An output buffer unit that converts the electric charge of the output node into a voltage signal according to the amount of electric charge and outputs the converted voltage signal.
A method for driving a solid-state image sensor, which includes a comparator that compares a voltage signal by the output buffer unit with a reference voltage and outputs a digitized comparison result signal.
When reading out the pixel signal of the pixel, in the comparator,
Under the control of the reading unit
A first comparison process is performed to output a digitized first comparison result signal with respect to the voltage signal corresponding to the overflow charge overflowing from the photoelectric conversion element to the output node during the accumulation period.
A second comparison process is performed to output a second digitized comparison result signal with respect to the voltage signal corresponding to the accumulated charge of the photoelectric conversion element transferred to the output node during the transfer period after the accumulation period.
A method for driving a solid-state image sensor that emits unnecessary charges from the photoelectric conversion element to the outside of the output node region when irregularly strong light is incident on the photoelectric conversion element during the second comparison process. Solid-state image sensor and
The solid-state image sensor has an optical system for forming a subject image and
The solid-state image sensor
The pixel part where the pixels that perform photoelectric conversion are arranged and
A reading unit that reads a pixel signal from the pixel of the pixel unit is included.
The pixel is
A photoelectric conversion element that accumulates the electric charge generated by photoelectric conversion during the storage period,
A transfer element capable of transferring the electric charge accumulated in the photoelectric conversion element during the transfer period after the accumulation period, and
An output node to which the electric charge accumulated in the photoelectric conversion element is transferred through the transfer element, and
An output buffer unit that converts the electric charge of the output node into a voltage signal according to the amount of electric charge and outputs the converted voltage signal.
A comparator that compares the voltage signal by the output buffer unit with the reference voltage and outputs a digitized comparison result signal is included.
The comparator is under the control of the reading unit.
A first comparison process for outputting a digitized first comparison result signal with respect to the voltage signal corresponding to the overflow charge overflowing from the photoelectric conversion element to the output node during the storage period.
A second comparison process for outputting a second digitized comparison result signal with respect to the voltage signal according to the accumulated charge of the photoelectric conversion element transferred to the output node during the transfer period after the storage period. Do,
An electronic device including a charge emitting unit capable of discharging unnecessary charges from the photoelectric conversion element to the outside of the output node region when irregular strong light is incident on the photoelectric conversion element during the second comparison process.

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