JP2017512331A - 温度ベースのワイヤルーティング - Google Patents

温度ベースのワイヤルーティング Download PDF

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Publication number
JP2017512331A
JP2017512331A JP2016549733A JP2016549733A JP2017512331A JP 2017512331 A JP2017512331 A JP 2017512331A JP 2016549733 A JP2016549733 A JP 2016549733A JP 2016549733 A JP2016549733 A JP 2016549733A JP 2017512331 A JP2017512331 A JP 2017512331A
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JP
Japan
Prior art keywords
route
expected
endpoint
temperature
routes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016549733A
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English (en)
Japanese (ja)
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JP2017512331A5 (enExample
Inventor
チュンチェン・リュウ
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2017512331A publication Critical patent/JP2017512331A/ja
Publication of JP2017512331A5 publication Critical patent/JP2017512331A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/08—Thermal analysis or thermal optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49162—Manufacturing circuit on or in base by using wire as conductive path

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2016549733A 2014-02-07 2015-02-06 温度ベースのワイヤルーティング Pending JP2017512331A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/175,429 2014-02-07
US14/175,429 US20150227667A1 (en) 2014-02-07 2014-02-07 Temperature-based wire routing
PCT/US2015/014770 WO2015120244A1 (en) 2014-02-07 2015-02-06 Temperature-based wire routing

Publications (2)

Publication Number Publication Date
JP2017512331A true JP2017512331A (ja) 2017-05-18
JP2017512331A5 JP2017512331A5 (enExample) 2018-03-08

Family

ID=52577974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016549733A Pending JP2017512331A (ja) 2014-02-07 2015-02-06 温度ベースのワイヤルーティング

Country Status (5)

Country Link
US (1) US20150227667A1 (enExample)
EP (1) EP3103041A1 (enExample)
JP (1) JP2017512331A (enExample)
CN (1) CN106030584A (enExample)
WO (1) WO2015120244A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018057454A1 (en) * 2016-09-20 2018-03-29 Octavo Systems Llc Method for routing bond wires in system in a package (sip) devices
US10515181B2 (en) * 2017-05-10 2019-12-24 International Business Machines Corporation Integrated circuit identification
CN119528602B (zh) * 2025-01-22 2025-05-23 成都工业学院 多孔碳化硅-碳化硼陶瓷基复合材料的致密化生产工艺

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3986717B2 (ja) 1999-12-01 2007-10-03 富士通株式会社 パス決定方法及び記憶媒体
US6766502B1 (en) * 1999-12-30 2004-07-20 Intel Corporation Method and apparatus for routing using deferred merging
EP1754986B1 (en) * 2002-04-01 2012-12-05 Ibiden Co., Ltd. Optical communication device and optical communication device manufacturing method
JP2005141679A (ja) * 2003-11-10 2005-06-02 Toshiba Microelectronics Corp 半導体集積回路装置、半導体集積回路装置のレイアウト方法および半導体集積回路装置のレイアウト設計プログラム
US7155686B2 (en) 2004-03-09 2006-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Placement and routing method to reduce Joule heating
US7725861B2 (en) 2006-05-15 2010-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method, apparatus, and system for LPC hot spot fix
US8104007B2 (en) * 2008-06-24 2012-01-24 Cadence Design Systems, Inc. Method and apparatus for thermal analysis
JP5390168B2 (ja) 2008-11-10 2014-01-15 ルネサスエレクトロニクス株式会社 配線のレイアウト方法及びプログラム

Also Published As

Publication number Publication date
EP3103041A1 (en) 2016-12-14
WO2015120244A1 (en) 2015-08-13
US20150227667A1 (en) 2015-08-13
CN106030584A (zh) 2016-10-12

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