JP2017510890A - 一般的なニューロンモデルの効率的な実装のための方法および装置 - Google Patents

一般的なニューロンモデルの効率的な実装のための方法および装置 Download PDF

Info

Publication number
JP2017510890A
JP2017510890A JP2016554451A JP2016554451A JP2017510890A JP 2017510890 A JP2017510890 A JP 2017510890A JP 2016554451 A JP2016554451 A JP 2016554451A JP 2016554451 A JP2016554451 A JP 2016554451A JP 2017510890 A JP2017510890 A JP 2017510890A
Authority
JP
Japan
Prior art keywords
neuron model
memory
instance
neuron
parameters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2016554451A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017510890A5 (enExample
Inventor
サラ、アンソニー
レビン、ジェフレイ・アレキサンダー
ゲールハー、ジェフレイ・バギンスキー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2017510890A publication Critical patent/JP2017510890A/ja
Publication of JP2017510890A5 publication Critical patent/JP2017510890A5/ja
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/10—Interfaces, programming languages or software development kits, e.g. for simulating neural networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0499—Feedforward networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/082—Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Evolutionary Computation (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Linguistics (AREA)
  • Artificial Intelligence (AREA)
  • Neurology (AREA)
  • Image Analysis (AREA)
  • Semiconductor Memories (AREA)
  • User Interface Of Digital Computer (AREA)
  • Stored Programmes (AREA)
JP2016554451A 2014-02-28 2015-02-12 一般的なニューロンモデルの効率的な実装のための方法および装置 Ceased JP2017510890A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461946051P 2014-02-28 2014-02-28
US61/946,051 2014-02-28
US14/267,394 2014-05-01
US14/267,394 US9672464B2 (en) 2014-02-28 2014-05-01 Method and apparatus for efficient implementation of common neuron models
PCT/US2015/015637 WO2015130476A2 (en) 2014-02-28 2015-02-12 Method and apparatus for efficient implementation of common neuron models

Publications (2)

Publication Number Publication Date
JP2017510890A true JP2017510890A (ja) 2017-04-13
JP2017510890A5 JP2017510890A5 (enExample) 2018-03-01

Family

ID=54006937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016554451A Ceased JP2017510890A (ja) 2014-02-28 2015-02-12 一般的なニューロンモデルの効率的な実装のための方法および装置

Country Status (7)

Country Link
US (1) US9672464B2 (enExample)
EP (1) EP3111378A2 (enExample)
JP (1) JP2017510890A (enExample)
KR (1) KR20160125967A (enExample)
CN (1) CN106068519B (enExample)
CA (1) CA2937945A1 (enExample)
WO (1) WO2015130476A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10068170B2 (en) * 2013-09-23 2018-09-04 Oracle International Corporation Minimizing global error in an artificial neural network
KR102372423B1 (ko) * 2017-05-16 2022-03-10 한국전자통신연구원 파라미터 공유 장치 및 방법
US11507806B2 (en) * 2017-09-08 2022-11-22 Rohit Seth Parallel neural processor for Artificial Intelligence
US11195079B2 (en) * 2017-11-22 2021-12-07 Intel Corporation Reconfigurable neuro-synaptic cores for spiking neural network
US11347998B2 (en) * 2018-02-26 2022-05-31 Fredric William Narcross Nervous system on a chip
CN108830379B (zh) * 2018-05-23 2021-12-17 电子科技大学 一种基于参数量化共享的神经形态处理器
CN109886384B (zh) * 2019-02-15 2021-01-05 北京工业大学 一种基于鼠脑海马网格细胞重构的仿生导航方法
US11270195B2 (en) 2019-03-05 2022-03-08 International Business Machines Corporation Neuromorphic computing in dynamic random access memory
WO2021137601A1 (ko) * 2019-12-30 2021-07-08 매니코어소프트주식회사 강화 학습 기반의 프로그램 최적화 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05128083A (ja) * 1991-10-31 1993-05-25 Ricoh Co Ltd 信号処理装置
WO1995016244A1 (en) * 1993-12-08 1995-06-15 Minnesota Mining And Manufacturing Company Facet classification neural network
US8027942B2 (en) * 2000-12-13 2011-09-27 International Business Machines Corporation Method and circuits for associating a complex operator to each component of an input pattern presented to an artificial neural network

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5222196A (en) * 1990-02-20 1993-06-22 International Business Machines Corporation Neural network shell for application programs
EP1172763A3 (en) 2000-07-13 2008-11-05 International Business Machines Corporation Method and circuits for associating a norm to each component of an input pattern presented to a neural network
TW538381B (en) * 2000-07-13 2003-06-21 Ibm Method and circuits for associating a norm to each component of an input pattern presented to a neural network
JP4710931B2 (ja) 2008-07-09 2011-06-29 ソニー株式会社 学習装置、学習方法、およびプログラム
CN102947818B (zh) 2010-05-19 2015-07-22 加利福尼亚大学董事会 神经处理单元
US8650008B2 (en) 2010-08-05 2014-02-11 International Business Machines Corporation Method and system of developing corner models for various classes on nonlinear systems
KR101888468B1 (ko) 2011-06-08 2018-08-16 삼성전자주식회사 Ｓｔｄｐ 기능 셀을 위한 시냅스, ｓｔｄｐ 기능 셀 및 ｓｔｄｐ 기능 셀을 이용한 뉴로모픽 회로
US9111224B2 (en) * 2011-10-19 2015-08-18 Qualcomm Incorporated Method and apparatus for neural learning of natural multi-spike trains in spiking neural networks
US9111225B2 (en) * 2012-02-08 2015-08-18 Qualcomm Incorporated Methods and apparatus for spiking neural computation
US9256823B2 (en) 2012-07-27 2016-02-09 Qualcomm Technologies Inc. Apparatus and methods for efficient updates in spiking neuron network
US9256215B2 (en) 2012-07-27 2016-02-09 Brain Corporation Apparatus and methods for generalized state-dependent learning in spiking neuron networks

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05128083A (ja) * 1991-10-31 1993-05-25 Ricoh Co Ltd 信号処理装置
WO1995016244A1 (en) * 1993-12-08 1995-06-15 Minnesota Mining And Manufacturing Company Facet classification neural network
US8027942B2 (en) * 2000-12-13 2011-09-27 International Business Machines Corporation Method and circuits for associating a complex operator to each component of an input pattern presented to an artificial neural network

Also Published As

Publication number Publication date
KR20160125967A (ko) 2016-11-01
US9672464B2 (en) 2017-06-06
WO2015130476A3 (en) 2015-10-22
WO2015130476A2 (en) 2015-09-03
CA2937945A1 (en) 2015-09-03
CN106068519A (zh) 2016-11-02
CN106068519B (zh) 2018-12-18
US20150248607A1 (en) 2015-09-03
EP3111378A2 (en) 2017-01-04

Similar Documents

Publication Publication Date Title
JP6130056B2 (ja) スパイキングネットワークの効率的なハードウェア実装
JP2016536679A (ja) ニューラルシミュレータ用の共有メモリアーキテクチャ
JP6275868B2 (ja) ニューラルウォッチドッグ
JP2017510890A (ja) 一般的なニューロンモデルの効率的な実装のための方法および装置
JP2017509982A (ja) 原位置ニューラルネットワークコプロセッシング
JP2017509952A (ja) シャドウネットワークでニューラルネットワークを監視すること
JP2016539414A (ja) スパイキングニューラルネットワークにおいてリプレーを使用するシナプス学習を実装すること
JP2017511936A (ja) 現在の計算リソースへのニューラルネットワーク適応
JP2016530630A (ja) ニューラルデバイスのトレーニングを調節するための方法および装置
WO2015053864A1 (en) Compiling network descriptions to multiple platforms
JP2016536657A (ja) ニューラルモデルのためのグループタグの実装のための方法および装置
JP2017519268A (ja) スパイキングニューラルネットワークにおけるグローバルスカラ値によって可塑性を調節すること
JP2017513108A (ja) サブしきい値変調を介するアナログ信号再構築および認識
JP2017509980A (ja) 動的な空間ターゲット選択
WO2015153150A2 (en) Probabilistic representation of large sequences using spiking neural network
JP6193509B2 (ja) 可塑性シナプス管理
JP2016537711A (ja) スパイキングニューロンのネットワークにおける輻輳回避
JP2017509956A (ja) 値をスパイクに変換するための方法
JP6219509B2 (ja) シナプス遅延を動的に割り当てることおおよび検査すること
JP2017509973A (ja) 座標変換のための位相コーディング
JP2017513110A (ja) ニューロモーフィックモデル開発のためのコンテキストリアルタイムフィードバック
JP2016536676A (ja) ニューラルモデル実行をリモートで制御および監視するための方法および装置
JP2017509979A (ja) 空間ターゲット選択のためのアンバランスな交差抑制メカニズム

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161027

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180117

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180117

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190226

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20190312

A045 Written measure of dismissal of application [lapsed due to lack of payment]

Free format text: JAPANESE INTERMEDIATE CODE: A045

Effective date: 20190730