JP2017228585A - Wiring board and method of manufacturing the same, and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board and a method of manufacturing the same, and a method of manufacturing a semiconductor device, that are capable of reducing variation in thickness of a wiring layer included in a rewiring layer.SOLUTION: A wiring board 10 comprises: a core substrate 20; and a rewiring layer 30 arranged on the core substrate 20, and having a wiring layer 32. The rewiring layer 30 has: an element mounting region 37 for mounting a semiconductor element 71; and an extension electrode layer 38 formed around the element mounting region 37 so as to surround the element mounting region 37.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a wiring board, a manufacturing method thereof, and a manufacturing method of a semiconductor device.

  Conventionally, as a semiconductor package on which a semiconductor element is mounted, for example, a package having a core substrate, a rewiring layer formed on the core substrate, and a semiconductor element mounted on a portion where the rewiring layer is formed Are known. Such a rewiring layer has a pattern structure made of an insulating material and a fine wiring layer disposed in a recess of the pattern structure.

JP 2013-258238 A

  Conventionally, in order to form a fine metal wiring layer with a high aspect ratio in the rewiring layer, a method of forming a wiring by depositing a metal film on the concave portion of the pattern structure using an electrolytic plating method is generally used. It has been. At this time, an outer peripheral electrode is disposed around the pattern structure, and a current is supplied from the electrode in the plating solution to the outer electrode, thereby depositing a plating layer in the concave portion of the pattern structure. However, particularly when the substrate size is increased or the metal wiring is fine, the resistance value against the current supplied to the seed electrode increases, and the thickness of the deposited plating layer (wiring layer) may vary in the plane. It has become a challenge. For example, while the thickness of the plating layer of the metal wiring located near the outer peripheral electrode is increased, there is a problem that the thickness of the plating layer of the metal wiring positioned far from the outer peripheral electrode is reduced.

  The present invention has been made in consideration of such points, and can reduce variations in the thickness of the wiring layer included in the rewiring layer, a wiring substrate, a manufacturing method thereof, and a semiconductor device manufacturing method. The purpose is to provide.

  The present invention includes a core substrate and a rewiring layer disposed on the core substrate and having a wiring layer, the rewiring layer including an element mounting area on which a semiconductor element is mounted, and a periphery of the element mounting area And an extended electrode layer formed so as to surround the element mounting region.

  The present invention is the wiring board characterized in that a plurality of the element mounting regions are provided, and the extended electrode layer is formed in a lattice shape.

  The width of the extended electrode layer may be 0.2 mm or more and 15 mm or less.

  The present invention comprises a core substrate, a rewiring layer disposed on the core substrate and having a wiring layer, and a semiconductor element mounted on the rewiring layer, and the rewiring layer is mounted with a semiconductor element The semiconductor device includes: an element mounting region to be formed; and an extended electrode layer formed so as to surround the element mounting region around the element mounting region.

  The present invention is the semiconductor device characterized in that a plurality of the element mounting regions are provided, and the extended electrode layer is formed in a lattice shape.

  The present invention is the semiconductor device, wherein the width of the extended electrode layer is 0.2 mm or more and 15 mm or less.

  The present invention includes a step of preparing a core substrate and a step of forming a rewiring layer having a wiring layer on the core substrate, the rewiring layer including an element mounting region on which the semiconductor element is mounted; And an extended electrode layer formed so as to surround the element mounting area around the element mounting area.

  In the present invention, the step of forming the rewiring layer includes a step of supplying an insulating resist on the core substrate, a mold is prepared, the mold and the core substrate are brought close to each other, and the mold and the core substrate are provided. Unfolding the insulating resist to form an insulating resist layer, curing the insulating resist layer to form an insulating material layer, separating the mold from the insulating material layer, and the insulating material Developing the material layer to form an insulating pattern structure having extended electrode recesses, and forming a conductive layer in the extended electrode recesses of the pattern structure by electrolytic plating. And the conductor layer constitutes at least a part of the extended electrode layer.

  The present invention is a method of manufacturing a semiconductor device, comprising the steps of preparing the wiring board and providing a semiconductor element on the rewiring layer of the wiring board.

  According to the present invention, variation in the thickness of the wiring layer included in the rewiring layer can be reduced.

FIG. 1 is a cross-sectional view showing a wiring board according to an embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view showing a wiring board according to an embodiment of the present invention. FIG. 3 is a plan view showing a wiring board according to an embodiment of the present invention. 4A to 4C are cross-sectional views illustrating a method of manufacturing a wiring board according to an embodiment of the present invention. 5A to 5C are cross-sectional views illustrating a method of manufacturing a wiring board and a semiconductor device according to an embodiment of the present invention. 6A to 6D are cross-sectional views illustrating a part of the process of forming the rewiring layer. 7A to 7C are cross-sectional views illustrating a part of the process of forming the rewiring layer. FIGS. 8A to 8C are cross-sectional views illustrating a part of the process of forming the rewiring layer. FIGS. 9A to 9C are cross-sectional views illustrating a part of the process of forming the rewiring layer.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. Note that, in the following drawings, the same portions are denoted by the same reference numerals, and some detailed description may be omitted.

(Configuration of wiring board)
First, the outline of the wiring board according to the present embodiment will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing a wiring board according to the present embodiment, and FIG. 2 is a partially enlarged view of FIG. FIG. 3 is a plan view showing a wiring board according to the present embodiment.

  As shown in FIG. 1, the wiring board 10 is for mounting a semiconductor element 71 (see FIG. 5C) described later. The wiring substrate 10 includes a core substrate 20 and a rewiring layer 30 disposed on the core substrate 20.

  FIG. 2 is a partial enlarged cross-sectional view of the wiring board 10. As shown in FIG. 2, the core substrate 20 includes a core base material 21, insulating layers 23 </ b> A, 23 </ b> B, 54 </ b> A, 54 </ b> B laminated on both surfaces of the core base material 21, and insulating layers on both surfaces of the core base material 21. It has a multilayer structure including a plurality of conductor layers 24A, 24B, 55A, 55B stacked via 23A, 23B, 54A, 54B.

  Among these, a plurality of front and back conductive via portions 22 penetrating the core base material 21 are embedded in the core base material 21. In addition, a conductor layer 22 a connected to a predetermined front / back conduction via portion 22 is provided on the surface of the core base material 21 (in the illustrated example, the surface side on which the rewiring layer 30 is disposed). Furthermore, a conductor layer 53 a connected to a predetermined front and back conductive via portion 22 is provided on the back surface of the core base material 21.

  Such a core substrate 21 may be an electrically insulating material such as glass cloth-containing epoxy resin, bismaleimide triazine resin, polyphenylene ether resin, aramid resin, benzocyclobutene resin, cycloolefin polymer, and the like.

  Conductive layers 24A and 24B are laminated on the surface side of the core substrate 21 via insulating layers 23A and 23B. The conductor layer 22a positioned above and below the conductor layer 24A is connected by the interlayer connector 25A via the insulating layer 23A, and the conductor layer 24A and conductor layer 24B positioned vertically via the insulating layer 23B are connected to the interlayer connector. 25B is connected.

  Further, conductor layers 55A and 55B are laminated on the back surface side of the core base material 21 via insulating layers 54A and 54B. Then, the conductor layer 53a positioned above and below via the insulating layer 54A and the conductor layer 55A are connected by an interlayer connector 56A, and the conductor layer 55A positioned above and below via the insulating layer 54B and the conductor layer 55B are interlayer connected. It is connected by a body 56B. The solder resist 27 is disposed so as to expose a desired portion of the conductor layer 55B, and the solder ball 51 is provided on the conductor layer 55B exposed from the solder resist 27.

  The conductor layer 24B located on the surface side of the core substrate 20 is a pad portion, and a rewiring layer 30 composed of a multilayer wiring structure 36 is disposed so as to be connected to the pad portion. The rewiring layer 30 has a wiring layer 32 (32A, 32B, 32C) composed of three layers.

  A nickel layer 57 and a gold layer 58 are sequentially provided on the wiring layer 32 </ b> C of the rewiring layer 30, and a solder resist 59 is disposed so as to expose the gold layer 58. The gold layer 58 is connected to the terminal 71a of the semiconductor element 71 through the connection pad 72 as described later.

  The rewiring layer 30 includes a pattern structure 31 (31A, 31B, 31C) formed on the core substrate 20 and a wiring layer 32 (32A, 32B, 32C) embedded in the pattern structure 31. Yes.

  The pattern structure 31 is made of, for example, a photocurable resin. This photocurable resin is generally composed of a main agent, an initiator, and a crosslinking agent. In addition, the photocurable resin may contain a release agent or an adhesive as an auxiliary agent as necessary. There is no restriction | limiting in particular in the photocurable resin used by this Embodiment, According to the use of the pattern structure 31, a required characteristic, a physical property, etc., it can select suitably from well-known photocurable resin. The thickness of the pattern structure 31 is preferably about 1 μm to 50 μm, for example.

  The wiring layer 32 includes a wiring 33, a pad portion 34, and an interlayer connection via 35 connected to the pad portion 34. The pad portion 34 and the interlayer connection via 35 are both made of the same material and integrated with each other. The wiring layer 32 is preferably made of a metal material having good conductivity, such as copper, nickel, nickel chrome alloy, or the like.

  In the present embodiment, the wiring layer 32 is formed in multiple layers. That is, a three-layer wiring layer including a wiring layer 32A disposed in the pattern structure 31A, a wiring layer 32B disposed in the pattern structure 31B, and a wiring layer 32C disposed in the pattern structure 31C. 32 is formed. That is, the rewiring layer 30 including the multilayer wiring structure 36 having a three-layer structure is disposed on the core substrate 20.

  As shown in FIG. 3, the wiring board 10 has a plurality of package regions 14. Each package region 14 is a region corresponding to one semiconductor device 70 (see FIG. 5C), and has a substantially rectangular shape in plan view. That is, a plurality of semiconductor devices 70 each corresponding to the package region 14 are manufactured from one wiring board 10. In FIG. 3, three package regions 14 are shown for convenience.

  As shown in FIG. 3, the redistribution layer 30 includes an element mounting region 37 and an extended electrode layer 38 formed around the element mounting region 37. Of these, the element mounting region 37 corresponds to a region where the semiconductor element 71 (see FIG. 5C) is mounted, and has a substantially rectangular shape. In this case, one package region 14 is provided with five element mounting regions 37, but the present invention is not limited to this, and one package region 14 includes one or more element mounting regions 37. It may be provided.

  In each element mounting region 37, the gold layer 58 connected to the terminal 71a of the semiconductor element 71 is exposed. In this case, each gold layer 58 has a substantially circular shape in plan view. The plurality of gold layers 58 are arranged in, for example, a square lattice point within each element mounting region 37. A solder resist 59 is disposed on the outer periphery of the gold layer 58. In FIG. 3, only a part of the gold layer 58 is shown for convenience.

  The extended electrode layer 38 is formed so as to surround the plurality of element mounting regions 37. Specifically, the extended electrode layer 38 is provided along the outer periphery of the package region 14. In this case, the extended electrode layer 38 is formed in a lattice shape in plan view, and the openings of the lattice correspond to the package regions 14. The extended electrode layer 38 is made of a plated layer formed by electrolytic plating as will be described later.

  In the present embodiment, the extended electrode layer 38 is formed over the entire outer periphery of the package region 14. That is, each side forming the lattice of the extended electrode layer 38 is disposed across two adjacent package regions 14. The width w of one side forming the lattice of the extended electrode layer 38 is preferably 0.2 mm or more and 15 mm or less, for example. By setting the width w of one side of the extended electrode layer 38 to 0.2 mm or more, variations in the electrical resistance value of the extended electrode layer 38 can be reduced, and in-plane variations in the thickness of the wiring layer 32 can be reduced. Further, by setting the width w of one side of the extended electrode layer 38 to 15 mm or less, preferably 5 mm or less, it is possible to secure a certain number or more of the package regions 14 included in the wiring board 10.

  The planar shape of the extended electrode layer 38 is not necessarily limited to this. The extended electrode layer 38 may be provided along only a part of the outer periphery of the package region 14, or may be formed regardless of the shape of the package region 14. For example, the extended electrode layer 38 may be disposed closer to each element mounting region 37. As will be described later, the extended electrode layer 38 is formed by covering the photosensitive insulating resist layer 42 with the light shielding layer 61 of the mold 60 to form a non-photosensitive region. For this reason, the extended electrode layer 38 can be made into an arbitrary shape by freely designing the shape of the light shielding layer 61.

  Referring to FIG. 2 again, the extended electrode layer 38 is formed over the entire thickness direction of the rewiring layer 30. That is, the thickness of the extended electrode layer 38 is the same as the thickness of the rewiring layer 30 and may be, for example, 1 μm or more and 50 μm or less. The cross-sectional area of the extended electrode layer 38 is larger than the cross-sectional area of each wiring constituting the wiring layer 32. For this reason, the electrical resistance of the extended electrode layer 38 is smaller than the electrical resistance of each wiring. The upper surface of the extended electrode layer 38 (the surface on the opposite side of the core substrate 20) is located on the same plane as the upper surface of the pattern structure 31C. The lower surface of the extended electrode layer 38 (the surface on the core substrate 20 side) is located on the same plane as the lower surface of the pattern structure 31A. The side surface of the extended electrode layer 38 is in close contact with the pattern structure 31. The extended electrode layer 38 is made of a metal material having high conductivity such as copper.

  In this embodiment, the extended electrode layer 38 is independent of the wiring layer 32 of the rewiring layer 30 and insulated from the wiring layer 32. However, the present invention is not limited to this, and the extended electrode layer 38 is wired. A part of the layer 32 may be connected. In this case, the extended electrode layer 38 can be electrically connected to a part of the terminals 71a of the semiconductor element 71 using, for example, a ground terminal.

(Manufacturing method of wiring board and semiconductor device)
Next, a method for manufacturing a wiring board according to the present embodiment will be described with reference to FIGS. FIGS. 4A to 4C are cross-sectional views illustrating a method for manufacturing a wiring board according to the present embodiment. FIGS. 5A to 5C illustrate the wiring board and the semiconductor device according to the present embodiment. It is sectional drawing which shows a manufacturing method. 6 to 9 are cross-sectional views showing a process of forming a rewiring layer.

  First, for example, a core substrate 20 made of a built-up substrate is prepared (FIG. 4A). The core substrate 20 includes a core base material 21, insulating layers 23 </ b> A, 23 </ b> B, 54 </ b> A and 54 </ b> B and conductor layers 22 a and 53 a respectively laminated on both surfaces of the core base material 21, and an insulating layer 23 </ b> A on both surfaces of the core base material 21. , 23B, 54A, 54B, and a plurality of conductor layers 24A, 24B, 55A, 55B. A solder resist 27 is provided on the lower surface of the insulating layer 54B.

  Next, a single-layer wiring structure 36A is formed on the core substrate 20 (FIG. 4B). The wiring structure 36A includes a pattern structure 31A and a wiring layer 32A. At this time, the partial extended electrode layer 38A constituting a part of the extended electrode layer 38 is formed on the insulating layer 23B of the core substrate 20 in a region corresponding to the space between the adjacent package regions 14 (see FIG. 3). It is formed.

  Next, as illustrated in FIG. 4C, the rewiring layer 30 is formed by sequentially forming the pattern structures 31 </ b> A, 31 </ b> B, 31 </ b> C and the wiring layers 32 </ b> A, 32 </ b> B, 32 </ b> C on the core substrate 20. In this case, the rewiring layer 30 includes a multilayer wiring structure 36 having a three-layer structure formed on the core substrate 20. The rewiring layer 30 is formed by, for example, an imprint method as will be described later. At this time, the extended electrode layer 38 is formed by the partially extended electrode layers 38A, 38B, and 38C laminated together. Next, a solder resist 59 is provided on the rewiring layer 30 of the core substrate 20. From the solder resist 59, the wiring layer 32C and the extended electrode layer 38 of the rewiring layer 30 are exposed. Thereafter, a nickel layer 57 and a gold layer 58 are sequentially stacked on the wiring layer 32 </ b> C of the rewiring layer 30.

  Subsequently, as shown in FIG. 5A, solder balls 51 are respectively provided on the conductor layers 55 </ b> B exposed from the solder resist 27 on the back surface side of the core substrate 20. In this way, the wiring substrate 10 (FIG. 1) including the core substrate 20 and the rewiring layer 30 including the multilayer wiring structure 36 formed on the core substrate 20 is obtained.

  Next, as shown in FIG. 5B, the semiconductor element 71 is mounted on the wiring layer 32 </ b> C exposed from the solder resist 59 on the surface side of the rewiring layer 30 through the connection pads 72. At this time, the connection pad 72 is thermocompression bonded to connect the gold layer 58 and the terminal 71 a of the semiconductor element 71. In addition, an underfill resin 73 is formed in the gap between the semiconductor element 71 and the rewiring layer 30 by filling a thermosetting resin and curing it. The plurality of semiconductor elements 71 mounted in this manner may be different kinds of semiconductor elements.

  Thereafter, as shown in FIG. 5C, the semiconductor device 70 is obtained by cutting the core substrate 20 and the redistribution layer 30 along the outer periphery of each package region 14 (see the drawing). At this time, the extended electrode layer 38 is cut at a substantially central portion in the width direction and disposed in each semiconductor device 70. In this case, the extended electrode layer 38 is provided in a rectangular shape along the outer periphery of the semiconductor device 70.

(Method for forming rewiring layer)
Next, the step of forming the rewiring layer 30 described above by the imprint method (FIG. 4C) will be described in detail with reference to FIGS.

  First, the photosensitive insulating resist 41 is supplied onto the core substrate 20 serving as a transfer base (FIG. 6A). 6 to 9, the detailed configuration of the core substrate 20 is not shown.

  Next, an imprint mold 60 is prepared (FIG. 6B), the mold 60 and the core substrate 20 are brought close to each other, and the photosensitive insulating resist 41 is developed between the mold 60 and the core substrate 20. Thus, a photosensitive insulating resist layer 42 is formed (FIG. 6C).

  Next, light is irradiated from the mold 60 side to cure the photosensitive insulating resist layer 42 to form the insulating material layer 43, and the photosensitive insulating resist layer positioned between the light shielding layer 61 of the mold 60 and the core substrate 20. 42 is left uncured (FIG. 6D).

  Thereafter, the mold 60 is separated from the insulating material layer 43 and the remaining photosensitive insulating resist layer 42 (FIG. 7A).

  Next, the insulating material layer 43 is developed to remove the remaining photosensitive insulating resist layer 42 (FIG. 7B). Thus, an insulating pattern structure having the recess 45, the through hole 46 for forming the interlayer connection via located in the recess 45, and the extended electrode recess 52 for forming the partial extended electrode layer 38A described later. A precursor 44 is formed on the core substrate 20.

  Thereafter, the pattern structure precursor 44 is subjected to a post-bake treatment to obtain a pattern structure 31 (FIG. 7C).

  Next, the conductor barrier layer 47 is formed on the pattern structure 31 (FIG. 8A). In the illustrated example, the conductor barrier layer 47 is indicated by a bold line. The conductor barrier layer 47 prevents the components of the conductor layer formed in the subsequent process from diffusing into the insulating pattern structure 31. The conductor barrier layer 47 has a surface resistance of several tens, such as titanium compounds such as TiN, tungsten alloys, molybdenum alloys, silicon compounds such as SiN, nickel compounds such as NiP, cobalt compounds such as CoWP, and tantalum compounds such as TaN. The material may be Ω / □ or more, and can be formed in a thickness range of 10 nm to 300 nm by a known vacuum film formation method such as a sputtering method.

  Next, a seed electrode layer 48 is formed on the conductor barrier layer 47 (FIG. 8B). The seed electrode layer 48 is preferably made of a material having a surface resistance of 1 Ω / □ or less, such as copper, nickel, nickel chrome alloy, etc., and has a thickness in the range of 10 nm to 500 nm by a known vacuum film formation method such as sputtering. Can be formed.

  Next, a conductor is deposited on the seed electrode layer 48 by electrolytic plating so that the recess 45 and the through hole 46 for forming the interlayer connection via located in the recess 45 for forming the pad portion are filled. A layer 49 is formed (FIG. 8C). Similarly, the conductor layer 49 is also embedded in the extended electrode recess 52 for forming the partial extended electrode layer 38A. At this time, an outer peripheral electrode 39 for electrolytic plating is disposed on the outer periphery of the core substrate 20. By flowing a current from an electrode (not shown) in the plating solution, a current flows from the seed electrode layer 48 of the core substrate 20 to the outer peripheral electrode 39, and the conductor layer 49 is deposited on the seed electrode layer 48. After the conductor layer 49 is deposited, a current also flows through the deposited conductor layer 49. The conductor layer 49 forms the wiring layer 32A, the interlayer connection via 35, and the partial extended electrode layer 38A. For example, a material having high conductivity such as copper, nickel, nickel chromium alloy is preferable.

  In the present embodiment, as described above, the partial extended electrode layer 38A is formed in the extended electrode recess 52 in a lattice shape in plan view. The cross-sectional area of the partial extended electrode layer 38A is larger than the cross-sectional area of individual wirings included in the wiring layer 32A. For this reason, the electrical resistance value of the partial extended electrode layer 38A becomes small, and current easily flows into the partial extended electrode layer 38A. As a result, the current substantially uniformly flows through the partial extended electrode layer 38A to the wiring layer 32A surrounded by the partial extended electrode layer 38A, and the thickness of the wiring layer 32A is made uniform in the plane of the core substrate 20. be able to. In particular, the thickness of the wiring layer 32A at a position away from the outer peripheral electrode 39 (inside the core substrate 20) and the thickness of the wiring layer 32A at a position closer to the outer peripheral electrode 39 (outer peripheral side of the core substrate 20) are substantially uniform. Can be.

  Such a conductor layer 49 is formed to be about several μm thick from the surface of the pattern structure 31. As described above, the thickness of the wiring layer 32 </ b> A is substantially uniform over the entire surface, so that the thickness at which the conductor layer 49 is thicker than the surface of the pattern structure 31 can be minimized.

  Next, the conductor layer 49 and the seed electrode layer 48 are polished, and conductors are respectively formed in the recess 45 of the pattern structure 31, the through hole 46 for forming the interlayer connection via located in the recess 45, and the extension electrode recess 52. The layer 49 and the seed electrode layer 48 are left (FIG. 9A). For example, the conductor layer 49 and the seed electrode layer 48 are polished by using the conductor barrier layer 47 as a polishing stopper and a metal having higher hardness than the conductor layer 49 such as titanium, tungsten, molybdenum, or an alloy containing any one of them. It can be carried out using a compound. Polishing of the conductor layer 49 and the seed electrode layer 48 can be performed by, for example, a CMP (Chemical mechanical polishing) method. As described above, since the thickness at which the conductor layer 49 is thicker than the surface of the pattern structure 31 can be minimized, the time used for polishing the conductor layer 49 and the seed electrode layer 48 can be shortened and the polishing pad Consumption can be reduced. In addition, since the number of polishing apparatuses (CMP apparatuses) can be suppressed, manufacturing costs can be reduced.

  Thereafter, the exposed conductor barrier layer 47 is further removed (FIG. 9B). The conductor barrier layer 47 can be removed by a flash etching method.

  Through the series of steps described above, the single wiring layer 32 and the partial extended electrode layer 38A can be formed on the core substrate 20. Thus, the wiring structure 36A is obtained by the pattern structure 31 formed on the core substrate 20, and the wiring layer 32 and the partial extended electrode layer 38A embedded in the pattern structure 31. Among these, the wiring layer 32 includes a wiring 33, a pad portion 34, and an interlayer connection via 35 connected to the pad portion 34.

  Subsequently, a desired wiring layer is formed in multiple layers by repeating the above series of steps a desired number of times. FIG. 9C shows the wiring layer 32A disposed in the pattern structure 31A, the wiring layer 32B disposed in the pattern structure 31B, and the pattern structure by repeating the above series of steps three times. In this example, three wiring layers including the wiring layer 32C disposed on 31C are formed. Further, the partial extended electrode layer 38A provided in the pattern structure 31A, the partial extended electrode layer 38B provided in the pattern structure 31B, and the partial extended electrode layer 38C provided in the pattern structure 31C. The extended electrode layer 38 is formed. Thereby, the rewiring layer 30 including the multilayer wiring structure 36 having a three-layer structure on the core substrate 20 is obtained.

  As described above, according to the present embodiment, the redistribution layer 30 has the element mounting region 37 on which the semiconductor element 71 is mounted and the extended electrode layer 38 formed around the element mounting region 37. ing. As a result, when the wiring layer 32 is formed by electroplating, the expansion electrode layer 38 (partial expansion electrode layers 38A to 38C) can cause a current to flow uniformly in the plane of the core substrate 20, and the thickness of the wiring layer 32 can be reduced. It can be made uniform in the plane of the core substrate 20.

  In addition, according to the present embodiment, a plurality of element mounting regions 37 are provided and the extended electrode layers 38 are formed in a lattice shape, so that the extended electrode layers 38 are uniformly arranged on the entire core substrate 20. . Thereby, the thickness of the wiring layer 32 located inside the core substrate 20 and the wiring layer 32 located outside the core substrate 20 can be made uniform.

  Further, according to the present embodiment, when the rewiring layer 30 is formed, first, the insulating resist 41 is supplied onto the core substrate 20, and then the mold 60 and the core substrate 20 are brought close to each other so that the mold 60 and the core An insulating resist 41 is developed between the substrate 20 and an insulating resist layer 42 is formed. Next, after the insulating resist layer 42 is cured to form the insulating material layer 43, the mold 60 is separated from the insulating material layer 43. Next, by developing the insulating material layer 43, the insulating pattern structure 31 having the extended electrode recess 52 is formed. Thereafter, a conductor layer 49 constituting a part of the extended electrode layer 38 is embedded in the extended electrode recess 52 by electrolytic plating. Thus, by appropriately setting the shape of the light shielding layer 61 of the mold 60, the extended electrode layer 38 having an arbitrary planar shape can be provided, and a path for passing a current to the wiring layer 32 can be freely set. it can.

  A plurality of constituent elements disclosed in the above-described embodiment can be appropriately combined as necessary. Or you may delete a some component from all the components shown by the said embodiment.

DESCRIPTION OF SYMBOLS 10 Wiring board 14 Package area | region 20 Core board | substrate 30 Rewiring layer 31 Pattern structure 32 Wiring layer 37 Element mounting area 38 Extended electrode layer 70 Semiconductor device 71 Semiconductor element

Claims (9)

A core substrate;
A rewiring layer disposed on the core substrate and having a wiring layer;
The rewiring layer includes an element mounting area on which a semiconductor element is mounted, and an extended electrode layer formed so as to surround the element mounting area around the element mounting area.   The wiring board according to claim 1, wherein a plurality of the element mounting regions are provided, and the extended electrode layer is formed in a lattice shape.   The wiring board according to claim 1, wherein the width of the extended electrode layer is 0.2 mm or more and 15 mm or less. A core substrate;
A rewiring layer disposed on the core substrate and having a wiring layer;
A semiconductor element mounted on the redistribution layer,
The redistribution layer includes an element mounting area on which the semiconductor element is mounted, and an extended electrode layer formed so as to surround the element mounting area around the element mounting area.   The semiconductor device according to claim 4, wherein a plurality of the element mounting regions are provided, and the extended electrode layer is formed in a lattice shape.   6. The semiconductor device according to claim 4, wherein a width of the extended electrode layer is not less than 0.2 mm and not more than 15 mm. Preparing a core substrate; and
Forming a rewiring layer having a wiring layer on the core substrate,
The rewiring layer includes an element mounting area on which a semiconductor element is mounted, and an extended electrode layer formed so as to surround the element mounting area around the element mounting area. Method. The step of forming the rewiring layer includes:
Supplying an insulating resist on the core substrate;
Preparing a mold, bringing the mold and the core substrate close to each other, developing the insulating resist between the mold and the core substrate, and forming an insulating resist layer;
Curing the insulating resist layer to form an insulating material layer;
Separating the mold from the insulating material layer;
Developing the insulating material layer to form an insulating pattern structure having extended electrode recesses; and
Including a step of forming a conductor layer by electrolytic plating in the extended electrode recess of the pattern structure,
The method for manufacturing a wiring board according to claim 7, wherein the conductor layer constitutes at least a part of the extended electrode layer. Preparing the wiring board according to any one of claims 1 to 3,
And a step of providing a semiconductor element on the rewiring layer of the wiring board.