JP7269755B2 - ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - Google Patents

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE Download PDF

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JP7269755B2
JP7269755B2 JP2019032444A JP2019032444A JP7269755B2 JP 7269755 B2 JP7269755 B2 JP 7269755B2 JP 2019032444 A JP2019032444 A JP 2019032444A JP 2019032444 A JP2019032444 A JP 2019032444A JP 7269755 B2 JP7269755 B2 JP 7269755B2
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resin layer
layer
main surface
conductor
electronic device
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JP2019032444A
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JP2020136629A (en
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秀彰 ▲柳▼田
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2019032444A priority Critical patent/JP7269755B2/en
Priority to CN201910988708.5A priority patent/CN111613586B/en
Priority to US16/704,961 priority patent/US11417624B2/en
Publication of JP2020136629A publication Critical patent/JP2020136629A/en
Priority to US17/811,530 priority patent/US20220344300A1/en
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Publication of JP7269755B2 publication Critical patent/JP7269755B2/en
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Description

本開示は、電子部品を備えた電子装置およびその製造方法に関する。 The present disclosure relates to an electronic device including electronic components and a manufacturing method thereof.

特許文献１には、電子部品を備えた、従来の電子装置が開示されている。同文献に記載の電子装置は、半導体基板、電子部品（微細電子素子チップ）および封止樹脂（絶縁性封止樹脂）を備えている。半導体基板は、たとえばＳｉ（シリコン）基板である。電子部品は、半導体基板の一面に実装されて、半導体基板に支持されている。よって、半導体基板は、電子部品を支持する支持部材である。封止樹脂は、たとえば絶縁性のエポキシ樹脂である。封止樹脂は、半導体基板の先述の一面の上に形成され、電子部品を覆う。封止樹脂は、光・熱や湿度などの環境から電子部品を保護する保護部材である。 Japanese Unexamined Patent Application Publication No. 2002-200002 discloses a conventional electronic device including electronic components. The electronic device described in the document includes a semiconductor substrate, an electronic component (microelectronic element chip), and a sealing resin (insulating sealing resin). The semiconductor substrate is, for example, a Si (silicon) substrate. The electronic component is mounted on one surface of the semiconductor substrate and supported by the semiconductor substrate. Therefore, the semiconductor substrate is a supporting member that supports electronic components. The sealing resin is, for example, insulating epoxy resin. A sealing resin is formed on the aforementioned one surface of the semiconductor substrate to cover the electronic components. A sealing resin is a protective member that protects electronic components from environments such as light, heat, and humidity.

特開２００９－９４４０９号公報JP 2009-94409 A

電子装置の通電時に、電子部品から熱が発生する。このとき、半導体基板と封止樹脂との熱膨張係数の違いから、半導体基板（支持部材）と封止樹脂（保護部材）との界面に熱応力がかかる。この熱応力により、封止樹脂が半導体基板から、すなわち、保護部材が支持部材から剥離する虞があり、電子装置の信頼性が低下する要因であった。 When the electronic device is energized, heat is generated from the electronic components. At this time, thermal stress is applied to the interface between the semiconductor substrate (supporting member) and the sealing resin (protective member) due to the difference in coefficient of thermal expansion between the semiconductor substrate and the sealing resin. Due to this thermal stress, the sealing resin may separate from the semiconductor substrate, that is, the protective member may separate from the supporting member, which is a factor in lowering the reliability of the electronic device.

本開示は、上記課題に鑑みて考え出されたものであり、その目的は、信頼性の低下を抑制できる電子装置および当該電子装置の製造方法を提供することにある。 The present disclosure has been conceived in view of the above problems, and an object thereof is to provide an electronic device capable of suppressing deterioration in reliability and a method of manufacturing the electronic device.

本開示の第１の側面によって提供される電子装置は、第１方向において互いに反対側を向く第１樹脂層主面および第１樹脂層裏面を有する第１樹脂層と、前記第１方向において互いに反対側を向く第１導電体主面および第１導電体裏面を有し、前記第１樹脂層を前記第１方向に貫通する第１導電体と、前記第１樹脂層主面と前記第１導電体主面とに跨る第１配線層と、前記第１方向において前記第１樹脂層主面と同じ側を向く第１素子主面および前記第１樹脂層裏面と同じ側を向く第１素子裏面を有し、前記第１配線層に導通接合された第１電子部品と、前記第１樹脂層主面と同じ方向を向く第２樹脂層主面および前記第１樹脂層主面に接する第２樹脂層裏面を有し、前記第１配線層および前記第１電子部品を覆う第２樹脂層と、前記第１樹脂層よりも前記第１樹脂層裏面が向く方向側に配置され、前記第１導電体に導通する外部電極とを備えることを特徴とする。 An electronic device provided by a first aspect of the present disclosure includes: a first resin layer having a first resin layer main surface and a first resin layer back surface facing opposite to each other in a first direction; a first conductor having a first conductor main surface and a first conductor back surface facing opposite sides and penetrating the first resin layer in the first direction; the first resin layer main surface and the first conductor; a first wiring layer straddling a conductor main surface, a first element main surface facing the same side as the first resin layer main surface in the first direction, and a first element facing the same side as the first resin layer back surface in the first direction a first electronic component having a back surface and conductively joined to the first wiring layer; a second resin layer main surface facing the same direction as the first resin layer main surface; a second resin layer having two resin layer back surfaces and covering the first wiring layer and the first electronic component; and an external electrode electrically connected to one conductor.

本開示の第２の側面によって提供される電子装置の製造方法は、第１方向において互いに反対側を向く基板主面および基板裏面を有する支持基板を用意する支持基板用意工程と、前記基板主面の上に、第１導電体を形成する第１導電体形成工程と、前記第１導電体を覆う第１樹脂層を形成する第１樹脂層形成工程と、前記第１方向において前記基板主面が向く側から前記基板裏面が向く側に前記第１樹脂層を研削し、前記第１導電体の一部を前記第１樹脂層から露出させることで、各々が前記第１方向において前記基板主面と同じ側を向く第１導電体主面および第１樹脂層主面を形成する第１樹脂層研削工程と、前記第１樹脂層主面と前記第１導電体主面とに跨る第１配線層を形成する第１配線層形成工程と、前記第１配線層の上に、第１電子部品を導通接合する第１電子部品搭載工程と、前記第１配線層および前記第１電子部品を覆う第２樹脂層を形成する第２樹脂層形成工程と、前記支持基板を除去することで、前記第１方向において前記第１樹脂層主面と反対側を向く第１樹脂層裏面を露出させる支持基板除去工程と、前記第１樹脂層よりも前記第１樹脂層裏面が向く方向側に配置され、前記第１導電体に導通する外部電極を形成する外部電極形成工程とを有することを特徴とする。 A method of manufacturing an electronic device provided by a second aspect of the present disclosure includes a supporting substrate preparing step of preparing a supporting substrate having a substrate main surface and a substrate back surface facing opposite to each other in a first direction; a first conductor forming step of forming a first conductor; a first resin layer forming step of forming a first resin layer covering the first conductor; and a main surface of the substrate in the first direction. By grinding the first resin layer from the side facing the back surface of the substrate to the side facing the back surface of the substrate and exposing a part of the first conductors from the first resin layer, a first resin layer grinding step of forming a first conductor main surface and a first resin layer main surface facing the same side as the surface; a first wiring layer forming step of forming a wiring layer; a first electronic component mounting step of conductively joining a first electronic component on the first wiring layer; a second resin layer forming step of forming a second resin layer to cover; and an external electrode forming step of forming an external electrode that is arranged on the side of the first resin layer in the direction in which the back surface of the first resin layer faces and that is electrically connected to the first conductor. and

本開示によれば、信頼性の低下が抑制された電子装置を提供できる。また、当該電子装置の製造方法を提供できる。 According to the present disclosure, it is possible to provide an electronic device in which deterioration in reliability is suppressed. Also, a method for manufacturing the electronic device can be provided.

第１実施形態にかかる電子装置を示す斜視図である。1 is a perspective view showing an electronic device according to a first embodiment; FIG. 第１実施形態にかかる電子装置を示す平面図である。1 is a plan view showing an electronic device according to a first embodiment; FIG. 図２のＩＩＩ－ＩＩＩ線に沿う断面図である。3 is a cross-sectional view taken along line III-III of FIG. 2; FIG. 図３の一部を拡大した部分拡大断面図である。4 is a partially enlarged sectional view enlarging a part of FIG. 3; FIG. 第１実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the electronic device according to the first embodiment; 第１実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the electronic device according to the first embodiment; 第１実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the electronic device according to the first embodiment; 第１実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the electronic device according to the first embodiment; 第１実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the electronic device according to the first embodiment; 第１実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the electronic device according to the first embodiment; 第１実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the electronic device according to the first embodiment; 第１実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the electronic device according to the first embodiment; 第１実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the electronic device according to the first embodiment; 第１実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the electronic device according to the first embodiment; 第１実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the electronic device according to the first embodiment; 第１実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the electronic device according to the first embodiment; 第１実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the electronic device according to the first embodiment; 第２実施形態にかかる電子装置を示す平面図である。It is a top view which shows the electronic device concerning 2nd Embodiment. 第２実施形態にかかる電子装置を示す平面図である。It is a top view which shows the electronic device concerning 2nd Embodiment. 図１８のＸＸ－ＸＸ線に沿う断面図である。FIG. 19 is a cross-sectional view along line XX-XX of FIG. 18; 図２０の一部を拡大した部分拡大断面図である。FIG. 21 is a partially enlarged sectional view enlarging a part of FIG. 20; 第２実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 10 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the second embodiment; 第２実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 10 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the second embodiment; 第２実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 10 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the second embodiment; 第２実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 10 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the second embodiment; 第２実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 10 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the second embodiment; 第２実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 10 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the second embodiment; 第２実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 10 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the second embodiment; 第２実施形態にかかる電子装置の製造方法の一工程を示す断面図である。FIG. 10 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the second embodiment; 第２実施形態の変形例にかかる電子装置を示す断面図である。FIG. 11 is a cross-sectional view showing an electronic device according to a modification of the second embodiment; 第３実施形態にかかる電子装置を示す断面図である。It is a sectional view showing an electronic device concerning a 3rd embodiment. 本開示の変形例にかかる電子装置を示す断面図である。FIG. 10 is a cross-sectional view showing an electronic device according to a modified example of the present disclosure; 本開示の変形例にかかる電子装置を示す断面図である。FIG. 10 is a cross-sectional view showing an electronic device according to a modified example of the present disclosure; 本開示の変形例にかかる電子装置を示す部分拡大断面図である。FIG. 11 is a partially enlarged cross-sectional view showing an electronic device according to a modification of the present disclosure; 本開示の変形例にかかる電子装置を示す部分拡大断面図である。FIG. 11 is a partially enlarged cross-sectional view showing an electronic device according to a modification of the present disclosure; 本開示の変形例にかかる電子装置を示す部分拡大断面図である。FIG. 11 is a partially enlarged cross-sectional view showing an electronic device according to a modification of the present disclosure; 本開示の変形例にかかる電子装置を示す断面図である。FIG. 10 is a cross-sectional view showing an electronic device according to a modified example of the present disclosure; 本開示の変形例にかかる電子装置を示す断面図である。FIG. 10 is a cross-sectional view showing an electronic device according to a modified example of the present disclosure; 本開示の変形例にかかる電子装置を示す平面図である。FIG. 11 is a plan view showing an electronic device according to a modified example of the present disclosure; 本開示の変形例にかかる電子装置を示す平面図である。FIG. 11 is a plan view showing an electronic device according to a modified example of the present disclosure; 本開示の変形例にかかる電子装置を示す平面図である。FIG. 11 is a plan view showing an electronic device according to a modified example of the present disclosure; 本開示の変形例にかかる電子装置を示す平面図である。FIG. 11 is a plan view showing an electronic device according to a modified example of the present disclosure; 本開示の変形例にかかる電子装置を示す断面図である。FIG. 10 is a cross-sectional view showing an electronic device according to a modified example of the present disclosure; 本開示の変形例にかかる電子装置を示す断面図である。FIG. 10 is a cross-sectional view showing an electronic device according to a modified example of the present disclosure;

本開示の電子装置および本開示の電子装置の製造方法の好ましい実施の形態について、図面を参照して、以下に説明する。 Preferred embodiments of the electronic device of the present disclosure and the method of manufacturing the electronic device of the present disclosure will be described below with reference to the drawings.

本開示における「第１」、「第２」、「第３」等の用語は、単にラベルとして用いたものであり、必ずしもそれらの対象物に順列を付することを意図していない。 The terms "first", "second", "third", etc. in this disclosure are used merely as labels and are not necessarily intended to impose a permutation of the objects.

本開示において、「ある物Ａがある物Ｂに形成されている」および「ある物Ａがある物Ｂ上に形成されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接形成されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに形成されていること」を含む。同様に、「ある物Ａがある物Ｂに配置されている」および「ある物Ａがある物Ｂ上に配置されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接配置されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに配置されていること」を含む。同様に、「ある物Ａがある物Ｂ上に位置している」とは、特段の断りのない限り、「ある物Ａがある物Ｂに接して、ある物Ａがある物Ｂ上に位置していること」、および、「ある物Ａとある物Ｂとの間に他の物が介在しつつ、ある物Ａがある物Ｂ上に位置していること」を含む。同様に、「ある物Ａがある物Ｂに積層されている」および「ある物Ａがある物Ｂ上に積層されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接積層されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに積層されていること」を含む。また、「ある物Ａがある物Ｂにある方向に見て重なる」とは、特段の断りのない限り、「ある物Ａがある物Ｂのすべてに重なること」、および、「ある物Ａがある物Ｂの一部に重なること」を含む。 In the present disclosure, unless otherwise specified, the terms “a certain entity A is formed on a certain entity B” and “a certain entity A is formed on a certain entity B” mean “a certain entity A is formed on a certain entity B”. It includes "being directly formed in entity B" and "being formed in entity B while another entity is interposed between entity A and entity B". Similarly, unless otherwise specified, ``an entity A is placed on an entity B'' and ``an entity A is located on an entity B'' mean ``an entity A is located on an entity B.'' It includes "directly placed on B" and "some entity A is placed on an entity B while another entity is interposed between an entity A and an entity B." Similarly, unless otherwise specified, ``an object A is located on an object B'' means ``an object A is adjacent to an object B and an object A is positioned on an object B. and "the thing A is positioned on the thing B while another thing is interposed between the thing A and the thing B". Similarly, unless otherwise specified, ``an object A is laminated on an object B'' and ``an object A is laminated on an object B'' means ``an object A is laminated on an object B.'' It includes "directly laminated on B" and "a thing A is laminated on a certain thing B while another thing is interposed between the thing A and the thing B". In addition, unless otherwise specified, ``an object A overlaps an object B when viewed in a certain direction'' means ``an object A overlaps all of an object B'' and ``an object A overlaps an object B.'' It includes "overlapping a part of a certain thing B".

＜第１実施形態＞
図１～図４は、第１実施形態にかかる電子装置を示している。第１実施形態の電子装置Ａ１は、電子部品１１、封止樹脂２０、内部電極３０、複数の外部電極４０、複数の接合部５１および枠状導電体６１を備えている。本実施形態において、内部電極３０は、複数の柱状導電体３１および複数の配線層３２を含んでいる。 <First embodiment>
1 to 4 show an electronic device according to a first embodiment. The electronic device A<b>1 of the first embodiment includes an electronic component 11 , a sealing resin 20 , an internal electrode 30 , a plurality of external electrodes 40 , a plurality of joints 51 and a frame-shaped conductor 61 . In this embodiment, the internal electrode 30 includes a plurality of columnar conductors 31 and a plurality of wiring layers 32 .

図１は、電子装置Ａ１を示す斜視図であって、底面側から見たときの状態を示している。図２は、電子装置Ａ１を示す平面図であって、封止樹脂２０を想像線（二点鎖線）で示している。図３は、図２のＩＩＩ－ＩＩＩ線に沿う断面図である。図４は、図３の一部を拡大した部分拡大断面図である。 FIG. 1 is a perspective view showing the electronic device A1, showing a state when viewed from the bottom side. FIG. 2 is a plan view showing the electronic device A1, and shows the sealing resin 20 with an imaginary line (chain double-dashed line). 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. FIG. 4 is a partially enlarged sectional view enlarging a part of FIG.

説明の便宜上、互いに直交する３つの方向を、ｘ方向、ｙ方向、ｚ方向と定義する。ｚ方向は、電子装置Ａ１の厚さ方向である。ｘ方向は、電子装置Ａ１の平面図（図２参照）における左右方向である。ｙ方向は、電子装置Ａ１の平面図（図２参照）における上下方向である。なお、必要に応じて、ｘ方向の一方をｘ１方向、ｘ方向の他方をｘ２方向とする。同様に、ｙ方向の一方をｙ１方向、ｙ方向の他方をｙ２方向とし、ｚ方向の一方をｚ１方向、ｚ方向の他方をｚ２方向とする。また、ｚ１方向を下、ｚ２方向を上という場合もある。ｚ方向が、特許請求の範囲に記載の「第１方向」に相当する。 For convenience of explanation, three mutually orthogonal directions are defined as the x-direction, the y-direction, and the z-direction. The z direction is the thickness direction of the electronic device A1. The x direction is the horizontal direction in the plan view (see FIG. 2) of the electronic device A1. The y direction is the vertical direction in the plan view (see FIG. 2) of the electronic device A1. Note that one of the x directions is defined as the x1 direction, and the other of the x directions is defined as the x2 direction, as required. Similarly, one of the y directions is the y1 direction, the other of the y directions is the y2 direction, one of the z directions is the z1 direction, and the other of the z directions is the z2 direction. In some cases, the z1 direction is referred to as the bottom, and the z2 direction is referred to as the top. The z-direction corresponds to the "first direction" described in claims.

電子部品１１は、電子装置Ａ１の機能中枢となる素子である。本実施形態において、電子部品１１は、半導体を材料とする半導体素子である。電子部品１１は、いわゆる能動素子であって、たとえばＬＳＩ（Large Scale Integration）などの集積回路（ＩＣ）、ＬＤＯ（Low Drop Out）などの電圧制御用素子、オペアンプなどの増幅用素子、あるいは、トランジスタやダイオードなどのディスクリート部品のいずれであってもよい。なお、電子部品１１は、半導体材料を含んでいなくてもよい。このようなものには、いわゆる受動素子であって、たとえば抵抗器、インダクタ、キャパシタなどがある。電子部品１１は、表面実装されうる構造のものである。電子部品１１は、平面視矩形状である。なお、電子部品１１の平面視形状は、特に限定されない。電子部品１１は、複数の接合部５１によって、複数の配線層３２に導通接合されている。電子部品１１が、特許請求の範囲に記載の「第１電子部品」に相当する。電子部品１１は、図３に示すように、素子主面１１１および素子裏面１１２を有する。 The electronic component 11 is an element serving as a functional core of the electronic device A1. In this embodiment, the electronic component 11 is a semiconductor element made of a semiconductor. The electronic component 11 is a so-called active element, for example, an integrated circuit (IC) such as an LSI (Large Scale Integration), a voltage control element such as an LDO (Low Drop Out), an amplification element such as an operational amplifier, or a transistor. or a discrete component such as a diode. Note that the electronic component 11 does not have to contain a semiconductor material. These include so-called passive elements, such as resistors, inductors and capacitors. The electronic component 11 is of a structure that can be surface-mounted. The electronic component 11 has a rectangular shape in plan view. In addition, the planar view shape of the electronic component 11 is not specifically limited. The electronic component 11 is conductively joined to the wiring layers 32 by the joints 51 . The electronic component 11 corresponds to the "first electronic component" recited in the claims. The electronic component 11 has an element main surface 111 and an element back surface 112, as shown in FIG.

素子主面１１１および素子裏面１１２は、ｚ方向において、離間し、かつ、反対側を向く。素子主面１１１は、ｚ２方向を向く。素子裏面１１２は、ｚ１方向を向く。素子裏面１１２には、複数の電極パッド（図示略）が形成されている。当該複数の電極パッドはそれぞれ、たとえばＡｌ（アルミニウム）から構成される。複数の電極パッドは、電子部品１１における端子である。複数の電極パッドの数および位置は、図２に示す態様に限定されない。素子主面１１１および素子裏面１１２が、特許請求の範囲に記載の「第１素子主面」および「第１素子裏面」にそれぞれ相当する。 The element main surface 111 and the element back surface 112 are spaced apart and face opposite sides in the z direction. The element main surface 111 faces the z2 direction. The element back surface 112 faces the z1 direction. A plurality of electrode pads (not shown) are formed on the element back surface 112 . Each of the plurality of electrode pads is made of Al (aluminum), for example. A plurality of electrode pads are terminals in the electronic component 11 . The number and positions of the multiple electrode pads are not limited to the embodiment shown in FIG. The element main surface 111 and the element back surface 112 respectively correspond to the "first element main surface" and the "first element back surface" described in the claims.

封止樹脂２０は、たとえば黒色のエポキシ樹脂を主剤とした合成樹脂である。なお、封止樹脂２０の構成材料は、電気絶縁性を有する樹脂材料であれば、先述のものに限定されない。封止樹脂２０は、図３に示すように、電子部品１１、内部電極３０および複数の接合部５１を覆っている。封止樹脂２０は、図２に示すように、平面視矩形状である。封止樹脂２０は、第１樹脂層２１および第２樹脂層２２を含んでいる。 The sealing resin 20 is a synthetic resin containing, for example, a black epoxy resin as a main component. In addition, the constituent material of the sealing resin 20 is not limited to the above-mentioned materials as long as it is a resin material having electrical insulation. The sealing resin 20 covers the electronic component 11, the internal electrodes 30, and the plurality of joints 51, as shown in FIG. The sealing resin 20 has a rectangular shape in plan view, as shown in FIG. The sealing resin 20 includes a first resin layer 21 and a second resin layer 22 .

第１樹脂層２１は、各柱状導電体３１の一部（後述の柱状導電体側面３１３）を覆っている。第１樹脂層２１は、複数の配線層３２を介して、電子部品１１を支持している。第１樹脂層２１は、電子装置Ａ１において、電子部品１１を支持する支持部材である。第１樹脂層２１は、第１樹脂層主面２１１、第１樹脂層裏面２１２および第１樹脂層側面２１３を有している。 The first resin layer 21 covers a part of each columnar conductor 31 (a columnar conductor side surface 313 to be described later). The first resin layer 21 supports the electronic component 11 via a plurality of wiring layers 32 . The first resin layer 21 is a supporting member that supports the electronic component 11 in the electronic device A1. The first resin layer 21 has a first resin layer main surface 211 , a first resin layer rear surface 212 and a first resin layer side surface 213 .

第１樹脂層主面２１１と第１樹脂層裏面２１２は、ｚ方向において、離間し、かつ、互いに反対側を向く。第１樹脂層主面２１１は、ｚ２方向を向き、第１樹脂層裏面２１２は、ｚ１方向を向く。第１樹脂層主面２１１には、後述する第１樹脂層研削工程によって形成された研削痕が形成されている。本実施形態においては、第１樹脂層裏面２１２から各柱状導電体３１の一部が露出している。第１樹脂層側面２１３は、第１樹脂層主面２１１および第１樹脂層裏面２１２の両方に繋がっている。本実施形態において、第１樹脂層側面２１３は、第１樹脂層主面２１１および第１樹脂層裏面２１２にそれぞれ直交する。第１樹脂層側面２１３は、ｘ方向において離間しかつ互いに反対側を向く一対の面、および、ｙ方向において離間しかつ互いに反対側を向く一対の面を有している。 The first resin layer main surface 211 and the first resin layer back surface 212 are separated from each other in the z direction and face opposite sides. The first resin layer main surface 211 faces the z2 direction, and the first resin layer rear surface 212 faces the z1 direction. Grinding traces are formed on the first resin layer main surface 211 by a first resin layer grinding step, which will be described later. In this embodiment, a part of each columnar conductor 31 is exposed from the back surface 212 of the first resin layer. The first resin layer side surface 213 is connected to both the first resin layer main surface 211 and the first resin layer back surface 212 . In this embodiment, the first resin layer side surface 213 is perpendicular to the first resin layer main surface 211 and the first resin layer rear surface 212, respectively. The first resin layer side surfaces 213 have a pair of surfaces that are spaced apart in the x direction and face opposite to each other, and a pair of surfaces that are spaced apart in the y direction and face opposite to each other.

第２樹脂層２２は、電子部品１１、複数の配線層３２、および、枠状導電体６１の一部を覆っている。第２樹脂層２２は、電子装置Ａ１において、電子部品１１を保護する保護部材である。第２樹脂層２２は、第２樹脂層主面２２１、第２樹脂層裏面２２２および第２樹脂層側面２２３を有している。 The second resin layer 22 covers the electronic component 11 , the plurality of wiring layers 32 , and part of the frame-shaped conductor 61 . The second resin layer 22 is a protective member that protects the electronic component 11 in the electronic device A1. The second resin layer 22 has a second resin layer main surface 221 , a second resin layer rear surface 222 and a second resin layer side surface 223 .

第２樹脂層主面２２１と第２樹脂層裏面２２２は、ｚ方向において、離間し、かつ、互いに反対側を向く。第２樹脂層主面２２１は、ｚ２方向を向き、第２樹脂層裏面２２２は、ｚ１方向を向く。第２樹脂層主面２２１には、後述する第２樹脂層研削工程によって形成された研削痕が形成されている。本実施形態においては、第２樹脂層主面２２１から枠状導電体６１の一部が露出している。第２樹脂層側面２２３は、第２樹脂層主面２２１および第２樹脂層裏面２２２の両方に繋がっている。本実施形態においては、第２樹脂層側面２２３は、第２樹脂層主面２２１および第２樹脂層裏面２２２にそれぞれ直交する。第２樹脂層側面２２３は、ｘ方向において離間しかつ互いに反対側を向く一対の面、および、ｙ方向において離間しかつ互いに反対側を向く一対の面を有している。 The second resin layer main surface 221 and the second resin layer back surface 222 are separated from each other and face opposite sides in the z-direction. The second resin layer main surface 221 faces the z2 direction, and the second resin layer rear surface 222 faces the z1 direction. Grinding traces are formed on the second resin layer main surface 221 by a second resin layer grinding step, which will be described later. In this embodiment, a portion of the frame-shaped conductor 61 is exposed from the second resin layer main surface 221 . The second resin layer side surface 223 is connected to both the second resin layer main surface 221 and the second resin layer back surface 222 . In the present embodiment, the second resin layer side surface 223 is perpendicular to the second resin layer main surface 221 and the second resin layer rear surface 222, respectively. The second resin layer side surfaces 223 have a pair of surfaces that are spaced apart in the x direction and face opposite to each other, and a pair of surfaces that are spaced apart in the y direction and face opposite to each other.

封止樹脂２０において、第１樹脂層２１と第２樹脂層２２とはｚ方向に積層されており、第１樹脂層主面２１１と第２樹脂層裏面２２２とが接している。また、封止樹脂２０において、第１樹脂層側面２１３と第２樹脂層側面２２３とは面一である。 In the sealing resin 20, the first resin layer 21 and the second resin layer 22 are laminated in the z-direction, and the first resin layer main surface 211 and the second resin layer rear surface 222 are in contact with each other. Moreover, in the sealing resin 20, the first resin layer side surface 213 and the second resin layer side surface 223 are flush with each other.

内部電極３０は、封止樹脂２０の内部において、電子部品１１と複数の外部電極４０との導通経路をなす。内部電極３０は、先述の通り、複数の柱状導電体３１および複数の配線層３２を含んでいる。 The internal electrodes 30 form conduction paths between the electronic component 11 and the plurality of external electrodes 40 inside the sealing resin 20 . The internal electrode 30 includes a plurality of columnar conductors 31 and a plurality of wiring layers 32 as described above.

複数の柱状導電体３１の各々は、ｚ方向において、各配線層３２と各外部電極４０との間に介在し、これらを導通させる。各柱状導電体３１は、第１樹脂層２１をｚ方向に貫通している。本実施形態において、各柱状導電体３１は、柱状であって、ｚ方向に直交する断面が略矩形である。なお、当該断面は、矩形に限定されず、円形、楕円形、あるいは、多角形などであってもよい。各柱状導電体３１の構成材料は、たとえばＣｕ（銅）である。なお、各柱状導電体３１は、たとえば、互いに積層された下地層およびめっき層を含んで構成されていてもよい。下地層は、互いに積層されたＴｉ（チタン）層およびＣｕ層から構成され、その厚みは２００～８００ｎｍ程度である。めっき層は、たとえばＣｕを含んでおり、下地層よりも厚く設定されている。複数の柱状導電体３１は、たとえば電解めっきにより形成される。各柱状導電体３１の構成材料および形成方法は、これに限定されない。複数の柱状導電体３１は、互いに離間して配置されている。柱状導電体３１が、特許請求の範囲に記載の「第１導電体」に相当する。各柱状導電体３１は、柱状導電体主面３１１、柱状導電体裏面３１２および柱状導電体側面３１３を有している。 Each of the plurality of columnar conductors 31 is interposed between each wiring layer 32 and each external electrode 40 in the z-direction to electrically connect them. Each columnar conductor 31 penetrates the first resin layer 21 in the z direction. In the present embodiment, each columnar conductor 31 has a columnar shape and a substantially rectangular cross section perpendicular to the z-direction. Note that the cross section is not limited to a rectangle, and may be circular, elliptical, or polygonal. The constituent material of each columnar conductor 31 is, for example, Cu (copper). Note that each columnar conductor 31 may include, for example, a base layer and a plated layer that are laminated to each other. The underlying layer is composed of a Ti (titanium) layer and a Cu layer laminated to each other, and has a thickness of about 200 to 800 nm. The plated layer contains Cu, for example, and is set thicker than the underlying layer. The plurality of columnar conductors 31 are formed by electrolytic plating, for example. The constituent material and formation method of each columnar conductor 31 are not limited to this. The plurality of columnar conductors 31 are arranged apart from each other. The columnar conductor 31 corresponds to the "first conductor" recited in the claims. Each columnar conductor 31 has a columnar conductor main surface 311 , a columnar conductor back surface 312 and a columnar conductor side surface 313 .

柱状導電体主面３１１および柱状導電体裏面３１２は、ｚ方向において、離間し、かつ、互いに反対側を向く。柱状導電体主面３１１は、第１樹脂層主面２１１から露出している。本実施形態においては、柱状導電体主面３１１は、第１樹脂層主面２１１から窪んでいる。この窪みの深さ（ｚ方向寸法）は、１μｍ程度である。なお、柱状導電体主面３１１と第１樹脂層主面２１１とが面一であってもよい。柱状導電体裏面３１２は、第１樹脂層裏面２１２から露出している。柱状導電体裏面３１２は、第１樹脂層裏面２１２と面一である。柱状導電体主面３１１は、配線層３２に接している。これにより、柱状導電体３１と配線層３２とが導通する。柱状導電体裏面３１２は、外部電極４０に接している。これにより、柱状導電体３１と外部電極４０とが導通する。柱状導電体側面３１３は、柱状導電体主面３１１および柱状導電体裏面３１２の両方に繋がっている。柱状導電体側面３１３は、柱状導電体主面３１１および柱状導電体裏面３１２にそれぞれ直交する。柱状導電体側面３１３は、第１樹脂層２１に接している。本実施形態において、柱状導電体側面３１３は、ｘ方向において離間しかつ互いに反対側を向く一対の面、および、ｙ方向において離間しかつ互いに反対側を向く一対の面を有している。柱状導電体主面３１１および柱状導電体裏面３１２が、特許請求の範囲に記載の「第１導電体主面」および「第１導電体裏面」にそれぞれ相当する。 The columnar conductor main surface 311 and the columnar conductor back surface 312 are separated from each other in the z-direction and face opposite sides. The columnar conductor main surface 311 is exposed from the first resin layer main surface 211 . In this embodiment, the columnar conductor main surface 311 is recessed from the first resin layer main surface 211 . The depth (dimension in the z direction) of this depression is about 1 μm. Note that the columnar conductor main surface 311 and the first resin layer main surface 211 may be flush with each other. The columnar conductor back surface 312 is exposed from the first resin layer back surface 212 . The columnar conductor back surface 312 is flush with the first resin layer back surface 212 . The columnar conductor main surface 311 is in contact with the wiring layer 32 . Thereby, the columnar conductor 31 and the wiring layer 32 are electrically connected. The columnar conductor back surface 312 is in contact with the external electrode 40 . Thereby, the columnar conductors 31 and the external electrodes 40 are electrically connected. The columnar conductor side surface 313 is connected to both the columnar conductor main surface 311 and the columnar conductor rear surface 312 . The columnar conductor side surface 313 is orthogonal to the columnar conductor main surface 311 and the columnar conductor rear surface 312 respectively. The columnar conductor side surface 313 is in contact with the first resin layer 21 . In this embodiment, the columnar conductor side surfaces 313 have a pair of surfaces that are spaced apart in the x direction and face opposite to each other, and a pair of surfaces that are spaced apart in the y direction and face opposite to each other. The columnar conductor principal surface 311 and the columnar conductor rear surface 312 respectively correspond to the "first conductor principal surface" and the "first conductor rear surface" described in the claims.

複数の配線層３２の各々は、各柱状導電体主面３１１と第１樹脂層主面２１１とに跨って形成されている。本実施形態においては、各配線層３２は、各柱状導電体３１の柱状導電体主面３１１の全面と第１樹脂層主面２１１の一部とを覆っている。複数の配線層３２は、互いに離間して配置されている。各配線層３２は、互いに積層された下地層およびめっき層を含んで構成される。下地層は、互いに積層されたＴｉ層およびＣｕ層から構成され、その厚みは２００～８００ｎｍ程度である。下地層は、たとえばスパッタリングにより形成されうる。めっき層は、たとえばＣｕを含んでおり、下地層よりも厚く設定されている。めっき層は、たとえば電解めっきにより形成されうる。なお、各配線層３２の構成材料および形成方法は、先述のものに限定されない。たとえば、下地層とめっき層との間にＮｉ層が形成されていてもよい。当該Ｎｉ層は、たとえば電解めっきにより形成されうる。また、各配線層３２の形成範囲は、図２に示す態様に限定されない。 Each of the plurality of wiring layers 32 is formed across each columnar conductor main surface 311 and the first resin layer main surface 211 . In this embodiment, each wiring layer 32 covers the entire columnar conductor main surface 311 of each columnar conductor 31 and part of the first resin layer main surface 211 . The plurality of wiring layers 32 are arranged apart from each other. Each wiring layer 32 includes an underlying layer and a plated layer that are laminated to each other. The underlying layer is composed of a Ti layer and a Cu layer laminated to each other, and has a thickness of about 200 to 800 nm. The underlayer can be formed, for example, by sputtering. The plated layer contains Cu, for example, and is set thicker than the underlying layer. The plated layer can be formed, for example, by electrolytic plating. Note that the constituent material and formation method of each wiring layer 32 are not limited to those described above. For example, a Ni layer may be formed between the underlying layer and the plating layer. The Ni layer can be formed, for example, by electrolytic plating. Also, the formation range of each wiring layer 32 is not limited to the mode shown in FIG.

各配線層３２は、配線層主面３２１および配線層裏面３２２を有している。配線層主面３２１および配線層裏面３２２は、ｚ方向において、離間し、かつ、互いに反対側を向く。配線層主面３２１は、ｚ２方向を向き、配線層裏面３２２は、ｚ１方向を向く。配線層主面３２１は、第２樹脂層２２に接している。配線層裏面３２２は、第１樹脂層２１に接している。また、各配線層３２において、ｘ方向あるいはｙ方向を向く端面は、第２樹脂層２２に覆われている。 Each wiring layer 32 has a wiring layer main surface 321 and a wiring layer back surface 322 . The wiring layer main surface 321 and the wiring layer back surface 322 are separated from each other in the z direction and face opposite sides. The wiring layer main surface 321 faces the z2 direction, and the wiring layer back surface 322 faces the z1 direction. The wiring layer main surface 321 is in contact with the second resin layer 22 . The wiring layer back surface 322 is in contact with the first resin layer 21 . Moreover, in each wiring layer 32 , the end face facing the x direction or the y direction is covered with the second resin layer 22 .

各配線層３２は、各配線層主面３２１からｚ方向に窪んだ凹部３２１ａを含んでいる。凹部３２１ａは、平面視において、柱状導電体３１に重なる。なお、柱状導電体主面３１１と第１樹脂層主面２１１とが面一である場合には、凹部３２１ａは形成されていない。 Each wiring layer 32 includes a recess 321a recessed in the z-direction from each wiring layer main surface 321 . The recess 321a overlaps the columnar conductor 31 in plan view. When the columnar conductor main surface 311 and the first resin layer main surface 211 are flush with each other, the recess 321a is not formed.

複数の外部電極４０の各々は、複数の内部電極３０の各々にそれぞれ１つずつ導通しており、かつ、電子装置Ａ１の外部に露出した導電体である。各外部電極４０は、電子装置Ａ１を電子機器などの回路基板に実装する際の端子となる。複数の外部電極４０は、無電解めっきにより形成されている。本実施形態においては、各外部電極４０は、互いに積層されたＮｉ（ニッケル）層、Ｐｄ（パラジウム）層およびＡｕ（金）層を含んで構成される。各外部電極４０のｚ方向寸法は、特に限定されないが、たとえば３～１０μｍ程度である。なお、外部電極４０のｚ方向寸法、構成材料および形成方法は、先述のものに限定されない。たとえば、各外部電極４０は、Ｎｉ層およびＡｕ層が積層されて構成されていてもよいし、Ｓｎ（スズ）であってもよい。 Each of the plurality of external electrodes 40 is a conductor that is electrically connected to each of the plurality of internal electrodes 30 and exposed to the outside of the electronic device A1. Each external electrode 40 serves as a terminal when the electronic device A1 is mounted on a circuit board such as an electronic device. The plurality of external electrodes 40 are formed by electroless plating. In this embodiment, each external electrode 40 includes a Ni (nickel) layer, a Pd (palladium) layer, and an Au (gold) layer that are laminated together. The z-direction dimension of each external electrode 40 is not particularly limited, but is, for example, about 3 to 10 μm. Note that the z-direction dimension, constituent material, and formation method of the external electrode 40 are not limited to those described above. For example, each external electrode 40 may be configured by stacking a Ni layer and an Au layer, or may be made of Sn (tin).

各外部電極４０は、封止樹脂２０から露出している。各外部電極４０は、第１樹脂層２１よりもｚ１方向側に配置されている。よって、各外部電極４０は、電子装置Ａ１の底面側に配置されている。本実施形態においては、各外部電極４０は、各柱状導電体３１に導通している。複数の外部電極４０は、複数の柱状導電体被覆部４１を含んでいる。 Each external electrode 40 is exposed from the sealing resin 20 . Each external electrode 40 is arranged on the z1 direction side of the first resin layer 21 . Therefore, each external electrode 40 is arranged on the bottom side of the electronic device A1. In this embodiment, each external electrode 40 is electrically connected to each columnar conductor 31 . The multiple external electrodes 40 include multiple columnar conductor covering portions 41 .

各柱状導電体被覆部４１は、各柱状導電体裏面３１２を覆っている。各柱状導電体被覆部４１は、各柱状導電体裏面３１２に接する。本実施形態において、電子部品１１は、各接合部５１、各配線層３２および各柱状導電体３１を介して、各柱状導電体被覆部４１に導通している。よって、複数の柱状導電体被覆部４１の各々は、電子部品１１に導通する、電子装置Ａ１の端子である。柱状導電体被覆部４１が、特許請求の範囲に記載の「第１導電体被覆部」に相当する。 Each columnar conductor covering portion 41 covers each columnar conductor rear surface 312 . Each columnar conductor covering portion 41 is in contact with each columnar conductor rear surface 312 . In this embodiment, the electronic component 11 is electrically connected to each columnar conductor covering portion 41 via each joint portion 51 , each wiring layer 32 and each columnar conductor 31 . Therefore, each of the plurality of columnar conductor covering portions 41 is a terminal of the electronic device A1 that conducts to the electronic component 11 . The columnar conductor covering portion 41 corresponds to the “first conductor covering portion” recited in the claims.

複数の接合部５１の各々は、電子部品１１（詳細には、先述の各電極パッド）と各配線層３２との間に介在する導電性接合材である。電子部品１１は、複数の接合部５１により複数の配線層３２に固着され、各配線層３２に搭載された構成となっている。あわせて、複数の接合部５１により、電子部品１１と複数の配線層３２との導通が確保される。本実施形態においては、各接合部５１は、図４に示すように、絶縁層５１１および接合層５１２を含んでいる。 Each of the plurality of joint portions 51 is a conductive joint material interposed between the electronic component 11 (specifically, each electrode pad described above) and each wiring layer 32 . The electronic component 11 is fixed to the plurality of wiring layers 32 by the plurality of bonding portions 51 and mounted on each wiring layer 32 . In addition, conduction between the electronic component 11 and the wiring layers 32 is ensured by the plurality of joints 51 . In this embodiment, each joint 51 includes an insulating layer 511 and a joint layer 512, as shown in FIG.

各絶縁層５１１は、図４に示すように、各配線層３２の上にそれぞれに形成されている。各絶縁層５１１は、平面視において、中央に開口した枠状である。各絶縁層５１１は、平面視において、各接合層５１２を囲んでいる。本実施形態において、各絶縁層５１１は、平面視において矩形環状を呈する。なお、各絶縁層５１１の平面視形状は、矩形環状に限定されず、円環状、楕円環状あるいは多角環状であってもよい。各絶縁層５１１の構成材料は、たとえばポリイミド樹脂であるが、これに限定されない。 Each insulating layer 511 is formed on each wiring layer 32, as shown in FIG. Each insulating layer 511 has a frame shape with an opening in the center in plan view. Each insulating layer 511 surrounds each bonding layer 512 in plan view. In this embodiment, each insulating layer 511 has a rectangular annular shape in plan view. The shape of each insulating layer 511 in plan view is not limited to a rectangular ring, and may be a circular ring, an elliptical ring, or a polygonal ring. The constituent material of each insulating layer 511 is, for example, polyimide resin, but is not limited to this.

各接合層５１２は、電子部品１１と各配線層３２とを導通接合する。各接合層５１２は、各配線層３２（配線層主面３２１）の上に形成されている。各接合層５１２は、各絶縁層５１１の開口した部分の表面を覆っている。各接合層５１２は、一部が各絶縁層５１１の開口部分に充填されている。本実施形態においては、各接合層５１２は、図４に示すように、互いに積層された第１層５１２ａ、第２層５１２ｂおよび第３層５１２ｃから構成される。 Each bonding layer 512 electrically connects the electronic component 11 and each wiring layer 32 . Each bonding layer 512 is formed on each wiring layer 32 (wiring layer main surface 321). Each bonding layer 512 covers the surface of the opening of each insulating layer 511 . Each bonding layer 512 partially fills the opening of each insulating layer 511 . In this embodiment, each bonding layer 512 is composed of a first layer 512a, a second layer 512b, and a third layer 512c laminated together, as shown in FIG.

第１層５１２ａは、各配線層３２（配線層主面３２１）の上に形成され、各配線層主面３２１に接する。第１層５１２ａの構成材料は、たとえばＣｕを含む金属である。第２層５１２ｂは、第１層５１２ａの上に形成され、第１層５１２ａに接する。第２層５１２ｂの構成材料は、たとえばＮｉを含む金属である。第３層５１２ｃは、第２層５１２ｂの上に形成され、第２層５１２ｂに接する。また、第３層５１２ｃは、電子部品１１（先述の電極パッド）に接する。第３層５１２ｃの構成材料は、たとえばＳｎを含む合金である。この合金を例示すると、Ｓｎ－Ｓｂ系合金またはＳｎ－Ａｇ系合金などの鉛フリーはんだである。接合層５１２が、特許請求の範囲に記載の「導電性接合層」に相当する。 The first layer 512 a is formed on each wiring layer 32 (wiring layer main surface 321 ) and is in contact with each wiring layer main surface 321 . A constituent material of the first layer 512a is, for example, a metal containing Cu. The second layer 512b is formed on and contacts the first layer 512a. The constituent material of the second layer 512b is, for example, a metal containing Ni. A third layer 512c is formed on and in contact with the second layer 512b. Also, the third layer 512c is in contact with the electronic component 11 (the electrode pads described above). The constituent material of the third layer 512c is, for example, an alloy containing Sn. Examples of this alloy are lead-free solders such as Sn--Sb based alloys or Sn--Ag based alloys. The bonding layer 512 corresponds to the "conductive bonding layer" described in claims.

枠状導電体６１は、平面視において、電子部品１１の周囲に配置されている。本実施形態においては、枠状導電体６１は、平面視において、電子部品１１を包囲している。枠状導電体６１は、平面視形状が矩形環状である。なお、枠状導電体６１の平面視形状は、特に限定されず、円環状、楕円環状、あるいは、多角環状などであってもよい。枠状導電体６１と電子部品１１との間には、第２樹脂層２２の一部が介在している。枠状導電体６１は、第１樹脂層２１の上に形成され、第１樹脂層主面２１１から起立している。本実施形態においては、枠状導電体６１は、内部電極３０から離間している。枠状導電体６１が、特許請求の範囲に記載の「第２導電体」に相当する。 The frame-shaped conductor 61 is arranged around the electronic component 11 in plan view. In this embodiment, the frame-shaped conductor 61 surrounds the electronic component 11 in plan view. The frame-shaped conductor 61 has a rectangular annular shape in plan view. The planar shape of the frame-shaped conductor 61 is not particularly limited, and may be a circular ring, an elliptical ring, or a polygonal ring. A portion of the second resin layer 22 is interposed between the frame-shaped conductor 61 and the electronic component 11 . The frame-shaped conductor 61 is formed on the first resin layer 21 and stands up from the main surface 211 of the first resin layer. In this embodiment, the frame-shaped conductor 61 is separated from the internal electrode 30 . The frame-shaped conductor 61 corresponds to the "second conductor" described in the claims.

枠状導電体６１は、たとえば、互いに積層された下地層およびめっき層を含んで構成されている。下地層は、互いに積層されたＴｉ層およびＣｕ層から構成され、その厚みは２００～８００ｎｍ程度である。めっき層は、主な成分がＣｕであり、下地層よりも厚く設定されている。枠状導電体６１は、たとえば電解めっきにより形成される。なお、枠状導電体６１の構成材料および形成方法は、先述のものに限定されない。 Frame-shaped conductor 61 includes, for example, an underlying layer and a plated layer that are laminated to each other. The underlying layer is composed of a Ti layer and a Cu layer laminated to each other, and has a thickness of about 200 to 800 nm. The plating layer is mainly composed of Cu and is set thicker than the underlying layer. Frame-shaped conductor 61 is formed, for example, by electrolytic plating. The constituent material and formation method of the frame-shaped conductor 61 are not limited to those described above.

枠状導電体６１は、内面６１１、外面６１２および頂面６１３を有している。内面６１１は、平面視における枠状導電体６１の内周によって形成される面である。内面６１１は、電子部品１１に対向する。外面６１２は、平面視における枠状導電体６１の外周によって形成される面である。頂面６１３は、ｘ２方向を向く面である。頂面６１３は、第２樹脂層２２から露出している。頂面６１３は、第２樹脂層２２の第２樹脂層主面２２１から窪んでいる。この窪みの深さ（ｚ方向寸法）は、１μｍ程度である。なお、頂面６１３が、第２樹脂層主面２２１と面一であってもよい。また、頂面６１３は、第２樹脂層２２に覆われていてもよい。本実施形態においては、頂面６１３は、ｚ方向において、素子主面１１１よりもｚ２方向に位置する。頂面６１３が、特許請求の範囲に記載の「第２導電体主面」に相当する。 The frame-shaped conductor 61 has an inner surface 611 , an outer surface 612 and a top surface 613 . The inner surface 611 is a surface formed by the inner circumference of the frame-shaped conductor 61 in plan view. The inner surface 611 faces the electronic component 11 . The outer surface 612 is a surface formed by the outer periphery of the frame-shaped conductor 61 in plan view. The top surface 613 is a surface facing the x2 direction. The top surface 613 is exposed from the second resin layer 22 . The top surface 613 is recessed from the second resin layer main surface 221 of the second resin layer 22 . The depth (dimension in the z direction) of this depression is about 1 μm. Note that the top surface 613 may be flush with the second resin layer main surface 221 . Also, the top surface 613 may be covered with the second resin layer 22 . In this embodiment, the top surface 613 is positioned in the z2 direction from the element main surface 111 in the z direction. The top surface 613 corresponds to the "second conductor main surface" described in the claims.

次に、第１実施形態にかかる電子装置Ａ１の製造方法の一例について、図５～図１７を参照して、説明する。以下に示す製造方法は、複数の電子装置Ａ１を製造する場合を示す。図５～図１７は、電子装置Ａ１の製造方法にかかる一工程を示す断面図である。 Next, an example of a method for manufacturing the electronic device A1 according to the first embodiment will be described with reference to FIGS. 5 to 17. FIG. The manufacturing method shown below shows the case of manufacturing a plurality of electronic devices A1. 5 to 17 are cross-sectional views showing one step in the method of manufacturing the electronic device A1.

まず、図５に示すように、支持基板８００を用意する。支持基板８００は、単結晶材料である半導体材料からなり、本実施形態においては、Ｓｉの単結晶材料である。支持基板８００を用意する工程（支持基板用意工程）では、支持基板８００として、たとえばＳｉウエハを用意する。本実施形態における支持基板８００の厚さは、たとえば７２５～７７５μｍ程度である。支持基板８００は、ｚ方向において、離間しかつ互いに反対側を向く支持基板主面８０１および支持基板裏面８０２を有する。支持基板主面８０１は、ｚ２方向を向き、支持基板裏面８０２は、ｚ１方向を向く。なお、用意する支持基板８００は、Ｓｉウエハに限定されず、たとえば、ガラス基板であってもよい。 First, as shown in FIG. 5, a support substrate 800 is prepared. The support substrate 800 is made of a semiconductor material that is a single crystal material, and in this embodiment is a single crystal material of Si. In the step of preparing the support substrate 800 (support substrate preparation step), a Si wafer, for example, is prepared as the support substrate 800 . The thickness of the support substrate 800 in this embodiment is, for example, about 725 to 775 μm. The support substrate 800 has a support substrate main surface 801 and a support substrate back surface 802 which are separated from each other and face opposite sides in the z-direction. The support substrate main surface 801 faces the z2 direction, and the support substrate back surface 802 faces the z1 direction. Note that the support substrate 800 to be prepared is not limited to a Si wafer, and may be, for example, a glass substrate.

次いで、図５に示すように、支持基板８００の上に柱状導電体８３１を形成する。柱状導電体８３１は、電子装置Ａ１の柱状導電体３１に対応する。柱状導電体８３１を形成する工程（柱状導電体形成工程）においては、まず、支持基板主面８０１に接する下地層を形成する。この下地層の形成は、スパッタリング法による。本実施形態においては、支持基板主面８０１に接するＴｉ層を形成した後、Ｔｉ層に接するＣｕ層を形成する。よって、下地層は、互いに積層されたＴｉ層およびＣｕ層から形成される。本実施形態においては、Ｔｉ層の厚さは１０～３０ｎｍ程度であり、Ｃｕ層の厚さは２００～８００ｎｍ程度である。なお、下地層の構成材料および厚さは先述のものに限定されない。続いて、下地層に接するめっき層を形成する。めっき層の形成は、フォトリソグラフィによるレジストパターンの形成および電解めっきによる。具体的には、下地層の全面を覆うように、感光性レジストを塗布し、この感光性レジストに対して露光・現像を行う。これにより、パターニングされたレジスト層（以下、「レジストパターン」という）を形成する。感光性レジストは、たとえばスピンコータを用いて塗布されるが、これに限定されない。このとき、レジストパターンから下地層の一部が露出する。続いて、下地層を導電経路として電解めっきを行う。これにより、レジストパターンから露出した下地層にめっき層が析出される。本実施形態にかかるめっき層の構成材料は、たとえばＣｕである。めっき層を形成した後は、レジストパターンを除去する。以上の工程により、図５に示す柱状導電体８３１が形成される。本実施形態においては、柱状導電体形成工程が、特許請求の範囲に記載の「第１導電体形成工程」に相当する。 Next, as shown in FIG. 5, columnar conductors 831 are formed on the support substrate 800 . The columnar conductor 831 corresponds to the columnar conductor 31 of the electronic device A1. In the step of forming the columnar conductors 831 (columnar conductor forming step), first, a base layer in contact with the main surface 801 of the support substrate is formed. The formation of this underlayer is based on the sputtering method. In this embodiment, after forming a Ti layer in contact with the main surface 801 of the supporting substrate, a Cu layer is formed in contact with the Ti layer. Therefore, the underlayer is formed from the Ti layer and the Cu layer laminated to each other. In this embodiment, the thickness of the Ti layer is about 10-30 nm, and the thickness of the Cu layer is about 200-800 nm. The constituent material and thickness of the underlayer are not limited to those described above. Subsequently, a plated layer is formed in contact with the underlying layer. The plating layer is formed by forming a resist pattern by photolithography and electroplating. Specifically, a photosensitive resist is applied so as to cover the entire surface of the underlying layer, and the photosensitive resist is exposed and developed. Thereby, a patterned resist layer (hereinafter referred to as "resist pattern") is formed. The photosensitive resist is applied using, for example, a spin coater, but is not limited to this. At this time, part of the underlying layer is exposed from the resist pattern. Subsequently, electrolytic plating is performed using the underlying layer as a conductive path. As a result, a plating layer is deposited on the underlying layer exposed from the resist pattern. A constituent material of the plating layer according to the present embodiment is, for example, Cu. After forming the plating layer, the resist pattern is removed. Through the above steps, the columnar conductors 831 shown in FIG. 5 are formed. In this embodiment, the columnar conductor forming step corresponds to the "first conductor forming step" described in the claims.

次いで、図６に示すように、柱状導電体８３１を覆う第１樹脂層８２１を形成する。第１樹脂層８２１を形成する工程（第１樹脂層形成工程）では、たとえばモールド成型による。本実施形態においては、第１樹脂層８２１は、電気絶縁性を有しており、たとえば黒色のエポキシ樹脂を主剤とした合成樹脂である。第１樹脂層形成工程によって、柱状導電体８３１は、第１樹脂層８２１で完全に覆われる。よって、第１樹脂層８２１のｚ２方向を向く面（第１樹脂層主面８２１ａ）は、柱状導電体８３１のｚ２方向を向く面よりも、ｚ２方向に位置する。 Next, as shown in FIG. 6, a first resin layer 821 is formed to cover the columnar conductors 831 . In the step of forming the first resin layer 821 (first resin layer forming step), for example, molding is performed. In this embodiment, the first resin layer 821 has electrical insulation, and is made of a synthetic resin containing, for example, a black epoxy resin as a main component. The columnar conductors 831 are completely covered with the first resin layer 821 by the first resin layer forming step. Therefore, the surface of the first resin layer 821 facing the z2 direction (the first resin layer main surface 821a) is located in the z2 direction relative to the surface of the columnar conductor 831 facing the z2 direction.

次いで、図７に示すように、第１樹脂層８２１を研削する。第１樹脂層８２１を研削する工程（第１樹脂層研削工程）では、たとえば機械研削盤を用いる。なお、第１樹脂層８２１の研削は、機械研削盤を用いた研削に限定されない。本実施形態においては、第１樹脂層８２１を、第１樹脂層主面８２１ａからｚ１方向に、砥石で削る。このとき、柱状導電体８３１が露出するまで、第１樹脂層８２１を研削する。第１樹脂層研削工程によって、第１樹脂層主面８２１ａがｚ１方向に移動し、柱状導電体８３１のｚ２方向を向く面（柱状導電体主面８３１ａ）が、第１樹脂層８２１（第１樹脂層主面８２１ａ）から露出する。また、第１樹脂層主面８２１ａには、砥石で削られた痕である研削痕が形成される。本実施形態においては、当該研削痕は、第１樹脂層主面８２１ａから柱状導電体主面８３１ａに跨って形成される。本実施形態においては、第１樹脂層８２１の研削の際、柱状導電体８３１も少し研削している。なお、研削後においては、柱状導電体８３１と第１樹脂層８２１との材質の違いにより、柱状導電体主面８３１ａにバリが生じうる。そのため、本実施形態においては、バリ除去のために薬液処理を行う。これにより、柱状導電体主面８３１ａが、第１樹脂層主面８２１ａよりもｚ方向に窪んでいる。 Next, as shown in FIG. 7, the first resin layer 821 is ground. In the step of grinding first resin layer 821 (first resin layer grinding step), for example, a mechanical grinder is used. The grinding of the first resin layer 821 is not limited to grinding using a mechanical grinder. In this embodiment, the first resin layer 821 is ground with a whetstone from the first resin layer main surface 821a in the z1 direction. At this time, the first resin layer 821 is ground until the columnar conductors 831 are exposed. By the first resin layer grinding step, the first resin layer main surface 821a moves in the z1 direction, and the surface of the columnar conductor 831 facing the z2 direction (the columnar conductor main surface 831a) becomes the first resin layer 821 (first It is exposed from the resin layer main surface 821a). Grinding traces, which are traces of grinding with a whetstone, are formed on the first resin layer main surface 821a. In this embodiment, the grinding marks are formed across the first resin layer main surface 821a and the columnar conductor main surface 831a. In this embodiment, when the first resin layer 821 is ground, the columnar conductors 831 are also slightly ground. After grinding, burrs may occur on the main surface 831a of the columnar conductor due to the material difference between the columnar conductor 831 and the first resin layer 821 . Therefore, in the present embodiment, chemical treatment is performed to remove burrs. As a result, the columnar conductor main surface 831a is recessed in the z direction from the first resin layer main surface 821a.

次いで、図８～図１２に示すように、配線層８３２、接合部８５１および枠状導電体８６１を形成する。配線層８３２、接合部８５１および枠状導電体８６１が、電子装置Ａ１の配線層３２、接合部５１および枠状導電体６１にそれぞれ対応する。これらを形成する工程には、次に示す５つの工程がある。 Next, as shown in FIGS. 8 to 12, wiring layers 832, joints 851 and frame-shaped conductors 861 are formed. The wiring layer 832, the joint portion 851 and the frame-shaped conductor 861 correspond to the wiring layer 32, the joint portion 51 and the frame-shaped conductor 61 of the electronic device A1, respectively. The process of forming these includes the following five processes.

１つ目の工程では、図８に示すように、下地層８９０ａを形成する。下地層８９０ａの形成は、たとえばスパッタリング法による。下地層８９０ａを形成する工程では、第１樹脂層主面８２１ａの全面および柱状導電体主面８３１ａの全面を覆うＴｉ層を形成した後、Ｔｉ層に接するＣｕ層を形成する。下地層８９０ａは、互いに積層されたＴｉ層およびＣｕ層から形成される。 In the first step, as shown in FIG. 8, an underlying layer 890a is formed. Underlying layer 890a is formed by sputtering, for example. In the step of forming the base layer 890a, after forming a Ti layer covering the entire surface of the first resin layer main surface 821a and the entire surface of the columnar conductor main surface 831a, a Cu layer is formed in contact with the Ti layer. The underlying layer 890a is formed of a Ti layer and a Cu layer laminated together.

２つ目の工程では、図９に示すように、めっき層８９０ｂを形成する。めっき層８９０ｂの形成は、たとえば、フォトリソグラフィによるレジストパターンの形成および電解めっきによる。めっき層８９０ｂを形成する工程では、下地層８９０ａの全面を覆うように、感光性レジストを塗布して、当該感光性レジストに対して露光および現像を行うことによって、レジスト層のパターニングを行う。これにより、レジストパターンが形成され、下地層８９０ａの一部（めっき層８９０ｂを形成する部分）が当該レジストパターンから露出する。続いて、下地層８９０ａを導電経路とした電解めっきにより、レジストパターンから露出する下地層８９０ａの上にめっき層８９０ｂを析出させる。本実施形態においては、めっき層８９０ｂとして、たとえばＣｕを含む金属層を析出させる。このとき、めっき層８９０ｂは、下地層８９０ａと一体的に形成される。その後、本工程において形成したレジストパターンを除去する。これにより、図９に示すめっき層８９０ｂが形成される。このめっき層８９０ｂとめっき層８９０ｂに覆われた下地層８９０ａが、後に、配線層８３２となる。配線層８３２は、電子装置Ａ１の配線層３２に対応する。 In the second step, as shown in FIG. 9, a plating layer 890b is formed. The plating layer 890b is formed by forming a resist pattern by photolithography and electroplating, for example. In the step of forming the plating layer 890b, a photosensitive resist is applied so as to cover the entire surface of the base layer 890a, and the resist layer is patterned by exposing and developing the photosensitive resist. As a result, a resist pattern is formed, and a portion of the underlying layer 890a (the portion forming the plating layer 890b) is exposed from the resist pattern. Subsequently, a plating layer 890b is deposited on the underlying layer 890a exposed from the resist pattern by electroplating using the underlying layer 890a as a conductive path. In this embodiment, a metal layer containing Cu, for example, is deposited as the plating layer 890b. At this time, the plating layer 890b is formed integrally with the underlying layer 890a. After that, the resist pattern formed in this step is removed. Thus, a plated layer 890b shown in FIG. 9 is formed. This plated layer 890b and the base layer 890a covered with the plated layer 890b will later become the wiring layer 832 . The wiring layer 832 corresponds to the wiring layer 32 of the electronic device A1.

３つ目の工程では、図１０に示すように、接合部８５１を形成する。本実施形態においては、接合部８５１として、絶縁層８５１ａおよび接合層８５１ｂを形成する。絶縁層８５１ａを形成する工程では、めっき層８９０ｂの全面およびめっき層８９０ｂから露出する下地層８９０ａの全面を覆うように感光性ポリイミドを塗布する。この感光性ポリイミドは、たとえばスピンコータを用いて塗布される。そして、塗布した感光性ポリイミドに対して露光・現像を行うことにより、枠状の絶縁層８５１ａを形成する。続いて、接合層８５１ｂを形成する工程では、まず、この接合層８５１ｂを形成するためのレジストパターンを形成する。このレジストパターンの形成においては、感光性レジストを塗布し、塗布した感光性レジストに対して露光・現像を行うことにより、レジスト層のパターニングを行う。これにより、レジストパターンが形成され、めっき層８９０ｂの一部（接合層８５１ｂを形成する部分）が当該レジストパターンから露出する。この露出した部分は、平面視において、枠状の絶縁層８５１ａの内方に位置する。そして、下地層８９０ａおよびめっき層８９０ｂを導電経路とした電解めっきにより、レジストパターンから露出するめっき層８９０ｂの上に、接合層８５１ｂを析出させる。本実施形態においては、接合層８５１ｂとして、Ｃｕを含む金属層、Ｎｉを含む金属層およびＳｎを含む合金層を順次積層させる。このＳｎを含む合金層は、たとえばＳｎ－Ｓｂ系合金またはＳｎ－Ａｇ系合金などの鉛フリーはんだである。その後、本工程において形成したレジストパターンを除去する。これにより、図１０に示す、絶縁層８５１ａおよび接合層８５１ｂを含む接合部８５１が形成される。接合部８５１は、電子装置Ａ１の接合部５１に対応する。 In the third step, as shown in FIG. 10, joints 851 are formed. In this embodiment, as the joint portion 851, an insulating layer 851a and a joint layer 851b are formed. In the step of forming the insulating layer 851a, photosensitive polyimide is applied so as to cover the entire surface of the plating layer 890b and the entire surface of the base layer 890a exposed from the plating layer 890b. This photosensitive polyimide is applied using, for example, a spin coater. Then, the frame-shaped insulating layer 851a is formed by exposing and developing the applied photosensitive polyimide. Subsequently, in the step of forming the bonding layer 851b, first, a resist pattern for forming the bonding layer 851b is formed. In forming the resist pattern, a photosensitive resist is applied, and the resist layer is patterned by exposing and developing the applied photosensitive resist. As a result, a resist pattern is formed, and part of the plating layer 890b (the part forming the bonding layer 851b) is exposed from the resist pattern. This exposed portion is positioned inside the frame-shaped insulating layer 851a in plan view. Then, a bonding layer 851b is deposited on the plating layer 890b exposed from the resist pattern by electroplating using the base layer 890a and the plating layer 890b as conductive paths. In this embodiment, a metal layer containing Cu, a metal layer containing Ni, and an alloy layer containing Sn are sequentially stacked as the bonding layer 851b. The alloy layer containing Sn is, for example, lead-free solder such as Sn--Sb alloy or Sn--Ag alloy. After that, the resist pattern formed in this step is removed. Thereby, a bonding portion 851 including an insulating layer 851a and a bonding layer 851b shown in FIG. 10 is formed. The joint 851 corresponds to the joint 51 of the electronic device A1.

４つ目の工程では、図１１に示すように、めっき層８９０ｃを形成する。めっき層８９０ｃの形成は、たとえば、フォトリソグラフィによるレジストパターンの形成および電解めっきによる。めっき層８９０ｃの形成は、めっき層８９０ｂの形成と同様に行われる。具体的には、めっき層８９０ｃを形成する工程では、めっき層８９０ｃを形成するためのレジストパターンを形成する。これにより、形成されたレジストパターンから、下地層８９０ａの一部（めっき層８９０ｃを形成する部分）が露出する。続いて、下地層８９０ａを導電経路とした電解めっきにより、レジストパターンから露出する下地層８９０ａの上にめっき層８９０ｃを析出させる。本実施形態においては、めっき層８９０ｃとして、たとえばＣｕを含む金属層を析出させる。めっき層８９０ｃは、下地層８９０ａと一体的に形成される。その後、本工程において形成したレジストパターンを除去する。これにより、図１１に示すめっき層８９０ｃが形成される。本実施形態においては、めっき層８９０ｃとめっき層８９０ｃに覆われた下地層８９０ａとが、後に、枠状導電体８６１となる。枠状導電体８６１は、電子装置Ａ１の枠状導電体６１に対応する。 In the fourth step, as shown in FIG. 11, a plating layer 890c is formed. The plating layer 890c is formed by forming a resist pattern by photolithography and electroplating, for example. The formation of the plating layer 890c is performed in the same manner as the formation of the plating layer 890b. Specifically, in the step of forming the plating layer 890c, a resist pattern for forming the plating layer 890c is formed. As a result, a portion of the underlying layer 890a (the portion forming the plating layer 890c) is exposed from the formed resist pattern. Subsequently, a plating layer 890c is deposited on the underlying layer 890a exposed from the resist pattern by electrolytic plating using the underlying layer 890a as a conductive path. In this embodiment, a metal layer containing Cu, for example, is deposited as the plating layer 890c. The plated layer 890c is formed integrally with the underlying layer 890a. After that, the resist pattern formed in this step is removed. Thereby, a plating layer 890c shown in FIG. 11 is formed. In the present embodiment, the plated layer 890c and the base layer 890a covered with the plated layer 890c will later become the frame-shaped conductor 861 . The frame-shaped conductor 861 corresponds to the frame-shaped conductor 61 of the electronic device A1.

５つ目の工程では、図１２に示すように、不要な下地層８９０ａを除去する。本実施形態においては、めっき層８９０ｂおよびめっき層８９０ｃのいずれにも覆われていない下地層８９０ａが不要な下地層８９０ａとして除去される。不要な下地層８９０ａは、たとえばＨ2ＳＯ4（硫酸）およびＨ2Ｏ2（過酸化水素）の混合溶液が用いられたウェットエッチングにより除去される。この不要な下地層８９０ａを除去する工程を経ることで、図１２に示すように、１つ目の工程で形成された下地層８９０ａが、めっき層８９０ｂに覆われた下地層８９０ａと、めっき層８９０ｃに覆われた下地層８９０ａとに分割される。これにより、図１２に示すように、めっき層８９０ｂおよびこれに覆われた下地層８９０ａによって、配線層８３２が形成され、めっき層８９０ｃおよびこれに覆われた下地層８９０ａによって、枠状導電体８６１が形成される。なお、図１３～１７においては、めっき層８９０ｂおよびこれに覆われた下地層８９０ａを配線層８３２として一体的に示し、めっき層８９０ｃおよびこれに覆われた下地層８９０ａを枠状導電体８６１として一体的に示す。 In the fifth step, as shown in FIG. 12, the unnecessary base layer 890a is removed. In this embodiment, the underlying layer 890a that is not covered with either the plating layer 890b or the plating layer 890c is removed as an unnecessary underlying layer 890a. Unnecessary underlayer 890a is removed by wet etching using, for example, a mixed solution of H 2 SO 4 (sulfuric acid) and H 2 O 2 (hydrogen peroxide). Through the step of removing the unnecessary base layer 890a, as shown in FIG. It is divided into an underlying layer 890a covered with 890c. Thus, as shown in FIG. 12, the wiring layer 832 is formed by the plating layer 890b and the base layer 890a covered therewith, and the frame-shaped conductor 861 is formed by the plating layer 890c and the base layer 890a covered therewith. is formed. 13 to 17, the plating layer 890b and the underlying layer 890a covered therewith are shown integrally as the wiring layer 832, and the plating layer 890c and the underlying layer 890a covered therewith are shown as the frame-shaped conductor 861. integrally shown.

以上で示した、５つの工程を経ることで、図１２に示すように、配線層８３２、接合部８５１および枠状導電体８６１が形成される。なお、本実施形態においては、同一の下地層８９０ａを利用して、配線層８３２および枠状導電体８６１を形成する場合を示したが、配線層８３２の形成と枠状導電体８６１の形成とで、それぞれ別々に下地層を形成してもよい。なお、本実施形態においては、下地層８９０ａを形成する工程、めっき層８９０ｂを形成する工程および不要な下地層８９０ａを除去する工程を合わせた工程が、特許請求の範囲に記載の「第１配線層形成工程」に相当する。また、下地層８９０ａを形成する工程、めっき層８９０ｃを形成する工程および不要な下地層８９０ａを除去する工程を合わせた工程が、特許請求の範囲に記載の「第２導電体形成工程」に相当する。 Through the five steps described above, the wiring layer 832, the joint portion 851, and the frame-shaped conductor 861 are formed as shown in FIG. In this embodiment, the wiring layer 832 and the frame-shaped conductor 861 are formed using the same base layer 890a. , and the underlying layers may be formed separately. In the present embodiment, the step of forming the base layer 890a, the step of forming the plated layer 890b, and the step of removing the unnecessary base layer 890a are combined to form the "first wiring line." layer forming step”. Further, the step of forming the base layer 890a, the step of forming the plated layer 890c, and the step of removing the unnecessary base layer 890a together correspond to the "second conductor forming step" described in the claims. do.

次いで、図１３に示すように、電子部品８１１を搭載する。電子部品８１１が、電子装置Ａ１の電子部品１１に対応する。電子部品８１１は、ｚ２方向を向く素子主面８１１ａおよびｚ１方向を向く素子裏面８１１ｂを有しており、素子裏面８１１ｂには、電極パッド（図示略）が形成されている。電子部品８１１を搭載する工程（第１電子部品搭載工程）は、フリップチップボンディングにより行う。具体的には、電子部品８１１の素子裏面８１１ｂにフラックスを塗布した後、たとえばフリップチップボンダを用いて電子部品８１１を接合部８５１の上に仮付けする。このとき、素子裏面８１１ｂは、配線層８３２に対向した姿勢となる。また、接合部８５１は、配線層８３２と、電子部品８１１の素子裏面８１１ｂに形成された電極パッド（図示略）との間に介在した状態となる。その後、接合部８５１の接合層８５１ｂをリフローにより溶融させて、電極パッドと結合させる。そして、接合部８５１の接合層８５１ｂを冷却し固化させる。これにより、電子部品８１１が配線層８３２に搭載され、電子部品８１１の電極パッドと配線層８３２とが接合部８５１を介して導通する。 Next, as shown in FIG. 13, an electronic component 811 is mounted. An electronic component 811 corresponds to the electronic component 11 of the electronic device A1. The electronic component 811 has an element main surface 811a facing in the z2 direction and an element back surface 811b facing in the z1 direction. Electrode pads (not shown) are formed on the element back surface 811b. The step of mounting the electronic component 811 (first electronic component mounting step) is performed by flip chip bonding. Specifically, after flux is applied to the element rear surface 811b of the electronic component 811, the electronic component 811 is temporarily attached onto the bonding portion 851 using, for example, a flip chip bonder. At this time, the back surface 811b of the element faces the wiring layer 832 . Also, the joint portion 851 is interposed between the wiring layer 832 and an electrode pad (not shown) formed on the back surface 811 b of the electronic component 811 . After that, the bonding layer 851b of the bonding portion 851 is melted by reflow and bonded to the electrode pad. Then, the bonding layer 851b of the bonding portion 851 is cooled and solidified. As a result, the electronic component 811 is mounted on the wiring layer 832 , and the electrode pads of the electronic component 811 and the wiring layer 832 are electrically connected through the joints 851 .

次いで、図１４に示すように、第２樹脂層８２２を形成する。第２樹脂層８２２を形成する工程（第２樹脂層形成工程）では、たとえばモールド成型による。第２樹脂層８２２は、第１樹脂層８２１と同様に、電気絶縁性を有しており、たとえば黒色のエポキシ樹脂を主剤とした合成樹脂である。本実施形態においては、電子部品８１１および枠状導電体８６１を覆う第２樹脂層８２２を、第１樹脂層８２１の上に形成する。第２樹脂層形成工程によって形成された第２樹脂層８２２は、電子部品８１１および枠状導電体８６１を完全に覆っている。よって、第２樹脂層８２２のｚ２方向を向く面（第２樹脂層主面８２２ａ）は、枠状導電体８６１のｚ２方向を向く面および素子主面８１１ａのいずれよりも、ｚ２方向に位置する。なお、第２樹脂層形成工程において、モールド成型を行う前に、電子部品８１１の下方（電子部品８１１と第１樹脂層主面８２１ａとの間）に、たとえばエポキシ樹脂を主剤としたアンダーフィルを充填させておいてもよい。 Next, as shown in FIG. 14, a second resin layer 822 is formed. In the step of forming the second resin layer 822 (second resin layer forming step), for example, molding is performed. The second resin layer 822 has electrical insulation, like the first resin layer 821, and is made of a synthetic resin containing, for example, a black epoxy resin as a main component. In this embodiment, a second resin layer 822 covering the electronic component 811 and the frame-shaped conductor 861 is formed on the first resin layer 821 . The second resin layer 822 formed by the second resin layer forming step completely covers the electronic component 811 and the frame-shaped conductor 861 . Therefore, the surface of the second resin layer 822 facing the z2 direction (the second resin layer main surface 822a) is positioned in the z2 direction more than both the surface of the frame-shaped conductor 861 facing the z2 direction and the element main surface 811a. . In the second resin layer forming step, under the electronic component 811 (between the electronic component 811 and the first resin layer main surface 821a), an underfill containing, for example, epoxy resin as a main component is applied before molding. You can leave it filled.

次いで、図１５に示すように、支持基板８００を除去する。支持基板８００を除去する工程（支持基板除去工程）では、機械研削盤を用いた研削による。なお、研削方法は、機械研削盤を用いた研削に限定されない。本実施形態においては、支持基板裏面８０２からｚ２方向に向かって支持基板８００を研削し、支持基板８００を完全に削り取ってしまう。本実施形態においては、支持基板８００を完全に研削するとともに、柱状導電体８３１の下地層も研削する。よって、柱状導電体８３１は、Ｃｕを含む金属層であるめっき層から構成される。なお、支持基板８００を研削するときに、柱状導電体８３１の下地層を残した場合には、柱状導電体８３１は、下地層およびめっき層を含んで構成される。当該支持基板除去工程により、第１樹脂層８２１のｚ１方向を向く面（第１樹脂層裏面８２１ｂ）および柱状導電体８３１のｚ１方向を向く面（柱状導電体裏面８３１ｂ）が外部に露出する。なお、支持基板８００としてガラス基板を用いた場合には、当該ガラス基板を薬液処理やレーザ照射によって剥離することで、支持基板８００を除去する。 Then, as shown in FIG. 15, the support substrate 800 is removed. The step of removing the support substrate 800 (support substrate removal step) is performed by grinding using a mechanical grinder. In addition, the grinding method is not limited to grinding using a mechanical grinder. In this embodiment, the support substrate 800 is ground from the support substrate rear surface 802 in the z2 direction, and the support substrate 800 is completely scraped off. In this embodiment, the support substrate 800 is completely ground, and the base layer of the columnar conductors 831 is also ground. Therefore, the columnar conductor 831 is composed of a plated layer that is a metal layer containing Cu. Note that when the base layer of the columnar conductors 831 is left when the support substrate 800 is ground, the columnar conductors 831 are configured to include the base layer and the plated layer. By the supporting substrate removing step, the surface of the first resin layer 821 facing in the z1 direction (first resin layer rear surface 821b) and the surface of the columnar conductor 831 facing in the z1 direction (columnar conductor rear surface 831b) are exposed to the outside. Note that when a glass substrate is used as the supporting substrate 800, the supporting substrate 800 is removed by peeling the glass substrate by chemical treatment or laser irradiation.

次いで、図１６に示すように、外部電極８４０を形成する。外部電極８４０を形成する工程（外部電極形成工程）は、無電解めっきによる。本実施形態においては、無電解めっきにより、Ｎｉ層、Ｐｄ層およびＡｕ層の順に各々を析出させる。このとき、柱状導電体裏面８３１ｂに接し、これを覆うＮｉ層が形成され、当該Ｎｉ層上にＰｄ層、Ｐｄ層上にＡｕ層が形成される。これにより、図１６に示す外部電極８４０が形成される。なお、外部電極８４０の形成方法は、これに限定されず、Ｎｉ層およびＡｕ層を順に析出させてもよいし、Ａｕ層のみであってもよいし、Ｓｎのみであってもよい。 Next, as shown in FIG. 16, external electrodes 840 are formed. The step of forming the external electrodes 840 (external electrode forming step) is by electroless plating. In this embodiment, a Ni layer, a Pd layer and an Au layer are deposited in this order by electroless plating. At this time, a Ni layer is formed in contact with and covering the back surface 831b of the columnar conductor, a Pd layer is formed on the Ni layer, and an Au layer is formed on the Pd layer. Thereby, the external electrodes 840 shown in FIG. 16 are formed. The method of forming the external electrode 840 is not limited to this, and a Ni layer and an Au layer may be deposited in order, only an Au layer may be deposited, or only Sn may be deposited.

次いで、図１７に示すように、第２樹脂層８２２を研削する。第２樹脂層８２２を研削する工程（第２樹脂層研削工程）では、たとえば、機械研削盤を用いて行われ、第２樹脂層８２２を砥石で削る。なお、第２樹脂層８２２の研削方法は、特に限定されない。本実施形態においては、第２樹脂層主面８２２ａからｚ１方向に、枠状導電体８６１が露出するまで、第２樹脂層８２２を、研削する。これにより、第２樹脂層主面８２２ａがｚ１方向に移動し、枠状導電体８６１のｚ方向を向く面（頂面８６１ｃ）が、第２樹脂層８２２（第２樹脂層主面８２２ａ）から露出する。本実施形態においては、第２樹脂層８２２の研削の際、枠状導電体８６１も少し研削される。なお、研削後においては、枠状導電体８６１と第２樹脂層８２２との材質の違いにより、頂面８６１ｃにバリが生じうる。そのため、バリ除去のために薬液処理を行っている。これにより、枠状導電体８６１の頂面８６１ｃが、第２樹脂層主面８２２ａよりもｚ方向に窪んでいる。 Next, as shown in FIG. 17, the second resin layer 822 is ground. In the step of grinding the second resin layer 822 (second resin layer grinding step), for example, a mechanical grinder is used to grind the second resin layer 822 with a whetstone. In addition, the grinding method of the 2nd resin layer 822 is not specifically limited. In this embodiment, the second resin layer 822 is ground in the z1 direction from the second resin layer main surface 822a until the frame-shaped conductor 861 is exposed. As a result, the second resin layer main surface 822a moves in the z1 direction, and the surface (top surface 861c) of the frame-shaped conductor 861 facing the z direction moves from the second resin layer 822 (second resin layer main surface 822a). expose. In this embodiment, when the second resin layer 822 is ground, the frame-shaped conductor 861 is also slightly ground. Note that after grinding, burrs may occur on the top surface 861 c due to the difference in material between the frame-shaped conductor 861 and the second resin layer 822 . Therefore, chemical treatment is performed to remove burrs. As a result, the top surface 861c of the frame-shaped conductor 861 is recessed in the z direction from the second resin layer main surface 822a.

次いで、電子部品８１１ごとの個片に分割する。個片に分割する工程（個片化工程）では、たとえばブレードダイシングによって、第１樹脂層８２１および第２樹脂層８２２を切断する。このとき、図１７に示す切断線ＣＬ１に沿って切断する。図１７においては、ブレードダイシングに用いるダイシングブレードの厚みを考慮して、切断線ＣＬ１を矩形で示している。なお、切断方法は、ブレードダイシングに限定されず、レーザダイシングあるいはプラズマダイシングなどの他のダイシング手法を用いてもよい。個片化工程により分割された個片が、図１～図４に示す電子装置Ａ１となる。 Next, it is divided into individual pieces for each electronic component 811 . In the step of dividing into individual pieces (individualizing step), the first resin layer 821 and the second resin layer 822 are cut by, for example, blade dicing. At this time, the cutting is performed along the cutting line CL1 shown in FIG. In FIG. 17, the cutting line CL1 is indicated by a rectangle in consideration of the thickness of the dicing blade used for blade dicing. The cutting method is not limited to blade dicing, and other dicing methods such as laser dicing or plasma dicing may be used. Individual pieces divided by the singulation process become electronic devices A1 shown in FIGS. 1 to 4. FIG.

以上の各工程を経ることで、図１～図４に示す電子装置Ａ１が複数個製造される。なお、先述の電子装置Ａ１の製造方法は、一例であって、これに限定されない。たとえば、第２樹脂層研削工程を、支持基板除去工程および外部電極形成工程の前に行ってもよい。この場合、外部電極形成工程における無電解めっきによって、第２樹脂層８２２から露出した枠状導電体８６１の頂面８６１ｃに外部電極８４０が形成されないように、外部電極形成工程の前に、第２樹脂層８２２の第２樹脂層主面８２２ａにダイシングテープを貼り付けておくとよい。また、電子部品８１１の電極パッドにはんだバンプなどの接合部材が形成されている場合には、先述の接合層８５１ｂを形成する工程により、接合部８５１の接合層８５１ｂを形成しなくてもよい。 Through the steps described above, a plurality of electronic devices A1 shown in FIGS. 1 to 4 are manufactured. Note that the above-described method for manufacturing the electronic device A1 is merely an example, and the present invention is not limited to this. For example, the second resin layer grinding step may be performed before the supporting substrate removing step and the external electrode forming step. In this case, in order to prevent the external electrodes 840 from being formed on the top surface 861c of the frame-shaped conductor 861 exposed from the second resin layer 822 by electroless plating in the external electrode forming process, the second A dicing tape is preferably attached to the second resin layer main surface 822 a of the resin layer 822 . Further, when bonding members such as solder bumps are formed on the electrode pads of the electronic component 811, it is not necessary to form the bonding layer 851b of the bonding portion 851 by the above-described step of forming the bonding layer 851b.

次に、第１実施形態にかかる電子装置Ａ１およびその製造方法の作用効果について説明する。 Next, the effects of the electronic device A1 and the manufacturing method thereof according to the first embodiment will be described.

電子装置Ａ１によれば、第１樹脂層２１および第２樹脂層２２を備えている。第１樹脂層２１は、複数の配線層３２を介して、電子部品１１を支持している。第２樹脂層２２は、第１樹脂層２１の上に形成され、電子部品１１を覆っている。この構成によると、第１樹脂層２１が、電子部品１１を支持する支持部材であり、第２樹脂層２２が、電子部品１１を覆う保護部材である。したがって、支持部材と保護部材との熱膨張係数の差を低減することができる。特に、本実施形態においては、第１樹脂層２１の構成材料と第２樹脂層２２の構成材料とがともにエポキシ樹脂であるので、支持部材と保護部材との熱膨張係数の差がほとんどない。そのため、電子装置Ａ１の通電時に生じる電子部品１１からの発熱によって、支持部材（第１樹脂層２１）と保護部材（第２樹脂層２２）との界面における熱応力を緩和させることができる。よって、保護部材が支持部材から剥離することを抑制できるので、電子装置Ａ１の信頼性を向上できる。 According to the electronic device A1, the first resin layer 21 and the second resin layer 22 are provided. The first resin layer 21 supports the electronic component 11 via a plurality of wiring layers 32 . The second resin layer 22 is formed on the first resin layer 21 and covers the electronic component 11 . According to this configuration, the first resin layer 21 is a supporting member that supports the electronic component 11 , and the second resin layer 22 is a protective member that covers the electronic component 11 . Therefore, the difference in thermal expansion coefficient between the support member and the protection member can be reduced. In particular, in the present embodiment, both the constituent material of the first resin layer 21 and the constituent material of the second resin layer 22 are epoxy resins, so there is almost no difference in thermal expansion coefficient between the support member and the protection member. Therefore, thermal stress at the interface between the support member (first resin layer 21) and the protection member (second resin layer 22) can be relaxed by the heat generated from the electronic component 11 when the electronic device A1 is energized. Therefore, it is possible to prevent the protective member from peeling off from the support member, thereby improving the reliability of the electronic device A1.

電子装置Ａ１によれば、電子部品１１は、モールド成型によって形成された第１樹脂層２１に支持されている。本開示の電子装置Ａ１と異なる電子装置であって、たとえば特許文献１に記載の電子装置においては、電子部品１１は、半導体基板（シリコン基板）に支持されている。そのため、当該電子装置の底面に端子を設ける際、ＴＳＶ（Through-Silicon Via）と呼ばれる貫通電極を形成する必要がある。このＴＳＶの形成には、たとえばボッシュポロセスとよばれるエッチング技術によって貫通孔を形成する必要があるが、半導体基板が厚いほど、貫通孔の形成が困難である。よって、支持部材（半導体基板）を貫通する貫通電極の形成が困難である。一方、本実施形態によれば、電解めっきにより柱状導電体３１（柱状導電体８３１）を形成した後、モールド成型によって第１樹脂層２１（第１樹脂層８２１）を形成している。そのため、比較的容易に支持部材（第１樹脂層２１）を貫通する貫通電極（柱状導電体３１）を形成できる。したがって、支持部材として半導体基板を用いた場合よりも、電子装置Ａ１の製造が容易になる。 According to the electronic device A1, the electronic component 11 is supported by the first resin layer 21 formed by molding. In an electronic device different from the electronic device A1 of the present disclosure, for example, in the electronic device described in Patent Document 1, an electronic component 11 is supported by a semiconductor substrate (silicon substrate). Therefore, when providing a terminal on the bottom surface of the electronic device, it is necessary to form a through electrode called a TSV (Through-Silicon Via). To form the TSV, it is necessary to form a through-hole by, for example, an etching technique called Bosch process. However, the thicker the semiconductor substrate, the more difficult it is to form the through-hole. Therefore, it is difficult to form a through electrode penetrating through the supporting member (semiconductor substrate). On the other hand, according to the present embodiment, after the columnar conductors 31 (columnar conductors 831) are formed by electrolytic plating, the first resin layer 21 (first resin layer 821) is formed by molding. Therefore, the through electrodes (the columnar conductors 31) penetrating the support member (the first resin layer 21) can be formed relatively easily. Therefore, the manufacture of the electronic device A1 becomes easier than when a semiconductor substrate is used as the supporting member.

電子装置Ａ１によれば、第１樹脂層２１の第１樹脂層主面２１１には研削痕が形成されている。よって、第１樹脂層主面２１１には、当該研削痕により微細な凹凸が形成されている。この構成によると、アンカー効果によって、第１樹脂層２１と第２樹脂層２２との接着強度を向上させることができる。よって、保護部材（第２樹脂層２２）が支持部材（第１樹脂層２１）から剥離することを抑制できるので、電子装置Ａ１の信頼性を向上できる。 According to the electronic device A<b>1 , grinding marks are formed on the first resin layer main surface 211 of the first resin layer 21 . Therefore, minute unevenness is formed on the main surface 211 of the first resin layer due to the grinding marks. According to this configuration, the adhesive strength between the first resin layer 21 and the second resin layer 22 can be improved by the anchor effect. Therefore, it is possible to prevent the protective member (second resin layer 22) from peeling off from the support member (first resin layer 21), thereby improving the reliability of the electronic device A1.

電子装置Ａ１によれば、各接合部５１は、絶縁層５１１を含んでいる。この構成によると、第１電子部品搭載工程時のリフローの熱により、接合層８５１ｂ（特に第３層５１２ｃに対応する部分）を溶融させたとき、当該接合層８５１ｂが意図せぬ部分に広がることを抑制することができる。したがって、意図せぬ短絡を抑制できるので、電子装置Ａ１の動作不良を抑制することができる。 According to the electronic device A<b>1 , each junction 51 includes an insulating layer 511 . According to this configuration, when the bonding layer 851b (especially the portion corresponding to the third layer 512c) is melted by reflow heat during the first electronic component mounting process, the bonding layer 851b spreads to an unintended portion. can be suppressed. Therefore, an unintended short circuit can be suppressed, and malfunction of the electronic device A1 can be suppressed.

電子装置Ａ１によれば、枠状導電体６１を備えている。枠状導電体６１は、金属製であって、平面視において電子部品１１を包囲する。この構成によると、枠状導電体６１が電磁シールドとして機能し、電子部品１１の側方からの電磁波を抑制することができる。よって、電子装置Ａ１の動作不良を抑制することができる。 According to the electronic device A1, the frame-shaped conductor 61 is provided. The frame-shaped conductor 61 is made of metal and surrounds the electronic component 11 in plan view. According to this configuration, the frame-shaped conductor 61 functions as an electromagnetic shield and can suppress electromagnetic waves from the sides of the electronic component 11 . Therefore, malfunction of the electronic device A1 can be suppressed.

以下に、本開示の電子装置およびその製造方法の、他の実施形態について、説明する。なお、先述の電子装置およびその製造方法と、同一あるいは類似の構成については、同じ符号を付して、その説明を省略する。 Other embodiments of the electronic device and the manufacturing method thereof according to the present disclosure will be described below. The same or similar configurations as those of the electronic device and the manufacturing method thereof described above are denoted by the same reference numerals, and the description thereof is omitted.

＜第２実施形態＞
図１８～図２１は、第２実施形態にかかる電子装置を示している。第２実施形態の電子装置Ａ２は、電子装置Ａ１と比較して、主に、電子部品１１と異なる電子部品１２を備えている点で異なる。 <Second embodiment>
18 to 21 show an electronic device according to the second embodiment. The electronic device A2 of the second embodiment differs from the electronic device A1 mainly in that it includes an electronic component 12 that is different from the electronic component 11 .

図１８は、電子装置Ａ２を示す平面図であって、封止樹脂２０を想像線（二点鎖線）で示している。図１９は、電子装置Ａ２を示す平面図であって、電子部品１１、封止樹脂２０、配線層３２、接合部５１および枠状導電体６１を想像線（二点鎖線）で示している。図２０は、図１８のＸＸ－ＸＸ線に沿う断面図である。図２１は、図２０の一部を拡大した部分拡大断面図である。 FIG. 18 is a plan view showing the electronic device A2, showing the sealing resin 20 with an imaginary line (chain double-dashed line). FIG. 19 is a plan view showing the electronic device A2, in which the electronic component 11, the sealing resin 20, the wiring layer 32, the joint 51, and the frame-shaped conductor 61 are indicated by imaginary lines (chain lines). 20 is a cross-sectional view taken along line XX-XX of FIG. 18. FIG. 21 is a partially enlarged sectional view enlarging a part of FIG. 20. FIG.

電子装置Ａ２は、図１８～図２１に示すように、電子部品１１，１２、封止樹脂２０（第１樹脂層２１および第２樹脂層２２）、複数の柱状導電体３１、複数の配線層３２，３３、複数の外部電極４０、複数の接合部５１，５２、枠状導電体６１および外部保護膜７１を備えている。よって、電子装置Ａ２は、図１８～図２１に示すように、電子装置Ａ１と比較して、電子部品１２、複数の配線層３３、複数の接合部５２および外部保護膜７１をさらに備えている。 As shown in FIGS. 18 to 21, the electronic device A2 includes electronic components 11 and 12, a sealing resin 20 (first resin layer 21 and second resin layer 22), a plurality of columnar conductors 31, and a plurality of wiring layers. 32 and 33 , a plurality of external electrodes 40 , a plurality of joints 51 and 52 , a frame-shaped conductor 61 and an external protective film 71 . Therefore, as shown in FIGS. 18 to 21, the electronic device A2 further includes an electronic component 12, multiple wiring layers 33, multiple junctions 52, and an external protective film 71 compared to the electronic device A1. .

電子部品１２は、電子部品１１とともに、電子装置Ａ２の機能中枢となる素子である。本実施形態において、電子部品１２は、電子部品１１と同様に、半導体を材料とする半導体素子である。電子部品１２は、電子部品１１と同様に、たとえばＬＳＩなどの集積回路（ＩＣ）、ＬＤＯなどの電圧制御用素子、オペアンプなどの増幅用素子、あるいは、トランジスタやダイオードなどのディスクリート部品のいずれであってもよい。なお、電子部品１２は、半導体材料を含んでいなくてもよい。このようなものには、いわゆる受動素子であって、たとえば抵抗器、インダクタ、キャパシタなどがある。電子部品１２は、平面視矩形状である。電子部品１２は、平面視において、電子部品１１よりも小さく、電子部品１１に完全に重なっている。電子部品１２は、ｚ方向において、電子部品１１よりも、ｚ１方向に位置する。なお、電子部品１２は、平面視において、電子部品１１よりも大きくてもよい。電子部品１２は、複数の接合部５２によって、複数の配線層３３に導通接合されている。電子部品１２は、表面実装されうる構造のものである。電子部品１２は、第１樹脂層２１に覆われている。電子部品１２が、特許請求の範囲に記載の「第２電子部品」に相当する。電子部品１２は、図２０に示すように、素子主面１２１および素子裏面１２２を有する。 The electronic component 12, together with the electronic component 11, is an element that serves as the functional core of the electronic device A2. In this embodiment, the electronic component 12 is a semiconductor element made of a semiconductor, like the electronic component 11 . Like the electronic component 11, the electronic component 12 may be an integrated circuit (IC) such as an LSI, a voltage control element such as an LDO, an amplifying element such as an operational amplifier, or a discrete component such as a transistor or diode. may Note that the electronic component 12 does not have to contain a semiconductor material. These include so-called passive elements, such as resistors, inductors and capacitors. The electronic component 12 has a rectangular shape in plan view. The electronic component 12 is smaller than the electronic component 11 in plan view and completely overlaps the electronic component 11 . The electronic component 12 is positioned in the z1 direction from the electronic component 11 in the z direction. Note that the electronic component 12 may be larger than the electronic component 11 in plan view. The electronic component 12 is conductively joined to the wiring layers 33 by the joints 52 . The electronic component 12 is of a structure that can be surface mounted. Electronic component 12 is covered with first resin layer 21 . The electronic component 12 corresponds to the "second electronic component" recited in the claims. The electronic component 12 has an element main surface 121 and an element back surface 122, as shown in FIG.

素子主面１２１および素子裏面１２２は、ｚ方向において、離間し、かつ、反対側を向く。素子主面１２１は、ｚ２方向を向く。素子裏面１２２は、ｚ１方向を向く。素子主面１２１は、第１樹脂層２１に覆われている。素子裏面１２２には、複数の電極パッド（図示略）が形成されている。当該複数の電極パッドはそれぞれ、たとえばＡｌから構成される。複数の電極パッドは、電子部品１２における端子である。複数の電極パッドの数および位置は、図１８および図１９に示す態様に限定されない。素子主面１２１が、特許請求の範囲に記載の「第２素子主面」に相当する。 The element main surface 121 and the element back surface 122 are spaced apart and face opposite sides in the z direction. The element main surface 121 faces the z2 direction. The element back surface 122 faces the z1 direction. The element main surface 121 is covered with the first resin layer 21 . A plurality of electrode pads (not shown) are formed on the element back surface 122 . Each of the plurality of electrode pads is made of Al, for example. A plurality of electrode pads are terminals in the electronic component 12 . The number and positions of the plurality of electrode pads are not limited to those shown in FIGS. 18 and 19. FIG. The element main surface 121 corresponds to the "second element main surface" described in the claims.

本実施形態において、複数の柱状導電体３１の各々は、各配線層３３の上に形成されている。各柱状導電体３１の柱状導電体裏面３１２は、各配線層３３に接している。本実施形態において、各柱状導電体３１の構成材料は、Ｃｕである。なお、各柱状導電体３１は、互いに積層された下地層およびめっき層を含んで構成されていてもよい。この場合、下地層は、Ｔｉ層およびＣｕ層を含んでおり、配線層３３の上にＴｉ層が形成され、当該Ｔｉ層の上にＣｕ層が形成されている。めっき層は、Ｃｕを含んでおり、下地層のＣｕ層の上に形成されている。 In this embodiment, each of the plurality of columnar conductors 31 is formed on each wiring layer 33 . A columnar conductor rear surface 312 of each columnar conductor 31 is in contact with each wiring layer 33 . In this embodiment, the constituent material of each columnar conductor 31 is Cu. In addition, each columnar conductor 31 may be configured to include an underlying layer and a plated layer that are laminated to each other. In this case, the underlying layer includes a Ti layer and a Cu layer, the Ti layer is formed on the wiring layer 33, and the Cu layer is formed on the Ti layer. The plated layer contains Cu and is formed on the Cu layer of the underlying layer.

複数の配線層３３の各々は、電子部品１２と各柱状導電体３１とを導通させる。各配線層３３の構成材料は、互いに積層された下地層およびめっき層を含んで構成されている。下地層は、互いに積層されたＴｉ層およびＣｕ層から構成され、その厚みは２００～８００ｎｍ程度である。めっき層は、たとえばＣｕを含んでおり、下地層よりも厚く設定されている。なお、各配線層３３の構成材料は、これに限定されない。また、各配線層３３の形成範囲は、図１８および図１９に示す態様に限定されない。配線層３３が、特許請求の範囲に記載の「第２配線層」に相当する。 Each of the plurality of wiring layers 33 electrically connects the electronic component 12 and each columnar conductor 31 . The constituent material of each wiring layer 33 includes an underlying layer and a plated layer that are laminated to each other. The underlying layer is composed of a Ti layer and a Cu layer laminated to each other, and has a thickness of about 200 to 800 nm. The plated layer contains Cu, for example, and is set thicker than the underlying layer. In addition, the constituent material of each wiring layer 33 is not limited to this. Also, the formation range of each wiring layer 33 is not limited to the modes shown in FIGS. The wiring layer 33 corresponds to the "second wiring layer" described in the claims.

各配線層３３は、配線層主面３３１および配線層裏面３３２を有している。配線層主面３３１および配線層裏面３３２は、ｚ方向において、離間し、かつ、互いに反対側を向く。配線層主面３３１は、ｚ２方向を向き、配線層裏面３３２は、ｚ１方向を向く。配線層主面３３１は、第１樹脂層２１に覆われている。各配線層主面３３１には、柱状導電体３１および接合部５２がそれぞれ１つずつ形成されている。配線層主面３３１は、その一部が柱状導電体裏面３１２に接する。配線層裏面３３２は、第１樹脂層２１（第１樹脂層裏面２１２）から露出している。本実施形態においては、配線層裏面３３２は、第１樹脂層裏面２１２と面一である。配線層裏面３３２は、その一部が外部電極４０に接する。配線層主面３３１および配線層裏面３３２が、特許請求の範囲に記載の「第２配線層主面」および「第２配線層裏面」にそれぞれ相当する。 Each wiring layer 33 has a wiring layer main surface 331 and a wiring layer back surface 332 . The wiring layer main surface 331 and the wiring layer back surface 332 are separated from each other in the z direction and face opposite sides. The wiring layer main surface 331 faces the z2 direction, and the wiring layer back surface 332 faces the z1 direction. The wiring layer main surface 331 is covered with the first resin layer 21 . Each wiring layer main surface 331 is formed with one columnar conductor 31 and one junction 52 . The wiring layer main surface 331 is partially in contact with the columnar conductor back surface 312 . The wiring layer back surface 332 is exposed from the first resin layer 21 (first resin layer back surface 212). In this embodiment, the wiring layer back surface 332 is flush with the first resin layer back surface 212 . A portion of the wiring layer back surface 332 is in contact with the external electrode 40 . The wiring layer main surface 331 and the wiring layer back surface 332 respectively correspond to the "second wiring layer main surface" and the "second wiring layer back surface" described in the claims.

本実施形態において、複数の外部電極４０は、複数の柱状導電体被覆部４１を含まず、複数の配線層被覆部４２を含んでいる。 In this embodiment, the plurality of external electrodes 40 does not include the plurality of columnar conductor covering portions 41 but includes the plurality of wiring layer covering portions 42 .

各配線層被覆部４２は、各配線層裏面３３２の一部ずつを覆っている。各配線層被覆部４２は、各配線層裏面３３２に接する。本実施形態において、電子部品１１は、各接合部５１、各配線層３２、各柱状導電体３１および各配線層３３を介して、各配線層被覆部４２に導通する。また、電子部品１２は、各接合部５２および各配線層３３を介して、各配線層被覆部４２に導通する。よって、各配線層被覆部４２は、電子部品１１および電子部品１２の両方に導通する、電子装置Ａ２の端子である。配線層被覆部４２が、特許請求の範囲に記載の「第２配線層被覆部」に相当する。 Each wiring layer covering portion 42 partially covers each wiring layer rear surface 332 . Each wiring layer covering portion 42 is in contact with each wiring layer rear surface 332 . In this embodiment, the electronic component 11 is electrically connected to each wiring layer covering portion 42 via each joint portion 51 , each wiring layer 32 , each columnar conductor 31 and each wiring layer 33 . Also, the electronic component 12 is electrically connected to each wiring layer covering portion 42 via each bonding portion 52 and each wiring layer 33 . Therefore, each wiring layer covering portion 42 is a terminal of the electronic device A2 that conducts to both the electronic component 11 and the electronic component 12 . The wiring layer covering portion 42 corresponds to the "second wiring layer covering portion" described in the claims.

複数の接合部５２の各々は、電子部品１２（詳細には、先述の電極パッド）と各配線層３３との間に介在する導電性接合材である。電子部品１２は、複数の接合部５２により複数の配線層３３に固着され、各配線層３３に搭載された構成となっている。あわせて、複数の接合部５２により、電子部品１２と複数の配線層３３との導通が確保される。本実施形態においては、接合部５２は、図２１に示すように、絶縁層５２１および接合層５２２を含んでいる。 Each of the plurality of joint portions 52 is a conductive joint material interposed between the electronic component 12 (specifically, the electrode pad described above) and each wiring layer 33 . The electronic component 12 is fixed to the plurality of wiring layers 33 by the plurality of bonding portions 52 and mounted on each wiring layer 33 . In addition, the plurality of joints 52 ensure electrical continuity between the electronic component 12 and the plurality of wiring layers 33 . In this embodiment, the joint portion 52 includes an insulating layer 521 and a joint layer 522, as shown in FIG.

絶縁層５２１は、図２１に示すように、各配線層３３の上にそれぞれに形成されている。絶縁層５２１は、絶縁層５１１と同様に構成されている。絶縁層５２１は、平面視において、中央に開口した枠状である。絶縁層５２１は、平面視において矩形環状を呈する。なお、絶縁層５２１の平面視形状は、矩形環状に限定されず、円環状、楕円環状あるいは多角環状であってもよい。絶縁層５２１は、平面視において、接合層５２２を囲んでいる。絶縁層５２１の構成材料は、たとえばポリイミド樹脂であるが、これに限定されない。 The insulating layer 521 is formed on each wiring layer 33, as shown in FIG. The insulating layer 521 is configured similarly to the insulating layer 511 . The insulating layer 521 has a frame shape with an opening in the center in plan view. The insulating layer 521 has a rectangular annular shape in plan view. In addition, the planar view shape of the insulating layer 521 is not limited to a rectangular annular shape, and may be a circular annular shape, an elliptical annular shape, or a polygonal annular shape. The insulating layer 521 surrounds the bonding layer 522 in plan view. A constituent material of the insulating layer 521 is, for example, a polyimide resin, but is not limited to this.

接合層５２２は、電子部品１２と各配線層３３とを導通接合する。接合層５２２は、配線層３３（配線層主面３３１）の上に形成されている。接合層５２２は、接合層５２２と同様に構成されている。具体的には、接合層５２２は、絶縁層５２１の開口した部分の表面を覆っている。本実施形態において、各接合層５２２は、一部が絶縁層５２１の開口部分に充填されている。本実施形態においては、各接合層５２２は、図２１に示すように、互いに積層された第１層５２２ａ、第２層５２２ｂおよび第３層５２２ｃから構成される。第１層５２２ａ、第２層５２２ｂおよび第３層５２２ｃはそれぞれ、各接合部５１の接合層５１２における第１層５１２ａ、第２層５１２ｂおよび第３層５１２ｃとそれぞれ同様に構成されている。 The bonding layer 522 electrically connects the electronic component 12 and each wiring layer 33 . The bonding layer 522 is formed on the wiring layer 33 (wiring layer main surface 331). The bonding layer 522 is configured similarly to the bonding layer 522 . Specifically, the bonding layer 522 covers the surface of the opening of the insulating layer 521 . In this embodiment, each bonding layer 522 partially fills the opening of the insulating layer 521 . In this embodiment, each bonding layer 522 is composed of a first layer 522a, a second layer 522b and a third layer 522c which are laminated together, as shown in FIG. The first layer 522a, the second layer 522b and the third layer 522c are configured similarly to the first layer 512a, the second layer 512b and the third layer 512c of the bonding layer 512 of each bonding portion 51, respectively.

外部保護膜７１は、絶縁性を有する樹脂膜である。外部保護膜７１の構成材料は、たとえばポリマー樹脂である。ポリマー樹脂としては、ポリイミド樹脂やフェノール樹脂などがある。なお、外部保護膜７１の構成材料は、絶縁性を有する樹脂材料であれば、これらに限定されない。外部保護膜７１は、少なくとも、外部電極４０の配線層被覆部４２から露出する配線層裏面３３２を覆っている。本実施形態においては、外部保護膜７１は、外部電極４０の配線層被覆部４２から露出する配線層裏面３３２および第１樹脂層裏面２１２の全面を覆っている。外部保護膜７１が、特許請求の範囲に記載の「保護膜」に相当する。 The external protective film 71 is an insulating resin film. A constituent material of the outer protective film 71 is, for example, a polymer resin. Polymer resins include polyimide resins and phenolic resins. In addition, the constituent material of the external protective film 71 is not limited to these as long as it is a resin material having insulating properties. The external protective film 71 covers at least the wiring layer rear surface 332 exposed from the wiring layer covering portion 42 of the external electrode 40 . In this embodiment, the external protective film 71 covers the wiring layer back surface 332 exposed from the wiring layer covering portion 42 of the external electrode 40 and the entire surface of the first resin layer back surface 212 . The external protective film 71 corresponds to the "protective film" described in the claims.

次に、第２実施形態にかかる電子装置Ａ２の製造方法の一例について、図２２～図２９を参照して、説明する。図２２～図２９は、電子装置Ａ２の製造方法にかかる一工程を示す断面図である。なお、第２実施形態にかかる各工程のうち、第１実施形態と同一あるいは類似の工程においては、先述の工程を参照して、その説明を省略する。 Next, an example of a method for manufacturing the electronic device A2 according to the second embodiment will be described with reference to FIGS. 22 to 29. FIG. 22 to 29 are cross-sectional views showing one step in the method of manufacturing the electronic device A2. Among the steps of the second embodiment, steps that are the same as or similar to those of the first embodiment will be referred to the steps described above, and descriptions thereof will be omitted.

まず、第１実施形態における支持基板用意工程と同様に、支持基板８００を用意する。 First, a support substrate 800 is prepared in the same manner as the support substrate preparation step in the first embodiment.

次いで、図２２～図２６に示すように、配線層８３３、接合部８５２および柱状導電体８３１を形成する。配線層８３３、接合部８５２および柱状導電体８３１が、電子装置Ａ２の配線層３２、接合部５２および柱状導電体３１にそれぞれ対応する。これらを形成する工程には、次に示す５つの工程がある。 Next, as shown in FIGS. 22 to 26, wiring layers 833, joints 852 and columnar conductors 831 are formed. The wiring layer 833, the joint portion 852 and the columnar conductor 831 correspond to the wiring layer 32, the joint portion 52 and the columnar conductor 31 of the electronic device A2, respectively. The process of forming these includes the following five processes.

１つ目の工程では、図２２に示すように、下地層８９１ａを形成する。下地層８９１ａの形成は、たとえばスパッタリング法による。下地層８９１ａを形成する工程では、支持基板主面８０１の全面を覆うＴｉ層を形成した後、Ｔｉ層に接するＣｕ層を形成する。下地層８９１ａは、互いに積層されたＴｉ層およびＣｕ層から形成される。 In the first step, as shown in FIG. 22, an underlying layer 891a is formed. The base layer 891a is formed by, for example, a sputtering method. In the step of forming the base layer 891a, after forming a Ti layer covering the entire main surface 801 of the supporting substrate, a Cu layer is formed in contact with the Ti layer. The underlying layer 891a is formed of a Ti layer and a Cu layer laminated together.

２つ目の工程では、図２３に示すように、めっき層８９１ｂを形成する。めっき層８９１ｂの形成は、たとえば、フォトリソグラフィによるレジストパターンの形成および電解めっきによる。めっき層８９１ｂを形成する工程では、下地層８９１ａの全面を覆うように、感光性レジストを塗布して、当該感光性レジストに対して露光および現像を行うことによって、レジスト層のパターニングを行う。これにより、レジストパターンが形成され、下地層８９１ａの一部（めっき層８９１ｂを形成する部分）がレジストパターンから露出する。続いて、下地層８９１ａを導電経路とした電解めっきにより、レジストパターンから露出する下地層８９１ａの上にめっき層８９１ｂを析出させる。本実施形態においては、めっき層８９１ｂとして、たとえばＣｕを含む金属層を析出させる。このとき、めっき層８９１ｂは、下地層８９１ａと一体的に形成される。その後、本工程において形成したレジスト層をすべて除去する。これにより、図２３に示すめっき層８９１ｂが形成される。このめっき層８９１ｂとめっき層８９１ｂに覆われた下地層８９１ａが、後に、配線層８３３となる。配線層８３３は、電子装置Ａ２の配線層３３に対応する。 In the second step, as shown in FIG. 23, a plating layer 891b is formed. The plating layer 891b is formed, for example, by forming a resist pattern by photolithography and electroplating. In the step of forming the plating layer 891b, a photosensitive resist is applied so as to cover the entire surface of the base layer 891a, and the resist layer is patterned by exposing and developing the photosensitive resist. As a result, a resist pattern is formed, and a portion of the underlying layer 891a (the portion forming the plated layer 891b) is exposed from the resist pattern. Subsequently, a plated layer 891b is deposited on the underlying layer 891a exposed from the resist pattern by electroplating using the underlying layer 891a as a conductive path. In this embodiment, a metal layer containing Cu, for example, is deposited as the plating layer 891b. At this time, the plated layer 891b is formed integrally with the underlying layer 891a. After that, all the resist layers formed in this step are removed. Thus, a plated layer 891b shown in FIG. 23 is formed. This plated layer 891b and the base layer 891a covered with the plated layer 891b will later become the wiring layer 833 . The wiring layer 833 corresponds to the wiring layer 33 of the electronic device A2.

３つ目の工程では、図２４に示すように、接合部８５２を形成する。本実施形態においては、接合部８５２として、絶縁層８５２ａおよび接合層８５２ｂを形成する。絶縁層８５２ａを形成する工程では、めっき層８９１ｂの全面およびめっき層８９１ｂから露出する下地層８９１ａの全面を覆うように感光性ポリイミドを塗布する。この感光性ポリイミドは、たとえばスピンコータを用いて塗布される。そして、塗布した感光性ポリイミドに対して露光・現像を行うことにより、枠状の絶縁層８５２ａを形成する。続いて、接合層８５２ｂを形成する工程では、まず、この接合層８５２ｂを形成するためのレジストパターンを形成する。このレジストパターンの形成においては、感光性レジストを塗布し、塗布した感光性レジストに対して露光・現像を行うことにより、レジスト層のパターニングを行う。これにより、レジストパターンが形成され、めっき層８９１ｂの一部（接合層８５２ｂを形成する部分）が当該レジストパターンから露出する。この露出した部分は、平面視において、枠状の絶縁層８５２ａの内方に位置する。そして、下地層８９１ａおよびめっき層８９１ｂを導電経路とした電解めっきにより、レジストパターンから露出するめっき層８９１ｂの上に、接合層８５２ｂを析出させる。本実施形態においては、接合層８５２ｂとして、Ｃｕを含む金属層、Ｎｉを含む金属層およびＳｎを含む合金層を順次積層させる。このＳｎを含む合金層は、たとえばＳｎ－Ｓｂ系合金またはＳｎ－Ａｇ系合金などの鉛フリーはんだである。その後、本工程において形成したレジストパターンを除去する。これにより、図２４に示す、絶縁層８５２ａおよび接合層８５２ｂを含む接合部８５２が形成される。接合部８５２は、電子装置Ａ２の接合部５２に対応する。 In the third step, as shown in FIG. 24, joints 852 are formed. In this embodiment, as the joint portion 852, an insulating layer 852a and a joint layer 852b are formed. In the step of forming the insulating layer 852a, photosensitive polyimide is applied so as to cover the entire surface of the plating layer 891b and the entire surface of the base layer 891a exposed from the plating layer 891b. This photosensitive polyimide is applied using, for example, a spin coater. Then, the frame-shaped insulating layer 852a is formed by exposing and developing the applied photosensitive polyimide. Subsequently, in the step of forming the bonding layer 852b, first, a resist pattern for forming the bonding layer 852b is formed. In forming the resist pattern, a photosensitive resist is applied, and the resist layer is patterned by exposing and developing the applied photosensitive resist. As a result, a resist pattern is formed, and a portion of the plating layer 891b (the portion forming the bonding layer 852b) is exposed from the resist pattern. This exposed portion is positioned inside the frame-shaped insulating layer 852a in plan view. Then, a bonding layer 852b is deposited on the plating layer 891b exposed from the resist pattern by electrolytic plating using the underlying layer 891a and the plating layer 891b as a conductive path. In this embodiment, a metal layer containing Cu, a metal layer containing Ni, and an alloy layer containing Sn are sequentially stacked as the bonding layer 852b. The alloy layer containing Sn is, for example, lead-free solder such as Sn--Sb alloy or Sn--Ag alloy. After that, the resist pattern formed in this step is removed. Thereby, a bonding portion 852 including an insulating layer 852a and a bonding layer 852b shown in FIG. 24 is formed. The joint 852 corresponds to the joint 52 of the electronic device A2.

４つ目の工程では、図２５に示すように、めっき層８９１ｃを形成する。めっき層８９１ｃの形成は、たとえば、フォトリソグラフィによるレジストパターンの形成および電解めっきによる。めっき層８９１ｃの形成は、めっき層８９１ｂの形成と同様に行われる。具体的には、めっき層８９１ｃを形成する工程では、めっき層８９１ｃを形成するためのレジストパターンを形成する。これにより、形成されたレジストパターンから、めっき層８９１ｂの一部（めっき層８９１ｃを形成する部分）が露出する。続いて、下地層８９１ａおよびめっき層８９１ｂを導電経路とした電解めっきにより、レジストパターンから露出するめっき層８９１ｂの上にめっき層８９１ｃを析出させる。本実施形態においては、めっき層８９１ｃとして、たとえばＣｕを含む金属層を析出させる。その後、本工程において形成されたレジストパターンを除去する。これにより、図２５に示すめっき層８９１ｃが形成される。本実施形態においては、めっき層８９１ｃが、柱状導電体８３１となる。 In the fourth step, as shown in FIG. 25, a plating layer 891c is formed. The plating layer 891c is formed by, for example, forming a resist pattern by photolithography and electroplating. The plating layer 891c is formed in the same manner as the plating layer 891b. Specifically, in the step of forming the plating layer 891c, a resist pattern for forming the plating layer 891c is formed. As a result, a portion of the plating layer 891b (the portion forming the plating layer 891c) is exposed from the formed resist pattern. Subsequently, a plating layer 891c is deposited on the plating layer 891b exposed from the resist pattern by electroplating using the base layer 891a and the plating layer 891b as conductive paths. In this embodiment, a metal layer containing Cu, for example, is deposited as the plating layer 891c. After that, the resist pattern formed in this step is removed. Thereby, a plated layer 891c shown in FIG. 25 is formed. In this embodiment, the plated layer 891c becomes the columnar conductor 831. As shown in FIG.

５つ目の工程では、図２６に示すように、不要な下地層８９１ａを除去する。本実施形態においては、めっき層８９１ｂに覆われていない下地層８９１ａが、不要な下地層８９１ａとして除去される。不要な下地層８９１ａの除去は、先述の不要な下地層８９０ａの除去と同様に、ウェットエッチングにより行われる。この不要な下地層８９１ａを除去する工程を経ることで、図２６に示すように、めっき層８９１ｂおよびこれに覆われた下地層８９１ａによって、配線層８３３が形成される。なお、図２７～図２９においては、めっき層８９１ｂおよびこれに覆われた下地層８９１ａを配線層８３３として一体的に示し、めっき層８９１ｃを、柱状導電体８３１として示す。 In the fifth step, as shown in FIG. 26, the unnecessary base layer 891a is removed. In this embodiment, the underlying layer 891a not covered with the plating layer 891b is removed as an unnecessary underlying layer 891a. The removal of the unnecessary base layer 891a is performed by wet etching, similarly to the removal of the unnecessary base layer 890a described above. Through the step of removing the unnecessary base layer 891a, as shown in FIG. 26, the wiring layer 833 is formed of the plating layer 891b and the base layer 891a covered with the plating layer 891b. 27 to 29, the plating layer 891b and the underlying layer 891a covered therewith are integrally shown as the wiring layer 833, and the plating layer 891c is shown as the columnar conductor 831. As shown in FIG.

以上で示した、５つの工程を経ることで、図２６に示すように、配線層８３３、接合部８５２、および、柱状導電体８３１が形成される。なお、本実施形態においては、下地層８９１ａを形成する工程、めっき層８９１ｃを形成する工程および不要な下地層８９１ａを除去する工程を合わせた工程が、特許請求の範囲に記載の「第２配線層形成工程」に相当する。また、下地層８９１ａを形成する工程、めっき層８９１ｃを形成する工程および不要な下地層８９１ａを除去する工程を合わせた工程が、特許請求の範囲に記載の「第１導電体形成工程」に相当する。 Through the five steps described above, the wiring layer 833, the joint 852, and the columnar conductor 831 are formed as shown in FIG. In the present embodiment, the step of forming the base layer 891a, the step of forming the plated layer 891c, and the step of removing the unnecessary base layer 891a are combined to form the "second wiring" described in the scope of claims. layer forming step”. Further, the step of forming the base layer 891a, the step of forming the plated layer 891c, and the step of removing the unnecessary base layer 891a together correspond to the "first conductor forming step" described in the claims. do.

次いで、図２７に示すように、電子部品８１２を搭載する。電子部品８１２が、電子装置Ａ２の電子部品１２に対応する。電子部品８１２は、ｚ２方向を向く素子主面８１２ａおよびｚ１方向を向く素子裏面８１２ｂを有しており、素子裏面８１２ｂには、電極パッド（図示略）が形成されている。電子部品８１２を搭載する工程（第２電子部品搭載工程）は、フリップチップボンディングにより行う。具体的には、電子部品８１２にフラックスを塗布した後、たとえばフリップチップボンダを用いて電子部品８１２を接合部８５２の上に仮付けする。このとき、接合部８５２は、配線層８３３と、電子部品８１２の素子裏面８１２ｂに形成された電極パッド（図示略）との間に介在した状態となる。その後、接合部８５２の接合層８５２ｂをリフローにより溶融させて、電極パッドと結合させる。そして、接合部８５２の接合層８５２ｂを冷却し固化させる。これにより、電子部品８１２が配線層８３３に搭載され、電子部品８１２の電極パッドと配線層８３３とが接合部８５２を介して導通する。 Next, as shown in FIG. 27, an electronic component 812 is mounted. Electronic component 812 corresponds to electronic component 12 of electronic device A2. The electronic component 812 has an element main surface 812a facing in the z2 direction and an element back surface 812b facing in the z1 direction. Electrode pads (not shown) are formed on the element back surface 812b. The step of mounting the electronic component 812 (second electronic component mounting step) is performed by flip chip bonding. Specifically, after applying flux to the electronic component 812, the electronic component 812 is temporarily attached onto the bonding portion 852 using, for example, a flip chip bonder. At this time, the joint portion 852 is interposed between the wiring layer 833 and the electrode pad (not shown) formed on the back surface 812 b of the electronic component 812 . After that, the bonding layer 852b of the bonding portion 852 is melted by reflow and bonded to the electrode pad. Then, the bonding layer 852b of the bonding portion 852 is cooled and solidified. As a result, the electronic component 812 is mounted on the wiring layer 833 , and the electrode pads of the electronic component 812 and the wiring layer 833 are electrically connected via the bonding portion 852 .

次いで、先述の電子装置Ａ１の製造方法と同様に、第１樹脂層形成工程、第１樹脂層研削工程、配線層８３２を形成する工程、接合部８５１を形成する工程、枠状導電体８６１を形成する工程、第１電子部品搭載工程、第２樹脂層形成工程、および、支持基板除去工程を行う（図６～図１５参考）。なお、本実施形態においては、先述の柱状導電体形成工程は、行わない。 Next, in the same manner as in the above-described method for manufacturing the electronic device A1, a first resin layer forming step, a first resin layer grinding step, a wiring layer 832 forming step, a joint portion 851 forming step, and a frame-shaped conductor 861 are formed. A forming step, a first electronic component mounting step, a second resin layer forming step, and a support substrate removing step are performed (see FIGS. 6 to 15). In addition, in this embodiment, the columnar conductor forming step described above is not performed.

次いで、図２８に示すように、外部保護膜８７１を形成する。外部保護膜８７１を形成する工程（外部保護膜形成工程）においては、配線層裏面８３３ｂの一部（後に外部電極８４０を形成する領域）を除いて、配線層裏面８３３ｂおよび第１樹脂層裏面８２１ｂに跨るように、ポリマー樹脂を形成する。本実施形態においては、ポリマー樹脂として、ポリイミド樹脂あるいはフェノール樹脂などを形成する。形成された外部保護膜８７１は、開口部８７１ａを有しており、当該開口部８７１ａから各配線層裏面８３３ｂの一部がそれぞれ露出する。 Next, as shown in FIG. 28, an external protective film 871 is formed. In the step of forming the external protective film 871 (external protective film forming step), the wiring layer back surface 833b and the first resin layer back surface 821b are removed except for a part of the wiring layer back surface 833b (the region where the external electrodes 840 are to be formed later). A polymer resin is formed so as to straddle the . In this embodiment, a polyimide resin, a phenol resin, or the like is used as the polymer resin. The formed external protective film 871 has an opening 871a, and a part of each wiring layer rear surface 833b is exposed from the opening 871a.

次いで、図２９に示すように、外部電極８４０を形成する。本実施形態における外部電極形成工程は、第１実施形態の外部電極形成工程と同様に、無電解めっきによる。これにより、外部保護膜８７１の開口部８７１ａから露出する各配線層裏面８３３ｂの一部に、Ｎｉ層、Ｐｄ層およびＡｕ層が順次積層される。よって、外部電極８４０は、Ｎｉ層、Ｐｄ層およびＡｕ層が積層された構造である。 Next, as shown in FIG. 29, external electrodes 840 are formed. The external electrode forming process in this embodiment is based on electroless plating, like the external electrode forming process in the first embodiment. As a result, a Ni layer, a Pd layer, and an Au layer are sequentially laminated on a portion of the back surface 833b of each wiring layer exposed from the opening 871a of the external protective film 871. Next, as shown in FIG. Therefore, the external electrode 840 has a structure in which a Ni layer, a Pd layer and an Au layer are laminated.

次いで、第１実施形態と同様に、第２樹脂層研削工程を経て、個片化工程を行う。これにより、図１８～図２１に示す電子装置Ａ２が製造される。なお、先述の電子装置Ａ２の製造方法は、一例であって、これに限定されない。たとえば、電子部品８１２の電極パッドにはんだバンプなどの接合部材が形成されている場合には、先述の接合層８５２ｂを形成する工程により、接合部８５２の接合層８５２ｂを形成しなくてもよい。 Then, similarly to the first embodiment, the singulation process is performed through the second resin layer grinding process. Thus, the electronic device A2 shown in FIGS. 18 to 21 is manufactured. Note that the above-described method for manufacturing the electronic device A2 is merely an example, and the present invention is not limited to this. For example, when bonding members such as solder bumps are formed on the electrode pads of the electronic component 812, the bonding layer 852b of the bonding portion 852 may not be formed by the above-described step of forming the bonding layer 852b.

次に、第２実施形態にかかる電子装置Ａ２およびその製造方法の作用効果について説明する。 Next, the effects of the electronic device A2 and the manufacturing method thereof according to the second embodiment will be described.

電子装置Ａ２によれば、電子装置Ａ１と同様に、第１樹脂層２１および第２樹脂層２２を備えている。第１樹脂層２１は、複数の配線層３２を介して、電子部品１１を支持している。第２樹脂層２２は、第１樹脂層２１の上に形成され、電子部品１１を覆っている。したがって、第１実施形態と同様に、支持部材（第１樹脂層２１）と保護部材（第２樹脂層２２）との熱膨張係数の差を低減することができる。よって、第１実施形態と同様に、支持部材と保護部材との界面における熱応力を緩和できるので、保護部材が支持部材から剥離することを抑制できる。もって、電子装置Ａ２の信頼性を向上できる。 The electronic device A2 includes the first resin layer 21 and the second resin layer 22, like the electronic device A1. The first resin layer 21 supports the electronic component 11 via a plurality of wiring layers 32 . The second resin layer 22 is formed on the first resin layer 21 and covers the electronic component 11 . Therefore, as in the first embodiment, the difference in thermal expansion coefficient between the support member (first resin layer 21) and the protection member (second resin layer 22) can be reduced. Therefore, as in the first embodiment, the thermal stress at the interface between the support member and the protection member can be alleviated, so the separation of the protection member from the support member can be suppressed. Accordingly, the reliability of the electronic device A2 can be improved.

電子装置Ａ２によれば、その他、電子装置Ａ１と同一あるいは類似の構成によって、先述した電子装置Ａ１の効果と同じ効果を奏することができる。 According to the electronic device A2, the same or similar configuration as that of the electronic device A1 can provide the same effects as those of the electronic device A1 described above.

電子装置Ａ２によれば、複数の電子部品１１，１２を備えている。電子部品１１は、第２樹脂層２２に覆われており、電子部品１２は、第１樹脂層２１に覆われている。第１樹脂層２１と第２樹脂層２２とは、ｚ方向に積層されている。よって、電子部品１１と電子部品１２とは、ｚ方向に多段実装された構造となっている。これにより、複数の電子部品１１，１２をｚ方向に重ねることが可能となるので、電子装置Ａ２の平面視寸法を小さくできる。また、各電子部品１１，１２は、第１樹脂層２１および第２樹脂層２２によって、多段実装されており、半導体基板を備えていない。そのため、半導体基板を加工する必要がないので、多段実装の形成が容易となる。 According to the electronic device A2, a plurality of electronic components 11 and 12 are provided. The electronic component 11 is covered with the second resin layer 22 , and the electronic component 12 is covered with the first resin layer 21 . The first resin layer 21 and the second resin layer 22 are laminated in the z direction. Therefore, the electronic component 11 and the electronic component 12 have a structure in which they are mounted in multiple stages in the z direction. As a result, a plurality of electronic components 11 and 12 can be stacked in the z direction, so that the planar view size of the electronic device A2 can be reduced. Further, each electronic component 11, 12 is multi-stage mounted by the first resin layer 21 and the second resin layer 22, and does not have a semiconductor substrate. Therefore, since it is not necessary to process the semiconductor substrate, it becomes easy to form multistage mounting.

第２実施形態において、電子部品１２の構造は、先述のものに限定されない。図３０は、電子部品１２の構造が異なる場合の電子装置を示している。図３０は、このような変形例にかかる電子装置を示す断面図であって、図２０の断面に対応する。本変形例における電子部品１２は、図３０に示すように、ｘ方向の両端に電極が形成されたものである。このような構造の電子部品１２には、たとえばチップコンデンサやチップ抵抗器などがある。図３０においては、接合部５３によって、電子部品１２が各配線層８３３に接合されている。接合部５３は、はんだペーストあるいは銀ペーストなどの導電性接合材である。接合部５３には、フィレットが形成されている。 In the second embodiment, the structure of the electronic component 12 is not limited to that described above. FIG. 30 shows an electronic device in which the electronic component 12 has a different structure. FIG. 30 is a cross-sectional view showing an electronic device according to such a modification, and corresponds to the cross-section of FIG. As shown in FIG. 30, the electronic component 12 in this modified example has electrodes formed at both ends in the x direction. Electronic components 12 having such a structure include, for example, chip capacitors and chip resistors. In FIG. 30 , the electronic component 12 is joined to each wiring layer 833 by the joints 53 . The joint portion 53 is a conductive joint material such as solder paste or silver paste. A fillet is formed in the joint portion 53 .

＜第３実施形態＞
図３１は、第３実施形態にかかる電子装置を示している。第３実施形態の電子装置Ａ３は、電子装置Ａ２と比較して、主に、素子主面１２１が第１樹脂層２１から露出している点で異なる。 <Third Embodiment>
FIG. 31 shows an electronic device according to the third embodiment. The electronic device A3 of the third embodiment differs from the electronic device A2 mainly in that the element main surface 121 is exposed from the first resin layer 21 .

図３１は、電子装置Ａ３を示す断面図であって、電子装置Ａ２における図２０の断面に対応する。 FIG. 31 is a cross-sectional view showing the electronic device A3 and corresponds to the cross-section of FIG. 20 for the electronic device A2.

電子装置Ａ３において、電子部品１２の素子主面１２１は、第１樹脂層２１の第１樹脂層主面２１１から露出している。本実施形態においては、素子主面１２１と第１樹脂層主面２１１とは面一である。素子主面１２１を第１樹脂層主面２１１から露出させるには、たとえば、先述の第１樹脂層研削工程において、電子部品８１２の素子主面８１２ａが露出するまで、第１樹脂層８２１を研削すればよい。 In the electronic device A<b>3 , the element main surface 121 of the electronic component 12 is exposed from the first resin layer main surface 211 of the first resin layer 21 . In this embodiment, the element main surface 121 and the first resin layer main surface 211 are flush with each other. In order to expose the element main surface 121 from the first resin layer main surface 211, for example, in the above-described first resin layer grinding step, the first resin layer 821 is ground until the element main surface 812a of the electronic component 812 is exposed. do it.

素子保護膜７２は、絶縁性を有する被膜である。素子保護膜７２は、電子部品１２の素子主面１２１を覆っている。素子保護膜７２は、平面視において、電子部品１２に重なる。素子保護膜７２の構成材料は、外部保護膜７１と同様に、ポリマー樹脂である。なお、素子保護膜７２の構成材料は、これに限定されない。素子保護膜７２の形成は、たとえば、第１樹脂層研削工程後であって、下地層８９１ａを形成する工程の前に行われる。なお、素子保護膜７２の形成は、このタイミングに限定されない。本実施形態においては、電子装置Ａ３が素子保護膜７２を備えている場合を示すが、これを備えていなくてもよい。 The element protective film 72 is a film having insulating properties. The element protection film 72 covers the element main surface 121 of the electronic component 12 . The element protective film 72 overlaps the electronic component 12 in plan view. The constituent material of the element protection film 72 is a polymer resin, like the external protection film 71 . Note that the constituent material of the device protection film 72 is not limited to this. The element protective film 72 is formed, for example, after the first resin layer grinding step and before the step of forming the base layer 891a. Note that the formation of the device protective film 72 is not limited to this timing. In this embodiment, the electronic device A3 is provided with the device protective film 72, but it may not be provided with it.

次に、第３実施形態にかかる電子装置Ａ３およびその製造方法の作用効果について説明する。 Next, the effects of the electronic device A3 and the manufacturing method thereof according to the third embodiment will be described.

電子装置Ａ３によれば、電子装置Ａ１と同様に、第１樹脂層２１および第２樹脂層２２を備えている。第１樹脂層２１は、複数の配線層３２を介して、電子部品１１を支持している。第２樹脂層２２は、第１樹脂層２１の上に形成され、電子部品１１を覆っている。したがって、第１実施形態と同様に、支持部材（第１樹脂層２１）と保護部材（第２樹脂層２２）との熱膨張係数の差を低減することができる。よって、第１実施形態と同様に、支持部材と保護部材との界面における熱応力を緩和できるので、保護部材が支持部材から剥離することを抑制できる。もって、電子装置Ａ３の信頼性を向上できる。 The electronic device A3 includes the first resin layer 21 and the second resin layer 22, like the electronic device A1. The first resin layer 21 supports the electronic component 11 via a plurality of wiring layers 32 . The second resin layer 22 is formed on the first resin layer 21 and covers the electronic component 11 . Therefore, as in the first embodiment, the difference in thermal expansion coefficient between the support member (first resin layer 21) and the protection member (second resin layer 22) can be reduced. Therefore, as in the first embodiment, the thermal stress at the interface between the support member and the protection member can be alleviated, so the separation of the protection member from the support member can be suppressed. Accordingly, the reliability of the electronic device A3 can be improved.

電子装置Ａ３によれば、その他、電子装置Ａ１，Ａ２と同一あるいは類似の構成によって、先述した電子装置Ａ１，Ａ２の効果と同じ効果を奏することができる。 According to the electronic device A3, the same or similar configuration as that of the electronic devices A1 and A2 can provide the same effects as those of the electronic devices A1 and A2 described above.

電子装置Ａ３によれば、第１樹脂層研削工程において、電子部品８１２の素子主面８１２ａが露出するまで、第１樹脂層８２１を研削している。この構成によると、電子装置Ａ３のｚ方向の寸法を小さくできる。よって、電子装置Ａ３の小型化を図ることができる。 According to the electronic device A3, in the first resin layer grinding process, the first resin layer 821 is ground until the element main surface 812a of the electronic component 812 is exposed. With this configuration, the size of the electronic device A3 in the z direction can be reduced. Therefore, it is possible to reduce the size of the electronic device A3.

電子装置Ａ３によれば、電子部品１２の素子主面１２１を覆う素子保護膜７２を備えている。電子装置Ａ３において、電子部品１２の素子主面１２１が第１樹脂層２１から露出しているため、電子装置Ａ３の製造過程で、素子主面１２１に、何らかの導電体が意図せず形成される可能性がある。よって、電子部品１２に意図せぬ短絡が生じる虞がある。そこで、素子保護膜７２を形成することで、電子部品１２の全面が、第１樹脂層２１および素子保護膜７２によって覆われるため、電子部品１２の意図せぬ短絡を抑制することができる。よって、電子装置Ａ３の信頼性を向上できる。 According to the electronic device A3, the element protective film 72 covering the element main surface 121 of the electronic component 12 is provided. In the electronic device A3, since the element main surface 121 of the electronic component 12 is exposed from the first resin layer 21, some kind of conductor is unintentionally formed on the element main surface 121 during the manufacturing process of the electronic device A3. there is a possibility. Therefore, an unintended short circuit may occur in the electronic component 12 . Therefore, by forming the element protective film 72 , the entire surface of the electronic component 12 is covered with the first resin layer 21 and the element protective film 72 , so that an unintended short circuit of the electronic component 12 can be suppressed. Therefore, the reliability of the electronic device A3 can be improved.

以下に、本開示の電子装置におけるその他の変形例について説明する。以下に示す各変形例は、適宜組み合わせることが可能である。 Other modifications of the electronic device of the present disclosure will be described below. Modifications shown below can be combined as appropriate.

本開示の電子装置は、第２樹脂層２２の第２樹脂層主面２２１の上に、金属製の被膜が形されていてもよい。図３２は、第１実施形態の電子装置Ａ１において、当該金属製の被膜（金属膜６２）を備えた場合を示している。図３２は、このような変形例にかかる電子装置を示す断面図であって、図３の断面に対応する。金属膜６２の構成材料は、たとえばＴｉ層、Ｃｕ層およびステンレス層が順に積層されたものである。金属膜６２の形成は、たとえばスパッタリングによる。なお、金属膜６２の構成材料および形成方法は、これに限定されない。金属膜６２は、枠状導電体６１の頂面６１３に接している。このように、金属膜６２を設けた場合、電子部品１１が完全に覆われるため、外部からの妨害電磁波を遮断することができる。なお、電子装置Ａ２，Ａ３においても、金属膜６２をさらに備えていてもよい。 In the electronic device of the present disclosure, a metal coating may be formed on the second resin layer major surface 221 of the second resin layer 22 . FIG. 32 shows a case where the electronic device A1 of the first embodiment is provided with the metal coating (metal film 62). FIG. 32 is a cross-sectional view showing an electronic device according to such a modification, and corresponds to the cross-section of FIG. The constituent material of the metal film 62 is, for example, a Ti layer, a Cu layer and a stainless steel layer laminated in order. The metal film 62 is formed by sputtering, for example. Note that the constituent material and formation method of the metal film 62 are not limited to this. The metal film 62 is in contact with the top surface 613 of the frame-shaped conductor 61 . In this way, when the metal film 62 is provided, the electronic component 11 is completely covered, so that external interfering electromagnetic waves can be blocked. Note that the electronic devices A2 and A3 may further include the metal film 62 .

本開示の電子装置において、各外部電極４０の構成は、第１実施形態ないし第３実施形態で示した構成に限定されない。たとえば、各外部電極４０は、球体状のはんだバンプ（はんだボール）であってもよい。図３３は、第１実施形態の電子装置Ａ１において、各外部電極４０をはんだボールで構成した場合を示している。図３３は、このような変形例にかかる電子装置を示す断面図であって、図３の断面に対応する。なお、電子装置Ａ２，Ａ３においても、各外部電極４０がはんだボールで構成されていてもよい。 In the electronic device of the present disclosure, the configuration of each external electrode 40 is not limited to the configurations shown in the first to third embodiments. For example, each external electrode 40 may be a spherical solder bump (solder ball). FIG. 33 shows a case where each external electrode 40 is configured by a solder ball in the electronic device A1 of the first embodiment. FIG. 33 is a cross-sectional view showing an electronic device according to such a modification, and corresponds to the cross-section of FIG. Also in the electronic devices A2 and A3, each external electrode 40 may be formed of a solder ball.

本開示の電子装置において、各接合部５１の構成は、第１実施形態ないし第３実施形態で示した構成に限定されない。図３４～図３６は、第１実施形態の電子装置Ａ１において、接合部５１の構造が異なる場合の一例を示している。図３４～図３６は、各変形例にかかる電子装置を示す部分拡大断面図であって、図４の部分拡大断面図に対応する。なお、電子装置Ａ１に限らず、電子装置Ａ２，Ａ３においても、同様に構成できる。また、第２実施形態および第３実施形態で示した接合部５２においても、図３４～図３６のそれぞれに示す接合部５１と同様に構成してもよい。 In the electronic device of the present disclosure, the configuration of each joint 51 is not limited to the configurations shown in the first to third embodiments. 34 to 36 show examples of the electronic device A1 of the first embodiment in which the structure of the joint 51 is different. 34 to 36 are partially enlarged cross-sectional views showing electronic devices according to modifications, and correspond to the partially enlarged cross-sectional view of FIG. It should be noted that not only the electronic device A1 but also the electronic devices A2 and A3 can be similarly configured. Also, the joint portion 52 shown in the second and third embodiments may be configured in the same manner as the joint portion 51 shown in FIGS.

図３４に示す接合部５１において、絶縁層５１１は、たとえば各配線層３２を覆うソルダーレジストである。絶縁層５１１は、各配線層３２の上の一部が開口している。接合層５１２は、一部が絶縁層５１１において開口した部分に充填されている。接合層５１２は、図３４に示すように、互いに積層された第１層５１２ａ、第２層５１２ｂ、第３層５１２ｃおよび第４層５１２ｄから構成される。第１層５１２ａは、互いに積層されたＴｉ層およびＣｕ層から構成される。当該Ｔｉ層が各配線層３２に接する。第１層５１２ａは、例えばスパッタリングにより形成されうる。第２層５１２ｂの構成材料は、Ｃｕを含む金属である。第３層５１２ｃの構成材料は、Ｎｉを含む金属である。第４層５１２ｄの構成材料は、たとえばＳｎを含む合金である。この合金を例示すると、Ｓｎ－Ｓｂ系合金またはＳｎ－Ａｇ系合金などの鉛フリーはんだである。第２層５１２ｂ、第３層５１２ｃおよび第４層５１２ｄは、例えば電解めっきによりそれぞれ形成されうる。 In the joint portion 51 shown in FIG. 34, the insulating layer 511 is, for example, a solder resist covering each wiring layer 32 . The insulating layer 511 is partially opened above each wiring layer 32 . The bonding layer 512 partially fills the opening in the insulating layer 511 . The bonding layer 512 is composed of a first layer 512a, a second layer 512b, a third layer 512c and a fourth layer 512d, which are laminated to each other, as shown in FIG. The first layer 512a is composed of a Ti layer and a Cu layer laminated together. The Ti layer is in contact with each wiring layer 32 . The first layer 512a can be formed by sputtering, for example. The constituent material of the second layer 512b is a metal containing Cu. The constituent material of the third layer 512c is a metal containing Ni. The constituent material of the fourth layer 512d is, for example, an alloy containing Sn. Examples of this alloy are lead-free solders such as Sn--Sb based alloys or Sn--Ag based alloys. The second layer 512b, the third layer 512c and the fourth layer 512d can each be formed by electroplating, for example.

図３５に示す接合部５１において、接合層５１２は、第１層５１２ａ、第３層５１２ｃおよび第４層５１２ｄから構成されている。つまり、図３４に示す態様と比較して、第２層５１２ｂを含んでいない。なお、絶縁層５１１は、図３４に示す態様と同じである。 In the joint portion 51 shown in FIG. 35, the joint layer 512 is composed of a first layer 512a, a third layer 512c and a fourth layer 512d. That is, it does not include the second layer 512b as compared to the embodiment shown in FIG. Note that the insulating layer 511 is the same as that shown in FIG.

図３６に示す接合部５１においては、絶縁層５１１を含んでおらず、接合層５１２から構成されている。接合層５１２は、たとえばＳｎを含む合金である。この合金は、たとえば、Ｓｎ－Ｓｂ系合金またはＳｎ－Ａｇ系合金などの鉛フリーはんだである。図３６において、電子部品１１の電極パッド１３を図示している。電極パッド１３は、互いに積層された第１層１３１および第２層１３２から構成される。第１層１３１は、たとえばＣｕを含む金属層であり、第２層１３２は、たとえばＮｉを含む金属層である。なお、図３６の変形例において、接合部５１に、絶縁層５１１を追加してもよい。 The bonding portion 51 shown in FIG. 36 does not include the insulating layer 511 and is composed of the bonding layer 512 . Bonding layer 512 is, for example, an alloy containing Sn. This alloy is, for example, a lead-free solder such as a Sn--Sb-based alloy or a Sn--Ag-based alloy. In FIG. 36, the electrode pads 13 of the electronic component 11 are illustrated. The electrode pad 13 is composed of a first layer 131 and a second layer 132 laminated together. The first layer 131 is a metal layer containing Cu, for example, and the second layer 132 is a metal layer containing Ni, for example. In addition, in the modification of FIG. 36 , an insulating layer 511 may be added to the joint portion 51 .

本開示の電子装置において、枠状導電体６１を備えていなくてもよい。図３７は、このような変形例にかかる電子装置を示している。図３７は、本変形例にかかる電子装置を示す断面図であって、図３の断面に対応する。なお、図３７は、第１実施形態の電子装置Ａ１において、枠状導電体６１を備えない場合を示しているが、電子装置Ａ２，Ａ３においても同様に構成できる。 The electronic device of the present disclosure may not include the frame-shaped conductor 61 . FIG. 37 shows an electronic device according to such a modification. FIG. 37 is a cross-sectional view showing an electronic device according to this modification, and corresponds to the cross-section of FIG. Although FIG. 37 shows the case where the frame-shaped conductor 61 is not provided in the electronic device A1 of the first embodiment, the electronic devices A2 and A3 can be configured in the same manner.

本開示の電子装置において、電子部品１１の素子主面１１１が第２樹脂層２２の第２樹脂層主面２２１から露出していてもよい。図３８は、このような変形例にかかる電子装置を示している。図３８は、本変形例にかかる電子装置を示す断面図であって、図３の断面に対応する。なお、図３８は、第１実施形態の電子装置Ａ１において、素子主面１１１を第２樹脂層主面２２１から露出させた場合を示しているが、電子装置Ａ２，Ａ３においても同様に構成できる。たとえば、第２樹脂層研削工程において、電子部品８１１の素子主面８１１ａが露出するまで、第２樹脂層８２２を研削することで製造される。なお、本変形例においては、電子部品１１の素子主面１１１が、電子装置の外部に露出するため、当該素子主面１１１を覆う保護膜を形成しておくとよい。本変形例においては、電子部品１１の素子主面１１１が露出するまで、第２樹脂層２２を研削するため、第２樹脂層２２の厚さ（ｚ方向寸法）を小さくできる。したがって、電子装置の厚さ（ｚ方向寸法）を小さくできるので、電子装置の小型化を図ることができる。さらに、電子部品１１の素子主面１１１が第２樹脂層２２から露出しているので、電子部品１１からの熱の放熱性が向上できる。 In the electronic device of the present disclosure, element main surface 111 of electronic component 11 may be exposed from second resin layer main surface 221 of second resin layer 22 . FIG. 38 shows an electronic device according to such a modification. FIG. 38 is a cross-sectional view showing an electronic device according to this modification, and corresponds to the cross-section of FIG. Although FIG. 38 shows the case where the element main surface 111 is exposed from the second resin layer main surface 221 in the electronic device A1 of the first embodiment, the electronic devices A2 and A3 can be configured in the same manner. . For example, in the second resin layer grinding step, the second resin layer 822 is ground until the element main surface 811a of the electronic component 811 is exposed. In addition, in this modification, since the element main surface 111 of the electronic component 11 is exposed to the outside of the electronic device, it is preferable to form a protective film covering the element main surface 111 . In this modification, since the second resin layer 22 is ground until the element main surface 111 of the electronic component 11 is exposed, the thickness (z-direction dimension) of the second resin layer 22 can be reduced. Therefore, the thickness (dimension in the z direction) of the electronic device can be reduced, so that the size of the electronic device can be reduced. Furthermore, since the element main surface 111 of the electronic component 11 is exposed from the second resin layer 22, the heat radiation from the electronic component 11 can be improved.

本開示の電子装置において、配線層３２の形成範囲は、第１実施形態ないし第３実施形態で示した態様に限定されない。たとえば、電子部品１１の素子裏面１１２に形成された電極パッドの数や位置、および、電子装置の端子（外部電極４０）の数や位置などに応じて、適宜変更可能である。図３９および図４０は、第１実施形態の電子装置Ａ１において、配線層３２の形成範囲が異なる場合を示している。図３９および図４０は、このような変形例にかかる電子装置を示す平面図である。なお、図３９および図４０に示す態様は、一例であって、これらに限定されるものではない。図３９および図４０においては、電子部品１１には８つの電極パッドが形成されており、形成された電極パッドの数に応じて、適宜配線層３２の形成範囲を変えている。なお、電子装置Ａ２，Ａ３においても、配線層３２の形成範囲を適宜変更可能である。 In the electronic device of the present disclosure, the formation range of the wiring layer 32 is not limited to the aspects shown in the first to third embodiments. For example, the number and positions of the electrode pads formed on the element back surface 112 of the electronic component 11 and the number and positions of the terminals (external electrodes 40) of the electronic device can be appropriately changed. FIGS. 39 and 40 show cases where the formation range of the wiring layer 32 is different in the electronic device A1 of the first embodiment. 39 and 40 are plan views showing electronic devices according to such modifications. Note that the modes shown in FIGS. 39 and 40 are only examples, and the present invention is not limited to these. In FIGS. 39 and 40, eight electrode pads are formed on the electronic component 11, and the formation range of the wiring layer 32 is appropriately changed according to the number of formed electrode pads. Also in the electronic devices A2 and A3, the formation range of the wiring layer 32 can be appropriately changed.

本開示の電子装置において、配線層３３の形成範囲は、第２実施形態および第３実施形態で示した態様に限定されない。配線層３３の形成範囲は、先述の配線層３２と同様に、適宜変更可能である。たとえば、電子部品１１の電極パッドの数や位置、電子部品１２の電極パッドの数や位置、電子部品１１と電子部品１２との導通経路、および、電子装置の端子（外部電極４０）の数や位置などに応じて、適宜変更可能である。 In the electronic device of the present disclosure, the formation range of the wiring layer 33 is not limited to the modes shown in the second and third embodiments. The formation range of the wiring layer 33 can be changed as appropriate in the same manner as the wiring layer 32 described above. For example, the number and positions of the electrode pads of the electronic component 11, the number and positions of the electrode pads of the electronic component 12, the conductive paths between the electronic components 11 and 12, and the number and positions of the terminals (external electrodes 40) of the electronic device. It can be changed as appropriate according to the position or the like.

本開示の電子装置において、電子部品１１と電子部品１２とは、平面視において重なっていなくてもよい。図４１は、このような変形例にかかる電子装置を示している。図４１は、当該電子装置を示す平面図であって、封止樹脂２０を想像線で示している。図４１に示す態様においては、平面視において、先述の通り、電子部品１１と電子部品１２とが重なっておらず、ｘ方向に並んでいる。また、図４１に示す態様においては、平面視において、電子部品１１と電子部品１２とが完全に重なっていない場合を示しているが、一部が重なり合う構成でもよい。 In the electronic device of the present disclosure, electronic component 11 and electronic component 12 do not have to overlap in plan view. FIG. 41 shows an electronic device according to such a modification. FIG. 41 is a plan view showing the electronic device, showing the sealing resin 20 with imaginary lines. In the mode shown in FIG. 41, in plan view, the electronic components 11 and 12 do not overlap and are arranged in the x direction as described above. Moreover, although the aspect shown in FIG. 41 shows the case where the electronic component 11 and the electronic component 12 do not completely overlap in plan view, they may be partially overlapped.

本開示の電子装置において、電子部品１１の数および電子部品１２の数は特に限定されない。図４２は、このような変形例にかかる電子装置を示している。図４２は、当該電子装置を示す平面図であって、第２実施形態の図１９に対応する。図４２に示す態様においては、２つの電子部品１２を備えており、各電子部品１２がそれぞれ各配線層３３に接合されている。なお、図４２においては、２つの電子部品１２を備えている場合を示したが、それ以上の電子部品１２を備えていてもよい。また、電子部品１１の数も２つ以上備えていてもよい。 In the electronic device of the present disclosure, the number of electronic components 11 and the number of electronic components 12 are not particularly limited. FIG. 42 shows an electronic device according to such a modification. FIG. 42 is a plan view showing the electronic device, and corresponds to FIG. 19 of the second embodiment. In the embodiment shown in FIG. 42, two electronic components 12 are provided, and each electronic component 12 is joined to each wiring layer 33, respectively. Although FIG. 42 shows a case in which two electronic components 12 are provided, more electronic components 12 may be provided. Also, two or more electronic components 11 may be provided.

本開示の電子装置において、外部電極４０の構成は、第１実施形態ないし第３実施形態で示した態様に限定されない。図４３は、外部電極４０が柱状導電体被覆部４１および配線層被覆部４２の両方を含んでいる場合を示している。図４４は、第２実施形態の電子装置Ａ２において、外部電極４０が配線層被覆部４２を含まず、柱状導電体被覆部４１を含んでいる場合を示している。図４３および図４４はともに、本変形例にかかる電子装置を示す断面図であって、図２０の断面に対応する。図４３に示す態様においては、柱状導電体３１が配線層３３の上に形成されておらず、電子部品１１と電子部品１２とが電子装置の内部で導通していない。電子部品１１は、接合部５１、配線層３２および柱状導電体３１を介して、柱状導電体被覆部４１（外部電極４０）に導通する。電子部品１２は、接合部５２および配線層３３を介して、配線層被覆部４２（外部電極４０）に導通する。よって、図４３に示す電子装置においては、柱状導電体被覆部４１は、電子部品１１に導通する端子であり、配線層被覆部４２は、電子部品１２に導通する端子である。図４４に示す態様においては、第１樹脂層２１の第１樹脂層主面２１１から第１樹脂層裏面２１２までｚ方向に貫通する第１の柱状導電体３１と、配線層３３の上に形成された第２の柱状導電体３１とを備えている。電子部品１１は、接合部５１、配線層３２および第１の柱状導電体３１を介して、柱状導電体被覆部４１（外部電極４０）に導通する。電子部品１２は、接合部５２、配線層３３、第２の柱状導電体３１、配線層３２および第１の柱状導電体３１を介して、柱状導電体被覆部４１（外部電極４０）に導通する。よって、図４４に示す電子装置においては、配線層被覆部４２（外部電極４０）は、電子部品１１および電子部品１２の両方に導通する端子である。 In the electronic device of the present disclosure, the configuration of the external electrodes 40 is not limited to the modes shown in the first to third embodiments. FIG. 43 shows a case where the external electrode 40 includes both the columnar conductor covering portion 41 and the wiring layer covering portion 42 . FIG. 44 shows a case where the external electrode 40 does not include the wiring layer covering portion 42 but includes the columnar conductor covering portion 41 in the electronic device A2 of the second embodiment. 43 and 44 are cross-sectional views showing the electronic device according to this modification, and correspond to the cross-section of FIG. In the embodiment shown in FIG. 43, columnar conductor 31 is not formed on wiring layer 33, and electronic component 11 and electronic component 12 are not electrically connected inside the electronic device. The electronic component 11 is electrically connected to the columnar conductor covering portion 41 (external electrode 40 ) through the joint portion 51 , the wiring layer 32 and the columnar conductor 31 . The electronic component 12 is electrically connected to the wiring layer cover portion 42 (external electrode 40 ) through the joint portion 52 and the wiring layer 33 . Therefore, in the electronic device shown in FIG. 43 , the columnar conductor covering portion 41 is a terminal electrically connected to the electronic component 11 , and the wiring layer covering portion 42 is a terminal electrically connected to the electronic component 12 . In the embodiment shown in FIG. 44, the first columnar conductors 31 penetrating from the first resin layer main surface 211 of the first resin layer 21 to the first resin layer rear surface 212 in the z-direction and formed on the wiring layer 33 . and a second columnar conductor 31 that has been formed. The electronic component 11 is electrically connected to the columnar conductor covering portion 41 (external electrode 40 ) via the joint portion 51 , the wiring layer 32 and the first columnar conductor 31 . The electronic component 12 is electrically connected to the columnar conductor covering portion 41 (external electrode 40) via the joint portion 52, the wiring layer 33, the second columnar conductor 31, the wiring layer 32, and the first columnar conductor 31. . Therefore, in the electronic device shown in FIG. 44 , wiring layer covering portion 42 (external electrode 40 ) is a terminal electrically connected to both electronic component 11 and electronic component 12 .

本開示の電子装置において、封止樹脂２０の構成は、第１実施形態ないし第３実施形態で示した態様に限定されず、第１樹脂層２１および第２樹脂層２２だけでなく、さらに１つ以上の樹脂層が積層された構成であってもよい。この場合、複数の樹脂層ごとに、各樹脂層を貫通する導電体、各樹脂層に覆われた電子部品、および、当該電子部品に導通する配線層を備えることで、電子装置Ａ２，Ａ３よりもさらなる多段実装構造を提供することができる。 In the electronic device of the present disclosure, the configuration of the sealing resin 20 is not limited to the aspects shown in the first to third embodiments, and not only the first resin layer 21 and the second resin layer 22 but also one A structure in which one or more resin layers are laminated may be used. In this case, for each of the plurality of resin layers, by providing a conductor passing through each resin layer, an electronic component covered with each resin layer, and a wiring layer conducting to the electronic component, the electronic devices A2 and A3 can also provide a further multi-stage mounting structure.

本開示にかかる電子装置およびその製造方法は、上記した実施形態に限定されるものではない。本開示の電子装置の各部の具体的な構成および本開示の電子装置の製造方法の各工程の具体的な処理は、種々に設計変更自在である。 The electronic device and manufacturing method thereof according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the electronic device of the present disclosure and the specific processing of each step of the method of manufacturing the electronic device of the present disclosure can be modified in various ways.

本開示にかかる電子装置およびその製造方法は、以下の付記に関する実施形態を含む。
［付記１］
第１方向において互いに反対側を向く第１樹脂層主面および第１樹脂層裏面を有する第１樹脂層と、
前記第１方向において互いに反対側を向く第１導電体主面および第１導電体裏面を有し、前記第１樹脂層を前記第１方向に貫通する第１導電体と、
前記第１樹脂層主面と前記第１導電体主面とに跨る第１配線層と、
前記第１方向において前記第１樹脂層主面と同じ側を向く第１素子主面および前記第１樹脂層裏面と同じ側を向く第１素子裏面を有し、前記第１配線層に導通接合された第１電子部品と、
前記第１樹脂層主面と同じ方向を向く第２樹脂層主面および前記第１樹脂層主面に接する第２樹脂層裏面を有し、前記第１配線層および前記第１電子部品を覆う第２樹脂層と、
前記第１樹脂層よりも前記第１樹脂層裏面が向く方向側に配置され、前記第１導電体に導通する外部電極と、を備えることを特徴とする電子装置。
［付記２］
前記第１樹脂層主面には、研削痕が形成されている、付記１に記載の電子装置。
［付記３］
前記第１導電体主面は、前記第１樹脂層主面に対して、窪んでいる、付記２に記載の電子装置。
［付記４］
前記第１方向において互いに反対側を向く第２配線層主面および第２配線層裏面を有する第２配線層をさらに備えており、
前記第２配線層裏面は、前記第１樹脂層裏面から露出している、付記１ないし付記３のいずれかに記載の電子装置。
［付記５］
前記第１電子部品と異なる第２電子部品をさらに備えており、
前記第２電子部品は、前記第２配線層に導通接合され、少なくとも一部が前記第１樹脂層に覆われている、付記４に記載の電子装置。
［付記６］
前記第２電子部品は、前記第１素子主面と同じ方向を向く第２素子主面を有しており、
前記第２素子主面は、前記第１樹脂層主面と面一である、付記５に記載の電子装置。
［付記７］
前記外部電極は、前記第１導電体裏面を覆う第１導電体被覆部を含んでいる、
付記１ないし付記６のいずれかに記載の電子装置。
［付記８］
前記外部電極は、前記第２配線層裏面の一部を覆う第２配線層被覆部を含んでいる、付記４ないし付記６のいずれかに記載の電子装置。
［付記９］
前記第２配線層裏面のうち前記外部電極から露出する部分を覆う保護膜をさらに備えている、付記８に記載の電子装置。
［付記１０］
前記第１導電体裏面は、前記第２配線層主面に接している、付記８または付記９に記載の電子装置。
［付記１１］
前記第１電子部品と前記第１配線層とを接合する導電性接合層をさらに備えており、
前記第１配線層は、前記第１方向に見て、一部が前記第１電子部品に重なり、
前記導電性接合層は、前記第１素子裏面と前記第１配線層との間に介在する、付記１ないし付記１０のいずれかに記載の電子装置。
［付記１２］
前記第２樹脂層を前記第１方向に貫通する第２導電体をさらに備えており、
前記第２導電体は、前記第１方向に見て、前記第１電子部品の周囲に配置されている、付記１ないし付記１１のいずれかに記載の電子装置。
［付記１３］
前記第２導電体は、前記第１方向に見て、前記第１配線層から離間している、付記１２に記載の電子装置。
［付記１４］
前記第２導電体は、前記第１方向に見て、前記第１電子部品を包囲している、付記１３に記載の電子装置。
［付記１５］
前記第２導電体は、前記第１方向において前記第２樹脂層主面と同じ方向を向く第２導電体主面を有しており、
前記第２導電体主面は、前記第２樹脂層主面から露出している、付記１２ないし付記１４のいずれかに記載の電子装置。
［付記１６］
前記第１方向に見て、前記第１電子部品に重なり、かつ、前記第２樹脂層主面の上に形成された金属膜をさらに備えている、付記１５に記載の電子装置。
［付記１７］
前記金属膜は、前記第２導電体主面に接する、付記１６に記載の電子装置。
［付記１８］
前記第２導電体主面は、前記第２樹脂層主面に対して、窪んでいる、付記１５ないし付記１７のいずれかに記載の電子装置。
［付記１９］
前記第１電子部品は、半導体を材料とする半導体素子である、付記１ないし付記１８のいずれかに記載の電子装置。
［付記２０］
第１方向において互いに反対側を向く基板主面および基板裏面を有する支持基板を用意する支持基板用意工程と、
前記基板主面の上に、第１導電体を形成する第１導電体形成工程と、
前記第１導電体を覆う第１樹脂層を形成する第１樹脂層形成工程と、
前記第１方向において前記基板主面が向く側から前記基板裏面が向く側に前記第１樹脂層を研削し、前記第１導電体の一部を前記第１樹脂層から露出させることで、各々が前記第１方向において前記基板主面と同じ側を向く第１導電体主面および第１樹脂層主面を形成する第１樹脂層研削工程と、
前記第１樹脂層主面と前記第１導電体主面とに跨る第１配線層を形成する第１配線層形成工程と、
前記第１配線層の上に、第１電子部品を導通接合する第１電子部品搭載工程と、
前記第１配線層および前記第１電子部品を覆う第２樹脂層を形成する第２樹脂層形成工程と、
前記支持基板を除去することで、前記第１方向において前記第１樹脂層主面と反対側を向く第１樹脂層裏面を露出させる支持基板除去工程と、
前記第１樹脂層よりも前記第１樹脂層裏面が向く方向側に配置され、前記第１導電体に導通する外部電極を形成する外部電極形成工程と、を有することを特徴とする電子装置の製造方法。
［付記２１］
前記支持基板用意工程の後であり、前記第１導電体形成工程の前に、前記基板主面の一部を覆う第２配線層を形成する第２配線層形成工程をさらに有しており、
前記第１導電体形成工程では、前記第２配線層の上に、前記第１導電体を形成する、付記２０に記載の電子装置の製造方法。
［付記２２］
前記第２配線層の上に、第２電子部品を導通接合する第２電子部品搭載工程をさらに有する、付記２１に記載の電子装置の製造方法。
［付記２３］
前記第１樹脂層研削工程の後であって、前記第２樹脂層形成工程の前に、前記第１樹脂層の一部の上に、第２導電体を形成する第２導電体形成工程をさらに有している、
付記２０ないし付記２２のいずれかに記載の電子装置の製造方法。 An electronic device and a manufacturing method thereof according to the present disclosure include embodiments related to the following notes.
[Appendix 1]
a first resin layer having a first resin layer main surface and a first resin layer back surface facing opposite to each other in the first direction;
a first conductor having a first conductor main surface and a first conductor back surface facing opposite to each other in the first direction and penetrating the first resin layer in the first direction;
a first wiring layer extending over the main surface of the first resin layer and the main surface of the first conductor;
It has a first element main surface facing the same side as the first resin layer main surface in the first direction and a first element back surface facing the same side as the first resin layer back surface, and is electrically connected to the first wiring layer. a first electronic component;
It has a second resin layer main surface facing the same direction as the first resin layer main surface and a second resin layer back surface in contact with the first resin layer main surface, and covers the first wiring layer and the first electronic component. a second resin layer;
An electronic device, comprising: an external electrode disposed on a side of the first resin layer in a direction toward which the back surface of the first resin layer faces, and electrically connected to the first conductor.
[Appendix 2]
The electronic device according to appendix 1, wherein grinding marks are formed on the main surface of the first resin layer.
[Appendix 3]
The electronic device according to appendix 2, wherein the first conductor main surface is recessed with respect to the first resin layer main surface.
[Appendix 4]
further comprising a second wiring layer having a second wiring layer main surface and a second wiring layer back surface facing opposite to each other in the first direction;
3. The electronic device according to any one of appendices 1 to 3, wherein the back surface of the second wiring layer is exposed from the back surface of the first resin layer.
[Appendix 5]
further comprising a second electronic component different from the first electronic component,
The electronic device according to appendix 4, wherein the second electronic component is conductively joined to the second wiring layer and at least partially covered with the first resin layer.
[Appendix 6]
The second electronic component has a second element main surface facing in the same direction as the first element main surface,
The electronic device according to appendix 5, wherein the second element main surface is flush with the first resin layer main surface.
[Appendix 7]
The external electrode includes a first conductor covering portion covering the back surface of the first conductor,
The electronic device according to any one of appendices 1 to 6.
[Appendix 8]
7. The electronic device according to any one of appendices 4 to 6, wherein the external electrode includes a second wiring layer covering portion covering part of the back surface of the second wiring layer.
[Appendix 9]
The electronic device according to appendix 8, further comprising a protective film covering a portion of the back surface of the second wiring layer that is exposed from the external electrode.
[Appendix 10]
The electronic device according to appendix 8 or 9, wherein the back surface of the first conductor is in contact with the main surface of the second wiring layer.
[Appendix 11]
further comprising a conductive bonding layer that bonds the first electronic component and the first wiring layer,
the first wiring layer partially overlaps the first electronic component when viewed in the first direction;
11. The electronic device according to any one of Appendixes 1 to 10, wherein the conductive bonding layer is interposed between the back surface of the first element and the first wiring layer.
[Appendix 12]
further comprising a second conductor penetrating the second resin layer in the first direction,
12. The electronic device according to any one of appendices 1 to 11, wherein the second conductor is arranged around the first electronic component when viewed in the first direction.
[Appendix 13]
13. The electronic device according to appendix 12, wherein the second conductor is separated from the first wiring layer when viewed in the first direction.
[Appendix 14]
14. The electronic device according to appendix 13, wherein the second conductor surrounds the first electronic component when viewed in the first direction.
[Appendix 15]
The second conductor has a second conductor main surface facing the same direction as the second resin layer main surface in the first direction,
15. The electronic device according to any one of Appendixes 12 to 14, wherein the second conductor main surface is exposed from the second resin layer main surface.
[Appendix 16]
16. The electronic device according to appendix 15, further comprising a metal film overlapping the first electronic component when viewed in the first direction and formed on the main surface of the second resin layer.
[Appendix 17]
17. The electronic device according to appendix 16, wherein the metal film is in contact with the second conductor main surface.
[Appendix 18]
18. The electronic device according to any one of Appendixes 15 to 17, wherein the second conductor main surface is recessed with respect to the second resin layer main surface.
[Appendix 19]
19. The electronic device according to any one of appendices 1 to 18, wherein the first electronic component is a semiconductor element made of a semiconductor.
[Appendix 20]
a support substrate preparing step of preparing a support substrate having a substrate main surface and a substrate back surface facing opposite to each other in a first direction;
a first conductor forming step of forming a first conductor on the main surface of the substrate;
a first resin layer forming step of forming a first resin layer covering the first conductor;
By grinding the first resin layer from the side facing the main surface of the substrate in the first direction to the side facing the back surface of the substrate in the first direction to expose a part of the first conductor from the first resin layer, a first resin layer grinding step of forming a first conductor main surface and a first resin layer main surface facing the same side as the substrate main surface in the first direction;
a first wiring layer forming step of forming a first wiring layer extending over the first resin layer main surface and the first conductor main surface;
a first electronic component mounting step of conductively joining a first electronic component on the first wiring layer;
a second resin layer forming step of forming a second resin layer covering the first wiring layer and the first electronic component;
a support substrate removing step of removing the support substrate to expose a rear surface of the first resin layer facing in the first direction opposite to the main surface of the first resin layer;
and an external electrode forming step of forming an external electrode that is disposed on the side of the first resin layer in the direction in which the back surface of the first resin layer faces and that is electrically connected to the first conductor. Production method.
[Appendix 21]
After the supporting substrate preparing step and before the first conductor forming step, the method further includes a second wiring layer forming step of forming a second wiring layer covering a part of the main surface of the substrate,
21. The method of manufacturing an electronic device according to appendix 20, wherein in the first conductor forming step, the first conductor is formed on the second wiring layer.
[Appendix 22]
22. The method of manufacturing an electronic device according to appendix 21, further comprising a second electronic component mounting step of electrically connecting a second electronic component on the second wiring layer.
[Appendix 23]
a second conductor forming step of forming a second conductor on a portion of the first resin layer after the first resin layer grinding step and before the second resin layer forming step; further have
23. The method of manufacturing an electronic device according to any one of appendices 20 to 22.

Ａ１，Ａ２，Ａ３：電子装置
１１，１２，８１１，８１２：電子部品
１１１，１２１，８１１ａ，８１２ａ：素子主面
１１２，１２２，８１１ｂ，８１２ｂ：素子裏面
１３ ：電極パッド
１３１ ：第１層
１３２ ：第２層
２０ ：封止樹脂
２１，８２１：第１樹脂層
２１１，８２１ａ：第１樹脂層主面
２１２，８２１ｂ：第１樹脂層裏面
２１３ ：第１樹脂層側面
２２，８２２：第２樹脂層
２２１，８２２ａ：第２樹脂層主面
２２２ ：第２樹脂層裏面
２２３ ：第２樹脂層側面
３０ ：内部電極
３１，８３１：柱状導電体
３１１，８３１ａ：柱状導電体主面
３１２，８３１ｂ：柱状導電体裏面
３１３ ：柱状導電体側面
３２，８３２：配線層
３２１ ：配線層主面
３２１ａ ：凹部
３２２ ：配線層裏面
３３，８３３：配線層
３３１ ：配線層主面
３３２，８３３ｂ：配線層裏面
４０，８４０：外部電極
４１ ：柱状導電体被覆部
４２ ：配線層被覆部
５１，５２，５３，８５１，８５２：接合部
５１１，５２１，８５１ａ，８５２ａ：絶縁層
５１２，５２２，８５１ｂ，８５２ｂ：接合層
５１２ａ，５２２ａ：第１層
５１２ｂ，５２２ｂ：第２層
５１２ｃ，５２２ｃ：第３層
５１２ｄ ：第４層
６１，８６１：枠状導電体
６１１ ：内面
６１２ ：外面
６１３，８６１ｃ：頂面
６２ ：金属膜
７１，８７１：外部保護膜
８７１ａ ：開口部
７２ ：素子保護膜
８００ ：支持基板
８０１ ：支持基板主面
８０２ ：支持基板裏面
８９０ａ，８９１ａ：下地層
８９０ｂ，８９０ｃ，８９１ｂ，８９１ｃ：めっき層 A1, A2, A3: electronic devices 11, 12, 811, 812: electronic components 111, 121, 811a, 812a: element main surfaces 112, 122, 811b, 812b: element back surface 13: electrode pads 131: first layer 132: Second layer 20: sealing resin 21, 821: first resin layer 211, 821a: first resin layer main surface 212, 821b: first resin layer rear surface 213: first resin layer side surface 22, 822: second resin layer 221, 822a: second resin layer main surface 222: second resin layer back surface 223: second resin layer side surface 30: internal electrodes 31, 831: columnar conductors 311, 831a: columnar conductor main surfaces 312, 831b: columnar conductors Body back surface 313: Columnar conductor side surface 32, 832: Wiring layer 321: Wiring layer main surface 321a: Recess 322: Wiring layer main surface 33, 833: Wiring layer 331: Wiring layer main surface 332, 833b: Wiring layer back surface 40, 840 : External electrode 41 : Columnar conductor covering portion 42 : Wiring layer covering portions 51, 52, 53, 851, 852: Joint portions 511, 521, 851a, 852a: Insulating layers 512, 522, 851b, 852b: Joint layer 512a, 522a: first layers 512b, 522b: second layers 512c, 522c: third layer 512d: fourth layers 61, 861: frame-shaped conductor 611: inner surface 612: outer surface 613, 861c: top surface 62: metal film 71, 871: External protective film 871a: Opening 72: Element protective film 800: Supporting substrate 801: Main surface of supporting substrate 802: Rear surface of supporting substrate 890a, 891a: Base layers 890b, 890c, 891b, 891c: Plating layer

Claims (27)

第１方向において互いに反対側を向く第１樹脂層主面および第１樹脂層裏面を有する第１樹脂層と、
前記第１方向において互いに反対側を向く第１導電体主面および第１導電体裏面を有し、前記第１樹脂層を前記第１方向に貫通する第１導電体と、
前記第１樹脂層主面と前記第１導電体主面とに跨る第１配線層と、
前記第１方向において前記第１樹脂層主面と同じ側を向く第１素子主面および前記第１樹脂層裏面と同じ側を向く第１素子裏面を有し、前記第１配線層に導通接合された第１電子部品と、
前記第１樹脂層主面と同じ方向を向く第２樹脂層主面および前記第１樹脂層主面に接する第２樹脂層裏面を有し、前記第１配線層および前記第１電子部品を覆う第２樹脂層と、
前記第１樹脂層よりも前記第１樹脂層裏面が向く方向側に配置され、前記第１導電体に導通する外部電極と、
を備えており、
前記第１導電体主面は、前記第１樹脂層主面に対して窪んでおり、
前記第１配線層は、前記第１方向において前記第１導電体主面と同じ方向を向く第１配線層主面と、前記第１配線層主面から前記第１方向に窪む凹部とを有し、
前記凹部は、前記第１方向に見て、前記第１導電体に重なる、
ことを特徴とする電子装置。 a first resin layer having a first resin layer main surface and a first resin layer back surface facing opposite to each other in the first direction;
a first conductor having a first conductor main surface and a first conductor back surface facing opposite to each other in the first direction and penetrating the first resin layer in the first direction;
a first wiring layer extending over the main surface of the first resin layer and the main surface of the first conductor;
It has a first element main surface facing the same side as the first resin layer main surface in the first direction and a first element back surface facing the same side as the first resin layer back surface, and is electrically connected to the first wiring layer. a first electronic component;
It has a second resin layer main surface facing the same direction as the first resin layer main surface and a second resin layer back surface in contact with the first resin layer main surface, and covers the first wiring layer and the first electronic component. a second resin layer;
an external electrode disposed on the side of the first resin layer in the direction in which the back surface of the first resin layer faces and electrically connected to the first conductor;
and
the main surface of the first conductor is recessed with respect to the main surface of the first resin layer;
The first wiring layer has a first wiring layer main surface facing in the same direction as the first conductor main surface in the first direction, and a recess recessed in the first direction from the first wiring layer main surface. have
The recess overlaps the first conductor when viewed in the first direction,
An electronic device characterized by: 前記第１樹脂層主面には、研削痕が形成されている、
請求項１に記載の電子装置。 Grinding marks are formed on the main surface of the first resin layer,
An electronic device according to claim 1 . 前記第１方向において互いに反対側を向く第２配線層主面および第２配線層裏面を有する第２配線層をさらに備えており、
前記第２配線層裏面は、前記第１樹脂層裏面から露出している、
請求項１または請求項２に記載の電子装置。 further comprising a second wiring layer having a second wiring layer main surface and a second wiring layer back surface facing opposite to each other in the first direction;
The back surface of the second wiring layer is exposed from the back surface of the first resin layer,
The electronic device according to claim 1 or 2 . 前記第１電子部品と異なる第２電子部品をさらに備えており、
前記第２電子部品は、前記第２配線層に導通接合され、少なくとも一部が前記第１樹脂層に覆われている、
請求項３に記載の電子装置。 further comprising a second electronic component different from the first electronic component,
The second electronic component is electrically connected to the second wiring layer and at least partially covered with the first resin layer.
4. Electronic device according to claim 3 . 前記第２電子部品は、前記第１素子主面と同じ方向を向く第２素子主面を有しており、
前記第２素子主面は、前記第１樹脂層主面と面一である、
請求項４に記載の電子装置。 The second electronic component has a second element main surface facing in the same direction as the first element main surface,
The second element main surface is flush with the first resin layer main surface,
5. The electronic device according to claim 4 . 前記外部電極は、前記第１導電体裏面を覆う第１導電体被覆部を含んでいる、
請求項１ないし請求項５のいずれか一項に記載の電子装置。 The external electrode includes a first conductor covering portion covering the back surface of the first conductor,
The electronic device according to any one of claims 1 to 5 . 前記外部電極は、前記第２配線層裏面の一部を覆う第２配線層被覆部を含んでいる、
請求項３ないし請求項５のいずれか一項に記載の電子装置。 The external electrode includes a second wiring layer covering portion covering a part of the back surface of the second wiring layer,
The electronic device according to any one of claims 3 to 5 . 前記第２配線層裏面のうち前記外部電極から露出する部分を覆う保護膜をさらに備えている、
請求項７に記載の電子装置。 further comprising a protective film covering a portion of the back surface of the second wiring layer that is exposed from the external electrode;
8. Electronic device according to claim 7 . 前記第１導電体裏面は、前記第２配線層主面に接している、
請求項７または請求項８に記載の電子装置。 the back surface of the first conductor is in contact with the main surface of the second wiring layer;
The electronic device according to claim 7 or 8 . 前記第１電子部品と前記第１配線層とを接合する導電性接合層をさらに備えており、
前記第１配線層は、前記第１方向に見て、一部が前記第１電子部品に重なり、
前記導電性接合層は、前記第１素子裏面と前記第１配線層との間に介在する、
請求項１ないし請求項９のいずれか一項に記載の電子装置。 further comprising a conductive bonding layer that bonds the first electronic component and the first wiring layer,
the first wiring layer partially overlaps the first electronic component when viewed in the first direction;
The conductive bonding layer is interposed between the back surface of the first element and the first wiring layer,
10. The electronic device according to any one of claims 1-9 . 前記第１方向に見て前記導電性接合層を囲む絶縁層をさらに備える、 further comprising an insulating layer surrounding the conductive bonding layer when viewed in the first direction;
請求項１０に記載の電子装置。11. Electronic device according to claim 10. 前記第２樹脂層を前記第１方向に貫通する第２導電体をさらに備えており、
前記第２導電体は、前記第１方向に見て、前記第１電子部品の周囲に配置されている、請求項１ないし請求項１１のいずれか一項に記載の電子装置。 further comprising a second conductor penetrating the second resin layer in the first direction,
12. The electronic device according to claim 1, wherein said second conductor is arranged around said first electronic component when viewed in said first direction. 前記第２導電体は、前記第１方向に見て、前記第１配線層から離間している、
請求項１２に記載の電子装置。 The second conductor is separated from the first wiring layer when viewed in the first direction,
13. Electronic device according to claim 12. 前記第２導電体は、前記第１方向に見て、前記第１電子部品を包囲している、
請求項１３に記載の電子装置。 The second conductor surrounds the first electronic component when viewed in the first direction,
14. Electronic device according to claim 13. 前記第２導電体は、前記第１方向において前記第２樹脂層主面と同じ方向を向く第２導電体主面を有しており、
前記第２導電体主面は、前記第２樹脂層主面から露出している、
請求項１２ないし請求項１４のいずれか一項に記載の電子装置。 The second conductor has a second conductor main surface facing the same direction as the second resin layer main surface in the first direction,
The second conductor main surface is exposed from the second resin layer main surface,
15. The electronic device according to any one of claims 12-14. 前記第１方向に見て、前記第１電子部品に重なり、かつ、前記第２樹脂層主面の上に形成された金属膜をさらに備えている、
請求項１５に記載の電子装置。 further comprising a metal film overlapping the first electronic component when viewed in the first direction and formed on the main surface of the second resin layer,
16. Electronic device according to claim 15. 前記金属膜は、前記第２導電体主面に接する、
請求項１６に記載の電子装置。 the metal film is in contact with the main surface of the second conductor;
17. Electronic device according to claim 16. 前記第２導電体主面は、前記第２樹脂層主面に対して、窪んでいる、
請求項１５ないし請求項１７のいずれか一項に記載の電子装置。 The second conductor main surface is recessed with respect to the second resin layer main surface,
18. The electronic device according to any one of claims 15-17. 前記第２導電体は、前記第１樹脂層主面に接する、 the second conductor is in contact with the main surface of the first resin layer;
請求項１２ないし請求項１８のいずれか一項に記載の電子装置。19. An electronic device according to any one of claims 12-18. 前記第１電子部品は、半導体を材料とする半導体素子である、
請求項１ないし請求項１９のいずれか一項に記載の電子装置。 The first electronic component is a semiconductor element made of a semiconductor,
20. An electronic device according to any one of claims 1-19 . 第１方向において互いに反対側を向く第１樹脂層主面および第１樹脂層裏面を有する第１樹脂層と、 a first resin layer having a first resin layer main surface and a first resin layer back surface facing opposite to each other in the first direction;
前記第１方向において互いに反対側を向く第１導電体主面および第１導電体裏面を有し、前記第１樹脂層を前記第１方向に貫通する第１導電体と、 a first conductor having a first conductor main surface and a first conductor back surface facing opposite to each other in the first direction and penetrating the first resin layer in the first direction;
前記第１樹脂層主面と前記第１導電体主面とに跨る第１配線層と、 a first wiring layer extending over the main surface of the first resin layer and the main surface of the first conductor;
前記第１方向において前記第１樹脂層主面と同じ側を向く第１素子主面および前記第１樹脂層裏面と同じ側を向く第１素子裏面を有し、前記第１配線層に導通接合された第１電子部品と、 It has a first element main surface facing the same side as the first resin layer main surface in the first direction and a first element back surface facing the same side as the first resin layer back surface, and is electrically connected to the first wiring layer. a first electronic component;
前記第１樹脂層主面と同じ方向を向く第２樹脂層主面および前記第１樹脂層主面に接する第２樹脂層裏面を有し、前記第１配線層および前記第１電子部品を覆う第２樹脂層と、 It has a second resin layer main surface facing the same direction as the first resin layer main surface and a second resin layer back surface in contact with the first resin layer main surface, and covers the first wiring layer and the first electronic component. a second resin layer;
前記第１樹脂層よりも前記第１樹脂層裏面が向く方向側に配置され、前記第１導電体に導通する外部電極と、 an external electrode disposed on the side of the first resin layer in the direction in which the back surface of the first resin layer faces and electrically connected to the first conductor;
前記第１方向において互いに反対側を向く第２配線層主面および第２配線層裏面を有する第２配線層と、 a second wiring layer having a second wiring layer main surface and a second wiring layer back surface facing opposite to each other in the first direction;
前記第１素子主面と同じ方向を向く第２素子主面を有する第２電子部品と、 a second electronic component having a second element main surface facing in the same direction as the first element main surface;
を備えており、and
前記第２配線層裏面は、前記第１樹脂層裏面から露出しており、 The back surface of the second wiring layer is exposed from the back surface of the first resin layer,
前記第２電子部品は、前記第２配線層に導通接合され、少なくとも一部が前記第１樹脂層に覆われており、 the second electronic component is conductively joined to the second wiring layer and at least partially covered with the first resin layer;
前記第２素子主面は、前記第１樹脂層主面と面一である、 The second element main surface is flush with the first resin layer main surface,
ことを特徴とする電子装置。An electronic device characterized by: 第１方向において互いに反対側を向く第１樹脂層主面および第１樹脂層裏面を有する第１樹脂層と、
前記第１方向において互いに反対側を向く第１導電体主面および第１導電体裏面を有し、前記第１樹脂層を前記第１方向に貫通する第１導電体と、
前記第１樹脂層主面と前記第１導電体主面とに跨る第１配線層と、
前記第１方向において前記第１樹脂層主面と同じ側を向く第１素子主面および前記第１樹脂層裏面と同じ側を向く第１素子裏面を有し、前記第１配線層に導通接合された第１電子部品と、
前記第１樹脂層主面と同じ方向を向く第２樹脂層主面および前記第１樹脂層主面に接する第２樹脂層裏面を有し、前記第１配線層および前記第１電子部品を覆う第２樹脂層と、
前記第１樹脂層よりも前記第１樹脂層裏面が向く方向側に配置され、前記第１導電体に導通する外部電極と、
前記第１方向において互いに反対側を向く第２配線層主面および第２配線層裏面を有する第２配線層と、
を備えており、
前記第２配線層裏面は、前記第１樹脂層裏面から露出しており、
前記外部電極は、前記第２配線層裏面の一部を覆う第２配線層被覆部を含んでいる、
ことを特徴とする電子装置。 a first resin layer having a first resin layer main surface and a first resin layer back surface facing opposite to each other in the first direction;
a first conductor having a first conductor main surface and a first conductor back surface facing opposite to each other in the first direction and penetrating the first resin layer in the first direction;
a first wiring layer extending over the main surface of the first resin layer and the main surface of the first conductor;
It has a first element main surface facing the same side as the first resin layer main surface in the first direction and a first element back surface facing the same side as the first resin layer back surface, and is electrically connected to the first wiring layer. a first electronic component;
It has a second resin layer main surface facing the same direction as the first resin layer main surface and a second resin layer back surface in contact with the first resin layer main surface, and covers the first wiring layer and the first electronic component. a second resin layer;
an external electrode disposed on the side of the first resin layer in the direction in which the back surface of the first resin layer faces and electrically connected to the first conductor;
a second wiring layer having a second wiring layer main surface and a second wiring layer back surface facing opposite to each other in the first direction;
and
The back surface of the second wiring layer is exposed from the back surface of the first resin layer,
The external electrode includes a second wiring layer covering portion covering a part of the back surface of the second wiring layer,
An electronic device characterized by: 第１方向において互いに反対側を向く基板主面および基板裏面を有する支持基板を用意する支持基板用意工程と、
前記基板主面の上に、第１導電体を形成する第１導電体形成工程と、
前記第１導電体を覆う第１樹脂層を形成する第１樹脂層形成工程と、
前記第１方向において前記基板主面が向く側から前記基板裏面が向く側に前記第１樹脂層を研削し、前記第１導電体の一部を前記第１樹脂層から露出させることで、各々が前記第１方向において前記基板主面と同じ側を向く第１導電体主面および第１樹脂層主面を形成する第１樹脂層研削工程と、
前記第１樹脂層研削工程後に、前記第１方向において、前記第１導電体主面を前記第１樹脂層主面に対して窪ませる工程と、
前記第１樹脂層主面と前記第１導電体主面とに跨る第１配線層を形成する第１配線層形成工程と、
前記第１配線層の上に、第１電子部品を導通接合する第１電子部品搭載工程と、
前記第１配線層および前記第１電子部品を覆う第２樹脂層を形成する第２樹脂層形成工程と、
前記支持基板を除去することで、前記第１方向において前記第１樹脂層主面と反対側を向く第１樹脂層裏面を露出させる支持基板除去工程と、
前記第１樹脂層よりも前記第１樹脂層裏面が向く方向側に配置され、前記第１導電体に導通する外部電極を形成する外部電極形成工程と、
を有することを特徴とする電子装置の製造方法。 a support substrate preparing step of preparing a support substrate having a substrate main surface and a substrate back surface facing opposite to each other in a first direction;
a first conductor forming step of forming a first conductor on the main surface of the substrate;
a first resin layer forming step of forming a first resin layer covering the first conductor;
By grinding the first resin layer from the side facing the main surface of the substrate in the first direction to the side facing the back surface of the substrate in the first direction to expose a part of the first conductor from the first resin layer, a first resin layer grinding step of forming a first conductor main surface and a first resin layer main surface facing the same side as the substrate main surface in the first direction;
a step of recessing the first conductor main surface with respect to the first resin layer main surface in the first direction after the first resin layer grinding step;
a first wiring layer forming step of forming a first wiring layer extending over the first resin layer main surface and the first conductor main surface;
a first electronic component mounting step of conductively joining a first electronic component on the first wiring layer;
a second resin layer forming step of forming a second resin layer covering the first wiring layer and the first electronic component;
a support substrate removing step of removing the support substrate to expose a rear surface of the first resin layer facing in the first direction opposite to the main surface of the first resin layer;
an external electrode forming step of forming an external electrode that is arranged on the side of the first resin layer in the direction in which the back surface of the first resin layer faces and that is electrically connected to the first conductor;
A method of manufacturing an electronic device, comprising: 前記支持基板用意工程の後であり、前記第１導電体形成工程の前に、前記基板主面の一部を覆う第２配線層を形成する第２配線層形成工程をさらに有しており、
前記第１導電体形成工程では、前記第２配線層の上に、前記第１導電体を形成する、
請求項２３に記載の電子装置の製造方法。 After the supporting substrate preparing step and before the first conductor forming step, the method further includes a second wiring layer forming step of forming a second wiring layer covering a part of the main surface of the substrate,
In the step of forming the first conductor, the first conductor is formed on the second wiring layer.
24. A method of manufacturing an electronic device according to claim 23 . 前記第２配線層の上に、第２電子部品を導通接合する第２電子部品搭載工程をさらに有する、
請求項２４に記載の電子装置の製造方法。 further comprising a second electronic component mounting step of electrically connecting a second electronic component on the second wiring layer;
25. A method of manufacturing an electronic device according to claim 24 . 前記第１樹脂層研削工程の後であって、前記第２樹脂層形成工程の前に、前記第１樹脂層の一部の上に、第２導電体を形成する第２導電体形成工程をさらに有している、
請求項２３ないし請求項２５のいずれか一項に記載の電子装置の製造方法。 a second conductor forming step of forming a second conductor on a portion of the first resin layer after the first resin layer grinding step and before the second resin layer forming step; further have
26. The method of manufacturing an electronic device according to any one of claims 23 to 25 . 第１方向において互いに反対側を向く基板主面および基板裏面を有する支持基板を用意する支持基板用意工程と、 a support substrate preparing step of preparing a support substrate having a substrate main surface and a substrate back surface facing opposite to each other in a first direction;
前記基板主面の上に、第１導電体を形成する第１導電体形成工程と、 a first conductor forming step of forming a first conductor on the main surface of the substrate;
前記第１導電体を覆う第１樹脂層を形成する第１樹脂層形成工程と、 a first resin layer forming step of forming a first resin layer covering the first conductor;
前記第１方向において前記基板主面が向く側から前記基板裏面が向く側に前記第１樹脂層を研削し、前記第１導電体の一部を前記第１樹脂層から露出させることで、各々が前記第１方向において前記基板主面と同じ側を向く第１導電体主面および第１樹脂層主面を形 By grinding the first resin layer from the side facing the main surface of the substrate in the first direction to the side facing the back surface of the substrate in the first direction to expose a part of the first conductor from the first resin layer, forms a first conductor main surface and a first resin layer main surface facing the same side as the substrate main surface in the first direction
成する第１樹脂層研削工程と、A first resin layer grinding step to form;
前記第１樹脂層主面と前記第１導電体主面とに跨る第１配線層を形成する第１配線層形成工程と、 a first wiring layer forming step of forming a first wiring layer extending over the first resin layer main surface and the first conductor main surface;
前記第１配線層の上に、第１電子部品を導通接合する第１電子部品搭載工程と、 a first electronic component mounting step of conductively joining a first electronic component on the first wiring layer;
前記第１配線層および前記第１電子部品を覆う第２樹脂層を形成する第２樹脂層形成工程と、 a second resin layer forming step of forming a second resin layer covering the first wiring layer and the first electronic component;
前記支持基板を除去することで、前記第１方向において前記第１樹脂層主面と反対側を向く第１樹脂層裏面を露出させる支持基板除去工程と、 a support substrate removing step of removing the support substrate to expose a rear surface of the first resin layer facing in the first direction opposite to the main surface of the first resin layer;
前記第１樹脂層よりも前記第１樹脂層裏面が向く方向側に配置され、前記第１導電体に導通する外部電極を形成する外部電極形成工程と、 an external electrode forming step of forming an external electrode that is arranged on the side of the first resin layer in the direction in which the back surface of the first resin layer faces and that is electrically connected to the first conductor;
を有しており、and
前記第１樹脂層研削工程の後であって、前記第２樹脂層形成工程の前に、前記第１樹脂層の一部の上に、第２導電体を形成する第２導電体形成工程をさらに有している、 a second conductor forming step of forming a second conductor on a portion of the first resin layer after the first resin layer grinding step and before the second resin layer forming step; further have
ことを特徴とする電子装置の製造方法。A method of manufacturing an electronic device, characterized by:
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