JP2007123578A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a high pattern accuracy and a superior electric connection while holding a function of an insulation resin layer as a buffer layer. <P>SOLUTION: The upside of a semiconductor substrate 2 with electrodes 3 provided on one surface is coated with an insulation resin 4a, a mold (not shown) having irregularities is pressed to the coated surface, and an exposure process is applied to the insulation resin 4a as it is to harden the insulation resin 4a, thus forming an insulation resin layer 4 having openings 5 and also conductive parts 6 to be electrically connected to the electrodes 3 through the openings 5. It is coated with a seal resin 7a so as to cover the insulation resin layer 4 and the conductive parts 6, the mold (not shown) is again pressed to the coated surface, the exposure process is applied to the seal resin 7a as it is to harden the resin 7a, thus forming a seal resin layer 7 having openings 8. Solder bumps 9 for mounting on a circuit board are provided in the openings 8 to form the semiconductor device 1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a wafer level CSP type semiconductor device that realizes packaging of a semiconductor chip in a wafer state, the semiconductor device having improved resin pattern accuracy, and a method of manufacturing the same.

  Conventionally, there is a semiconductor package structure generally called “wafer level CSP” (hereinafter sometimes referred to as “wafer level package”). FIG. 7 is a schematic cross-sectional view showing an example thereof. As shown in FIG. 7, in this semiconductor device 101, for example, an insulating resin layer 104 is provided as a buffer layer on a wafer substrate 102, a wiring layer 106 and a sealing resin layer 107 are provided thereon, and solder bumps are further provided. 109 or the like is provided. The semiconductor device having such a structure can be a semiconductor chip having a package structure by cutting the wafer into a predetermined chip size in the final process.

  The semiconductor device 101 is manufactured as shown in FIG. 8, for example. First, the semiconductor substrate 102 provided with the electrode 103 on one side is prepared [FIG. 8A]. Next, a photosensitive insulating resin 104a is entirely applied so as to cover the upper surface of the semiconductor substrate 102 [FIG. 8B]. Here, a negative example is shown as the photosensitive insulating resin 104a, but a positive may be used. Next, after applying the insulating resin 104a, exposure is performed through a mask 110 on which a desired pattern that transmits exposure light is formed [FIG. 8C]. After the exposure, the insulating resin layer 104 is removed from the vicinity of the electrode 103 by development to form an opening 105 in the insulating resin layer 104 [FIG. 8D]. Subsequently, a wiring layer 106 electrically connected to the electrode 103 through the opening 105 is formed so as to cover a part of the insulating resin layer 4 by plating treatment [FIG. 8E]. Thereafter, a sealing resin 107a is applied so as to cover the insulating resin layer 104 and the wiring layer 106 [FIG. 8 (f)]. Then, similarly to the insulating resin 104a, the semiconductor device as shown in FIG. 7 in which the opening 108 is formed in the sealing resin layer 107 by performing exposure through a mask in which a pattern that transmits exposure light is formed. 101.

The feature of the wafer level CSP is that all members constituting the package are processed in the formation of the wafer. That is, the insulating resin layer, wiring layer, sealing resin layer, solder bump, and the like are all formed by handling the wafer.
The wafer level package is formed by laminating a package member on the surface of the wafer on the device circuit side, and is separated into pieces by a dicing process and mounted on a circuit board using terminals of a semiconductor package formed on the wafer. It is used for electronic equipment.

  In addition, with recent demands for higher functionality and lighter and thinner electronic devices, electronic components have been increasingly integrated and further mounted with high density, and semiconductor devices used in these electronic devices have been developed. Is becoming more and more compact than ever before. Some of these miniaturized semiconductor devices are multi-layered by repeating the sequential lamination of an insulating resin layer and a wiring layer.

  However, the insulating resin conventionally used for this type of semiconductor package is thick because it is necessary to retain the function as a buffer layer, and sufficient pattern accuracy cannot be obtained. That is, in the case of pattern formation, photosensitive polybenzoxazole (PBO) or polyimide resin is used as the insulating layer, and these resins are coated and patterned by using a photolithography technique. However, if the thickness of the resin layer is 10 μm or more, the size and shape of the opening for exposing the electrode provided on one surface of the wafer substrate and the opening for exposing a part of the wiring layer are set. There is a problem that it is difficult to control and pattern formation cannot be performed with high accuracy. Further, since the resin layer is easily affected by the base shape, it is difficult to obtain a uniform thickness. Therefore, there is a possibility that an electrical connection failure may occur between the electrode provided on one surface of the wafer substrate and the wiring layer or between the stacked wiring layers.

Furthermore, when the resin layer is made multilayer, it is difficult to obtain a uniform thickness, and uneven undulation steps are generated on the surface. Therefore, it has been difficult to obtain a semiconductor device having a flat surface. For this reason, the pattern accuracy is further deteriorated.
Furthermore, adhesion between materials is important for multilayering of the resin layer, and if there are undulating steps such as warpage or undulation on the surface of the resin layer, multilayering such as three layers or four layers becomes difficult.

  On the other hand, as means for easily and accurately forming a fine wiring pattern in an interlayer insulating layer of a multilayer printed wiring board, an interlayer insulating layer formed on a core substrate is made of a thermosetting resin, a thermosetting resin, and a thermoplastic resin. A resin mixture, a thermosetting resin imparted photosensitivity, a mixed resin of a thermosetting resin imparted photosensitivity and a thermoplastic resin, and at least one resin selected from the photosensitive resin, the interlayer After softening the insulating layer, and then press-fitting the mold having the concavo-convex portion into the softened interlayer insulating layer to transfer the wiring pattern forming grooves, etc. It has been proposed to remove the mold from the interlayer insulating layer and then fill the groove with a conductor (for example, see Patent Document 1).

However, the means described in Patent Document 1 requires a plurality of troublesome work and many steps such as heat softening of the resin and lowering or raising of the resin temperature, and has a problem that the processing time becomes long. .
JP 2005-108924 A

The present invention has been made in view of the above circumstances, and an object thereof is to obtain a semiconductor device having good pattern accuracy and excellent electrical connection while maintaining the function of the insulating resin layer as a buffer layer. And
Another object of the present invention is to provide a method for manufacturing a semiconductor device that does not require a cumbersome process associated with heat treatment and can be applied to a multilayer printed wiring board.

  According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate provided with an electrode on one surface; and a first opening provided so as to cover one surface of the semiconductor substrate and aligned with the electrode. 1 resin layer, a conductive portion provided so as to cover a part of the first resin layer, and electrically connected to the electrode through the first opening, and the first resin layer And a second resin layer covering the conductive portion and having a second opening at a position aligned with the conductive portion, the semiconductor device comprising: a first resin layer disposed on the first resin layer The opening of 1 has an arbitrary shape when viewed from above, the side surface thereof has a steep slope, and the upper surface of the first resin layer is flat.

  A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein an upper surface of the second resin layer covering at least the conductive portion is flat.

  A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein the conductive portion and the second resin layer are alternately laminated, and at least the number of laminations is two or more. It is characterized by.

  A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the third aspect, wherein the second resin layer has a convex portion in a region on the upper surface thereof where the conductive portion is not provided. It is characterized by being.

  The semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein the second resin layer is made of a photosensitive resin.

  According to a sixth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a semiconductor substrate having an electrode provided on one surface; A first resin layer, a conductive portion provided so as to cover a portion of the first resin layer, and electrically connected to the electrode through the first opening, and the first And a second resin layer that covers the conductive portion and has a second opening at a position aligned with the conductive portion, wherein an electrode is provided on one surface. Applying the first resin so as to cover the one surface of the obtained semiconductor substrate, and after applying the first resin, pressing the uneven surface of the mold having unevenness against the first resin application surface; A convex region made of the first resin and the electrode for exposing the electrode The first resin is cured while pressing the mold and the first resin layer is formed by the concave region and the first resin layer by the convex region. Step C is provided at least.

  A semiconductor device manufacturing method according to a seventh aspect of the present invention is the method for manufacturing a semiconductor device according to a sixth aspect, wherein the first resin layer is partially covered with the first resin layer following the step C. Forming a conductive portion electrically connected to the electrode through the opening, applying a second resin so as to cover the first resin layer and the conductive portion, and After the application of the second resin, the uneven surface of the mold having unevenness is pressed against the second resin application surface to expose the convex region made of the second resin and a part of the conductive portion. The step F for forming the recessed region, and the second resin is cured while pressing the mold, thereby forming the second opening by the recessed region and the second resin layer by the protruding region. Step G is provided at least.

  The semiconductor device manufacturing method according to an eighth aspect of the present invention is the semiconductor device manufacturing method according to the seventh aspect, wherein the second resin layer protrudes into an area where the conductive portion is not provided on the upper surface. And the convex portion is formed simultaneously with the second resin layer by pressing the mold.

  The method of manufacturing a semiconductor device according to claim 9 of the present invention is the method of manufacturing a semiconductor device according to any one of claims 6 to 8, wherein the resin pressed against the mold is made of a photosensitive resin, and is exposed. It is characterized by being cured by.

  According to the present invention, the first opening disposed in the first resin layer has an arbitrary shape when viewed from above, and the side surface has a steep slope. Even if the thickness is increased in order to maintain the function as the buffer layer, the size of the opening can be adjusted with high accuracy and the electrode can be sufficiently exposed. Further, since the upper surface of the first resin layer is flat, the pattern accuracy of the resin laminated thereon can be improved. Therefore, a semiconductor device having good pattern accuracy and excellent electrical connection can be obtained.

  Further, according to the present invention, after applying the first resin so as to cover the one surface of the semiconductor substrate on which the electrode is provided on one surface, the uneven surface of the mold having unevenness is applied to the first resin-coated surface. Since the first resin is cured while pressing and pressing the mold, the side surface of the first opening disposed in the first resin layer is along the convex side surface of the mold The slope of the transferred side surface becomes steep, and the electrode can be sufficiently exposed. Therefore, a troublesome process accompanying heat treatment is unnecessary, and a semiconductor device that can be applied to a multilayer printed wiring board can be easily manufactured. And according to this invention, it can form easily in a short time.

The present invention will be described below with reference to the drawings based on the best mode.
FIG. 1 is a cross-sectional view showing an example of a semiconductor device of the present invention.
As shown in FIG. 1, the semiconductor device 1 according to this embodiment includes a semiconductor substrate 2, an insulating resin layer 4 provided on the upper surface of the semiconductor substrate 2, and a conductive portion provided on the upper surface of the insulating resin layer 4. 6 and a sealing resin layer 7 provided on the upper surface of the conductive portion 6. In the case of the present embodiment, the insulating resin layer 4 that is the lower (semiconductor substrate 2) resin layer shown in the figure is the first resin layer, and the sealing resin layer 7 that is the upper resin layer is the first resin layer. 2 resin layers.

  The semiconductor substrate 2 is provided with an Al pad, for example, as an electrode 3 on one surface thereof. The semiconductor substrate 2 is a semiconductor wafer such as a silicon wafer, and may be a semiconductor chip obtained by cutting (dicing) the semiconductor wafer into chip dimensions.

The insulating resin layer 4 is provided so as to cover one surface of the semiconductor substrate 2 and has an opening 5 at a position aligned with the electrode 3. The insulating resin layer 4 is made of, for example, polyimide resin, epoxy resin, silicone resin, or the like, and the thickness thereof is preferably set to 2 to 200 μm, for example. The insulating resin layer 4 has photosensitivity.
The opening 5 can have an arbitrary shape when viewed from above, and the side surface has a steep slope. Thereby, the electrode is sufficiently exposed.
The upper surface of the insulating resin layer 4 is flat. Thereby, the pattern precision of resin laminated | stacked on it can be improved, and it can be equipped with the outstanding electrical connection.

  The conductive portion 6 is a wiring layer provided so as to cover a part of the insulating resin layer 4 and electrically connected to the electrode 3 through the opening 5. The conductive portion 6 can be freely formed according to the design. Moreover, as a material of the electroconductive part 6, Cu is used, for example, and the thickness is 2-20 micrometers, for example. Thereby, sufficient conductivity can be obtained. The conductive portion 6 may be formed of Au or the like. The conductive portion 6 can be formed by, for example, a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.

The sealing resin layer 7 covers the insulating resin layer 4 and the conductive part 6, and has an opening 8 at a position aligned with the conductive part 6. The sealing resin layer 7 is made of, for example, a polyimide resin, an epoxy resin, a silicone resin, or the like, and the thickness thereof is preferably 2 to 200 μm, for example. Moreover, the sealing resin layer 7 has photosensitivity.
Further, the opening 8 has an arbitrary shape when viewed from above, and the side surface thereof has a steep slope. Thereby, the magnitude | size of an opening part is adjusted with a sufficient precision, and the outstanding electrical connection will be achieved reliably.
The upper surface of the sealing resin layer 7 is also flat. Thereby, the pattern precision of resin laminated | stacked on it can be improved, and it can be set as a multilayered structure easily.

Next, an example of the manufacturing method of the electroconductive part in this invention is demonstrated.
2 and 3 are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device in the order of steps when the insulating resin layer 4 as a buffer layer is a single layer.
As shown in FIG. 2, first, a semiconductor substrate 2 is prepared [see FIG. 2 (a)]. Examples of the semiconductor substrate 2 include a semiconductor wafer having an electrode 3 and a passivation film (not shown) formed on the surface.
Next, an insulating resin 4a is applied entirely so as to cover the upper surface of the semiconductor substrate 2 [see FIG. 2 (b)]. The insulating resin 4a is made of, for example, a polyimide-based, epoxy-based, or silicone-based liquid resin, and the applied thickness is, for example, about 2 to 200 μm. The material used for the insulating resin 4a has photosensitivity and is cured by exposure.

Next, after applying the insulating resin 4a, the uneven surface 10a of the mold 10 made of, for example, quartz material having unevenness corresponding to the mirror image of the circuit pattern to be formed is pressed against the application surface of the insulating resin 4a [FIG. c)].
Subsequently, in order to expose the insulating resin 4a by exposing the insulating resin 4a by exposing the insulating resin 4a to the insulating resin 4a while the mold 10 is pressed, thereby exposing the convex region formed of the insulating resin 4a and the electrode 3. Are formed [see FIG. 2 (d)].

  Thereafter, the mold 10 is removed, and the opening 5 by the concave region and the insulating resin layer 4 by the convex region are formed [see FIG. 2 (e)]. The inclination of the side surface of the opening 5 is steep, and its shape and size are adjusted with high accuracy by the mold 10. This ensures that an excellent electrical connection with the electrode is achieved. In addition, since the pressing by the mold 10 and the exposure are performed at the same time in this way, the convex portion region having a predetermined shape can be formed without deforming the opening 5.

  Further, a seed layer (not shown) serving as a seed for the plating layer is formed on the semiconductor substrate 2 on which the insulating resin layer 4 is formed. This seed layer can be formed by sputtering, for example. The seed layer can also be formed by a vapor deposition method. This seed layer ensures adhesion with the underlying insulating resin layer 4. This seed layer is a laminate composed of a Cr layer and a Cu layer, or a laminate composed of a Ti layer and a Cu layer, and the thickness thereof is, for example, about 0.05 to 0.5 μm.

  Further, a resist film (not shown) is formed on the seed layer. This resist film is formed except for the conductive portion formation region. The thickness of the resist film is made thicker than the conductive portion 6 which is a wiring layer formed in the next plating step. For the plating process, both electrolytic plating and electroless plating can be used.

  Thereafter, as shown in FIG. 3, the conductive portion 6 electrically connected to the electrode 3 through the opening 5 so as to cover a part of the insulating resin layer 4 by plating is provided in the conductive portion formation region. Then, a circuit pattern composed of the conductive portion 6 is formed on the semiconductor substrate 2 [see FIG. 3A]. After the conductive portion 6 is formed, the resist is removed. In addition, since the seed layer remains in the area without plating, the unnecessary seed layer in the area is also removed by etching or the like, and the insulating resin layer 4 is exposed in portions other than the conductive portion 6. The conductive portion 6 is made of Cu or Au and has a thickness of about 2 to 200 μm, for example.

Next, a sealing resin 7a is applied so as to cover the insulating resin layer 4 and the conductive portion 6 [see FIG. 3 (b)]. The sealing resin 7a is made of, for example, a polyimide-based, epoxy-based, or silicone-based liquid resin, and the applied thickness is, for example, about 2 to 200 μm. The material used for the sealing resin 7a is also photosensitive and is cured by exposure.
Next, after application of the sealing resin 7a, the uneven surface 10a of the mold 10 having unevenness is pressed against the application surface of the sealing resin 7a [see FIG. 3 (c)].

Subsequently, the sealing mold 7a is pressed and exposed to exposure light by being exposed to the sealing resin 7a to be cured by exposure, thereby exposing a convex region made of the sealing resin 7a and a part of the conductive portion 6. And a recessed region for forming the same [see FIG. 3 (d)].
Thereafter, the mold 10 is removed, and the opening 8 by the concave region and the sealing resin layer 7 by the convex region are formed [see FIG. 3 (e)]. The side surface of the opening 8 also has a steep slope, and the shape and size thereof are adjusted with high accuracy by the mold 10. As described above, since the pressing by the mold 10 and the exposure are performed at the same time, the convex portion region having a predetermined shape can be formed without causing the opening 8 to lose its shape.

Then, by providing the opening 8 with solder bumps 9 for mounting on a circuit board, a semiconductor device 1 as shown in FIG. 1 can be obtained.
Note that, after forming the sealing resin layer 7, solder bumps 9 are provided and diced into predetermined dimensions, whereby a packaged semiconductor chip can be obtained.

The semiconductor device 1 configured as described above is such that the opening 5 and the opening 8 are formed by physically contacting the mold 10 with the insulating resin 4a and the sealing resin 7 and applying a predetermined pressure. Therefore, in order to maintain the function as a buffer layer, the slope of the side surface of the opening 5 disposed in the insulating resin layer 4 having a large thickness or the opening 8 disposed in the sealing resin 7 is steep, The shape and size are adjusted with high accuracy. Therefore, a semiconductor device having good pattern accuracy and excellent electrical connection can be obtained. In addition, since the upper surface of the insulating resin layer 4 and the upper surface of the sealing resin 7 are flattened by pressing the mold 10, a semiconductor device with even better pattern accuracy can be obtained.
In addition, the semiconductor device manufacturing method according to the present invention does not require a troublesome process associated with heat treatment, and thus the semiconductor device can be easily manufactured.

In addition, the semiconductor device of the present invention can have a multilayer structure as shown in FIGS.
Hereinafter, other embodiments of the present invention will be described. In the embodiments described later, the same reference numerals are used for the same components as those in the above-described embodiments, and the description thereof will be omitted.

FIG. 4 is a cross-sectional view showing an example of the second embodiment of the semiconductor device.
As shown in FIG. 4, the semiconductor device 11 in this embodiment includes a semiconductor substrate 2, a first insulating resin layer 4A as a buffer layer provided on the upper surface of the semiconductor substrate 2, and the first insulating resin layer 4A. The first conductive portion 6A provided on the upper surface of the first conductive portion, the second insulating resin layer 4B as a buffer layer provided on the upper surface of the first conductive portion 6A, and the upper surface of the second insulating resin layer 4B. At least a second conductive part 6B and a sealing resin layer 7 provided on the upper surface of the second conductive part 6B are provided. In the case of the present embodiment, the first insulating resin layer 4A, which is the lower (semiconductor substrate 2) resin layer shown in the figure, becomes the first resin layer, and the second insulating resin layer that is the intermediate resin layer. 4B and the sealing resin layer 7 which is the upper resin layer serve as the second resin layer.

The first insulating resin layer 4 </ b> A is provided so as to cover one surface of the semiconductor substrate 2, and has an opening 5 </ b> A at a position aligned with the electrode 3.
The first conductive portion 6A is a wiring layer that is provided so as to cover a part of the first insulating resin layer 4A and is electrically connected to the electrode 3 through the opening 5A.
The second insulating resin layer 4B covers the first insulating resin layer 4A and the first conductive portion 6A and has an opening 5B at a position aligned with the first conductive portion 6A.
The second conductive portion 6B is a wiring layer provided so as to cover a part of the second insulating resin layer 4B and electrically connected to the first conductive portion 6A through the opening 5B.
The sealing resin layer 7 covers the second insulating resin layer 4B and the second conductive portion 6B, and has an opening 8 at a position aligned with the second conductive portion 6B.

  The semiconductor device 11 configured as described above is excellent because the upper surfaces of the first insulating resin layer 4A and the second insulating resin layer 4B and the upper surface of the sealing resin layer 7 are planarized. The first conductive portion 6A and the second conductive portion B are provided on the upper surfaces of the first insulating resin layer 4A and the second insulating resin layer 4B, respectively, and thus have an excellent electrical connection. A semiconductor device having a multilayer structure can be obtained.

In the present invention, a large number of conductive portions and resin layers may be alternately stacked to achieve multi-layered conductive portions.
FIG. 5 is a sectional view showing an example of the third embodiment of the semiconductor device.
As shown in FIG. 5, the semiconductor device 21 in the present embodiment includes a semiconductor substrate 2, a first insulating resin layer 4A as a buffer layer provided on the upper surface of the semiconductor substrate 2, and the first insulating resin layer 4A. The first conductive portion 6A provided on the upper surface of the first conductive portion, the second insulating resin layer 4B as a buffer layer provided on the upper surface of the first conductive portion 6A, and the upper surface of the second insulating resin layer 4B. A second conductive portion 6B, a third insulating resin layer 4C as a buffer layer provided on the upper surface of the second conductive portion 6B, and a third conductive portion 6C provided on the upper surface of the third insulating resin layer 4C; A fourth insulating resin layer 4D as a buffer layer provided on the upper surface of the third conductive portion 6C, a fourth conductive portion 6D provided on the upper surface of the fourth insulating resin layer 4D, and the fourth conductive portion. And a sealing resin layer 7 provided on the upper surface of 6D. That is, in the case of this embodiment, the number of times the conductive portion and the resin layer are stacked is 4, and the first insulating resin layer 4A that is the resin layer on the lowermost layer (semiconductor substrate 2 side) shown in the figure is the first resin. The four layers of the second insulating resin layer 4B, the third insulating resin layer 4C, the fourth insulating resin layer 4D, and the sealing resin layer 7 on the second insulating resin layer 4B, which are shown in the figure, are the second resin layer. It becomes.

The first insulating resin layer 4 </ b> A is provided so as to cover one surface of the semiconductor substrate 2, and has an opening 5 </ b> A at a position aligned with the electrode 3.
The first conductive portion 6A is a wiring layer that is provided so as to cover a part of the first insulating resin layer 4A and is electrically connected to the electrode 3 through the opening 5A.
The second insulating resin layer 4B covers the first insulating resin layer 4A and the first conductive portion 6A and has an opening 5B at a position aligned with the first conductive portion 6A.
The second conductive portion 6B is a wiring layer provided so as to cover a part of the second insulating resin layer 4B and electrically connected to the first conductive portion 6A through the opening 5B.

The third insulating resin layer 4C covers the second insulating resin layer 4B and the second conductive portion 6B, and has an opening 5C at a position aligned with the second conductive portion 6B.
The third conductive portion 6C is a wiring layer that is provided so as to cover a part of the third insulating resin layer 4C and is electrically connected to the second conductive portion 6B through the opening 5C.
The fourth insulating resin layer 4D covers the third insulating resin layer 4C and the third conductive portion 6C, and has an opening 5D at a position aligned with the third conductive portion 6C.
The fourth conductive portion 6D is a wiring layer that is provided so as to cover a part of the fourth insulating resin layer 4D and is electrically connected to the third conductive portion 6C through the opening 5D.
The sealing resin layer 7 covers the fourth insulating resin layer 4D and the fourth conductive portion 6D, and has an opening 8 at a position aligned with the fourth conductive portion 6D.

In the semiconductor device 21 configured as described above, the upper surface of the first insulating resin layer 4A, which is the first resin layer, also has the second insulating resin layer 4B, the third insulating resin layer 4C, which is the second resin layer, Since the upper surfaces of the fourth insulating resin layer 4D and the sealing resin layer 7 are also flattened, a resin layer having good pattern accuracy can be easily formed, and the conductive portions and the resin layers are alternately formed. Thus, a semiconductor device can be obtained in which a large number of conductive layers are stacked to achieve a multi-layered conductive portion.
FIG. 5 shows an example in which the openings 8 overlap at substantially the same position in the thickness direction, but the present invention is not limited to this. For example, the opening 8 may be configured to partially overlap or not overlap at all in the thickness direction.

Furthermore, the semiconductor device of the present invention showing an example of the second embodiment of the present semiconductor device can have a reliable and stable multilayer structure as shown in FIG. FIG. 6 is a cross-sectional view showing an example of the fourth embodiment of the semiconductor device.
As shown in FIG. 6, the semiconductor device 31 in this embodiment includes a semiconductor substrate 2, a first insulating resin layer 4A as a buffer layer provided on the upper surface of the semiconductor substrate 2, and the first insulating resin layer 4A. At least a first conductive portion 6A provided on the top surface of the first conductive portion 6A and a second insulating resin layer 4B as a buffer layer provided on the top surface of the first conductive portion 6A. A convex portion 14 is provided on the upper surface of the insulating resin layer 4B. Then, the second conductive portion 6B is provided on the upper surface of the second insulating resin layer 4B, and the sealing resin layer 7 is provided on the upper surface of the second conductive portion 6B.

The second insulating resin layer 4B covers the first insulating resin layer 4A and the first conductive portion 6A, and has an opening 5B at a position aligned with the first conductive portion 6A. The convex portion 14 is also provided in a region where the second conductive portion 6B is not provided.
In the same manner as forming the opening in the semiconductor device according to the first embodiment shown in FIG. 1, the protrusion 14 and the second insulating resin layer 4B are pressed by a mold that forms the opening 5B. Formed simultaneously. Thereby, since the convex part 14 is formed simultaneously with the formation of the second insulating resin layer 4B and the opening 5B, the process is simplified.

  In the semiconductor device 31 configured as described above, the second conductive portion 6B is provided in a region where the convex portion 14 is not provided on the upper surface of the second insulating resin layer 4B, and the sealing resin 7 is provided so as to cover the second insulating resin layer 4B together with the convex portion 14 provided on the upper surface thereof, so that the adhesiveness with the upper layer when multilayered by the convex portion 14 can be improved. It becomes. Therefore, the adhesiveness between the laminated resins becomes good, and a multilayered structure can be obtained reliably and stably.

  The present invention has good pattern accuracy, high electrical connection reliability, and can be easily formed in a short time. Therefore, the present invention can be applied to various types of semiconductor devices of wafer level CSP type that are multi-layered and miniaturized.

It is sectional drawing which shows an example of the 1st semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the manufacturing process of the 1st semiconductor device which concerns on this invention. FIG. 3 is a cross-sectional view showing an example of a manufacturing process following the process shown in FIG. 2. It is sectional drawing which shows an example of the 2nd semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the 3rd semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the 4th semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the conventional semiconductor device. It is sectional drawing which shows an example of the manufacturing process of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 Semiconductor substrate, 3 Electrode, 4 Insulating resin layer (buffer layer), 5 1st opening part, 6 Conductive part (wiring layer), 7 Sealing resin layer, 8 2nd opening part, 9 Solder Bump, 10 mold, 14 convex.

Claims (9)

A semiconductor substrate provided with electrodes on one surface;
A first resin layer provided so as to cover one surface of the semiconductor substrate and having a first opening at a position aligned with the electrode;
A conductive portion provided so as to cover a part of the first resin layer and electrically connected to the electrode through the first opening;
A semiconductor device comprising at least a second resin layer that covers the first resin layer and the conductive portion and has a second opening at a position aligned with the conductive portion;
The first opening disposed in the first resin layer has an arbitrary shape when viewed from above, the side surface has a steep slope, and the upper surface of the first resin layer is flat. Is,
A semiconductor device.   The semiconductor device according to claim 1, wherein an upper surface of at least the second resin layer covering the conductive portion is flat.   3. The semiconductor device according to claim 1, wherein the conductive portion and the second resin layer are alternately laminated, and at least the number of lamination is two or more.   The semiconductor device according to claim 3, wherein the second resin layer has a convex portion in a region on the upper surface thereof where the conductive portion is not provided.   The semiconductor device according to claim 1, wherein the second resin layer is made of a photosensitive resin. A semiconductor substrate provided with electrodes on one surface;
A first resin layer provided so as to cover one surface of the semiconductor substrate and having a first opening at a position aligned with the electrode;
A conductive portion provided so as to cover a part of the first resin layer and electrically connected to the electrode through the first opening;
A method for manufacturing a semiconductor device comprising at least a second resin layer that covers the first resin layer and the conductive portion and has a second opening at a position aligned with the conductive portion,
Applying a first resin so as to cover the one surface of the semiconductor substrate provided with electrodes on one surface; and
After application of the first resin, an uneven surface of a mold having unevenness is pressed against the first resin application surface, and a convex region made of the first resin, and a concave region for exposing the electrode, Forming step B;
Step C of curing the first resin while pressing the mold, and forming a first opening by the concave region and a first resin layer by the convex region;
A method for manufacturing a semiconductor device, comprising: Following the step C,
Forming a conductive portion electrically connected to the electrode through the first opening so as to cover a part of the first resin layer; and
Applying a second resin so as to cover the first resin layer and the conductive portion; and
After the application of the second resin, the uneven surface of the mold having unevenness is pressed against the second resin application surface to expose the convex region made of the second resin and a part of the conductive portion. Forming a recessed region of
A step G of curing the second resin while pressing the mold, and forming a second opening by the concave region and a second resin layer by the convex region;
The method of manufacturing a semiconductor device according to claim 6, comprising at least:   The second resin layer has a convex portion in an area where the conductive portion is not provided on the upper surface, and the convex portion is formed simultaneously with the second resin layer by pressing the mold. The method of manufacturing a semiconductor device according to claim 7. 9. The method of manufacturing a semiconductor device according to claim 6, wherein the resin pressed against the mold is made of a photosensitive resin and is cured by exposure.

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