JP2017224790A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is suitable for use as a power control semiconductor device and can efficiently radiate heat, and to provide a method of manufacturing the semiconductor device.SOLUTION: A semiconductor device according to the invention includes: a heat sink including a center part and an outer periphery part which is an outer area of the center part on a rear surface; a substrate disposed on a surface of the heat sink; a semiconductor element disposed on the surface of the substrate; a first thermal interface material provided at the outer periphery part; and a second thermal interface material which is provided at the center part and thicker than the first thermal interface material.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device suitable for use as a power control semiconductor device and a manufacturing method thereof.

  Patent Document 1 discloses a semiconductor device having a function of radiating heat from a semiconductor element. In this semiconductor device, a thermal interface material is provided between the semiconductor element and the radiator. The thermal interface material is provided to reduce the thermal resistance between the semiconductor element and the heat radiating body.

JP 2014-143238 A

  A semiconductor device may be warped due to thermal stress. When warping occurs, the contact between the thermal interface material and the heat sink becomes unstable. At this time, the thermal resistance between the semiconductor element and the heat sink increases, and the semiconductor element becomes difficult to dissipate heat.

The present invention has been made to solve the above-described problems, and a first object is to obtain a semiconductor device capable of efficiently radiating heat.
The second object is to obtain a method for manufacturing a semiconductor device capable of efficiently dissipating heat.

  A semiconductor device according to the present invention includes a heat sink having a central portion and an outer peripheral portion that is an area outside the central portion on a back surface, a substrate disposed on a surface of the heat sink, and a surface of the substrate. , A first thermal interface material provided on the outer periphery, and a second thermal interface material provided at the center and thicker than the first thermal interface material.

A method for manufacturing a semiconductor device according to the present invention includes a step of disposing a semiconductor element on a surface of a substrate,
A step of disposing the substrate on a surface of a heat sink having a central portion and an outer peripheral portion which is an area outside the central portion; and a first opening at a position overlapping the outer peripheral portion of the first mask. Forming the first mask in a state where the first mask is disposed on the back surface, and the first mask is disposed on the back surface so that the first opening is disposed on the outer periphery. Applying a first thermal interface material to the outer peripheral portion so as to fill the outer periphery, forming a second opening at a position overlapping the central portion of the second mask thicker than the first mask, and the second mask Etching to form a groove in which the first thermal interface material is received, and the second mask, the back surface so that the first thermal interface material is in the groove. Placing, in a state in which the second mask is arranged on the rear surface, and a step of applying a second thermal interface material to the central portion so as to fill the second opening.

  In the semiconductor device according to the present invention, the second thermal interface material formed in the central portion is thicker than the first thermal interface material formed in the outer peripheral portion. When warpage occurs due to thermal stress, the semiconductor device may be unstable in contact with the heat sink at the center. Therefore, by providing a thick thermal interface material at the center, it is possible to stabilize the contact between the semiconductor device and the heat sink. For this reason, it is possible to efficiently dissipate heat from the semiconductor device.

  In the method for manufacturing a semiconductor device according to the present invention, the second thermal interface material formed in the central portion is formed using a second mask that is thicker than the first thermal interface material formed in the outer peripheral portion. Therefore, the second thermal interface material is formed thicker than the first thermal interface material. When warpage occurs due to thermal stress, the semiconductor device may be unstable in contact with the heat sink at the center. Therefore, by providing a thick thermal interface material at the center, it is possible to stabilize the contact between the semiconductor device and the heat sink. For this reason, it is possible to efficiently dissipate heat from the semiconductor device.

It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a top view of the semiconductor device concerning a comparative example. It is sectional drawing obtained by cut | disconnecting the semiconductor device which concerns on a comparative example along an I-II straight line. It is a top view of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 2 of this invention. It is an enlarged view of the semiconductor device which concerns on Embodiment 2 of this invention. It is a top view of the semiconductor device which concerns on Embodiment 3 of this invention.

  A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. The semiconductor device 100 according to the present embodiment includes a heat sink 14. The heat sink 14 is made of metal. The heat sink 14 includes a bolt fastening portion 18 for fastening the heat sink and the semiconductor device 100 with bolts. The bolt fastening portions 18 are arranged at the four corners of the back surface 141 of the heat radiating plate 14. The substrate 12 is disposed on the surface 142 of the heat sink 14. The substrate 12 has an insulating property. A semiconductor element 10 is disposed on the surface of the substrate 12. The surfaces of the heat sink 14, the substrate 12, and the semiconductor element 10 are sealed with a sealing material 16. The sealing material 16 is a resin.

  The heat radiating plate 14 includes a central portion 143 and an outer peripheral portion 144 on the back surface 141. The outer peripheral portion 144 is a region outside the central portion 143. A plurality of first thermal interface materials (Thermal Interface Material, hereinafter referred to as TIM) 20 are provided on the outer peripheral portion 144. A plurality of second TIMs 21 are provided in the central portion 143. The second TIM 21 is thicker than the first TIM 20. In the present embodiment, the bolt fastening portion 18 is disposed outside the outer peripheral portion 144.

  In the semiconductor device 100 according to the present embodiment, the semiconductor element 10 serves as a heat source. A substrate 12 on which the semiconductor element 10 is mounted is disposed on the surface 142 of the heat sink 14. In this structure, the back surface 141 of the heat radiating plate 14 becomes the heat radiating surface of the semiconductor device 100. The first TIM 20 and the second TIM 21 are disposed between the heat sink 14 and the heat sink when the semiconductor device 100 is bonded to the heat sink. The first TIM 20 and the second TIM 21 are provided to fill the gap between the heat sink 14 and the heat sink and reduce the thermal resistance. Therefore, by providing the first TIM 20 and the second TIM 21 on the heat dissipation surface, it is possible to easily transfer the heat generated from the semiconductor element 10 to the heat sink. Therefore, the semiconductor device 100 can be efficiently dissipated.

  As materials for the first TIM 20 and the second TIM 21, metals such as indium, silicon, ceramics, graphite, carbon nanotubes, rubber, thermal conductive grease, and phase change materials can be used.

  Next, a method for manufacturing the semiconductor device 100 will be described. 2 to 7 are views showing a method of manufacturing the semiconductor device according to the first embodiment of the present invention. For convenience, the numbers of the first TIM 20 and the second TIM 21 are different from those in FIG. 1 in FIGS. 3, 4, 6, and 7, the substrate 12, the semiconductor element 10, and the bolt fastening portion 18 are omitted.

  First, the semiconductor element 10 is disposed on the surface of the substrate 12. Next, bolt fastening portions 18 are formed at the four corners of the heat sink 14. Next, the substrate 12 is disposed on the surface 142 of the heat sink 14. Next, the heat radiating plate 14, the substrate 12, and the surface of the semiconductor element 10 are sealed with a sealing material 16. Next, as shown in Step 1 of FIG. 2, a plurality of first openings 51 are formed in the first mask 50. The first opening 51 is formed at a position overlapping the outer peripheral portion 144 when the first mask 50 is disposed on the back surface 141 of the heat sink 14.

  Next, as shown in Step 2 of FIG. 3, the first mask 50 is disposed on the back surface 141 of the heat sink 14. At this time, the first mask 50 is disposed so that the first opening 51 is disposed on the outer peripheral portion 144. Next, the first TIM 20 is applied from the front surface of the first mask 50 to the outer peripheral portion 144 with the first mask 50 disposed on the back surface 141. In this step, the first TIM 20 is applied using the squeegee 52 so as to fill the first opening 51. Next, as shown in step 3 of FIG. 4, the first mask 50 is removed. As described above, the first TIM 20 is formed on the outer peripheral portion 144.

  Next, as shown in Step 4 of FIG. 5, a plurality of second openings 55 are formed in the second mask 54. The second mask 54 is thicker than the first mask 50. The second opening 55 is formed at a position overlapping the central portion 143 when the second mask 54 is disposed on the back surface 141 of the heat sink 14. Next, the second mask 54 is etched to form a plurality of grooves 56. The groove 56 is formed at a position overlapping the first TIM 20 when the second mask 54 is disposed on the back surface 141 of the heat sink 14. Further, the groove 56 has a bottom area and a depth in which the first TIM 20 can be accommodated. In the present embodiment, one first TIM 20 is accommodated in one groove 56. In contrast, a plurality of first TIMs 20 may be accommodated in one groove 56.

  Next, as shown in Step 5 of FIG. 6, the second mask 54 is disposed on the back surface 141 so that the first TIM 20 is accommodated in the groove 56. Next, the second TIM 21 is applied from the front surface of the second mask 54 to the central portion 143 with the second mask 54 disposed on the back surface 141. In this step, the second TIM 21 is applied using the squeegee 52 so as to fill the second opening 55. Next, as shown in Step 6 of FIG. 7, the second mask 54 is removed. As described above, the second TIM 21 is formed in the central portion 143.

  In step 4, the groove 56 was formed after the second opening 55 was formed in the second mask 54. On the other hand, the second opening 55 may be formed after the groove 56 is formed. The first mask 50 and the second mask 54 are metal masks. As the second mask 54, a mask for half etching is used.

  FIG. 8 is a plan view of a semiconductor device according to a comparative example. FIG. 9 is a cross-sectional view obtained by cutting the semiconductor device according to the comparative example along the I-II line. The semiconductor device 800 according to the comparative example includes a TIM 820 having a uniform thickness on the back surface 141 of the heat sink 14. Other structures are the same as those of the semiconductor device 100. Similar to the semiconductor device 100, the heat sink 14 is made of metal. Moreover, the sealing material 16 is resin. At this time, the linear expansion coefficient of the sealing material 16 is larger than the linear expansion coefficient of the heat sink 14. Therefore, the semiconductor device 800 warps so as to be convex opposite to the side on which the TIM 820 is formed due to the temperature rise.

  The semiconductor device 800 is fastened with a heat sink and a bolt. When warpage occurs in the semiconductor device 800, the contact between the semiconductor device 800 and the heat sink becomes unstable at the central portion of the heat radiating plate 14 away from the bolt fastening portion 18. Therefore, the heat dissipation efficiency of the semiconductor device 800 may decrease. Further, there is a possibility that a gap is generated between the heat sink and the TIM 820 in the central portion due to warpage. At this time, when the TIM 820 wets and spreads, the TIM 820 may be insufficient. Therefore, the wettability of the TIM 820 is deteriorated, and there is a possibility that heat can not be efficiently dissipated.

  As a countermeasure against a reduction in heat dissipation efficiency due to warpage of the semiconductor device 800, it is conceivable to form the TIM 820 with a uniform thickness. By forming the TIM 820 thick, the shortage of the TIM 820 at the center can be compensated. On the other hand, the thicker the TIM 820, the stronger the stress acting on the periphery of the bolt fastening portion 18 during bolt fastening. For this reason, when TIM 820 is applied thickly, a strong stress acts on the end portion of the substrate 12 at the time of bolt fastening. For this reason, the board | substrate 12 may crack. Therefore, when TIM 820 is applied thickly, resistance to bolt tightening may be reduced. Further, when the substrate 12 is cracked, the insulating function of the semiconductor device 800 is degraded.

  In the semiconductor device 100 according to the present embodiment, the thick second TIM 21 is formed in the central portion 143 of the heat sink 14. For this reason, when the semiconductor device 100 has a warp that is convex opposite to the side on which the TIM is formed, the contact between the semiconductor device 100 and the heat sink at the central portion 143 can be stabilized. In addition, since the thick second TIM 21 is formed in the central portion 143, the amount of TIM per unit area is larger in the central portion 143 than in the outer peripheral portion 144. For this reason, the shortage of TIM in the center part 143 can be prevented. Therefore, when the second TIM 21 spreads wet, the wettability can be improved.

  In the semiconductor device 100 according to the present embodiment, the first TIM 20 provided on the outer peripheral portion 144 is formed thin. Here, the thicker the TIM around the bolt fastening portion 18, the stronger the stress acting on the periphery of the bolt fastening portion 18 during bolt fastening. For this reason, the stress acting on the periphery of the bolt fastening portion 18 can be reduced by forming the first TIM 20 provided in the outer peripheral portion 144 thin. Therefore, in this embodiment, it is possible to prevent the substrate 12 from cracking and to prevent the insulation function from deteriorating. Moreover, it becomes possible to improve the tolerance with respect to bolt fastening.

  In the semiconductor device 100 according to the present embodiment, the central portion 143 where the thick second TIM 21 is formed includes a region facing the arrangement position of the semiconductor element 10 with the heat sink 14 interposed therebetween. In the vicinity of the semiconductor element 10 that is a heat source, the temperature tends to increase. By providing a thick TIM in the central portion 143, which is a region close to the semiconductor element 10, heat can be efficiently radiated. Further, the central portion 143 may be provided so as to include a part of a region facing the arrangement position of the semiconductor element 10 and the heat sink 14.

  The number of the first TIM 20 and the second TIM 21 provided on the heat sink 14 is not limited to that shown in FIG. In FIG. 1, the second TIM 21 is wider than the first TIM 20. On the other hand, the second TIM 21 may have the same width or the same area as the first TIM 20 as long as the second TIM 21 is provided thicker than the first TIM 20. Further, the shape of the first TIM 20 and the second TIM 21 in a plan view may be arbitrary. In the present embodiment, the semiconductor device 100 includes a plurality of first TIMs 20 and a plurality of second TIMs 21. On the other hand, the semiconductor device 100 may include one first TIM 20 and one second TIM 21 one by one. In this case, the second TIM 21 is formed so as to cover the central portion 143. The first TIM 20 is formed so as to cover the outer peripheral portion 144 and surround the second TIM 21.

  In the present embodiment, the first TIM 20 and the second TIM 21 having thicknesses set in two stages are provided. On the other hand, the semiconductor device 100 may include a TIM having a thickness set in three or more stages. In this case, the TIM is formed so that the thickness of the TIM decreases from the central portion 143 toward the outer peripheral portion 144.

  In semiconductor device 100 according to the present embodiment, outer peripheral portion 144 is provided outside center portion 143. The outer peripheral portion 144 may be disposed so as to surround the central portion 143. Moreover, the outer peripheral part 144 may be arrange | positioned at the both sides of the longitudinal direction of the heat sink 14 so that the center part 143 may be pinched | interposed. Further, in the present embodiment, the outer peripheral portion 144 is an area outside the central portion 143 and is disposed inside the bolt fastening portion 18. On the other hand, the outer peripheral portion 144 may be provided up to the end portion of the semiconductor device 100. In this case, the first TIM 20 is formed up to the end of the semiconductor device 100. Further, the bolt fastening portion 18 is surrounded by the outer peripheral portion 144.

  Further, in the present embodiment, the bolt fastening portions 18 are disposed at the four corners of the heat radiating plate 14. On the other hand, the bolt fastening portion 18 may be arranged at one place on both sides of the heat radiating plate 14. Further, the bolt fastening portion 18 may be arranged at another location as long as it is formed outside the central portion 143 of the heat radiating plate 14. These modifications can be applied as appropriate to semiconductor devices according to the following embodiments.

Embodiment 2. FIG.
FIG. 10 is a plan view of the semiconductor device according to the second embodiment of the present invention. FIG. 11 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention. The semiconductor device 200 according to the present embodiment includes a first TIM 220 and a second TIM 221. Other structures are the same as those of the semiconductor device 100. The semiconductor device 200 according to the present embodiment includes a first TIM 220 on the outer peripheral portion 144. In addition, a second TIM 221 that is thicker than the first TIM 220 is provided in the central portion 143.

  The first TIM 220 has a plurality of portions 226 separated from each other. The second TIM 221 has a plurality of portions 222 that are separated from each other. The area of each of the plurality of portions 222 of the second TIM 221 is larger than the area of each of the plurality of portions 226 of the first TIM 220.

  FIG. 12 is an enlarged view of the semiconductor device according to the second embodiment of the present invention. FIG. 12 is an enlarged view of the central portion 143 according to the present embodiment. In the present embodiment, the central portion 143 is covered with the second TIM 221. The second TIM 221 is formed from a plurality of portions 222. The plurality of portions 222 forming the second TIM 221 are separated from each other by a gap 224. Each of the plurality of portions 222 of the second TIM 221 is a quadrangular shape with rounded corners. The second TIM 221 is formed by regularly arranging a plurality of portions 222.

  Similar to the central portion 143, the outer peripheral portion 144 is covered with the first TIM 220. Similar to the second TIM 221, the plurality of portions 226 forming the first TIM 220 are separated from each other by gaps. Each of the plurality of portions 226 of the first TIM 220 is a hexagon having a smaller area than each of the plurality of portions 222 of the second TIM 221. The first TIM 220 is formed by regularly arranging a plurality of portions 226. In the semiconductor device 200 according to the present embodiment, the central portion 143 has a larger area covered by the TIM per unit area than the outer peripheral portion 144.

  Next, a method for manufacturing the semiconductor device 200 will be described. The manufacturing method of the semiconductor device 200 is different from that of the first embodiment in the step of forming the first opening 51 and the second opening 55 in the first mask 50 and the second mask 54. The rest is the same as in the first embodiment. Similar to the manufacturing method of the semiconductor device 100, the first TIM 220 is formed using the first mask 50. The second TIM 221 is formed using a second mask 54 that is thicker than the first mask 50.

  A plurality of first openings 51 are formed in the first mask 50. A plurality of second openings 55 are formed in the second mask 54. The area of each second opening 55 is formed to be larger than the area of each first opening 51. By using the first mask 50 and the second mask 54, the area of each portion 222 of the second TIM 221 becomes larger than the area of each portion 226 of the first TIM 220.

  Further, the second mask 54 is formed so that the ratio of the print opening area is larger than that of the first mask 50 and the ratio of the mask slit area is smaller. That is, the area occupied by the second opening 55 per unit area of the second mask 54 is larger than the area occupied by the first opening 51 per unit area of the first mask 50. By using the first mask 50 and the second mask 54, the central portion 143 has a larger area covered by the TIM per unit area than the outer peripheral portion 144.

  If the gap formed between the TIMs is large, the amount of air that is engulfed in the TIM when the TIM spreads wet. The air entrained by the TIM expands and contracts due to temperature changes. For this reason, when the TIM entrains air, the TIM is pushed out by the expansion of the air, and there is a possibility that a pumping out in which the TIM contracts by entraining the external air due to the contraction of the air may occur. When pumping out occurs, the contact between the semiconductor device and the heat sink becomes unstable. Therefore, if the amount of air that the TIM entrains increases, the product life may be reduced.

  In contrast, in the semiconductor device 200 according to the present embodiment, the area of each of the plurality of portions 222 of the second TIM 221 is larger than the area of each of the plurality of portions 226 of the first TIM 220. By forming the second TIM 221 covering the central portion 143 from the portion 222 having a large area, when the first TIM 220 and the second TIM 221 spread out wet, it becomes difficult to entrain air inside. Further, the central portion 143 has a larger area covered by the TIM per unit area than the outer peripheral portion 144. Therefore, the central portion 143 has a smaller area ratio occupied by the gap than the outer peripheral portion 144. Since the gap 224 is narrowly formed in the central portion 143, when the first TIM 220 and the second TIM 221 are spread and spread, it becomes difficult to entrain air inside. Therefore, the amount of air included in the first TIM 220 and the second TIM 221 can be reduced. At this time, it becomes possible to suppress pumping out with respect to a temperature change such as a temperature cycle test. Therefore, the product life can be improved.

  In the semiconductor device 200, the shape of each portion 226 of the first TIM 220 is a hexagon. Further, the shape of each portion 222 of the second TIM 221 is a quadrangular shape with rounded corners. On the other hand, the shape of each part of the first TIM 220 and the second TIM 221 may be an arbitrary shape. In the present embodiment, the first TIM 220 and the second TIM 221 have different thicknesses and areas. On the other hand, each of the plurality of portions 226 of the first TIM 220 and each of the plurality of portions 222 of the second TIM 221 may have the same thickness and different areas.

Embodiment 3 FIG.
FIG. 13 is a plan view of a semiconductor device according to the third embodiment of the present invention. The semiconductor device 300 includes a position recognition mark 360. Other structures are the same as those of the semiconductor device 200. The position recognition mark 360 is disposed on the back surface 141 of the heat sink 14.

  Next, a method for manufacturing the semiconductor device 300 will be described. In the method for manufacturing the semiconductor device 300, the manufacturing apparatus includes a step of reading the position recognition mark 360 in the step of arranging the second mask 54 on the back surface 141. The manufacturing apparatus collates the position of the position recognition mark 360 with the position information of the design drawing. From this result, the amount of positional deviation between the second mask 54 and the heat sink 14 is calculated. Further, the second mask 54 is disposed on the back surface 141 of the heat sink 14 after correcting the calculated positional deviation amount.

  As a result, the second mask 54 can be arranged with high accuracy so that the first TIM 220 can be accommodated in the groove 56. Therefore, the second TIM 221 can be applied without interfering with the first TIM 220. Further, the step of placing the first mask 50 on the back surface 141 may include a step of reading the position recognition mark 360. Thereby, the first TIM 220 can be arranged with high accuracy. Accordingly, defects in the TIM printing process can be reduced.

  In addition to the semiconductor element 10 formed of silicon, a semiconductor element 10 formed of a wide band gap semiconductor may be used. Wide band gap semiconductors include silicon carbide, gallium nitride-based materials, and diamond. Wide band gap semiconductors have high heat resistance. For this reason, the heat resistance of the semiconductor element 10 can be improved. By improving the heat resistance of the semiconductor element 10, the heat sink 14 and the heat sink can be reduced in size. Therefore, it is possible to reduce the size of the semiconductor devices 100, 200, and 300 and the device on which the semiconductor devices are mounted. The technical features described in each embodiment may be used in appropriate combination.

100, 200, 300 Semiconductor device, 143 Central part, 144 Outer part, 141 Back surface, 14 Heat sink, 12 Substrate, 10 Semiconductor element, 20, 220 1st TIM, 21 221 2nd TIM, 18 Bolt fastening part, 360 Position recognition Mark, 50 First mask, 54 Second mask, 51 First opening, 55 Second opening, 56 Groove, 222, 226

Claims (10)

A heat sink with a central portion and an outer peripheral portion that is an area outside the central portion on the back surface,
A substrate disposed on a surface of the heat sink;
A semiconductor element disposed on a surface of the substrate;
A first thermal interface material provided on the outer periphery;
A second thermal interface material provided in the central portion and thicker than the first thermal interface material;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the heat radiating plate includes a bolt fastening portion outside the center portion.   The semiconductor device according to claim 1, wherein the central portion includes a region facing the arrangement position of the semiconductor element with the heat sink interposed therebetween. The first thermal interface material has a plurality of parts separated from each other;
The second thermal interface material has a plurality of portions separated from each other;
The area of each of the plurality of portions of the second thermal interface material is larger than the area of each of the plurality of portions of the first thermal interface material. A semiconductor device according to 1.   The semiconductor device according to claim 1, further comprising a position recognition mark for obtaining position information on the back surface on the back surface. Placing a semiconductor element on the surface of the substrate;
A step of disposing the substrate on the surface of the heat radiating plate provided on the back surface with a central portion and an outer peripheral portion which is a region outside the central portion;
Forming a first opening at a position overlapping the outer periphery of the first mask;
Disposing the first mask on the back surface such that the first opening is disposed on the outer periphery; and
Applying the first thermal interface material to the outer peripheral portion so as to fill the first opening with the first mask disposed on the back surface;
Forming a second opening at a position overlapping the central portion of the second mask that is thicker than the first mask;
Etching the second mask to form a groove for receiving the first thermal interface material;
Placing the second mask on the back surface such that the first thermal interface material fits in the groove;
Applying the second thermal interface material to the central portion so as to fill the second opening in a state where the second mask is disposed on the back surface;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 6, further comprising a step of forming a bolt fastening portion outside the central portion of the heat radiating plate.   The method of manufacturing a semiconductor device according to claim 6, wherein the central portion includes a region facing the arrangement position of the semiconductor element with the heat sink interposed therebetween. Forming a plurality of the first openings in the first mask;
Forming a plurality of second openings in the second mask;
9. The method of manufacturing a semiconductor device according to claim 6, wherein an area of each of the plurality of second openings is larger than an area of each of the plurality of first openings. The heat radiating plate includes a position recognition mark for obtaining position information on the back surface on the back surface,
Reading the position recognition mark;
A step of calculating a positional deviation amount;
The method for manufacturing a semiconductor device according to claim 6, comprising:

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