JP2017212426A - Mounting structure of capacitor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress vibration generated in a circuit module formed by embedding a plurality of capacitor elements on a wiring board with a sealing resin layer.SOLUTION: A circuit module is formed in which a first multilayer ceramic capacitor 10A and a second multilayer ceramic capacitor 10B each having a rectangular parallelepiped shape are embedded on a wiring board 2 with a sealing resin layer 5. The first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are arranged side by side along a direction parallel to and near a principal surface of the wiring board 2, and are electrically connected in series or in parallel via a conductive pattern mounted on the wiring board 2. One of a pair of end surface 15 included in the first multilayer ceramic capacitor 10A is arranged so as to face one of width-direction side surfaces 17 as a pair of side surfaces included in the second multilayer ceramic capacitor 10B via the sealing resin layer 5.SELECTED DRAWING: Figure 12

Description

  The present invention relates to a capacitor element mounting structure in which a plurality of rectangular parallelepiped capacitor elements are mounted on a wiring board, and the plurality of capacitor elements are embedded in a sealing resin layer on the wiring board.

In recent years, with the increase in performance of electronic devices, the capacity of multilayer ceramic capacitors as electronic components has been increasing. In a large capacity multilayer ceramic capacitor, a ceramic material having a high dielectric constant such as barium titanate (BaTiO ₃ ) is used as a dielectric material.

  Since these high dielectric constant ceramic materials have piezoelectricity and electrostrictive properties, in a multilayer ceramic capacitor including a dielectric made of a high dielectric constant ceramic material, when a voltage is applied, it is mechanical. Distortion will occur.

  Therefore, when an AC voltage or a DC voltage on which an AC component is superimposed is applied to a large-capacity multilayer ceramic capacitor mounted on a wiring board, vibration is generated due to mechanical distortion generated in the ceramic material. As a result, the vibration is propagated to the wiring board, causing the circuit board to vibrate.

  Here, when the circuit board vibrates at a frequency of 20 [Hz] to 20 [kHz] which is an audible frequency range due to the propagated vibration, a so-called “acoustic noise” is generated. Become.

  For example, a DC / DC converter mounted on an electronic device converts a direct current voltage into a predetermined direct current voltage suitable for each electronic device and supplies it as electric power. In order to reduce noise generated based on a switching operation, a decoupling multilayer ceramic capacitor is connected to the circuit. A ripple voltage superimposed on a DC voltage is applied to the multilayer ceramic capacitor by the switching operation. However, the ripple voltage causes mechanical distortion having a frequency in the audible frequency range in the multilayer ceramic capacitor. As this propagates to the wiring board, noise is generated in the circuit board.

  In addition, when a sensor such as an acceleration sensor or an angular velocity sensor is mounted on the wiring board on which the multilayer ceramic capacitor is mounted, the circuit board may vibrate to cause malfunction of these sensors.

  Therefore, conventionally, various techniques for suppressing vibration of the circuit board due to mechanical distortion of the multilayer ceramic capacitor have been proposed. For example, in Japanese Patent Laid-Open No. 2000-233203 (Patent Document 1), a pair of multilayer ceramic capacitors having equivalent specifications are mounted symmetrically at corresponding positions on the front and back surfaces of a wiring board, thereby providing one multilayer ceramic. A mounting structure in which the vibration propagated from the capacitor to the wiring board and the vibration propagated from the other monolithic ceramic capacitor to the wiring board cancel each other, thereby suppressing the vibration of the circuit board Is disclosed.

  Japanese Patent Laid-Open No. 2002-232110 (Patent Document 2) discloses a method of mounting a pair of multilayer ceramic capacitors close to each other so that their long axes are arranged in parallel on the same main surface of the wiring board. The circuit board is designed to suppress the vibration of the circuit board by applying a ripple voltage to the pair of multilayer ceramic capacitors so that the vibration of the vibration wave transmitted to the A structure is disclosed.

  The mounting structures disclosed in Patent Documents 1 and 2 described above are each mounted so that the multilayer ceramic capacitor is exposed on the main surface of the wiring board. However, as a multilayer ceramic capacitor mounting structure, in addition to this, by covering the main surface of the wiring board on which the multilayer ceramic capacitor is mounted with a sealing resin layer, the multilayer ceramic capacitor can be applied to the sealing resin layer. Some of them are embedded. For example, International Publication No. 2011-135926 (Patent Document 3) is a document in which the configuration is disclosed.

JP 2000-23320 A Japanese Patent Laid-Open No. 2002-232110 International Publication No. 2011/135926

  Here, there is a significant difference in the mode of vibration generated on the circuit board between when the multilayer ceramic capacitor is exposed on the wiring board and when the multilayer ceramic capacitor is embedded in the sealing resin layer on the wiring board. Arise. In the former, the vibration transmission path is limited to the solder joint in the former, whereas in the latter, the vibration transmission path is not limited to the solder joint, and the sealing resin layer that embeds the multilayer ceramic capacitor is also included. This is because it becomes a vibration transmission path. In addition, when the entire main surface of the wiring board on which the multilayer ceramic capacitor is mounted is covered with a sealing resin layer, vibrations are generated not only on the wiring board but also on the entire circuit board including the sealing resin layer. Therefore, the aspect of vibration is also different in this respect.

  Therefore, it can be said that the technique as disclosed in Patent Documents 1 and 2 described above can be suitably applied to a mounting structure in which a multilayer ceramic capacitor is necessarily embedded in a sealing resin layer on a wiring board. Absent.

  Therefore, the present invention has been made in view of the above-described situation, and in a mounting structure for a capacitor element in which a plurality of capacitor elements are embedded in a sealing resin layer on a wiring board, the mounting structure The purpose is to suppress vibrations generated in

  A capacitor element mounting structure according to a first aspect of the present invention includes a first capacitor element and a second capacitor element including a rectangular parallelepiped laminate including dielectric layers and internal electrode layers alternately laminated in the lamination direction. A capacitor element; a wiring board including a main surface on which the first capacitor element and the second capacitor element are mounted; and a sealing resin layer embedding the first capacitor element and the second capacitor element. Yes. The first capacitor element and the second capacitor element are electrically connected in series or in parallel via a conductive pattern provided on the wiring board. The surfaces of the first capacitor element and the second capacitor element facing the wiring board have a short side and a long side. Each of the first capacitor element and the second capacitor element includes a pair of end faces that are positioned relative to each other in the direction in which the long side extends, and a pair of terminals that are positioned relative to each other in the direction in which the short side extends. It has a side surface and a pair of external electrodes provided on the outer surface of the laminate so as to be separated from each other. Each of the external electrodes included in the first capacitor element and the second capacitor element is bonded to a land provided on the wiring board corresponding to each of the external electrodes via a conductive bonding member. ing. One of the pair of end faces of the first capacitor element faces one of the pair of side faces of the second capacitor element via the sealing resin layer.

  In the capacitor element mounting structure according to the first aspect of the present invention, the stacking direction of the first capacitor element and the stacking direction of the second capacitor element are both of the wiring board. It is preferable to face the direction along the main surface.

  A capacitor element mounting structure according to a second aspect of the present invention includes a first capacitor element including a rectangular parallelepiped-shaped multilayer body including dielectric layers and internal electrode layers alternately stacked along the stacking direction, A capacitor element, a third capacitor element, a wiring board including a main surface on which the first capacitor element, the second capacitor element, and the third capacitor element are mounted; the first capacitor element; the second capacitor element; And a sealing resin layer for embedding the third capacitor element. The first capacitor element, the second capacitor element, and the third capacitor element are electrically connected in series or in parallel via a conductive pattern provided on the wiring board. The surfaces of the first capacitor element, the second capacitor element, and the third capacitor element that face the wiring board have a short side and a long side. Each of the first capacitor element, the second capacitor element, and the third capacitor element has a pair of end faces that are positioned relative to each other in the direction in which the long side extends and a relative direction in the direction in which the short side extends. And a pair of external electrodes provided apart from each other on the outer surface of the laminate. Each of the external electrodes included in the first capacitor element, the second capacitor element, and the third capacitor element is a conductive bonding member on a land provided on the wiring board corresponding to each of the external electrodes. Are joined to each other. One of the pair of end faces of the first capacitor element, the pair of end faces of the second capacitor element, and the pair of end faces of the third capacitor element is the pair of end faces of the first capacitor element. The first capacitor is opposed to any one of the side surfaces of the second capacitor element, the pair of side surfaces of the second capacitor element, and the pair of side surfaces of the third capacitor element via the sealing resin layer. The remaining one of the pair of end surfaces of the element, the pair of end surfaces of the second capacitor element, and the pair of end surfaces of the third capacitor element is the pair of side surfaces of the first capacitor element, It faces one of the pair of side surfaces of the second capacitor element and the pair of side surfaces of the third capacitor element through the sealing resin layer.

  In the capacitor element mounting structure according to the second aspect of the present invention, one of the pair of end faces of the first capacitor element is one of the pair of side faces of the second capacitor element. One side of the pair of end surfaces of the first capacitor element is opposed to the other side of the pair of side surfaces of the third capacitor element. You may oppose through a stop resin layer.

  In the capacitor element mounting structure according to the second aspect of the present invention, one of the pair of end faces of the first capacitor element is one of the pair of side faces of the second capacitor element. One side of the pair of end surfaces of the third capacitor element is opposed to the other side of the pair of side surfaces of the second capacitor element, and the other side is opposed to the other side of the sealing resin layer. You may oppose through a stop resin layer.

  In the capacitor element mounting structure according to the second aspect of the present invention, one of the pair of end faces of the first capacitor element and one of the pair of end faces of the third capacitor element. One may face one of the pair of side surfaces of the second capacitor element via the sealing resin layer.

  In the capacitor element mounting structure according to the second aspect of the present invention, the stacking direction of the first capacitor element and the stacking direction of the second capacitor element are both of the wiring board. It is preferable to face the direction along the main surface.

  In the capacitor element mounting structure according to the second aspect of the present invention, the stacking direction of the third capacitor element may face the direction along the main surface of the wiring board.

  In the capacitor element mounting structure according to the second aspect of the present invention, the stacking direction of the third capacitor elements may face a direction not along the main surface of the wiring board.

  A capacitor element mounting structure according to a third aspect of the present invention includes a first capacitor element including a rectangular parallelepiped-shaped multilayer body including dielectric layers and internal electrode layers alternately stacked along a stacking direction, and a second capacitor element. A capacitor element, a third capacitor element, a fourth capacitor element, a wiring board including a main surface on which the first capacitor element, the second capacitor element, the third capacitor element and the fourth capacitor element are mounted; And a sealing resin layer that embeds the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element. The first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element are electrically connected in series or in parallel via a conductive pattern provided on the wiring board. The surfaces of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element that face the wiring board have a short side and a long side. Each of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element has a pair of end faces that are positioned relative to each other in a direction in which the long side extends, and the short side is It has a pair of side surfaces located opposite to each other in the extending direction, and a pair of external electrodes provided on the outer surface of the laminate so as to be separated from each other. Each of the external electrodes included in the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element is a land provided on the wiring board corresponding to each of the external electrodes. Are joined to each other via a conductive joining member. One of the pair of end faces of the first capacitor element faces one of the pair of side faces of the second capacitor element via the sealing resin layer. One of the pair of end faces of the second capacitor element faces one of the pair of side faces of the third capacitor element via the sealing resin layer. One of the pair of end faces of the third capacitor element is opposed to one of the pair of side faces of the fourth capacitor element via the sealing resin layer. One of the pair of end faces of the fourth capacitor element faces one of the pair of side faces of the first capacitor element via the sealing resin layer.

  In the capacitor element mounting structure according to the third aspect of the present invention, the stacking direction of the first capacitor element and the stacking direction of the second capacitor element are both of the wiring board. It is preferable to face the direction along the main surface.

  In the capacitor element mounting structure according to the third aspect of the present invention, the stacking direction of the third capacitor element and the stacking direction of the fourth capacitor element are the main layers of the wiring board. You may face the direction along the surface.

  In the capacitor element mounting structure according to the third aspect of the present invention, the stacking direction of the third capacitor element and the stacking direction of the fourth capacitor element are the main layers of the wiring board. You may face the direction not along the surface.

  A capacitor element mounting structure according to a fourth aspect of the present invention includes a first capacitor element including a rectangular parallelepiped-shaped multilayer body including dielectric layers and internal electrode layers alternately stacked along a stacking direction; A capacitor element, a third capacitor element, a fourth capacitor element, a wiring board including a main surface on which the first capacitor element, the second capacitor element, the third capacitor element and the fourth capacitor element are mounted; And a sealing resin layer that embeds the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element. The first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element are electrically connected in series or in parallel via a conductive pattern provided on the wiring board. The surfaces of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element that face the wiring board have a short side and a long side. Each of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element has a pair of end faces that are positioned relative to each other in a direction in which the long side extends, and the short side is It has a pair of side surfaces located opposite to each other in the extending direction, and a pair of external electrodes provided on the outer surface of the laminate so as to be separated from each other. Each of the external electrodes included in the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element is a land provided on the wiring board corresponding to each of the external electrodes. Are joined to each other via a conductive joining member. One of the pair of end faces of the first capacitor element faces one of the pair of side faces of the second capacitor element via the sealing resin layer. One of the pair of end faces of the third capacitor element is opposed to one of the pair of side faces of the fourth capacitor element via the sealing resin layer. The stacking direction of the first capacitor element and the stacking direction of the second capacitor element are all directed along the main surface of the wiring board. The stacking direction of the third capacitor element and the stacking direction of the fourth capacitor element are all directed in a direction not along the main surface of the wiring board.

  In the capacitor element mounting structure according to the fourth aspect of the present invention, the other of the pair of side surfaces of the second capacitor element is the one of the pair of end surfaces of the third capacitor element. It is preferable to face the other through the sealing resin layer.

  In the capacitor element mounting structure according to the fourth aspect of the present invention, one of the pair of side surfaces of the first capacitor element is one of the pair of side surfaces of the third capacitor element. One of the pair of end faces of the second capacitor element is opposed to the other via the sealing resin layer, and the sealing resin layer is disposed on one of the pair of end faces of the fourth capacitor element. It is preferable to face each other.

  Here, in the term “cuboid capacitor element” described above, there are rounded corners and ridges, and there are steps and irregularities on the surface that can be ignored as a whole. What is provided shall be included.

  In addition, the term “rectangular surface” described above includes a case where the corner of the outline is rounded, or the side of the outline is bent or bent so that it can be ignored as a whole. Shall be included.

  Further, the term “the end face and the side face each other” described above includes not only the case where the entire area of one of the end face and the side face the other face, but also the one face. A case where a part of the region faces only a part of the other surface is included.

  ADVANTAGE OF THE INVENTION According to this invention, the vibration which generate | occur | produces in the said mounting structure can be suppressed in the mounting structure body of the capacitor element formed by embedding a some capacitor | condenser element with the sealing resin layer on a wiring board.

1 is a perspective view of a multilayer ceramic capacitor provided in a circuit module according to an embodiment of the present invention. It is sectional drawing along the II-II line shown in FIG. 1 of the multilayer ceramic capacitor shown in FIG. It is sectional drawing along the III-III line | wire shown in FIG. 1 of the multilayer ceramic capacitor shown in FIG. It is a figure which shows the result of having simulated the distortion which arises at the time of a voltage application to the laminated body of the laminated ceramic capacitor shown in FIG. It is a schematic cross section which shows the 1st mounting aspect to the circuit module of the multilayer ceramic capacitor shown in FIG. It is a schematic cross section which shows the 2nd mounting aspect to the circuit module of the multilayer ceramic capacitor shown in FIG. FIG. 6 is a schematic diagram showing first to third layout patterns belonging to a first layout group when two multilayer ceramic capacitors are arranged close to each other. It is a schematic diagram which shows the 4th thru | or 6th layout pattern which belongs to the 2nd layout group in the case of arrange | positioning two multilayer ceramic capacitors adjacently. It is a schematic diagram which shows the 7th thru | or 10th layout pattern which belongs to the 3rd layout group in the case of arrange | positioning two multilayer ceramic capacitors adjacently. It is a schematic perspective view of the circuit module which concerns on a 1st structural example. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor with which the circuit module which concerns on a 1st structural example was equipped. FIG. 12 is a schematic cross-sectional view taken along line XII-XII shown in FIG. 11 of the circuit module according to the first configuration example. FIG. 13 is a diagram illustrating a circuit configuration example of a circuit including the multilayer ceramic capacitor illustrated in FIGS. 10 to 12. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor comprised by the circuit module which concerns on a 2nd structural example. It is a schematic cross section along the XV-XV line | wire shown in FIG. 14 of the circuit module which concerns on a 2nd structural example. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor comprised by the circuit module which concerns on a 3rd structural example. FIG. 17 is a schematic cross-sectional view taken along line XVII-XVII shown in FIG. 16 of the circuit module according to the third configuration example. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor comprised by the circuit module which concerns on a 4th. It is a schematic cross section along the XIX-XIX line shown in FIG. 18 of the circuit module which concerns on a 4th structural example. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor with which the circuit module which concerns on a 5th structural example was equipped. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor comprised by the circuit module which concerns on a 6th structural example. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor with which the circuit module which concerns on a 7th structural example was equipped. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor comprised by the circuit module which concerns on an 8th structural example. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor comprised by the circuit module which concerns on the 9th structural example. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor and IC provided in the circuit module according to the tenth configuration example. It is a model top view which shows the layout of the multilayer ceramic capacitor and IC which were equipped with the circuit module which concerns on an 11th structural example. It is a model top view which shows the layout of the multilayer ceramic capacitor and IC which were equipped with the circuit module which concerns on the 12th structural example. It is a figure which shows the mounting layout of the multilayer ceramic capacitor which concerns on the comparative examples 1 and 2 and Example 1, 2 verified in the 1st verification test. It is the schematic which shows the measuring method of the sound pressure level of the noise in a 1st verification test. It is a graph which shows the result of a 1st verification test. It is a figure which shows the mounting layout of the multilayer ceramic capacitor which concerns on the comparative example 3 and Example 3, 4 verified in the 2nd verification test. It is a graph which shows the result of the 2nd verification test. It is a figure which shows the mounting layout of the multilayer ceramic capacitor which concerns on Examples 5-8 which verified in the 3rd verification test. It is a figure which shows the mounting layout of the multilayer ceramic capacitor which concerns on Example 9 and 10 verified in the 3rd verification test. It is a graph which shows the result of a 3rd verification test.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, the same or common parts are denoted by the same reference numerals in the drawings, and description thereof will not be repeated.

  In the following embodiment, a circuit module in which a multilayer ceramic capacitor using a ceramic material as a dielectric material is embedded as a capacitor element will be described as an example. The circuit module to which the present invention can be applied includes a circuit module in which a laminated metallized film capacitor using a resin film as a dielectric material is embedded as a capacitor element.

  FIG. 1 is a perspective view of a multilayer ceramic capacitor provided in a circuit module according to an embodiment of the present invention. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along the line II-II shown in FIG. 1, and FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. FIG. First, the multilayer ceramic capacitor provided in the circuit module according to the present embodiment will be described with reference to FIGS.

  As shown in FIGS. 1 to 3, the multilayer ceramic capacitor 10 is an electronic component having a rectangular parallelepiped shape as a whole, and includes a multilayer body 11 and a pair of external electrodes 14.

  As shown in FIGS. 2 and 3, the multilayer body 11 includes dielectric layers 12 and internal electrode layers 13 that are alternately laminated along a predetermined direction. Dielectric layer 12 is formed of, for example, a ceramic material mainly composed of barium titanate. In addition, the dielectric layer 12 may contain a Mn compound, Mg compound, Si compound, Co compound, Ni compound, rare earth compound, or the like as a subcomponent of a ceramic powder that is a raw material of a ceramic sheet described later. On the other hand, the internal electrode layer 13 is formed of a metal material typified by Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or the like.

  The laminate 11 is prepared by preparing a plurality of material sheets on which a conductive paste to be the internal electrode layer 13 is printed on the surface of a ceramic sheet (so-called green sheet) to be the dielectric layer 12, and laminating the plurality of material sheets. Manufactured by crimping and firing.

The material of the dielectric layer 12 is not limited to the above-described ceramic material mainly composed of barium titanate, and other high dielectric constant ceramic materials (for example, those composed mainly of CaTiO ₃ , SrTiO _3, etc.) May be selected as the material of the dielectric layer 12. Further, the material of the internal electrode layer 13 is not limited to the metal material described above, and other conductive materials may be selected as the material of the internal electrode layer 13.

  As shown in FIGS. 1 and 2, the pair of external electrodes 14 are provided so as to be separated from each other so as to cover the outer surfaces of both end portions in a predetermined direction of the laminate 11. The pair of external electrodes 14 are each composed of a conductive film.

  The pair of external electrodes 14 is composed of a laminated film of a sintered metal layer and a plating layer, for example. A sintered metal layer is formed by baking pastes, such as Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, for example. A plating layer is comprised by the Ni plating layer and the Sn plating layer which covers this, for example. Instead of this, the plated layer may be a Cu plated layer or an Au plated layer. Further, the pair of external electrodes 14 may be constituted only by a plating layer.

  Furthermore, as the pair of external electrodes 14, a conductive resin paste containing a metal component and a resin component can be used. When a conductive resin paste is used as the pair of external electrodes 14, the resin component contained in the conductive resin paste exhibits an effect of absorbing vibration generated in the multilayer body 11, so that it propagates from the multilayer body 11 to the outside. It is possible to effectively attenuate the vibration that occurs.

  As shown in FIG. 2, one of the pair of internal electrode layers 13 adjacent to each other with the dielectric layer 12 sandwiched in the stacking direction is connected to one of the pair of external electrodes 14 inside the multilayer ceramic capacitor 10. The other of the pair of internal electrode layers 13 that are electrically connected and are adjacent to each other with the dielectric layer 12 sandwiched in the stacking direction is the other of the pair of external electrodes 14 in the multilayer ceramic capacitor 10. Is electrically connected. As a result, a plurality of capacitor elements are electrically connected in parallel between the pair of external electrodes 14.

  Here, as shown in FIGS. 1 to 3, the direction in which the pair of external electrodes 14 are arranged is defined as the length direction L of the multilayer ceramic capacitor 10, and the dielectric layer 12 and the internal electrode layer 13 in the multilayer body 11 are defined. When the stacking direction is defined as the thickness direction T, and the direction perpendicular to both the length direction L and the thickness direction T is defined as the width direction W, the multilayer ceramic capacitor 10 in the present embodiment is It has an elongated rectangular parallelepiped shape that is configured such that the outer dimension along the length is the longest.

  As representative values of the outer dimension in the length direction L and the outer dimension in the width direction W of the multilayer ceramic capacitor 10 (usually, the outer dimension in the thickness direction T is the same as the outer dimension in the width direction W), For example, 3.2 [mm] × 1.6 [mm], 2.0 [mm] × 1.25 [mm], 1.6 [mm] × 0.8 [mm], 1.0 [mm] × 0.5 [mm], 0.8 [mm] × 0.4 [mm], 0.6 [mm] × 0.3 [mm], 0.4 [mm] × 0.2 [mm], etc. Can be mentioned.

  In addition, among the six surfaces of the rectangular parallelepiped multilayer ceramic capacitor 10, a pair of surfaces positioned in the length direction L are defined as end surfaces 15, and four surfaces connecting the pair of end surfaces 15 are side surfaces 16, 17. It is defined as Further, of the four side surfaces 16 and 17, a pair of surfaces positioned relative to each other in the thickness direction T is defined as a thickness direction side surface 16, and a pair of surfaces positioned relative to each other in the width direction W is defined as a width direction side surface 17 The terms are defined and used in the following description. Each of the pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17 has a rectangular shape including a pair of long sides extending in the length direction L and a pair of short sides connecting the pair of long sides. ing.

  FIG. 4 is a diagram showing a result of simulating distortion generated when a voltage is applied to the multilayer ceramic capacitor body shown in FIG. Next, with reference to this FIG. 4, the distortion which may arise in the multilayer ceramic capacitor with which the circuit module in this Embodiment is equipped is demonstrated.

  When an AC voltage or a DC voltage on which an AC component is superimposed is applied to the pair of external electrodes 14 of the multilayer ceramic capacitor 10 described above, mechanical distortion as shown in FIG. This is a distortion of the multilayer ceramic capacitor 10.

As shown in FIG. 4, when a voltage is applied, the laminate 11 along the thickness direction T is distorted significantly larger outward as indicated by an arrow AR _T in the figure. Accordingly, the arrow AR laminate 11 along the length L is in slightly larger distortion, also laminated body 11 in the drawing along the width direction W inward as indicated by an arrow AR _L in the drawings _As shown by _W , it is slightly distorted inward. On the other hand, almost no distortion occurs in the corner 18 of the laminate 11 having an elongated rectangular parallelepiped shape. In the drawing, the distortion generated toward the outer side of the laminated body 11 is indicated by a white arrow, and the distortion generated toward the inner side of the laminated body 11 is indicated by a black arrow, and the magnitude of those distortions. Is indicated by the size of the arrow.

  Therefore, in the multilayer ceramic capacitor 10, the same distortion occurs when a voltage is applied, and the above-described distortion repeatedly occurs in accordance with the period of the voltage applied to the multilayer ceramic capacitor 10. . As a result, in the circuit module including the multilayer ceramic capacitor 10, the multilayer ceramic capacitor 10 serves as a vibration source, and the vibration is propagated to the sealing resin layer and the wiring board, so that the circuit module vibrates, resulting in noise. Occur or cause malfunction of other elements.

  5 and 6 are schematic cross-sectional views showing first and second mounting modes of the multilayer ceramic capacitor shown in FIG. 1 on a circuit module, respectively. As the mounting mode of the above-described multilayer ceramic capacitor to the circuit module, two mounting modes having different directions with respect to the wiring board are assumed. Hereinafter, the two implementation modes will be described with reference to FIGS. 5 and 6. Note that the cross sections shown in FIGS. 5B and 6B are cross sections taken along lines VB-VB and VIB-VIB shown in FIGS. 5A and 6A, respectively.

  As shown in FIGS. 5 and 6, in both the first mounting mode 10 (H) and the second mounting mode 10 (V), the multilayer ceramic capacitor 10 has a length that is a direction connecting the pair of end faces 15. Arranged on the main surface of the wiring board 2 so that the direction L faces the direction along the main surface of the wiring board 2. That is, one of the rectangular side surfaces 16 and 17 including the long side and the short side is a facing surface that faces the main surface of the wiring board 2. Furthermore, a sealing resin layer 5 is formed on the main surface of the wiring board 2 so as to embed the multilayer ceramic capacitor 10 in this state.

  The wiring substrate 2 is made of an insulating substrate having a conductive pattern formed on at least one of the pair of main surfaces. As a material of the wiring board 2, a material made of a resin material such as an epoxy resin, a ceramic material such as alumina, or a material in which a filler or a woven fabric made of an inorganic material or an organic material is added, or the like can be used. . Generally, as the wiring board 2, a glass epoxy board in which a glass woven fabric is added to a base material made of an epoxy resin is preferably used.

  A pair of lands 3 are provided on the main surface of the wiring board 2 so as to correspond to the multilayer ceramic capacitor 10. Each of the pair of lands 3 corresponds to a part of the conductive pattern described above, and is disposed so as to be spaced apart from each other.

  In addition, each of the pair of lands 3 is formed in a size corresponding to the pair of external electrodes 14 included in each of the multilayer ceramic capacitors 10, and both of the corresponding external electrodes 14 are connected to the wiring board 2. The part which opposes along the normal line direction of the main surface is included. In addition, as a material of a pair of land 3, various conductive materials can be utilized, but generally metal materials, such as copper foil, are utilized suitably.

  A pair of external electrodes 14 included in each of the multilayer ceramic capacitors 10 and a pair of lands 3 provided on the wiring board 2 are joined by a conductive joining member 4. As the joining member 4, for example, a conductive adhesive or solder can be used. Here, when a conductive adhesive is used as the bonding member 4, the resin component contained in the conductive adhesive exhibits an effect of absorbing vibration generated in the multilayer ceramic capacitor 10. It is possible to effectively attenuate the vibration propagating from the outside to the outside.

  The sealing resin layer 5 is positioned so as to cover the main surface of the wiring board 2 where the multilayer ceramic capacitor 10 is mounted, and embeds the multilayer ceramic capacitor 10 on the main surface of the wiring board 2. ing. More specifically, the sealing resin layer 5 is provided so as to cover the main surface of the wiring substrate 2, the surface of the land 3 provided on the wiring substrate 2, the surface of the bonding member 4, and the surface of the multilayer ceramic capacitor 10. The surface of these members is prevented from being exposed to the outside of the circuit module. It is preferable that the space between the wiring substrate 2 and the multilayer ceramic capacitor 10 and between the pair of lands 3 and between the pair of bonding members 4 is buried with the sealing resin layer 5. The space does not necessarily have to be embedded with the sealing resin layer 5, and the space may only be surrounded by the sealing resin layer 5.

  The material of the sealing resin layer 5 is not particularly limited, and various thermoplastic resin materials or thermosetting resin materials can be used. In addition, fillers made of various materials may be added to the sealing resin layer 5. From the viewpoint of the reliability of the circuit module, it is preferable that the difference in linear expansion coefficient between the wiring board 2 and various electronic components mounted thereon is preferably small. When the above-described glass epoxy board is used as the wiring board 2 For the sealing resin layer 5, an epoxy resin is usually used. Although not shown, a member such as a conductive layer may be separately provided on the surface of the sealing resin layer 5.

  In assembling the multilayer ceramic capacitor 10 to the circuit module, first, a conductive adhesive or solder paste is applied onto a pair of lands 3 provided in advance on the wiring board 2 by screen printing or the like, and then the multilayer ceramic capacitor 10 is laminated thereon. With the capacitor 10 being placed, these are put into a reflow furnace. Thereby, a fillet is formed in the joining member 4 and the multilayer ceramic capacitor 10 is mounted on the wiring board 2. Thereafter, a sealing resin layer 5 is formed on the main surface of the wiring board 2 on which the multilayer ceramic capacitor 10 is mounted by transfer molding, potting, or the like, whereby a circuit module is manufactured.

  Here, as shown in FIGS. 5A and 5B, in the first mounting mode 10 (H), the dielectric layer 12 and the internal electrode layer 13 in the multilayer body 11 of the multilayer ceramic capacitor 10. The stacking direction is such that the thickness direction T is a direction not along the main surface of the wiring board 2 (that is, the thickness direction T of the multilayer ceramic capacitor 10 is orthogonal to the main surface of the wiring board 2). A ceramic capacitor 10 is disposed on the wiring board 2. Thereby, in the said 1st mounting aspect 10 (H), one of the pair of thickness direction side surfaces 16 located facing in the thickness direction T of the multilayer ceramic capacitor 10 is the opposing surface 16a which opposes the wiring board 2. FIG. Will be.

  On the other hand, as shown in FIGS. 6A and 6B, in the second mounting mode 10 (V), the dielectric layers 12 and the internal electrode layers 13 in the multilayer body 11 of the multilayer ceramic capacitor 10. Stacking is performed so that the thickness direction T, which is the stacking direction, faces the direction along the main surface of the wiring board 2 (that is, the thickness direction T of the multilayer ceramic capacitor 10 is positioned parallel to the main surface of the wiring board 2). A ceramic capacitor 10 is disposed on the wiring board 2. As a result, in the second mounting mode 10 (V), one of the pair of width direction side surfaces 17 positioned in the width direction W of the multilayer ceramic capacitor 10 is opposed to the wiring substrate 2. Will be.

  7 to 9 are schematic views showing various layout patterns when two multilayer ceramic capacitors are arranged close to each other. Here, FIGS. 7A to 7C are schematic views showing first to third layout patterns belonging to the first layout group, respectively, and FIGS. 8A to 8C are FIGS. 9A to 9D are schematic views showing fourth to sixth layout patterns belonging to the second layout group, respectively, and FIGS. 9A to 9D show seventh to tenth layout patterns belonging to the third layout group, respectively. It is a schematic diagram. Next, details of various layout patterns when two multilayer ceramic capacitors are arranged close to each other will be described with reference to FIGS. 7 to 9, and when these layout patterns are adopted, these two of the circuit modules will be described. The magnitude of vibration generated in the region R where the single multilayer ceramic capacitors are arranged will be described. Here, the “vicinity” mentioned above means a range in which the distance between two ceramic capacitors is preferably 1.0 [mm] or less. 7 to 9, illustration of the sealing resin layer 5 is omitted.

  As shown in FIGS. 7A to 7C, the first to third layout patterns LP1 to LP3 belonging to the first layout group are all along the length direction L of the two multilayer ceramic capacitors. These two monolithic ceramic capacitors are arranged such that the axes are positioned parallel to each other on the main surface of the wiring board 2 with a distance.

  In the first layout pattern LP1 shown in FIG. 7A, two multilayer ceramic capacitors are both mounted in the above-described first mounting mode 10 (H). In this case, one of the pair of width direction side surfaces 17 of one multilayer ceramic capacitor faces one of the pair of width direction side surfaces 17 of the other multilayer ceramic capacitor through the sealing resin layer 5.

The and when the first layout pattern LP1, the X-axis direction shown in the figure, the distortion (see arrow AR _L) slightly greater along the length direction L that occurs in one of the multilayer ceramic capacitor, the other lamination slightly larger strain along the length L caused by ceramic capacitors (see arrow AR _L) but acts to amplify the oscillations with respect to each other in the region R, the vibration in the X-axis direction increases approximately equivalent. Also, the when the first layout pattern LP1 is the Y-axis direction shown in the figure, and one slightly larger distortion along the width direction W caused by the multilayer ceramic capacitor (see arrow AR _W), the other a slightly larger distortion along the width direction W caused by multilayer ceramic capacitors (see arrow AR _W) but, although acts to amplify the oscillations with respect to each other in the region R, the vibration in the Y-axis direction is relatively small It is suppressed.

  In the second layout pattern LP2 shown in FIG. 7B, two multilayer ceramic capacitors are both mounted in the above-described second mounting mode 10 (V). In this case, one of the pair of thickness direction side surfaces 16 of one multilayer ceramic capacitor faces one of the pair of thickness direction side surfaces 16 of the other multilayer ceramic capacitor through the sealing resin layer 5.

The and when the second layout pattern LP2, in the X-axis direction shown in the figure, the distortion (see arrow AR _L) slightly greater along the length direction L that occurs in one of the multilayer ceramic capacitor, the other lamination slightly larger strain along the length L caused by ceramic capacitors (see arrow AR _L) but acts to amplify the oscillations with respect to each other in the region R, the vibration in the X-axis direction increases approximately equivalent. Also, the when the second layout pattern LP2 is the Y-axis direction shown in the figure, a significantly greater strain along the thickness direction T caused by one of the multilayer ceramic capacitor (see the arrow AR _T), the other a significantly greater strain along the thickness direction T caused by multilayer ceramic capacitors (see arrow AR _T) but acts to amplify the oscillations with respect to each other in the region R, the vibration in the Y-axis direction is extremely large .

  In the third layout pattern LP3 shown in FIG. 7C, one of the two multilayer ceramic capacitors is mounted in the second mounting mode 10 (V) described above, and the two multilayer ceramic capacitors The other of them is mounted in the first mounting mode 10 (H) described above. In this case, one of the pair of thickness direction side surfaces 16 of one multilayer ceramic capacitor faces one of the pair of width direction side surfaces 17 of the other multilayer ceramic capacitor through the sealing resin layer 5.

The when the third layout pattern LP3 is the X-axis direction shown in the figure, the distortion (see arrow AR _L) slightly greater along the length direction L that occurs in one of the multilayer ceramic capacitor, the other lamination slightly larger strain along the length L caused by ceramic capacitors (see arrow AR _L) but acts to amplify the oscillations with respect to each other in the region R, the vibration in the X-axis direction increases approximately equivalent. Also, the when the third layout pattern LP3 is the Y-axis direction shown in the figure, a significantly greater strain along the thickness direction T caused by one of the multilayer ceramic capacitor (see the arrow AR _T), the other stacking (see arrow AR _W) slightly larger distortion along the width direction W caused by ceramic capacitors and although the act to cancel the vibration from one another in the region R, the vibration in the Y-axis direction is small as equivalent It is suppressed.

  As is clear from the above, among the first to third layout patterns LP1 to LP3 belonging to the first layout group, the third layout pattern LP3 in which the vibration is partially canceled in the region R suppresses the vibration. It can be said that it is suitable from the viewpoint of doing.

  As shown in FIGS. 8A to 8C, the fourth to sixth layout patterns LP4 to LP6 belonging to the second layout group are all along the length direction L of the two multilayer ceramic capacitors. These two multilayer ceramic capacitors are arranged such that the axis is located on the same straight line on the main surface of the wiring board 2.

  In the fourth layout pattern LP4 shown in FIG. 8A, two multilayer ceramic capacitors are both mounted in the first mounting mode 10 (H) described above. In this case, one of the pair of end faces 15 of one multilayer ceramic capacitor faces one of the pair of end faces 15 of the other multilayer ceramic capacitor through the sealing resin layer 5.

The when the fourth layout pattern LP4, in X-axis direction shown in the figure, the distortion (see arrow AR _L) slightly greater along the length direction L that occurs in one of the multilayer ceramic capacitor, the other lamination slightly larger strain along the length L caused by ceramic capacitors (see arrow AR _L) but acts to amplify the oscillations with respect to each other in the region R, the vibration in the X-axis direction increases approximately equivalent. Further, the and when the fourth layout pattern LP4, in the Y-axis direction shown in the figure, a slightly larger distortion along the width direction W occurring at one of the laminated ceramic capacitor (see arrow AR _W), the other a slightly larger distortion along the width direction W caused by multilayer ceramic capacitors (see arrow AR _W) but, although acts to amplify the oscillations with respect to each other in the region R, the vibration in the Y-axis direction is relatively small It is suppressed.

  In the fifth layout pattern LP5 shown in FIG. 8B, two multilayer ceramic capacitors are both mounted in the second mounting mode 10 (V) described above. In this case, one of the pair of end faces 15 of one multilayer ceramic capacitor faces one of the pair of end faces 15 of the other multilayer ceramic capacitor through the sealing resin layer 5.

The when the fifth layout pattern LP5, in X-axis direction shown in the figure, the distortion (see arrow AR _L) slightly greater along the length direction L that occurs in one of the multilayer ceramic capacitor, the other lamination slightly larger strain along the length L caused by ceramic capacitors (see arrow AR _L) but acts to amplify the oscillations with respect to each other in the region R, the vibration in the X-axis direction increases approximately equivalent. Also, the when the fifth layout pattern LP5, in Y-axis direction shown in the figure, a significantly greater strain along the thickness direction T caused by one of the multilayer ceramic capacitor (see the arrow AR _T), the other a significantly greater strain along the thickness direction T caused by multilayer ceramic capacitors (see arrow AR _T) but acts to amplify the oscillations with respect to each other in the region R, the vibration in the Y-axis direction is extremely large .

  In the sixth layout pattern LP6 shown in FIG. 8C, one of the two multilayer ceramic capacitors is mounted in the second mounting mode 10 (V) described above, and The other of them is mounted in the first mounting mode 10 (H) described above. In this case, one of the pair of end faces 15 of one multilayer ceramic capacitor faces one of the pair of end faces 15 of the other multilayer ceramic capacitor through the sealing resin layer 5.

The when the sixth layout pattern LP6, in X-axis direction shown in the figure, the distortion (see arrow AR _L) slightly greater along the length direction L that occurs in one of the multilayer ceramic capacitor, the other lamination slightly larger strain along the length L caused by ceramic capacitors (see arrow AR _L) but acts to amplify the oscillations with respect to each other in the region R, the vibration in the X-axis direction increases approximately equivalent. Also, the when the sixth layout pattern LP6, in Y-axis direction shown in the figure, a significantly greater strain along the thickness direction T caused by one of the multilayer ceramic capacitor (see the arrow AR _T), the other stacking (see arrow AR _W) slightly larger distortion along the width direction W caused by ceramic capacitors and although the act to cancel the vibration from one another in the region R, the vibration in the Y-axis direction is small as equivalent It is suppressed.

  As is clear from the above, among the fourth to sixth layout patterns LP4 to LP6 belonging to the second layout group, the sixth layout pattern LP6 in which the vibration is partially canceled in the region R suppresses the vibration. It can be said that it is suitable from the viewpoint of doing.

  As shown in FIGS. 9A to 9D, the seventh to tenth layout patterns LP7 to LP10 belonging to the third layout group are all along the length direction L of the two multilayer ceramic capacitors. These two multilayer ceramic capacitors are arranged so that the axes are orthogonal to each other on the main surface of the wiring board 2.

  In the seventh layout pattern LP7 shown in FIG. 9A, two multilayer ceramic capacitors are both mounted in the first mounting mode 10 (H) described above. In this case, one of the pair of end faces 15 of one multilayer ceramic capacitor faces one of the pair of width direction side surfaces 17 of the other multilayer ceramic capacitor via the sealing resin layer 5.

The when the seventh layout pattern LP7, in X-axis direction shown in the figure, and one slightly larger distortion along the width direction W caused by the multilayer ceramic capacitor (see arrow AR _W), the other lamination slightly larger strain along the length L caused by ceramic capacitors (see arrow AR _L) but, although acts to amplify the oscillations with respect to each other in the region R, the vibration in the X-axis direction is relatively small inhibition The Also, the when the seventh layout pattern LP7, in Y-axis direction shown in the figure, the distortion (see arrow AR _L) slightly greater along the length direction L that occurs in one of the multilayer ceramic capacitor, the other a slightly larger distortion along the width direction W caused by multilayer ceramic capacitors (see arrow AR _W) but, although acts to amplify the oscillations with respect to each other in the region R, the vibration in the X-axis direction is relatively small It is suppressed.

  In the eighth layout pattern LP8 shown in FIG. 9B, each of the two multilayer ceramic capacitors is mounted in the second mounting mode 10 (V) described above. In this case, one of the pair of end faces 15 of one multilayer ceramic capacitor faces one of the pair of thickness direction side surfaces 16 of the other multilayer ceramic capacitor through the sealing resin layer 5.

The when the eighth layout pattern LP8, in X-axis direction shown in the figure, a significantly greater strain along the thickness direction T caused by one of the multilayer ceramic capacitor (see the arrow AR _T), the other lamination slightly larger strain along the length L caused by ceramic capacitors (see arrow AR _L) but acts to cancel the vibration from one another in the region R, the vibration in the X-axis direction is significantly small suppressed . Further, the and when the eighth layout pattern LP8, in the Y-axis direction shown in the figure, the distortion (see arrow AR _L) slightly greater along the length direction L that occurs in one of the multilayer ceramic capacitor, the other a laminated significantly greater strain along the thickness direction T caused by ceramic capacitors (see arrow AR _T) but acts to cancel the vibration from one another in the region R, the vibration in the Y-axis direction is significantly suppressed small Is done.

  In the ninth layout pattern LP9 shown in FIG. 9C, one of the two multilayer ceramic capacitors is mounted in the second mounting mode 10 (V) described above. The other of them is mounted in the first mounting mode 10 (H) described above. In this case, one of the pair of end faces 15 of one multilayer ceramic capacitor faces one of the pair of width direction side surfaces 17 of the other multilayer ceramic capacitor via the sealing resin layer 5.

The when the ninth layout pattern LP9, in X-axis direction shown in the figure, a significantly greater strain along the thickness direction T caused by one of the multilayer ceramic capacitor (see the arrow AR _T), the other lamination slightly larger strain along the length L caused by ceramic capacitors (see arrow AR _L) but acts to cancel the vibration from one another in the region R, the vibration in the X-axis direction is significantly small suppressed . Also, the when the ninth layout pattern LP9, in Y-axis direction shown in the figure, the distortion (see arrow AR _L) slightly greater along the length direction L that occurs in one of the multilayer ceramic capacitor, the other a slightly larger distortion along the width direction W caused by multilayer ceramic capacitors (see arrow AR _W) but, although acts to amplify the oscillations with respect to each other in the region R, the vibration in the Y-axis direction is relatively small It is suppressed.

  In the tenth layout pattern LP10 shown in FIG. 9D, one of the two multilayer ceramic capacitors is mounted in the above-described first mounting mode 10 (H). The other of them is mounted in the second mounting mode 10 (V) described above. In this case, one of the pair of end faces 15 of one multilayer ceramic capacitor faces one of the pair of thickness direction side surfaces 16 of the other multilayer ceramic capacitor through the sealing resin layer 5.

The when the tenth layout pattern LP10 is the X-axis direction shown in the figure, and one slightly larger distortion along the width direction W caused by the multilayer ceramic capacitor (see arrow AR _W), the other lamination slightly larger strain along the length L caused by ceramic capacitors (see arrow AR _L) but, although acts to amplify the oscillations with respect to each other in the region R, the vibration in the X-axis direction is relatively small inhibition The Further, the and when the tenth layout pattern LP10, in the Y-axis direction shown in the figure, the distortion (see arrow AR _L) slightly greater along the length direction L that occurs in one of the multilayer ceramic capacitor, the other a laminated significantly greater strain along the thickness direction T caused by ceramic capacitors (see arrow AR _T) but acts to cancel the vibration from one another in the region R, the vibration in the Y-axis direction is significantly suppressed small Is done.

  As is clear from the above, among the seventh to tenth layout patterns LP7 to LP10 belonging to the third layout group, the eighth to tenth layout patterns LP8 to LP10 in which the vibration is canceled at least partially in the region R are. From the viewpoint of suppressing vibration, it can be said that it is preferable. In particular, in the eighth layout pattern LP8, the vibration is greatly canceled in both the X-axis direction and the Y-axis direction in the region R. Therefore, it can be said that this is particularly preferable from the viewpoint of suppressing the vibration.

  On the other hand, for the seventh layout pattern LP7 belonging to the third layout group, although the vibration is not canceled in the region R, the degree of vibration to be amplified is relatively small, and the seventh layout pattern LP7 is also vibrated. It can be said that it is suitable from the viewpoint of suppressing the above.

  In any layout pattern belonging to the third layout group, the length directions L of the two multilayer ceramic capacitors in the direction along the main surface of the wiring board are different from each other. A slightly larger strain along the line is not related to amplifying the vibration. Further, in any layout pattern belonging to the third layout group, the thickness direction T of the two multilayer ceramic capacitors is directed in different directions, and thus a significantly large strain along the thickness direction T vibrates. There is no relationship to amplify. Therefore, from the viewpoint of suppressing vibration, it can be said that the layout pattern belonging to the third layout group is more suitable than the layout pattern belonging to the first and second layout groups.

  Therefore, based on the above consideration, when two monolithic ceramic capacitors are arranged close to each other, one of the pair of end faces 15 of one monolithic ceramic capacitor is connected to a pair of side surfaces (a pair of thicknesses of the other monolithic ceramic capacitor) It can be said that it is preferable to dispose these two monolithic ceramic capacitors so as to face one of the direction side surface 16 and the pair of width direction side surfaces 17 via the sealing resin layer 5.

  Here, when two multilayer ceramic capacitors are arranged close to each other, as described above, it is particularly preferable to employ the eighth layout pattern LP8 from the viewpoint of suppressing vibration. In consideration of this point, when three or more multilayer ceramic capacitors are arranged close to each other, two of these multilayer ceramic capacitors are mounted in the second mounting mode 10 (V) according to the layout pattern LP8. Further, it is preferable to mount the remaining one or more multilayer ceramic capacitors in the first mounting mode 10 (H) so as to be close to these two multilayer ceramic capacitors.

  With this configuration, vibrations that cannot be canceled out in the two multilayer ceramic capacitors mounted according to the eighth layout pattern LP8 are further reduced in the X-axis direction in the region R by one or more remaining multilayer ceramic capacitors. Since it is possible to cancel both in the Y-axis direction, a high vibration suppressing effect can be obtained.

  Based on the above knowledge, in the following, in a circuit module including a plurality of multilayer ceramic capacitors, attention is paid to a multilayer ceramic capacitor group including a plurality of specific multilayer ceramic capacitors included in the plurality of multilayer ceramic capacitors. The circuit modules according to the first to twelfth configuration examples in which the occurrence of vibration is suppressed by applying a characteristic layout to the mounting positions of a plurality of multilayer ceramic capacitors included in the ceramic capacitor group will be described in detail.

(First configuration example)
10 and 11 are a schematic perspective view and a schematic plan view showing the layout of the multilayer ceramic capacitor provided in the circuit module according to the first configuration example based on the present embodiment. 12 is a schematic cross-sectional view of the circuit module shown in FIGS. 10 and 11 along the line XII-XII shown in FIG. 11, and FIG. 13 includes the multilayer ceramic capacitor shown in FIGS. It is a figure which shows the circuit structural example of a circuit. In FIG. 11, the sealing resin layer 5 is not shown.

  In the first configuration example, as a plurality of multilayer ceramic capacitors included in the above-described multilayer ceramic capacitor group, the same design specifications (same design) that are electrically connected in series or in parallel via a conductive pattern provided on a wiring board This is focused on two monolithic ceramic capacitors with the same capacity). The layout pattern of the two multilayer ceramic capacitors in the circuit module according to the first configuration example matches the seventh layout pattern LP7 belonging to the third layout group described above.

  As shown in FIGS. 10 to 13, in the circuit module 1 </ b> A according to the first configuration example, the first multilayer ceramic capacitor 10 </ b> A and the second multilayer ceramic capacitor 10 </ b> B are conductive patterns provided on the wiring board 2. They are electrically connected to each other in series or in parallel via a certain land 3 and wirings 6A to 6C, and are electrically connected to the same power source 7 and electrically connected to the ground terminal GND. That is, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are connected in series or in parallel to the same power supply line.

  The circuit configuration shown in FIG. 13A shows a case where the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are electrically connected in series. In this case, one of the pair of external electrodes 14 of the first multilayer ceramic capacitor 10A and one of the pair of external electrodes 14 of the second multilayer ceramic capacitor 10B are electrically connected via the land 3 and the wiring 6C. The other of the pair of external electrodes 14 of the first multilayer ceramic capacitor 10A and the power source 7 are electrically connected via the land 3 and the wiring 6A, and the pair of second multilayer ceramic capacitor 10B. The other of the external electrodes 14 and the ground terminal GND are electrically connected via the land 3 and the wiring 6B.

  The circuit configuration shown in FIG. 13B shows a case where the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are electrically connected in parallel. In this case, one of the pair of external electrodes 14 of the first multilayer ceramic capacitor 10A, one of the pair of external electrodes 14 of the second multilayer ceramic capacitor 10B, and the power source 7 are connected to the land 3 and the wiring. 6A, the other of the pair of external electrodes 14 of the first multilayer ceramic capacitor 10A, the other of the pair of external electrodes 14 of the second multilayer ceramic capacitor 10B, and the ground terminal GND Are electrically connected through the land 3 and the wiring 6B. That is, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are connected in parallel to the same power supply line. In other words, when viewed in an equivalent circuit, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are connected to the same node.

  As shown in FIGS. 10 to 12, both the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are mounted in the first mounting mode 10 (H) described above. That is, the rectangular thickness direction side surface 16 having the long side and the short side of each of the first multilayer ceramic capacitor 10 </ b> A and the second multilayer ceramic capacitor 10 </ b> B is opposed to the opposing surface 16 a positioned facing the main surface of the wiring board 2. It has become.

  The opposing surface 16a of each of the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B is such that the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B both have a rectangular parallelepiped shape, and further their length direction L Are mounted on the wiring board 2 so as to be parallel to the main surface of the wiring board 2, both have a rectangular shape having a pair of short sides and a pair of long sides.

  Here, in the circuit module 1A according to the first configuration example, the long side of the facing surface 16a of the first multilayer ceramic capacitor 10A extends and the long side of the facing surface 16a of the second multilayer ceramic capacitor 10B. Is perpendicular to the extending direction, and one of the pair of end faces 15 of the first multilayer ceramic capacitor 10A is placed on one of the pair of width direction side faces 17 of the second multilayer ceramic capacitor 10B. The first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are mounted on the wiring board 2 so as to face each other.

  Preferably, when viewed from the main surface of the wiring substrate 2, an axis parallel to the length direction L passing through the center of the first multilayer ceramic capacitor 10A passes through the second multilayer ceramic capacitor 10B. Further, preferably, when viewed from the main surface of the wiring board 2, an axis parallel to the width direction W passing through the center of the second multilayer ceramic capacitor 10B passes through the first multilayer ceramic capacitor 10A. More preferably, the axis parallel to the length direction L passing through the center of the first multilayer ceramic capacitor 10A and the axis parallel to the width direction W passing through the center of the second multilayer ceramic capacitor 10B are matched. Configure.

  Here, a direction parallel to the main surface of the wiring board 2 and perpendicular to the length direction L of the first multilayer ceramic capacitor 10A is defined as an X-axis direction, and is parallel to the main surface of the wiring board 2 and the first multilayer ceramic. A direction parallel to the length direction L of the capacitor 10A is defined as a Y-axis direction. At this time, the width direction W of the first multilayer ceramic capacitor 10A and the length direction L of the second multilayer ceramic capacitor 10B face the same X-axis direction, and the length direction L of the first multilayer ceramic capacitor 10A and the second direction The width direction W of the multilayer ceramic capacitor 10B faces the same Y-axis direction.

In this case, the vibration mode due to the distortion along the width direction W of the first multilayer ceramic capacitor 10A (see arrows VMA _W shown in FIG. 11), along the length L of the second multilayer ceramic capacitor 10B vibration mode (see arrow VMB _L shown in FIG. 11), but due to the distortion, it becomes to meet along the X-axis direction of the circuit module 1A to face the same direction each other, the first laminated ceramic vibration mode due to the distortion along the length direction L of the capacitor 10A (see arrows VMA _L shown in FIG. 11), the vibration mode (FIG due to distortion along the width direction W of the second multilayer ceramic capacitor 10B 11 (see arrow VMB _W shown in FIG. 11) coincides with each other along the Y-axis direction of the circuit module 1A in the same direction.

  Therefore, as mentioned in the description of the seventh layout pattern LP7 belonging to the third layout group described above, it is caused by distortion generated in the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B when a voltage is applied. Thus, it is possible to prevent the vibration of the circuit module 1A generated from being excessively amplified. Thereby, generation | occurrence | production of noise can be suppressed and the malfunctioning of another element can be prevented.

(Second configuration example)
FIG. 14 is a schematic plan view showing the layout of the multilayer ceramic capacitor provided in the circuit module according to the second configuration example based on the present embodiment, and FIG. 15 is a diagram of FIG. 14 of the circuit module shown in FIG. It is a schematic cross section along the XV-XV line shown in FIG. In FIG. 14, the sealing resin layer 5 is not shown.

  This second configuration example matches the eighth layout pattern LP8 belonging to the third layout group described above. Specifically, as shown in FIGS. 14 and 15, in the circuit module 1 </ b> B according to the second configuration example, the first multilayer ceramic capacitor 10 </ b> A and the second multilayer ceramic capacitor 10 </ b> B are both described above. The second mounting example 10 (V) is different from the first configuration example in that it is mounted, and the other configuration is the same as the first configuration example.

  That is, the rectangular width direction side surface 17 including the long side and the short side of the first multilayer ceramic capacitor 10 </ b> A and the second multilayer ceramic capacitor 10 </ b> B is a facing surface 17 a that is positioned facing the main surface of the wiring board 2. Yes. As a result, one of the pair of end faces 15 of the first multilayer ceramic capacitor 10 </ b> A faces one of the pair of thickness direction side faces 16 of the second multilayer ceramic capacitor 10 </ b> B via the sealing resin layer 5.

  Here, a direction parallel to the main surface of the wiring board 2 and perpendicular to the length direction L of the first multilayer ceramic capacitor 10A is defined as an X-axis direction, and is parallel to the main surface of the wiring board 2 and the first multilayer ceramic. A direction parallel to the length direction L of the capacitor 10A is defined as a Y-axis direction. At this time, the thickness direction T of the first multilayer ceramic capacitor 10A and the length direction L of the second multilayer ceramic capacitor 10B face the same X-axis direction, and the length direction L of the first multilayer ceramic capacitor 10A and the second direction L The thickness direction T of the multilayer ceramic capacitor 10B faces the same Y-axis direction.

In this case, the vibration mode due to the distortion along the thickness direction T of the first laminated ceramic capacitor 10A (see arrows VMA _T shown in FIG. 14), along the length L of the second multilayer ceramic capacitor 10B vibration mode (see arrow VMB _L shown in FIG. 14), but due to the distortion, it becomes to conform to face the same direction each other along the X-axis direction of the circuit module 1B, the first laminated ceramic vibration mode due to the distortion along the length direction L of the capacitor 10A and (see arrows VMA _L shown in FIG. 14), the vibration mode (FIG due to strain along the thickness direction T of the second multilayer ceramic capacitor 10B and see the arrow VMB _T) shown in 14, but will be matched to face the same direction each other along the Y-axis direction of the circuit module 1B.

  Therefore, as mentioned in the description of the eighth layout pattern LP8 belonging to the third layout group described above, it is caused by distortion generated in the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B when a voltage is applied. Thus, the vibration of the circuit module 1A generated is canceled in both the X-axis direction and the Y-axis direction. Thereby, generation | occurrence | production of noise can be suppressed and the malfunctioning of another element can be prevented.

  Further, when configured as described above, one end face 15 of the first multilayer ceramic capacitor 10A and one thickness direction side face 16 of the second multilayer ceramic capacitor 10B are arranged to face each other in the Y-axis direction. Therefore, the propagation directions of the vibration modes generated along the Y-axis direction face each other, and the vibration canceling action can be obtained more efficiently.

(Third configuration example)
FIG. 16 is a schematic plan view showing the layout of the multilayer ceramic capacitor provided in the circuit module according to the third configuration example based on the present embodiment, and FIG. 17 is a diagram of the circuit module shown in FIG. It is a schematic cross section along the XVII-XVII line shown in FIG. In FIG. 16, the sealing resin layer 5 is not shown.

  The third configuration example matches the ninth layout pattern LP9 belonging to the third layout group described above. Specifically, as shown in FIGS. 16 and 17, in the circuit module 1C according to the third configuration example, the first multilayer ceramic capacitor 10A is mounted in the second mounting mode 10 (V) described above. The second multilayer ceramic capacitor 10B is different from the first configuration example in that the second multilayer ceramic capacitor 10B is mounted in the first mounting mode 10 (H) described above, and is otherwise the same as the first configuration example. It is configured.

  That is, the rectangular width direction side surface 17 including the long side and the short side of the first multilayer ceramic capacitor 10 </ b> A serves as a facing surface 17 a that faces the main surface of the wiring board 2, and the second multilayer ceramic capacitor A rectangular thickness direction side surface 16 including the long side and the short side of 10 </ b> B serves as a facing surface 16 a positioned facing the main surface of the wiring board 2. Thus, one of the pair of end faces 15 of the first multilayer ceramic capacitor 10A is opposed to one of the pair of width direction side faces 17 of the second multilayer ceramic capacitor 10B via the sealing resin layer 5.

  Here, a direction parallel to the main surface of the wiring board 2 and perpendicular to the length direction L of the first multilayer ceramic capacitor 10A is defined as an X-axis direction, and is parallel to the main surface of the wiring board 2 and the first multilayer ceramic. A direction parallel to the length direction L of the capacitor 10A is defined as a Y-axis direction. At this time, the thickness direction T of the first multilayer ceramic capacitor 10A and the length direction L of the second multilayer ceramic capacitor 10B face the same X-axis direction, and the length direction L of the first multilayer ceramic capacitor 10A and the second direction L The width direction W of the multilayer ceramic capacitor 10B faces the same Y-axis direction.

In this case, the vibration mode due to the distortion along the thickness direction T of the first laminated ceramic capacitor 10A (see arrows VMA _T shown in FIG. 16), along the length L of the second multilayer ceramic capacitor 10B vibration mode (see arrow VMB _L shown in FIG. 16), but due to the distortion, it becomes to meet along the X-axis direction of the circuit module 1C so as to face the same directions, the first laminated ceramic vibration mode due to the distortion along the length direction L of the capacitor 10A (see arrows VMA _L shown in FIG. 16), the vibration mode (FIG due to distortion along the width direction W of the second multilayer ceramic capacitor 10B 16 (see arrow VMB _W shown in FIG. 16) coincide with each other along the Y-axis direction of the circuit module 1C in the same direction.

  Therefore, as mentioned in the description of the ninth layout pattern LP9 belonging to the third layout group described above, it is caused by distortion generated in the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B when a voltage is applied. Thus, the vibration of the circuit module 1A generated is canceled in the X-axis direction. Thereby, generation | occurrence | production of noise can be suppressed and the malfunctioning of another element can be prevented.

(Fourth configuration example)
18 is a schematic plan view showing a layout of the multilayer ceramic capacitor provided in the circuit module according to the fourth configuration example based on the present embodiment, and FIG. 19 is a diagram of FIG. 18 of the circuit module shown in FIG. It is a schematic cross section along the XIX-XIX line shown in FIG. In FIG. 18, the sealing resin layer 5 is not shown.

  The fourth configuration example matches the tenth layout pattern LP10 belonging to the third layout group described above. Specifically, as shown in FIGS. 18 and 19, in the circuit module 1D according to the fourth configuration example, the first multilayer ceramic capacitor 10A is mounted in the above-described first mounting mode 10 (H). The second multilayer ceramic capacitor 10B is different from the first configuration example in that the second multilayer ceramic capacitor 10B is mounted in the above-described second mounting mode 10 (V), and is otherwise the same as the first configuration example. It is configured.

  That is, the rectangular thickness direction side surface 16 including the long side and the short side of the first multilayer ceramic capacitor 10 </ b> A serves as a facing surface 16 a located facing the main surface of the wiring board 2, and the second multilayer ceramic capacitor A rectangular width direction side surface 17 including a long side and a short side of 10B is a facing surface 17a located facing the main surface of the wiring board 2. As a result, one of the pair of end faces 15 of the first multilayer ceramic capacitor 10 </ b> A faces one of the pair of thickness direction side faces 16 of the second multilayer ceramic capacitor 10 </ b> B via the sealing resin layer 5.

  Here, a direction parallel to the main surface of the wiring board 2 and perpendicular to the length direction L of the first multilayer ceramic capacitor 10A is defined as an X-axis direction, and is parallel to the main surface of the wiring board 2 and the first multilayer ceramic. A direction parallel to the length direction L of the capacitor 10A is defined as a Y-axis direction. At this time, the width direction W of the first multilayer ceramic capacitor 10A and the length direction L of the second multilayer ceramic capacitor 10B face the same X-axis direction, and the length direction L of the first multilayer ceramic capacitor 10A and the second direction The thickness direction T of the multilayer ceramic capacitor 10B faces the same Y-axis direction.

In this case, the vibration mode due to the distortion along the width direction W of the first multilayer ceramic capacitor 10A (see arrows VMA _W shown in FIG. 18), along the length L of the second multilayer ceramic capacitor 10B vibration mode (see arrow VMB _L shown in FIG. 18), but due to the distortion, it becomes to conform to face the same direction each other along the X-axis direction of the circuit module 1D, the first laminated ceramic vibration mode due to the distortion along the length direction L of the capacitor 10A and (see arrows VMA _L shown in FIG. 18), the vibration mode (FIG due to strain along the thickness direction T of the second multilayer ceramic capacitor 10B and see the arrow VMB _T) shown in 18, but will be matched to face the same direction each other along the Y-axis direction of the circuit module 1D.

  Therefore, as mentioned in the description of the tenth layout pattern LP10 belonging to the third layout group described above, it is caused by the distortion generated in the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B when a voltage is applied. Thus, the vibration of the circuit module 1A generated is canceled in the Y-axis direction. Thereby, generation | occurrence | production of noise can be suppressed and the malfunctioning of another element can be prevented.

  Further, when configured as described above, one end face 15 of the first multilayer ceramic capacitor 10A and one thickness direction side face 16 of the second multilayer ceramic capacitor 10B are arranged to face each other in the Y-axis direction. Therefore, the propagation directions of the vibration modes generated along the Y-axis direction face each other, and the vibration canceling action can be obtained more efficiently.

(Fifth configuration example)
FIG. 20 is a schematic plan view showing a layout of the multilayer ceramic capacitor provided in the circuit module according to the fifth configuration example based on the present embodiment. In FIG. 20, the illustration of the sealing resin layer 5 is omitted.

  In the fifth configuration example, as the plurality of multilayer ceramic capacitors included in the above-described multilayer ceramic capacitor group, the same design specifications (same design) that are electrically connected in series or in parallel via the conductive pattern provided on the wiring board In this example, three monolithic ceramic capacitors having the same capacity and the same size are focused. Note that the three multilayer ceramic capacitors in the circuit module according to the fifth configuration example are electrically connected to each other in series or in parallel as in the case of the first configuration example.

  As shown in FIG. 20, in the circuit module 1E according to the fifth configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C are each in the first mounting mode 10 described above. (H) and the second mounting mode 10 (V). Specifically, each of the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C has a length direction L parallel to the main surface of the wiring board 2 and a width direction thereof. It is mounted on the wiring board 2 so that either W or the thickness direction T is parallel to the normal direction of the main surface of the wiring board 2 (in the Z-axis direction shown in the figure). Further, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are disposed so as to be adjacent to each other, and the first multilayer ceramic capacitor 10A and the third multilayer ceramic capacitor 10C are adjacent to each other. It is arranged to be located.

  When configured in this manner, one of the pair of end faces 15 of the first multilayer ceramic capacitor 10A is a pair of side surfaces of the second multilayer ceramic capacitor 10B (a pair of thickness direction side faces 16 and a pair of width directions). Of the first multilayer ceramic capacitor 10 </ b> A and the other of the pair of end surfaces 15 of the first multilayer ceramic capacitor 10 </ b> C is the third multilayer ceramic capacitor 10 </ b> C. One of the pair of side surfaces (including the pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17) is opposed to the sealing resin layer 5 therebetween.

  Therefore, in the fifth configuration example, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B that are located adjacent to each other serve as the seventh to tenth layout patterns LP7 to LP10 in the third layout group described above. The first multilayer ceramic capacitor 10A and the third multilayer ceramic capacitor 10C that are adjacent to each other have the positional relationship as described above, and the seventh to tenth layout patterns LP7 to LP10 in the third layout group described above. The positional relationship is as follows.

  Therefore, by adopting this configuration, the vibration of the circuit module 1E generated due to the distortion generated in the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C during voltage application is a region. As a result, the generation of noise can be suppressed, and malfunction of other elements can be prevented.

  Here, the circuit module 1E is manufactured by aligning the stacking directions of the dielectric layer 12 and the internal electrode layer 13 in each of the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C in the same direction. From the viewpoint of suppressing the vibration generated in the circuit module 1E while facilitating the process, for example, referring to FIG. 20, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C are respectively It is preferable to mount in the second mounting mode 10 (V) described above.

  On the other hand, from the viewpoint of maximally suppressing the vibration generated in the circuit module 1E, referring to FIG. 20, for example, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are respectively described in the second mounting mode 10 ( It is preferable that the third multilayer ceramic capacitor 10C is mounted in the first mounting mode 10 (H) described above.

(Sixth configuration example)
FIG. 21 is a schematic plan view showing a layout of the multilayer ceramic capacitor provided in the circuit module according to the sixth configuration example based on the present embodiment. In FIG. 21, the illustration of the sealing resin layer 5 is omitted.

  In the sixth configuration example, as a plurality of multilayer ceramic capacitors included in the above-described multilayer ceramic capacitor group, the same design specifications (same design) that are electrically connected in series or in parallel via a conductive pattern provided on the wiring board In this example, three monolithic ceramic capacitors having the same capacity and the same size are focused. Note that the three multilayer ceramic capacitors in the circuit module according to the sixth configuration example are electrically connected to each other in series or in parallel as in the case of the first configuration example.

  As shown in FIG. 21, in the circuit module 1F according to the sixth configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C are each provided in the first mounting mode 10 described above. (H) and the second mounting mode 10 (V). Specifically, each of the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C has a length direction L parallel to the main surface of the wiring board 2 and a width direction thereof. It is mounted on the wiring board 2 so that either W or the thickness direction T is parallel to the normal direction of the main surface of the wiring board 2 (in the Z-axis direction shown in the figure). Further, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are disposed so as to be adjacent to each other, and the second multilayer ceramic capacitor 10B and the third multilayer ceramic capacitor 10C are adjacent to each other. It is arranged to be located.

  When configured in this manner, one of the pair of end faces 15 of the first multilayer ceramic capacitor 10A is a pair of side surfaces of the second multilayer ceramic capacitor 10B (a pair of thickness direction side faces 16 and a pair of width directions). One of the side surfaces 17) via the sealing resin layer 5, and one of the pair of end surfaces 15 of the third multilayer ceramic capacitor 10C is the second multilayer ceramic capacitor 10B. The other of the pair of side surfaces (including the pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17) is opposed to the other side through the sealing resin layer 5.

  Therefore, in the sixth configuration example, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B that are adjacent to each other are connected to the seventh to tenth layout patterns LP7 to LP10 in the third layout group described above. The second multilayer ceramic capacitor 10B and the third multilayer ceramic capacitor 10C that are adjacent to each other have the positional relationship as described above, and the seventh to tenth layout patterns LP7 to LP10 in the third layout group described above. The positional relationship is as follows.

  Therefore, by adopting the configuration, the vibration of the circuit module 1F generated due to the distortion generated in the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C when a voltage is applied is a region. As a result, the generation of noise can be suppressed, and malfunction of other elements can be prevented.

  Here, the circuit module 1F is manufactured by aligning the stacking directions of the dielectric layer 12 and the internal electrode layer 13 in each of the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C in the same direction. From the viewpoint of suppressing the vibration generated in the circuit module 1F while facilitating the process, for example, referring to FIG. 21, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C are respectively It is preferable to mount in the second mounting mode 10 (V) described above.

  On the other hand, from the viewpoint of suppressing the vibration generated in the circuit module 1F to the maximum extent, referring to FIG. 21, for example, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are respectively described in the second mounting mode 10 ( It is preferable that the third multilayer ceramic capacitor 10C is mounted in the first mounting mode 10 (H) described above.

(Seventh configuration example)
FIG. 22 is a schematic plan view showing a layout of the multilayer ceramic capacitor provided in the circuit module according to the seventh configuration example based on the present embodiment. In FIG. 22, the sealing resin layer 5 is not shown.

  In the seventh configuration example, as the plurality of multilayer ceramic capacitors included in the above-described multilayer ceramic capacitor group, the same design specifications (same design) that are electrically connected in series or in parallel via a conductive pattern provided on the wiring board In this example, three monolithic ceramic capacitors having the same capacity and the same size are focused. Note that the three multilayer ceramic capacitors in the circuit module according to the seventh configuration example are electrically connected to each other in series or in parallel as in the case of the first configuration example.

  As shown in FIG. 22, in the circuit module 1G according to the seventh configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C are each in the first mounting mode 10 described above. (H) and the second mounting mode 10 (V). Specifically, each of the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C has a length direction L parallel to the main surface of the wiring board 2 and a width direction thereof. It is mounted on the wiring board 2 so that either W or the thickness direction T is parallel to the normal direction of the main surface of the wiring board 2 (in the Z-axis direction shown in the figure). Further, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C are arranged so as to be adjacent to each other.

  When configured in this manner, one of the pair of end faces 15 of the first multilayer ceramic capacitor 10A is a pair of side surfaces of the second multilayer ceramic capacitor 10B (a pair of thickness direction side faces 16 and a pair of width directions). One of the side surfaces 17) via the sealing resin layer 5, and one of the pair of end surfaces 15 of the third multilayer ceramic capacitor 10C is the second multilayer ceramic capacitor 10B. One of the pair of side surfaces (including the pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17) is opposed to the one through the sealing resin layer 5.

  Therefore, in the seventh configuration example, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B that are adjacent to each other are connected to the seventh to tenth layout patterns LP7 to LP10 in the third layout group described above. The third multilayer ceramic capacitor 10C and the second multilayer ceramic capacitor 10B that are adjacent to each other have the positional relationship as described above, and the seventh to tenth layout patterns LP7 to LP10 in the third layout group described above. The positional relationship is as follows.

  Therefore, by adopting the configuration, the vibration of the circuit module 1G caused by the distortion generated in the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C during voltage application is a region. As a result, the generation of noise can be suppressed, and malfunction of other elements can be prevented.

  Here, the circuit module 1G is manufactured by aligning the lamination directions of the dielectric layer 12 and the internal electrode layer 13 in each of the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C. For example, referring to FIG. 22, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C are respectively configured from the viewpoint of suppressing vibration generated in the circuit module 1G. It is preferable to mount in the second mounting mode 10 (V) described above.

  On the other hand, from the viewpoint of maximally suppressing the vibration generated in the circuit module 1G, referring to FIG. 22, for example, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are respectively described in the second mounting mode 10 ( It is preferable that the third multilayer ceramic capacitor 10C is mounted in the first mounting mode 10 (H) described above.

(Eighth configuration example)
FIG. 23 is a schematic plan view showing a layout of the multilayer ceramic capacitor provided in the circuit module according to the eighth configuration example based on the present embodiment. In FIG. 23, illustration of the sealing resin layer 5 is omitted.

  In the eighth configuration example, as a plurality of multilayer ceramic capacitors included in the above-described multilayer ceramic capacitor group, the same design specifications (same design) that are electrically connected in series or in parallel via a conductive pattern provided on the wiring board In this case, attention is paid to four monolithic ceramic capacitors having the same capacity and the same size. Note that the four multilayer ceramic capacitors in the circuit module according to the eighth configuration example are electrically connected to each other in series or in parallel as in the case of the first configuration example.

  As shown in FIG. 23, in the circuit module 1H according to the eighth configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D are respectively It is mounted in either the first mounting mode 10 (H) or the second mounting mode 10 (V) described above. Specifically, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D have their length directions L parallel to the main surface of the wiring board 2. In addition, each of the width direction W and the thickness direction T is mounted on the wiring board 2 so as to be parallel to the normal direction of the main surface of the wiring board 2 and the Z-axis direction shown in the drawing. Yes. The first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D are arranged adjacent to each other. More specifically, the first multilayer ceramic capacitor 10 </ b> A and the third multilayer ceramic capacitor 10 </ b> C have their axes along the length direction L positioned parallel to each other on the main surface of the wiring board 2. The second multilayer ceramic capacitor 10 </ b> B and the fourth multilayer ceramic capacitor 10 </ b> D are positioned so that their axes along the length direction L are collinear with each other on the main surface of the wiring board 2. It is arranged to be.

  When configured in this manner, one of the pair of end faces 15 of the first multilayer ceramic capacitor 10A is a pair of side surfaces of the second multilayer ceramic capacitor 10B (a pair of thickness direction side faces 16 and a pair of width directions). One of the side surfaces 17) through the sealing resin layer 5, and one of the pair of end surfaces 15 of the third multilayer ceramic capacitor 10C is the fourth multilayer ceramic capacitor 10D. One of the pair of side surfaces (including the pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17) is opposed to the sealing resin layer 5 therebetween.

  Therefore, in the eighth configuration example, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B that are adjacent to each other, and the third multilayer ceramic capacitor 10C and the fourth multilayer ceramic capacitor 10D that are adjacent to each other are provided. These have the positional relationship as the seventh to tenth layout patterns LP7 to LP10 in the third layout group described above.

  Therefore, by adopting this configuration, it is caused by distortion generated in the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D when a voltage is applied. The vibration of the circuit module 1H can be suppressed in the region R. As a result, generation of noise can be suppressed and malfunction of other elements can be prevented.

  Here, the stacking directions of the dielectric layer 12 and the internal electrode layer 13 in each of the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D are aligned in the same direction. From the viewpoint of suppressing the vibration generated in the circuit module 1H while facilitating the manufacture of the circuit module 1H, for example, referring to FIG. 23, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the second It is preferable to mount the 3 multilayer ceramic capacitor 10C and the fourth multilayer ceramic capacitor 10D in the second mounting mode 10 (V) described above.

  On the other hand, from the viewpoint of suppressing the vibration generated in the circuit module 1H to the maximum extent, referring to FIG. 23, for example, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are respectively described in the second mounting mode 10 ( It is preferable that the third multilayer ceramic capacitor 10C and the fourth multilayer ceramic capacitor 10D are respectively mounted in the first mounting mode 10 (H) described above.

(Ninth configuration example)
FIG. 24 is a schematic plan view showing a layout of the multilayer ceramic capacitor provided in the circuit module according to the ninth configuration example based on the present embodiment. In FIG. 24, illustration of the sealing resin layer 5 is omitted.

  In the ninth configuration example, the same design specifications (same as the plurality of multilayer ceramic capacitors included in the above-described multilayer ceramic capacitor group) are electrically connected in series or in parallel via the conductive pattern provided on the wiring board. In this case, attention is paid to four monolithic ceramic capacitors having the same capacity and the same size. Note that the four monolithic ceramic capacitors in the circuit module according to the ninth configuration example are electrically connected to each other in series or in parallel as in the case of the first configuration example.

  As shown in FIG. 24, in the circuit module 1I according to the ninth configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D are respectively It is mounted in either the first mounting mode 10 (H) or the second mounting mode 10 (V) described above. Specifically, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D have their length directions L parallel to the main surface of the wiring board 2. In addition, each of the width direction W and the thickness direction T is mounted on the wiring board 2 so as to be parallel to the normal direction of the main surface of the wiring board 2 and the Z-axis direction shown in the drawing. Yes. The first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D are arranged adjacent to each other. More specifically, the first multilayer ceramic capacitor 10 </ b> A and the third multilayer ceramic capacitor 10 </ b> C have their axes along the length direction L positioned parallel to each other on the main surface of the wiring board 2. The second multilayer ceramic capacitor 10 </ b> B and the fourth multilayer ceramic capacitor 10 </ b> D are positioned so that their axes along the length direction L are parallel to each other on the main surface of the wiring board 2. It is arranged to be.

  When configured in this manner, one of the pair of end faces 15 of the first multilayer ceramic capacitor 10A is a pair of side surfaces of the second multilayer ceramic capacitor 10B (a pair of thickness direction side faces 16 and a pair of width directions). One of the side surfaces 17) through the sealing resin layer 5, and one of the pair of end surfaces 15 of the second multilayer ceramic capacitor 10B is the third multilayer ceramic capacitor 10C. One of the pair of side surfaces (including the pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17) is opposed to the sealing resin layer 5 therebetween. In addition, one of the pair of end faces 15 included in the third multilayer ceramic capacitor 10C is a pair of side surfaces (including the pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17) included in the fourth multilayer ceramic capacitor 10D. One of the pair of end surfaces 15 of the fourth multilayer ceramic capacitor 10D is a pair of side surfaces of the first multilayer ceramic capacitor 10A (a pair of side surfaces). One of the thickness direction side surface 16 and the pair of width direction side surfaces 17).

  Therefore, in the ninth configuration example, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B that are adjacent to each other, the second multilayer ceramic capacitor 10B and the third multilayer ceramic capacitor 10C that are adjacent to each other, are adjacent to each other. The third multilayer ceramic capacitor 10C and the fourth multilayer ceramic capacitor 10D that are positioned in the same direction, and the fourth multilayer ceramic capacitor 10D and the first multilayer ceramic capacitor 10A that are positioned adjacent to each other are respectively in the third layout group described above. The positional relationship is as shown in the seventh to tenth layout patterns LP7 to LP10.

  Therefore, by adopting this configuration, it is caused by distortion generated in the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D when a voltage is applied. The vibration of the circuit module 1I can be suppressed in the region R. As a result, generation of noise can be suppressed and malfunction of other elements can be prevented.

  Here, the stacking directions of the dielectric layer 12 and the internal electrode layer 13 in each of the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D are aligned in the same direction. From the viewpoint of suppressing the vibration generated in the circuit module 1I while facilitating the manufacture of the circuit module 1I, for example, referring to FIG. 24, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the first It is preferable to mount the 3 multilayer ceramic capacitor 10C and the fourth multilayer ceramic capacitor 10D in the second mounting mode 10 (V) described above.

  On the other hand, from the viewpoint of suppressing the vibration generated in the circuit module 1I to the maximum, referring to, for example, FIG. 24, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are respectively described in the second mounting mode 10 ( It is preferable that the third multilayer ceramic capacitor 10C and the fourth multilayer ceramic capacitor 10D are respectively mounted in the first mounting mode 10 (H) described above.

(10th configuration example)
FIG. 25 is a schematic plan view showing the layout of the multilayer ceramic capacitor and IC provided in the circuit module according to the tenth configuration example. In FIG. 25, the sealing resin layer 5 is not shown.

  As shown in FIG. 25, the circuit module 1J according to the tenth configuration example is mounted on the wiring board 2, the IC (Integrated Circuit) 20 as an integrated circuit element mounted on the wiring board 2, and the wiring board 2. A capacitor element group composed of two decoupling multilayer ceramic capacitors 10 connected to the IC, and a sealing resin layer (not shown), and the two decoupling multilayer ceramics The layout of the capacitor 10 is one of the layouts of the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B shown in the circuit modules 1A to 1D according to the first to fourth configuration examples described above (that is, the above-described third multilayer ceramic capacitor 10B). Any one of the seventh to tenth layout patterns LP7 to LP10 in the layout group) It is applied. Here, the two multilayer ceramic capacitors 10 for decoupling have different capacities, and both are embedded on the wiring board 2 by the above-described sealing resin layer (not shown).

  More specifically, the IC 20 has a plurality of terminals for performing input / output with an external circuit, and the plurality of terminals include a power supply terminal 21 and a ground terminal 22. The above-described two decoupling monolithic ceramic capacitors 10 are arranged side by side in the vicinity of the IC 20 along a direction parallel to the main surface on the main surface of the wiring board 2 on which the IC 20 is mounted.

  Each of the lands 3 connected to the external electrode of each of the two decoupling multilayer ceramic capacitors 10 via the bonding member 4 is associated with the power supply terminal 21 and the ground terminal 22 of the IC 20 via wiring. It is connected. As a result, the two decoupling multilayer ceramic capacitors 10 are electrically connected in parallel between the power supply terminal 21 and the ground terminal 22.

  Here, the decoupling multilayer ceramic capacitor is connected between the power supply line and the ground in order to suppress fluctuations in the power supply voltage and interference between circuits. The decoupling circuit composed of the multilayer ceramic capacitor for decoupling has a plurality of capacitances different between the power supply line and the ground so that a high noise absorption effect is exhibited in a wide frequency range. In general, the multilayer ceramic capacitors are electrically connected in parallel. Various ICs are assumed as the IC to which the decoupling circuit is attached, and examples include a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and an APU (Accelerated Processing Unit).

  As described above, in the circuit module 1J according to the tenth configuration example, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B illustrated in the circuit modules 1A to 1D according to the first to fourth configuration examples are provided. One of the layouts is applied to the layout of the two decoupling multilayer ceramic capacitors 10. With this configuration, the detailed description will be repeated and will be omitted. However, vibrations generated in the region R where the two decoupling multilayer ceramic capacitors 10 are disposed can be suppressed. As a result, the generation of noise can be reduced.

  Further, as described above, by disposing these two decoupling multilayer ceramic capacitors 10 in the vicinity of the IC 20, not only the circuit module 1J can be prevented from being enlarged, but also formed on the wiring board 2. It is also possible to reduce the loop inductance of the circuit.

  Therefore, by adopting a configuration such as the circuit module 1J according to the tenth configuration example to configure the decoupling circuit, it is possible to suppress the generation of noise while preventing the electronic device from becoming large. Here, in the tenth configuration example, the case where the two decoupling multilayer ceramic capacitors 10 and the IC 20 are arranged so as to be aligned on the same straight line is illustrated, but the two decoupling multilayer ceramic capacitors are illustrated. The capacitor 10 may be arranged so that the direction in which the capacitors 10 are arranged and the direction in which the capacitor element group including the two decoupling multilayer ceramic capacitors 10 and the IC 20 are arranged intersect each other.

(Eleventh configuration example)
FIG. 26 is a schematic plan view showing the layout of the multilayer ceramic capacitor and IC provided in the circuit module according to the eleventh configuration example. In FIG. 26, illustration of the sealing resin layer 5 is omitted.

  As shown in FIG. 26, the circuit module 1K according to the eleventh configuration example includes the wiring board 2, the IC 20 mounted on the wiring board 2, and the 3 connected to the IC by being mounted on the wiring board 2. This includes a capacitor element group composed of two decoupling monolithic ceramic capacitors 10 and a sealing resin layer (not shown). The layout of the three decoupling monolithic ceramic capacitors 10 is the same as that described above. The layout of the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C shown in the circuit module 1E according to the configuration example is applied. Here, the three decoupling multilayer ceramic capacitors 10 are a combination of a large-capacity, medium-capacitance, and small-capacitance capacitors, all of which are encapsulated on the wiring board 2 by the above-described sealing resin layer (not shown). Buried.

  More specifically, as in the case of the tenth configuration example described above, the IC 20 has a plurality of terminals for inputting and outputting with external circuits, and the plurality of terminals include the power supply terminal 21. And a ground terminal 22 are included. The above-described three decoupling monolithic ceramic capacitors 10 are arranged in the vicinity of the IC 20 along a direction parallel to the main surface on the main surface of the wiring board 2 on which the IC 20 is mounted.

  Each of the lands 3 connected to the external electrode of each of the three decoupling multilayer ceramic capacitors 10 via the bonding member 4 is associated with the power supply terminal 21 and the ground terminal 22 of the IC 20 via wiring. It is connected. Accordingly, the three decoupling multilayer ceramic capacitors 10 are electrically connected in parallel between the power supply terminal 21 and the ground terminal 22.

  As described above, in the circuit module 1K according to the eleventh configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor shown in the circuit module 1E according to the fifth configuration example. The layout of 10C is applied to the layout of the multilayer ceramic capacitor 10 for three decoupling. With this configuration, the detailed description will be repeated and will be omitted, but vibrations generated in the region R in which the three decoupling multilayer ceramic capacitors 10 are disposed can be suppressed. As a result, the generation of noise can be reduced.

  Further, as described above, by disposing these three decoupling multilayer ceramic capacitors 10 in the vicinity of the IC 20, not only the circuit module 1K can be prevented from being enlarged, but also formed on the wiring board 2. It is also possible to reduce the loop inductance of the circuit.

  Therefore, by adopting the configuration as in the circuit module 1K according to the eleventh configuration example to configure the decoupling circuit, it is possible to suppress the generation of noise while preventing the electronic device from becoming large. Here, in the eleventh configuration example, the case where the three decoupling multilayer ceramic capacitors 10 and the IC 20 are arranged so as to be aligned on the same straight line is illustrated, but the three decoupling multilayer ceramics are illustrated. The capacitor 10 may be arranged so that the direction in which the capacitors 10 are arranged and the direction in which the capacitor element group including the three decoupling multilayer ceramic capacitors 10 and the IC 20 are arranged intersect each other.

(Twelfth configuration example)
FIG. 27 is a schematic plan view showing the layout of the multilayer ceramic capacitor and IC provided in the circuit module according to the twelfth configuration example. In FIG. 27, the sealing resin layer 5 is not shown.

  As shown in FIG. 27, the circuit module 1L according to the twelfth configuration example includes the wiring board 2, the IC 20 mounted on the wiring board 2, and the 4 connected to the IC by being mounted on the wiring board 2. This includes a capacitor element group composed of two decoupling multilayer ceramic capacitors 10 and a sealing resin layer (not shown). The layout of the four decoupling multilayer ceramic capacitors 10 includes the above-described ninth configuration. The layout of the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D shown in the circuit module 1I according to the configuration example is applied. Here, the four decoupling monolithic ceramic capacitors 10 are composed of a combination of a large-capacity, medium-capacitance, and small-capacitance capacitors, and the large-capacity capacitors are supported by two monolithic ceramic capacitors 10 having the same capacity. In addition, each of the medium-capacitance and small-capacitance capacitors is associated with one monolithic ceramic capacitor 10. The four decoupling monolithic ceramic capacitors 10 are all embedded on the wiring board 2 with the above-described sealing resin layer (not shown).

  More specifically, as in the case of the tenth configuration example described above, the IC 20 has a plurality of terminals for inputting and outputting with external circuits, and the plurality of terminals include the power supply terminal 21. And a ground terminal 22 are included. The above-described four decoupling monolithic ceramic capacitors 10 are arranged in the vicinity of the IC 20 along a direction parallel to the main surface on the main surface of the wiring board 2 on which the IC 20 is mounted.

  Each of the lands 3 connected to the external electrodes of each of the four decoupling multilayer ceramic capacitors 10 via the bonding member 4 is associated with the power supply terminal 21 and the ground terminal 22 of the IC 20 via wiring. It is connected. Accordingly, the four decoupling multilayer ceramic capacitors 10 are electrically connected in parallel between the power supply terminal 21 and the ground terminal 22.

  As described above, in the circuit module 1L according to the twelfth configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor shown in the circuit module 1I according to the ninth configuration example. The layout of 10C and the fourth multilayer ceramic capacitor 10D is applied to the layout of the four decoupling multilayer ceramic capacitors 10. With this configuration, the detailed description will be repeated and will be omitted. However, vibrations generated in the region R where the four decoupling multilayer ceramic capacitors 10 are disposed can be suppressed. As a result, the generation of noise can be reduced.

  Further, as described above, by disposing these four decoupling multilayer ceramic capacitors 10 in the vicinity of the IC 20, not only the circuit module 1L can be prevented from being enlarged, but also formed on the wiring board 2. It is also possible to reduce the loop inductance of the circuit.

  Therefore, by adopting a configuration such as the circuit module 1L according to the twelfth configuration example to configure the decoupling circuit, it is possible to suppress the generation of noise while preventing the electronic device from becoming large.

(Verification test)
Below, the verification test conducted in order to confirm the effect of this invention is demonstrated. As a verification test, by changing the mounting layout of the multilayer ceramic capacitor on the wiring board or by changing the mounting mode of the multilayer ceramic capacitor on the wiring board, the sound pressure level of the noise generated during voltage application can be changed. The 1st and 2nd verification test which verified whether such a change arises was implemented.

(First verification test)
FIG. 28 is a diagram showing a mounting layout of multilayer ceramic capacitors according to Comparative Examples 1 and 2 and Examples 1 and 2 that were verified in the first verification test. In FIG. 28, illustration of the sealing resin layer is omitted. In the first verification test, a circuit module to which the multilayer ceramic capacitor mounting layout shown in FIGS. 28A to 28D is applied is prepared as a sample, and a voltage is actually applied to each of these samples. The sound pressure level of the noise generated at that time was measured.

  Of the samples prepared in the first verification test, the sample according to Comparative Example 1 (see FIG. 28A) and the sample according to Example 1 (see FIG. 28C) are both included in the sample. The two laminated ceramic capacitors 10 are mounted in the first mounting mode 10 (H) described above, and the sample according to Comparative Example 2 (see FIG. 28B) and the sample according to Example 2 (see FIG. 28 (D)) is a case where two multilayer ceramic capacitors 10 included in the sample are mounted in the above-described second mounting mode 10 (V).

  As shown in FIG. 28A, the mounting layout according to Comparative Example 1 is the fourth layout pattern LP4 of the second layout group described above, and the length direction L of the two multilayer ceramic capacitors 10 is The circuit board is mounted so that it matches the X-axis direction of the wiring board 2 and the width direction W of the two multilayer ceramic capacitors 10 matches the Y-axis direction of the wiring board 2.

  As shown in FIG. 28B, the mounting layout according to the comparative example 2 is the fifth layout pattern LP5 of the second layout group described above, and the length direction L of the two multilayer ceramic capacitors 10 is It is mounted so that it matches the X-axis direction of the wiring board 2 and the thickness direction T of the two multilayer ceramic capacitors 10 matches the Y-axis direction of the wiring board 2.

  As shown in FIG. 28C, the mounting layout according to the first embodiment is the seventh layout pattern LP7 (that is, the mounting layout as in the first configuration example) of the third layout group described above. The width direction W of one multilayer ceramic capacitor 10 and the length direction L of the other multilayer ceramic capacitor 10 coincide with the X-axis direction of the wiring board 2, and the length direction L of the one multilayer ceramic capacitor 10 The other multilayer ceramic capacitor 10 is mounted so that the width direction W thereof matches the Y-axis direction of the wiring board 2. One of the pair of axial end surfaces of one multilayer ceramic capacitor 10 faces one of the pair of width direction end surfaces of the other multilayer ceramic capacitor 10 with a sealing resin layer interposed therebetween. .

  As shown in FIG. 28D, the mounting layout according to the second embodiment is the eighth layout pattern LP8 of the third layout group (that is, the mounting layout as in the second configuration example). The thickness direction T of one multilayer ceramic capacitor 10 and the length direction L of the other multilayer ceramic capacitor 10 coincide with the X-axis direction of the wiring board 2, and the length direction L of the one multilayer ceramic capacitor 10 It is mounted so that the thickness direction T of the other multilayer ceramic capacitor 10 matches the Y-axis direction of the wiring board 2. One of the pair of axial end faces of one multilayer ceramic capacitor 10 faces one of the pair of thickness direction end faces of the other multilayer ceramic capacitor 10 via a sealing resin layer. .

  The laminated ceramic capacitors 10 used in Comparative Examples 1 and 2 and Examples 1 and 2 were all of the same design specifications. More specifically, the outer dimension in the length direction L, the outer dimension in the width direction W, and the outer dimension in the thickness direction T of the multilayer ceramic capacitor 10 are 1.0 [mm] × 0.5 [mm] × 0.5. [mm] and the capacitance is 2.2 [μF]. In Comparative Examples 1 and 2 and Examples 1 and 2, all of the multilayer ceramic capacitors 10 were electrically connected in parallel. Note that a glass epoxy substrate having a thickness of 0.8 [mm] is used as the wiring substrate 2, and the multilayer ceramic capacitors 10 each have a thickness of 0.8 [mm] as the sealing resin layer 5. It was embedded with an epoxy resin layer.

  FIG. 29 is a schematic diagram showing a method for measuring the sound pressure level of noise in the first verification test. As shown in FIG. 29, when actually measuring the sound pressure level of noise, the sample S is placed in the anechoic box 200, and in this state, an AC voltage of 2 [Vpp] is applied to the multilayer ceramic capacitor 10 at 4.5. It was performed by applying a frequency in the range of [kHz] to 5.0 [kHz] and measuring the maximum value of noise generated at that time.

  The sound pressure level of the noise is measured by placing the sound collection microphone 210 facing the sample S in the anechoic box 200 and collecting the sound emitted from the sample S by the sound collection microphone 210 and the sound collection meter 220. The sound pressure level was analyzed by using the FFT analyzer 230 based on the sound.

  When measuring the sound pressure level of noise, the sound pressure level of noise due to vibration along the X-axis direction of the wiring board 2 and the sound pressure level of noise due to vibration along the Y-axis direction of the wiring board 2 are calculated. A wiring board 2 having a rectangular shape including a long side and a short side was used as a wiring board 2 in each sample so that measurement was possible individually. That is, for each of Comparative Examples 1 and 2 and Examples 1 and 2, in order to measure the sound pressure level of noise caused by vibration along the X-axis direction, in the long side direction of the wiring board 2 having a rectangular shape The X-axis direction is matched and the size of the mounting area of the multilayer ceramic capacitor 10 in the Y-axis direction is matched with the length of the rectangular side of the wiring board 2 along the Y-axis direction. As a means for measuring the sound pressure level of noise caused by vibration, the Y-axis direction is matched with the long side direction of the wiring board 2 having a rectangular shape, and the size of the mounting area of the multilayer ceramic capacitor 10 in the X-axis direction is rectangular. A wiring board 2 having a length in the short side direction is prepared, and the sound pressure level of noise is measured for each of them.

  FIG. 30 is a graph showing the results of the first verification test. In the graph shown in FIG. 30, the horizontal axis represents the sound pressure level [dB] of noise due to vibration along the X-axis direction, and the vertical axis represents the sound pressure level [dB of noise due to vibration along the Y-axis direction. ].

  As shown in FIG. 30, in the relationship between Comparative Example 1 and Examples 1 and 2, in Examples 1 and 2 to which the present invention is applied, the X axis is compared to Comparative Example 1 to which the present invention is not applied. It was confirmed that the sound pressure level of noise was significantly reduced in the direction, and in the relationship between Comparative Example 2 and Examples 1 and 2, the present invention was applied in Examples 1 and 2 to which the present invention was applied. It was confirmed that the sound pressure level of noise was significantly reduced in both the X-axis direction and the Y-axis direction as compared with Comparative Example 2 that was not performed. In particular, in the relationship between Comparative Example 2 and Examples 1 and 2, in Examples 1 and 2 to which the present invention is applied, compared to Comparative Example 2 to which the present invention is not applied, the noise noise in the Y-axis direction. The pressure level is significantly reduced.

  In addition, in the relationship between the first embodiment and the second embodiment, in the second embodiment to which the present invention is applied, noises in both the X-axis direction and the Y-axis direction are compared to the first embodiment to which the present invention is applied. It was confirmed that the sound pressure level was significantly reduced.

  Based on the first verification test described above, it can be said that by applying the present invention, it has been experimentally confirmed that the transmission of vibration is suppressed, and as a result, noise can be reduced.

(Second verification test)
FIG. 31 is a diagram showing a mounting layout of the multilayer ceramic capacitors according to Comparative Example 3 and Examples 3 and 4 verified in the second verification test. In FIG. 31, the sealing resin layer is not shown. In the second verification test, a circuit module to which the multilayer ceramic capacitor mounting layout shown in FIGS. 31A to 31C is applied is prepared as a sample, and a voltage is actually applied to each of these samples. The sound pressure level of the noise generated at that time was measured.

  Note that each sample prepared in the second verification test is one in which the three multilayer ceramic capacitors included in the sample are mounted in the second mounting mode 10 (V) described above.

  As shown in FIG. 31A, the mounting layout according to the comparative example 3 is such that the length direction L of the three multilayer ceramic capacitors 10 matches the X-axis direction of the wiring board 2 and three multilayer ceramic capacitors. 10 is mounted such that the width direction W matches the Y-axis direction of the wiring board 2. The length direction L of the three multilayer ceramic capacitors 10 is configured to be located on the same straight line.

  As shown in FIG. 31 (B), the mounting layout according to the third embodiment is a mounting layout as in the fifth configuration example, and the remaining 2 in the length direction L of one multilayer ceramic capacitor 10 are left. The thickness direction T of each multilayer ceramic capacitor 10 matches the X-axis direction of the wiring board 2, and the thickness direction T of the one multilayer ceramic capacitor 10 and the length direction L of the two multilayer ceramic capacitors 10. Are mounted so as to match the Y-axis direction of the wiring board 2. One of the pair of axial end faces of the single multilayer ceramic capacitor 10 is sealed with one of the pair of thickness direction end faces of one of the two multilayer ceramic capacitors 10. The other of the pair of axial end faces of the single multilayer ceramic capacitor 10 facing each other through the resin layer is a pair of thicknesses of the remaining one of the two multilayer ceramic capacitors 10. It faces one of the direction end faces through a sealing resin layer.

  As shown in FIG. 31C, the mounting layout according to the fourth embodiment is a mounting layout as in the seventh configuration example, and the thickness direction T of the two multilayer ceramic capacitors 10 and the remaining one The length direction L of the multilayer ceramic capacitor 10 coincides with the X-axis direction of the wiring board 2, and the length direction L of the two multilayer ceramic capacitors 10 and the thickness direction T of the single multilayer ceramic capacitor 10. Are mounted so as to match the Y-axis direction of the wiring board 2. One of the pair of axial end surfaces of each of the two multilayer ceramic capacitors 10 is sealed with a sealing resin layer on one of the pair of thickness direction end surfaces of the one multilayer ceramic capacitor 10. Is facing through.

  The multilayer ceramic capacitors 10 used in Comparative Example 3 and Examples 3 and 4 were all of the same design specifications. More specifically, the outer dimension in the length direction L, the outer dimension in the width direction W, and the outer dimension in the thickness direction T of the multilayer ceramic capacitor 10 are 1.0 [mm] × 0.5 [mm] × 0.5. [mm] and the capacitance is 2.2 [μF]. In Comparative Example 3 and Examples 3 and 4, a plurality of multilayer ceramic capacitors 10 were all electrically connected in parallel. In addition, a glass epoxy substrate having a thickness of 0.8 [mm] is used as the wiring substrate 2, and each of the plurality of multilayer ceramic capacitors 10 has a thickness of 0.8 [mm] as the sealing resin layer 5. It was embedded with an epoxy resin layer. In the second verification test, the sound pressure level of noise generated in the sample was measured using a measurement method similar to the measurement method of the sound pressure level of noise shown in the first verification test described above.

  FIG. 32 is a graph showing the results of the second verification test. In the graph shown in FIG. 32, the horizontal axis represents the sound pressure level [dB] of noise caused by vibration along the X-axis direction, and the vertical axis represents the sound pressure level [dB] of noise caused by vibration along the Y-axis direction. ].

  As shown in FIG. 32, in the relationship between Comparative Example 3 and Examples 3 and 4, in Examples 3 and 4 to which the present invention is applied, compared to Comparative Example 3 to which the present invention is not applied, the Y axis It was confirmed that the sound pressure level of noise was significantly reduced in the direction. In particular, in the relationship between Comparative Example 3 and Example 3, the sound pressure level of noise in the Y-axis direction is much higher in Example 3 to which the present invention is applied than in Comparative Example 3 to which the present invention is not applied. Has been significantly reduced.

  Based on the second verification test described above, it can be said that by applying the present invention, it has been experimentally confirmed that the transmission of vibration is suppressed and as a result noise can be reduced.

(Third verification test)
FIG. 33 is a diagram showing a mounting layout of the multilayer ceramic capacitors according to Examples 5 to 8 verified in the third verification test. FIG. 34 is a diagram showing a mounting layout of the multilayer ceramic capacitors according to Examples 9 and 10 verified in the third verification test. In FIGS. 33 and 34, the sealing resin layer is not shown. In the third verification test, circuit modules to which the multilayer ceramic capacitor mounting layout shown in FIGS. 33 (A) to 33 (D) and FIGS. 34 (A) and 34 (B) are applied are prepared as samples. A voltage was actually applied to each of these, and the sound pressure level of the noise generated at that time was measured.

  Of the samples prepared in the third verification test, the sample according to Example 5 (see FIG. 33A), the sample according to Example 8 (see FIG. 33D), and the sample according to Example 9 ( 34 (A)) and the sample according to Example 10 (see FIG. 34 (B)) are both the first mounting mode in which two of the four multilayer ceramic capacitors 10 included in the sample are described above. 10 (H) and the remaining two are mounted in the second mounting mode 10 (V) described above. A sample according to Example 6 (see FIG. 33B) is obtained by mounting the four multilayer ceramic capacitors 10 included in the sample in the above-described second mounting mode 10 (V). The sample according to Example 7 (see FIG. 33C) is obtained by mounting the four multilayer ceramic capacitors 10 included in the sample in the first mounting mode 10 (H) described above.

  As shown in FIGS. 33A to 33D, the mounting layouts according to the fifth to eighth embodiments are the same as the ninth layout example shown in FIG.

  As shown in FIG. 24 and FIG. 33 (A), in the mounting layout according to the fifth embodiment, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are mounted in the second mounting mode 10 (V). The third multilayer ceramic capacitor 10C and the fourth multilayer ceramic capacitor 10D are mounted in the first mounting mode 10 (H).

  As shown in FIGS. 24 and 33 (B), in the mounting layout according to the sixth embodiment, the first multilayer ceramic capacitor 10A to the fourth multilayer ceramic capacitor 10D are mounted in the second mounting mode 10 (V). .

  As shown in FIGS. 24 and 33C, the mounting layout according to the seventh embodiment is such that the first multilayer ceramic capacitor 10A to the fourth multilayer ceramic capacitor 10D are mounted in the first mounting mode 10 (H). .

  As shown in FIGS. 24 and 33 (D), in the mounting layout according to the eighth embodiment, the second multilayer ceramic capacitor 10B and the fourth multilayer ceramic capacitor 10D are mounted in the second mounting mode 10 (V). The first multilayer ceramic capacitor 10A and the third multilayer ceramic capacitor 10C are mounted in the first mounting mode 10 (H).

  As shown in FIG. 34A, the mounting layout according to the ninth embodiment is a mounting layout as in the eighth configuration example shown in FIG. As shown in FIGS. 23 and 34 (A), in the mounting layout according to the ninth embodiment, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are mounted in the second mounting mode 10 (V). The third multilayer ceramic capacitor 10C and the fourth multilayer ceramic capacitor 10D are mounted in the first mounting mode 10 (H).

  As shown in FIG. 34B, the mounting layout according to the tenth embodiment has a relationship between the first configuration example shown in FIG. 11 and the second configuration example shown in FIG. 14 and the fourth configuration example shown in FIG. The mounting layout is combined so as to hold. As shown in FIG. 34B, in the mounting layout according to the tenth embodiment, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are mounted in the second mounting mode 10 (V). The multilayer ceramic capacitor 10C and the fourth multilayer ceramic capacitor 10D are mounted in the first mounting mode 10 (H).

  The laminated ceramic capacitors 10 used in these Examples 5 to 10 were all of the same design specifications. More specifically, the outer dimension in the length direction L, the outer dimension in the width direction W, and the outer dimension in the thickness direction T of the multilayer ceramic capacitor 10 are 1.0 [mm] × 0.5 [mm] × 0.5. [mm] and the capacitance is 2.2 [μF]. In Examples 5 to 8, a plurality of multilayer ceramic capacitors 10 were all electrically connected in parallel. In addition, a glass epoxy substrate having a thickness of 0.8 [mm] is used as the wiring substrate 2, and each of the plurality of multilayer ceramic capacitors 10 has a thickness of 0.8 [mm] as the sealing resin layer 5. It was embedded with an epoxy resin layer. In the third verification test, the sound pressure level of noise generated in the sample was measured using a measurement method similar to the measurement method of the sound pressure level of noise shown in the first verification test described above.

  FIG. 35 is a graph showing the results of the third verification test. In the graph shown in FIG. 35, the horizontal axis represents the sound pressure level [dB] of noise due to vibration along the X-axis direction, and the vertical axis represents the sound pressure level [dB of noise due to vibration along the Y-axis direction. ].

  As shown in FIG. 35, in the relationship between the fifth, ninth, and tenth examples and the sixth, seventh, and eighth examples, compared with the sixth, seventh, and eighth examples, the fifth, ninth, and tenth sounds It was confirmed that the pressure level was significantly reduced. However, also in Examples 6, 7, and 8, four multilayer ceramic capacitors 10 are arranged as compared with the sound pressure level of the noise shown in FIG. 32 of Comparative Example 3 in which three multilayer ceramic capacitors 10 are arranged. In spite of this, the sound pressure level of noise was reduced.

  Based on the third verification test described above, it can be said that by applying the present invention, it has been experimentally confirmed that the transmission of vibration is suppressed, and as a result, noise can be reduced.

  In some of the first to twelfth configuration examples based on the embodiment of the present invention described above, the multilayer ceramic capacitor mounted in the first mounting mode 10 (H) described above and the second mounting mode described above. The case where the monolithic ceramic capacitor mounted at 10 (V) is mixed is illustrated. However, in the case where the mounting mode of the multilayer ceramic capacitor is the above-described first mounting mode 10 (H) and the above-described second mounting mode 10 (V), the multilayer ceramic capacitor prepared for mounting is used. Is different. Therefore, in order to facilitate the preparation of the multilayer ceramic capacitor, the mounting mode of the plurality of multilayer ceramic capacitors mounted on the circuit module is either the first mounting mode 10 (H) or the second mounting mode 10 (V). It is preferable to adopt a configuration example arranged in either one of them.

  The layout of the multilayer ceramic capacitor shown in the circuit modules according to the first to twelfth configuration examples based on the above-described embodiments of the present invention reduces noise without being limited by the capacity and size of the multilayer ceramic capacitor. It is a possible layout. However, since the sound pressure level of noise generally tends to increase as the capacitance of the multilayer ceramic capacitor increases, the present invention has at least one capacitance among the multilayer ceramic capacitor group assembled in the circuit module. It can be suitably applied when it is [μF] or more, and can be particularly preferably applied when it is 10 [μF] or more.

  Further, in the tenth to twelfth configuration examples based on the above-described embodiment of the present invention, the case where the present invention is applied to the multilayer ceramic capacitor group constituting the decoupling circuit is exemplified. Of course, the present invention can also be applied to a multilayer ceramic capacitor group included in a circuit for other applications connected to a line in which a voltage variation including an audible frequency component (20 [Hz] to 20 [kHz]) may occur.

  Further, in the first to ninth configuration examples based on the above-described embodiments of the present invention, a plurality of multilayer ceramic capacitors connected in series or in parallel have the same design specifications (the same capacity and the same size). However, the plurality of multilayer ceramic capacitors may have different design specifications.

  Furthermore, as described above, the present invention is not limited to the multilayer ceramic capacitor mounting structure as exemplified in the above-described embodiment of the present invention, but is applied to a multilayer metallized film capacitor. The present invention can also be applied to mounting structures of other types of representative capacitor elements.

  Here, as an example to which the present invention can be preferably applied, one capacitor element is replaced with two or more capacitor elements, and the two replaced capacitor elements are electrically connected in parallel. Examples of applying the present invention are given above. In this case, the vibration generated in the circuit module can be reduced by substituting with a capacitor element having a smaller capacity and a smaller size, and the vibration of the circuit module can also be reduced by the above-described vibration suppression effect of the present invention. Can be further reduced, and as a result, noise can be greatly reduced. For example, by replacing a capacitor element with a capacitance of 10 [μF] with two capacitor elements with a capacitance of 4.7 [μF], it is possible to significantly reduce noise without increasing the mounting area extremely. Become.

  The characteristic configurations shown in the first to twelfth configuration examples based on the above-described embodiments of the present invention can naturally be combined with each other without departing from the gist of the present invention.

  Thus, the above-described embodiment disclosed herein is illustrative in all respects and is not restrictive. The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1A to 1L circuit module, 2 wiring board, 3 lands, 4 bonding member, 5 sealing resin layer, 6A to 6C wiring, 7 power supply, 10, 10A to 10D multilayer ceramic capacitor, 11 multilayer body, 12 dielectric layer, 13 Internal electrode layer, 14 External electrode, 15 End face, 16 Thickness side face, 16a Opposing face, 17 Width side face, 17a Opposing face, 18 corner, 20 IC, 21 Power supply terminal, 22 Ground terminal, 200 Anechoic box, 210 Sound collecting microphone, 220 sound collecting meter, 230 FFT analyzer.

Claims (16)

A first capacitor element and a second capacitor element including a rectangular parallelepiped-shaped stacked body including dielectric layers and internal electrode layers alternately stacked along the stacking direction;
A wiring board including a main surface on which the first capacitor element and the second capacitor element are mounted;
A capacitor element mounting structure comprising: a sealing resin layer that embeds the first capacitor element and the second capacitor element;
The first capacitor element and the second capacitor element are electrically connected in series or in parallel via a conductive pattern provided on the wiring board,
The surfaces of the first capacitor element and the second capacitor element facing the wiring board have a short side and a long side,
Each of the first capacitor element and the second capacitor element includes a pair of end faces positioned relative to each other in a direction in which the long side extends and a pair of pins positioned relative to each other in the direction in which the short side extends. Having a side surface and a pair of external electrodes provided apart from each other on the outer surface of the laminate,
Each of the external electrodes included in the first capacitor element and the second capacitor element is bonded to a land provided on the wiring board corresponding to each of the external electrodes via a conductive bonding member. ,
The capacitor element mounting structure, wherein one of the pair of end faces of the first capacitor element is opposed to one of the pair of side faces of the second capacitor element with the sealing resin layer interposed therebetween. .   2. The capacitor element according to claim 1, wherein the stacking direction of the first capacitor element and the stacking direction of the second capacitor element are both directed in a direction along the main surface of the wiring board. Mounting structure. A first capacitor element, a second capacitor element, and a third capacitor element, each including a rectangular parallelepiped stacked body including dielectric layers and internal electrode layers stacked alternately along the stacking direction;
A wiring board including a main surface on which the first capacitor element, the second capacitor element, and the third capacitor element are mounted;
A capacitor element mounting structure comprising: a first resin element; a second resin element; and a sealing resin layer embedding the third capacitor element;
The first capacitor element, the second capacitor element, and the third capacitor element are electrically connected in series or in parallel via a conductive pattern provided on the wiring board,
The surfaces of the first capacitor element, the second capacitor element, and the third capacitor element that face the wiring board have a short side and a long side,
Each of the first capacitor element, the second capacitor element, and the third capacitor element has a pair of end faces that are positioned relative to each other in a direction in which the long side extends and a relative direction in the direction in which the short side extends. A pair of side surfaces positioned on each other and a pair of external electrodes provided apart from each other on the outer surface of the laminate,
Each of the external electrodes included in the first capacitor element, the second capacitor element, and the third capacitor element is electrically connected to a land provided on the wiring board corresponding to each of the external electrodes. Are joined respectively through
Any one of the pair of end faces of the first capacitor element, the pair of end faces of the second capacitor element, and the pair of end faces of the third capacitor element is the pair of end faces of the first capacitor element. The one side of the pair of side surfaces of the second capacitor element and the pair of side surfaces of the third capacitor element through the sealing resin layer,
The remaining one of the pair of end surfaces of the first capacitor element, the pair of end surfaces of the second capacitor element, and the pair of end surfaces of the third capacitor element is the first surface of the first capacitor element. A capacitor element that is opposed to any one of a pair of side surfaces, the pair of side surfaces of the second capacitor element, and the pair of side surfaces of the third capacitor element with the sealing resin layer interposed therebetween; Mounting structure. One of the pair of end surfaces of the first capacitor element is opposed to one of the pair of side surfaces of the second capacitor element through the sealing resin layer,
4. The remaining one of the pair of end faces of the first capacitor element is opposed to one of the pair of side faces of the third capacitor element via the sealing resin layer. 5. Mounting structure for capacitor elements. One of the pair of end surfaces of the first capacitor element is opposed to one of the pair of side surfaces of the second capacitor element through the sealing resin layer,
4. The one of the pair of end faces of the third capacitor element is opposed to the remaining other of the pair of side faces of the second capacitor element through the sealing resin layer. Mounting structure for capacitor elements.   One of the pair of end faces of the first capacitor element and one of the pair of end faces of the third capacitor element are sealed on one of the pair of side faces of the second capacitor element. The capacitor element mounting structure according to claim 3, wherein the capacitor element mounting structure faces each other via a stop resin layer.   The stacking direction of the first capacitor element and the stacking direction of the second capacitor element are both oriented in a direction along the main surface of the wiring board. The capacitor element mounting structure described.   8. The capacitor element mounting structure according to claim 7, wherein the stacking direction of the third capacitor elements is directed in a direction along the main surface of the wiring board.   8. The capacitor element mounting structure according to claim 7, wherein the stacking direction of the third capacitor elements is directed in a direction not along the main surface of the wiring board. A first capacitor element, a second capacitor element, a third capacitor element, and a fourth capacitor element, each including a rectangular parallelepiped stacked body including dielectric layers and internal electrode layers stacked alternately along the stacking direction;
A wiring board including a main surface on which the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element are mounted;
A capacitor element mounting structure comprising: a first resin element; a second capacitor element; a third capacitor element; and a sealing resin layer that embeds the fourth capacitor element;
The first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element are electrically connected in series or in parallel via a conductive pattern provided on the wiring board,
The surfaces of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element that face the wiring board have a short side and a long side,
Each of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element has a pair of end faces that are positioned in the direction in which the long side extends, and the short side A pair of side surfaces that are positioned relative to each other in the extending direction, and a pair of external electrodes that are spaced apart from each other on the outer surface of the laminate,
Each of the external electrodes included in the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element is a land provided on the wiring board corresponding to each of the external electrodes. Are joined to each other via a conductive joining member,
One of the pair of end surfaces of the first capacitor element is opposed to one of the pair of side surfaces of the second capacitor element through the sealing resin layer,
One of the pair of end surfaces of the second capacitor element is opposed to one of the pair of side surfaces of the third capacitor element through the sealing resin layer,
One of the pair of end surfaces of the third capacitor element is opposed to one of the pair of side surfaces of the fourth capacitor element through the sealing resin layer,
A mounting structure for a capacitor element, wherein one of the pair of end faces of the fourth capacitor element is opposed to one of the pair of side faces of the first capacitor element via the sealing resin layer. .   11. The capacitor element according to claim 10, wherein the stacking direction of the first capacitor element and the stacking direction of the second capacitor element are both directed in a direction along the main surface of the wiring board. Mounting structure.   12. The capacitor element according to claim 11, wherein the stacking direction of the third capacitor element and the stacking direction of the fourth capacitor element are both directed in a direction along the main surface of the wiring board. Mounting structure.   12. The capacitor element according to claim 11, wherein the stacking direction of the third capacitor element and the stacking direction of the fourth capacitor element are both oriented in a direction not along the main surface of the wiring board. Mounting structure. A first capacitor element, a second capacitor element, a third capacitor element, and a fourth capacitor element, each including a rectangular parallelepiped stacked body including dielectric layers and internal electrode layers stacked alternately along the stacking direction;
A wiring board including a main surface on which the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element are mounted;
A capacitor element mounting structure comprising: a first resin element; a second capacitor element; a third capacitor element; and a sealing resin layer that embeds the fourth capacitor element;
The first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element are electrically connected in series or in parallel via a conductive pattern provided on the wiring board,
The surfaces of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element that face the wiring board have a short side and a long side,
Each of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element has a pair of end faces that are positioned in the direction in which the long side extends, and the short side A pair of side surfaces that are positioned relative to each other in the extending direction, and a pair of external electrodes that are spaced apart from each other on the outer surface of the laminate,
Each of the external electrodes included in the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element is a land provided on the wiring board corresponding to each of the external electrodes. Are joined to each other via a conductive joining member,
One of the pair of end surfaces of the first capacitor element is opposed to one of the pair of side surfaces of the second capacitor element through the sealing resin layer,
One of the pair of end surfaces of the third capacitor element is opposed to one of the pair of side surfaces of the fourth capacitor element through the sealing resin layer,
The laminating direction of the first capacitor element and the laminating direction of the second capacitor element are both oriented along the main surface of the wiring board,
The capacitor element mounting structure, wherein the stacking direction of the third capacitor element and the stacking direction of the fourth capacitor element are both oriented in a direction not along the main surface of the wiring board.   The other of the pair of side surfaces of the second capacitor element is opposed to the other of the pair of end faces of the third capacitor element via the sealing resin layer. Capacitor element mounting structure. One of the pair of side surfaces of the first capacitor element is opposed to one of the pair of side surfaces of the third capacitor element through the sealing resin layer,
The one of the pair of end faces of the second capacitor element is opposed to one of the pair of end faces of the fourth capacitor element via the sealing resin layer. Capacitor element mounting structure.