JP7058938B2 - Capacitor element mounting structure - Google Patents

Description

The present invention relates to a mounting structure of a capacitor element in which a plurality of rectangular parallelepiped-shaped capacitor elements are mounted on a wiring board and the plurality of capacitor elements are embedded in a sealing resin layer on the wiring board.

In recent years, as the performance of electronic devices has improved, the capacity of monolithic ceramic capacitors as electronic components has been increasing. In a large-capacity multilayer ceramic capacitor, a ceramic material having a high dielectric constant such as barium titanate (BaTIO ₃ ) is used as a dielectric material.

Since these high dielectric constant ceramic materials have piezoelectricity and electrolytic distortion, in a laminated ceramic capacitor containing a dielectric made of a high dielectric constant ceramic material, mechanically when a voltage is applied. Distortion will occur.

Therefore, when an AC voltage or a DC voltage on which an AC component is superimposed is applied to a large-capacity multilayer ceramic capacitor mounted on a wiring board, vibration occurs due to mechanical strain generated in the ceramic material. As a result, the vibration propagates to the wiring board, causing the circuit board to vibrate.

Here, when the circuit board vibrates at a frequency of 20 [Hz] to 20 [kHz], which is the audible frequency range, due to the propagated vibration, so-called "acoustic noise" is generated. Become.

For example, a DC / DC converter mounted on an electronic device converts a DC voltage into a predetermined DC voltage suitable for each electronic device and supplies the DC voltage as power. The input / output of the DC / DC converter. A monolithic ceramic capacitor for decoupling is connected to the circuit in order to reduce the noise generated based on the switching operation. A ripple voltage superimposed on the DC voltage is applied to the multilayer ceramic capacitor by the switching operation, but the ripple voltage causes mechanical distortion in the multilayer ceramic capacitor having a frequency in the audible frequency range. When this propagates to the wiring board, noise is generated on the circuit board.

Further, when a sensor such as an acceleration sensor or an angular velocity sensor is mounted on a wiring board on which a multilayer ceramic capacitor is mounted, vibration of the circuit board may cause malfunction of these sensors.

Therefore, various techniques for suppressing the vibration of the circuit board caused by the mechanical distortion of the monolithic ceramic capacitor have been conventionally proposed. For example, in Japanese Patent Application Laid-Open No. 2000-23230 (Patent Document 1), one laminated ceramic is mounted in a plane-symmetrical manner by mounting a pair of laminated ceramic capacitors having the same specifications at corresponding positions on the front and back surfaces of a wiring board. A mounting structure in which the vibration propagated from the capacitor to the wiring board and the vibration propagated from the other multilayer ceramic capacitor to the wiring board cancel each other out, thereby suppressing the vibration of the circuit board. Is disclosed.

Further, in Japanese Patent Application Laid-Open No. 2002-232110 (Patent Document 2), a pair of multilayer ceramic capacitors are mounted on the same main surface of a wiring board so that their major axes are arranged in parallel so as to be close to each other, and a wiring board is mounted. By configuring the pair of laminated ceramic capacitors to apply a ripple voltage so that the vibration of the vibration wave transmitted to the capacitor has an amplitude relationship of almost opposite phases, the vibration of the circuit board is suppressed. The structure is disclosed.

The mounting structures disclosed in Patent Documents 1 and 2 described above are all mounted so that the multilayer ceramic capacitor is exposed on the main surface of the wiring board. However, as a mounting structure for the monolithic ceramic capacitor, in addition to this, by covering the main surface of the wiring board on which the monolithic ceramic capacitor is mounted with a sealing resin layer, the laminated ceramic capacitor can be used as the sealing resin layer. Some are embedded in the structure. As a document in which the structure is disclosed, for example, there is International Publication No. 2011/135926 (Patent Document 3).

Japanese Unexamined Patent Publication No. 2000-23230 Japanese Unexamined Patent Publication No. 2002-232110 International Publication No. 2011/135926

Here, there is a remarkable difference in the mode of vibration generated on the circuit board between the case where the laminated ceramic capacitor is exposed on the wiring board and the case where the laminated ceramic capacitor is embedded in the sealing resin layer on the wiring board. Occurs. In the former, the vibration transmission path is limited to the solder joint, whereas in the latter, the vibration transmission path is not limited to the solder joint, and the sealing resin layer that embeds the laminated ceramic capacitor is also available. This is because it becomes a vibration transmission path. Further, when the entire main surface of the wiring board on which the multilayer ceramic capacitor is mounted is covered with the sealing resin layer, vibration occurs not only in the wiring board but also in the entire circuit board including the sealing resin layer. Therefore, the mode of vibration is different in this respect as well.

Therefore, it can be said that the techniques disclosed in Patent Documents 1 and 2 described above can be suitably applied to a mounting structure in which a laminated ceramic capacitor is necessarily embedded in a sealing resin layer on a wiring board. not.

Therefore, the present invention has been made in view of the above-mentioned situation, and is a mounting structure of a capacitor element in which a plurality of capacitor elements are embedded in a sealing resin layer on a wiring board. The purpose is to suppress the vibration generated in the capacitor.

The mounting structure of the capacitor element based on the first aspect of the present invention includes a first capacitor element and a second capacitor element having a rectangular shape including a dielectric layer and an internal electrode layer alternately laminated along the stacking direction. A wiring board including a capacitor element, a main surface on which the first capacitor element and the second capacitor element are mounted, and a sealing resin layer for embedding the first capacitor element and the second capacitor element are provided. There is. The first capacitor element and the second capacitor element are electrically connected in series or in parallel via a conductive pattern provided on the wiring board. The surfaces of the first capacitor element and the second capacitor element facing the wiring board have short sides and long sides. Each of the first capacitor element and the second capacitor element has a pair of end faces that are located relative to each other in the direction in which the long side extends, and a pair of end faces that are located relative to each other in the direction in which the short side extends. It has a side surface and a pair of external electrodes provided apart from each other on the outer surface of the laminate. Each of the first capacitor element and the external electrode included in the second capacitor element is bonded to a land provided on the wiring board corresponding to each of the external electrodes via a conductive bonding member. ing. One of the pair of end faces of the first capacitor element faces one of the pair of side surfaces of the second capacitor element via the sealing resin layer.

In the capacitor element mounting structure based on the first aspect of the present invention, the stacking direction of the first capacitor element and the stacking direction of the second capacitor element are both of the wiring board. It is preferable that the orientation is along the main surface.

The mounting structure of the capacitor element based on the second aspect of the present invention is a first capacitor element including a rectangular structure including a dielectric layer and an internal electrode layer alternately laminated along the stacking direction. A wiring board including a capacitor element and a third capacitor element, a main surface on which the first capacitor element, the second capacitor element, and the third capacitor element are mounted, the first capacitor element, the second capacitor element, and the like. It includes a sealing resin layer that embeds the third capacitor element. The first capacitor element, the second capacitor element, and the third capacitor element are electrically connected in series or in parallel via a conductive pattern provided on the wiring board. The surfaces of the first capacitor element, the second capacitor element, and the third capacitor element facing the wiring board have short sides and long sides. Each of the first capacitor element, the second capacitor element, and the third capacitor element is relative to a pair of end faces located relative to each other in the direction in which the long side extends and in the direction in which the short side extends. It has a pair of side surfaces that are located on the outer surface of the laminated body and a pair of external electrodes that are provided apart from each other on the outer surface of the laminated body. Each of the first capacitor element, the second capacitor element, and the external electrode included in the third capacitor element is a bonding member conductive to a land provided on the wiring board corresponding to each of the external electrodes. Each is joined via. One of the pair of end faces of the first capacitor element, the pair of end faces of the second capacitor element, and the pair of end faces of the third capacitor element is the pair of the first capacitor elements. The side surface, the pair of side surfaces of the second capacitor element, and any one of the pair of side surfaces of the third capacitor element face each other via the sealing resin layer, and the first capacitor The remaining one of the pair of end faces of the element, the pair of end faces of the second capacitor element, and the pair of end faces of the third capacitor element is the pair of side surfaces of the first capacitor element. It faces any one of the pair of side surfaces of the second capacitor element and the pair of side surfaces of the third capacitor element via the sealing resin layer.

In the capacitor element mounting structure based on the second aspect of the present invention, one of the pair of end faces of the first capacitor element is one of the pair of side surfaces of the second capacitor element. One of them faces the sealing resin layer via the sealing resin layer, and the remaining one of the pair of end faces of the first capacitor element is sealed on one of the pair of side surfaces of the third capacitor element. They may face each other via a waterproof resin layer.

In the capacitor element mounting structure based on the second aspect of the present invention, one of the pair of end faces of the first capacitor element is one of the pair of side surfaces of the second capacitor element. One of the pair of end faces of the third capacitor element faces the other via the sealing resin layer, and the other of the pair of side surfaces of the second capacitor element is sealed. They may face each other via a waterproof resin layer.

In the capacitor element mounting structure based on the second aspect of the present invention, one of the pair of end faces of the first capacitor element and the pair of end faces of the third capacitor element. One may face one of the pair of side surfaces of the second capacitor element via the sealing resin layer.

In the capacitor element mounting structure based on the second aspect of the present invention, the stacking direction of the first capacitor element and the stacking direction of the second capacitor element are both of the wiring board. It is preferable that the orientation is along the main surface.

In the mounting structure of the capacitor element based on the second aspect of the present invention, the stacking direction of the third capacitor element may be directed along the main surface of the wiring board.

In the capacitor element mounting structure based on the second aspect of the present invention, the stacking direction of the third capacitor element may be directed not along the main surface of the wiring board.

The mounting structure of the capacitor element based on the third aspect of the present invention is the first capacitor element, the second capacitor element, which includes a rectangular body-shaped laminate including dielectric layers and internal electrode layers alternately laminated along the stacking direction. A wiring board including a capacitor element, a third capacitor element and a fourth capacitor element, a main surface on which the first capacitor element, the second capacitor element, the third capacitor element and the fourth capacitor element are mounted, and the above. It includes a first capacitor element, the second capacitor element, the third capacitor element, and a sealing resin layer that embeds the fourth capacitor element. The first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element are electrically connected in series or in parallel via a conductive pattern provided on the wiring board. The surfaces of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element facing the wiring board have short sides and long sides. Each of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element has a pair of end faces located opposite to each other in the direction in which the long side extends, and the short side. It has a pair of side surfaces that are located relative to each other in the extending direction, and a pair of external electrodes that are provided apart from each other on the outer surface of the laminated body. Each of the first capacitor element, the second capacitor element, the third capacitor element, and the external electrode included in the fourth capacitor element is a land provided on the wiring board corresponding to each of the external electrodes. They are joined to each other via a conductive joining member. One of the pair of end faces of the first capacitor element faces one of the pair of side surfaces of the second capacitor element via the sealing resin layer. One of the pair of end faces of the second capacitor element faces one of the pair of side surfaces of the third capacitor element via the sealing resin layer. One of the pair of end faces of the third capacitor element faces one of the pair of side surfaces of the fourth capacitor element via the sealing resin layer. One of the pair of end faces of the fourth capacitor element faces one of the pair of side surfaces of the first capacitor element via the sealing resin layer.

In the capacitor element mounting structure based on the third aspect of the present invention, the stacking direction of the first capacitor element and the stacking direction of the second capacitor element are both of the wiring board. It is preferable that the orientation is along the main surface.

In the capacitor element mounting structure based on the third aspect of the present invention, the stacking direction of the third capacitor element and the stacking direction of the fourth capacitor element are the main components of the wiring board. It may be oriented along the surface.

In the capacitor element mounting structure based on the third aspect of the present invention, the stacking direction of the third capacitor element and the stacking direction of the fourth capacitor element are the main components of the wiring board. It may be oriented in a direction that does not follow the surface.

The mounting structure of the capacitor element based on the fourth aspect of the present invention is the first capacitor element, the second capacitor element, which includes a rectangular structure including a dielectric layer and an internal electrode layer alternately laminated along the stacking direction. A wiring board including a capacitor element, a third capacitor element and a fourth capacitor element, a main surface on which the first capacitor element, the second capacitor element, the third capacitor element and the fourth capacitor element are mounted, and the above. It includes a first capacitor element, the second capacitor element, the third capacitor element, and a sealing resin layer that embeds the fourth capacitor element. The first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element are electrically connected in series or in parallel via a conductive pattern provided on the wiring board. The surfaces of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element facing the wiring board have short sides and long sides. Each of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element has a pair of end faces located opposite to each other in the direction in which the long side extends, and the short side. It has a pair of side surfaces that are located relative to each other in the extending direction, and a pair of external electrodes that are provided apart from each other on the outer surface of the laminated body. Each of the first capacitor element, the second capacitor element, the third capacitor element, and the external electrode included in the fourth capacitor element is a land provided on the wiring board corresponding to each of the external electrodes. They are joined to each other via a conductive joining member. One of the pair of end faces of the first capacitor element faces one of the pair of side surfaces of the second capacitor element via the sealing resin layer. One of the pair of end faces of the third capacitor element faces one of the pair of side surfaces of the fourth capacitor element via the sealing resin layer. The stacking direction of the first capacitor element and the stacking direction of the second capacitor element are both oriented along the main surface of the wiring board. Both the stacking direction of the third capacitor element and the stacking direction of the fourth capacitor element are oriented so as not to follow the main surface of the wiring board.

In the capacitor element mounting structure based on the fourth aspect of the present invention, the other of the pair of side surfaces of the second capacitor element is the pair of end faces of the third capacitor element. On the other hand, it is preferable that they face each other via the sealing resin layer.

In the capacitor element mounting structure based on the fourth aspect of the present invention, one of the pair of side surfaces of the first capacitor element is one of the pair of side surfaces of the third capacitor element. One of the pair of end faces of the second capacitor element faces the one side via the sealing resin layer, and the sealing resin layer is placed on one of the pair of end faces of the fourth capacitor element. It is preferable that they face each other via.

Here, the term "rectangular parallelepiped-shaped capacitor element" described above includes rounded corners and ridges, and steps and irregularities on the surface that can be ignored as a whole. It shall include those provided.

In addition, the term "rectangular surface" described above includes rounded corners of the contour line, and folds and bends that can be ignored as a whole on the sides of the contour line. It shall be included in the one provided with.

Further, the term "end face and side surface facing each other" described above includes not only the case where the entire surface of one of the end face and the side surface faces the other face, but also the case of one face. It is assumed that a part of the region faces only a part of the other surface.

According to the present invention, in a mounting structure of a capacitor element in which a plurality of capacitor elements are embedded in a sealing resin layer on a wiring board, vibration generated in the mounting structure can be suppressed.

It is a perspective view of the multilayer ceramic capacitor provided in the circuit module in embodiment of this invention. It is sectional drawing along the line II-II shown in FIG. 1 of the multilayer ceramic capacitor shown in FIG. FIG. 3 is a cross-sectional view taken along the line III-III shown in FIG. 1 of the monolithic ceramic capacitor shown in FIG. It is a figure which shows the result of simulating the strain which occurs at the time of applying a voltage to the laminated body of the laminated ceramic capacitor shown in FIG. 1. FIG. 3 is a schematic cross-sectional view showing a first mounting mode of the multilayer ceramic capacitor shown in FIG. 1 on a circuit module. FIG. 3 is a schematic cross-sectional view showing a second mounting mode of the monolithic ceramic capacitor shown in FIG. 1 on a circuit module. It is a schematic diagram which shows the 1st to 3rd layout patterns belonging to the 1st layout group when two laminated ceramic capacitors are arranged close to each other. It is a schematic diagram which shows the 4th to 6th layout patterns belonging to the 2nd layout group when two laminated ceramic capacitors are arranged close to each other. It is a schematic diagram which shows the 7th to 10th layout patterns belonging to the 3rd layout group when two laminated ceramic capacitors are arranged close to each other. It is a schematic perspective view of the circuit module which concerns on 1st configuration example. It is a schematic plan view which shows the layout of the laminated ceramic capacitor provided in the circuit module which concerns on 1st configuration example. FIG. 3 is a schematic cross-sectional view taken along the line XII-XII shown in FIG. 11 of the circuit module according to the first configuration example. 10 is a diagram showing a circuit configuration example of a circuit including the multilayer ceramic capacitor shown in FIGS. 10 to 12. It is a schematic plan view which shows the layout of the laminated ceramic capacitor provided in the circuit module which concerns on 2nd configuration example. FIG. 3 is a schematic cross-sectional view taken along the line XV-XV shown in FIG. 14 of the circuit module according to the second configuration example. It is a schematic plan view which shows the layout of the laminated ceramic capacitor provided in the circuit module which concerns on 3rd configuration example. 6 is a schematic cross-sectional view taken along the line XVII-XVII shown in FIG. 16 of the circuit module according to the third configuration example. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor provided in the circuit module which concerns on 4th. It is a schematic cross-sectional view along the XIX-XIX line shown in FIG. 18 of the circuit module which concerns on 4th configuration example. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor provided in the circuit module which concerns on 5th configuration example. It is a schematic plan view which shows the layout of the laminated ceramic capacitor provided in the circuit module which concerns on 6th configuration example. It is a schematic plan view which shows the layout of the laminated ceramic capacitor provided in the circuit module which concerns on 7th configuration example. It is a schematic plan view which shows the layout of the laminated ceramic capacitor provided in the circuit module which concerns on 8th configuration example. It is a schematic plan view which shows the layout of the laminated ceramic capacitor provided in the circuit module which concerns on 9th configuration example. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor and IC provided in the circuit module which concerns on 10th configuration example. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor and IC provided in the circuit module which concerns on 11th configuration example. It is a schematic plan view which shows the layout of the multilayer ceramic capacitor and IC provided in the circuit module which concerns on a twelfth configuration example. It is a figure which shows the mounting layout of the laminated ceramic capacitor which concerns on Comparative Examples 1 and 2 and Example 1 and 2 which were verified in the 1st verification test. It is a schematic diagram which shows the measuring method of the sound pressure level of noise in the 1st verification test. It is a graph which shows the result of the 1st verification test. It is a figure which shows the mounting layout of the laminated ceramic capacitor which concerns on Comparative Example 3 and Example 3 and 4 verified in the 2nd verification test. It is a graph which shows the result of the 2nd verification test. It is a figure which shows the mounting layout of the laminated ceramic capacitor which concerns on Example 5-8 which verified in the 3rd verification test. It is a figure which shows the mounting layout of the laminated ceramic capacitor which concerns on Examples 9 and 10 which verified in the 3rd verification test. It is a graph which shows the result of the 3rd verification test.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the embodiments shown below, the same or common parts are designated by the same reference numerals in the drawings, and the description thereof will not be repeated.

In the embodiment shown below, a circuit module in which a multilayer ceramic capacitor using a ceramic material as a dielectric material is embedded as a capacitor element will be described as an example. In addition, as a circuit module to which the present invention can be applied, there is a circuit module in which a laminated metallized film capacitor or the like using a resin film as a dielectric material is embedded as a capacitor element.

FIG. 1 is a perspective view of a multilayer ceramic capacitor provided in a circuit module according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG. 1 of the multilayer ceramic capacitor shown in FIG. 1, and FIG. 3 is a sectional view taken along the line III-III shown in FIG. 1 of the multilayer ceramic capacitor shown in FIG. It is a cross-sectional view along. First, the monolithic ceramic capacitor provided in the circuit module according to the present embodiment will be described with reference to FIGS. 1 to 3.

As shown in FIGS. 1 to 3, the laminated ceramic capacitor 10 is an electronic component having a rectangular parallelepiped shape as a whole, and has a laminated body 11 and a pair of external electrodes 14.

As shown in FIGS. 2 and 3, the laminated body 11 is composed of a dielectric layer 12 and an internal electrode layer 13 alternately laminated along a predetermined direction. The dielectric layer 12 is formed of, for example, a ceramic material containing barium titanate as a main component. Further, the dielectric layer 12 may contain Mn compound, Mg compound, Si compound, Co compound, Ni compound, rare earth compound and the like as subcomponents of the ceramic powder which is a raw material of the ceramic sheet described later. On the other hand, the internal electrode layer 13 is made of a metal material typified by, for example, Ni, Cu, Ag, Pd, Ag—Pd alloy, Au or the like.

For the laminate 11, a plurality of material sheets in which a conductive paste to be an internal electrode layer 13 is printed on the surface of a ceramic sheet (so-called green sheet) to be a dielectric layer 12 are prepared, and these plurality of material sheets are laminated. Manufactured by crimping and firing.

The material of the dielectric layer 12 is not limited to the above-mentioned ceramic material containing barium titanate as a main component, but other ceramic materials having a high dielectric constant (for example, those containing CaTIO ₃ , SrTiO ₃ , etc. as a main component). May be selected as the material of the dielectric layer 12. Further, the material of the internal electrode layer 13 is not limited to the metal material described above, and another conductive material may be selected as the material of the internal electrode layer 13.

As shown in FIGS. 1 and 2, the pair of external electrodes 14 are provided apart from each other so as to cover the outer surfaces of both ends of the laminated body 11 in a predetermined direction. Each of the pair of external electrodes 14 is composed of a conductive film.

The pair of external electrodes 14 are composed of, for example, a laminated film of a sintered metal layer and a plating layer. The sintered metal layer is formed by baking a paste such as Cu, Ni, Ag, Pd, Ag—Pd alloy, Au or the like. The plating layer is composed of, for example, a Ni plating layer and a Sn plating layer covering the Ni plating layer. The plating layer may be a Cu plating layer or an Au plating layer instead. Further, the pair of external electrodes 14 may be composed of only the plating layer.

Further, as the pair of external electrodes 14, it is also possible to use a conductive resin paste containing a metal component and a resin component. When the conductive resin paste is used as the pair of external electrodes 14, the resin component contained in the conductive resin paste has the effect of absorbing the vibration generated in the laminated body 11, and thus propagates from the laminated body 11 to the outside. It becomes possible to effectively attenuate the vibration.

As shown in FIG. 2, one of the pair of internal electrode layers 13 adjacent to each other with the dielectric layer 12 interposed therebetween along the stacking direction is one of the pair of external electrodes 14 inside the laminated ceramic capacitor 10. The other of the pair of internal electrode layers 13 that are electrically connected and are adjacent to each other with the dielectric layer 12 interposed therebetween in the stacking direction is the other of the pair of external electrodes 14 inside the laminated ceramic capacitor 10. Is electrically connected to. As a result, a plurality of capacitor elements are electrically connected in parallel between the pair of external electrodes 14.

Here, as shown in FIGS. 1 to 3, the direction in which the pair of external electrodes 14 are arranged is defined as the length direction L of the laminated ceramic capacitor 10, and the dielectric layer 12 and the internal electrode layer 13 in the laminated body 11 are defined. When the stacking direction is defined as the thickness direction T and the direction orthogonal to both the length direction L and the thickness direction T is defined as the width direction W, the laminated ceramic capacitor 10 in the present embodiment is defined as the length direction L. It has an elongated rectangular shape configured so that the outer dimensions along it are the longest.

As typical values of the external dimensions of the multilayer ceramic capacitor 10 in the length direction L and the external dimensions in the width direction W (usually, the external dimensions in the thickness direction T are the same as the external dimensions in the width direction W). For example, 3.2 [mm] x 1.6 [mm], 2.0 [mm] x 1.25 [mm], 1.6 [mm] x 0.8 [mm], 1.0 [mm] x 0.5 [mm], 0.8 [mm] x 0.4 [mm], 0.6 [mm] x 0.3 [mm], 0.4 [mm] x 0.2 [mm], etc. Can be mentioned.

Further, among the six faces of the rectangular parallelepiped-shaped multilayer ceramic capacitor 10, the pair of faces facing each other in the length direction L is defined as the end face 15, and the four faces connecting the pair of end faces 15 are the side surfaces 16 and 17. Is defined as. Further, of the four side surfaces 16 and 17, a pair of surfaces facing each other in the thickness direction T is defined as a thickness direction side surface 16, and a pair of surfaces facing each other in the width direction W is defined as a width direction side surface 17. It is defined and the term is used in the following description. The pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17 each have a rectangular shape including a pair of long sides extending in the length direction L and a pair of short sides connecting the pair of long sides. ing.

FIG. 4 is a diagram showing the results of simulating the strain generated when a voltage is applied to the laminated body of the multilayer ceramic capacitor shown in FIG. 1. Next, with reference to FIG. 4, the distortion that can occur in the multilayer ceramic capacitor provided in the circuit module in the present embodiment will be described.

When an AC voltage or a DC voltage on which an AC component is superimposed is applied to the pair of external electrodes 14 of the multilayer ceramic capacitor 10 described above, mechanical distortion as shown in FIG. 4 occurs in the laminated body 11. This causes distortion of the monolithic ceramic capacitor 10.

As shown in FIG. 4, when a voltage is applied, the laminated body 11 is significantly significantly distorted outward along the thickness direction _T as indicated by the arrow ART in the figure. Along with this, the laminated body 11 is slightly distorted inward along the length direction L as indicated by the arrow AR _L in the drawing, and the laminated body 11 is distorted slightly inward along the width direction W by the arrow AR in the drawing. As indicated by _W , it is slightly distorted inward. On the other hand, in the corner portion 18 of the laminated body 11 having an elongated rectangular parallelepiped shape, almost no distortion occurs. In the figure, the strain generated toward the outside of the laminated body 11 is indicated by a white arrow, and the strain generated toward the inside of the laminated body 11 is indicated by a black arrow, and the magnitude of these strains is indicated by a black arrow. Are indicated by the size of the arrows.

Therefore, even in the monolithic ceramic capacitor 10, the same distortion will occur when the voltage is applied, and the distortion as described above will repeatedly occur in accordance with the period of the voltage applied to the monolithic ceramic capacitor 10. .. As a result, in the circuit module provided with the monolithic ceramic capacitor 10, the monolithic ceramic capacitor 10 becomes a vibration source, and the vibration propagates to the sealing resin layer and the wiring board to vibrate the circuit module, resulting in noise. It occurs or induces malfunction of other elements.

5 and 6 are schematic cross-sectional views showing the first and second mounting modes of the monolithic ceramic capacitor shown in FIG. 1, respectively, in the circuit module. As the mounting mode of the above-mentioned multilayer ceramic capacitor on the circuit module, two mounting modes having different orientations with respect to the wiring board are assumed. Hereinafter, the two mounting embodiments will be described with reference to FIGS. 5 and 6. The cross sections shown in FIGS. 5 (B) and 6 (B) are cross sections along the VB-VB line and the VIB-VIB line shown in FIGS. 5 (A) and 6 (A), respectively.

As shown in FIGS. 5 and 6, in both the first mounting mode 10 (H) and the second mounting mode 10 (V), the multilayer ceramic capacitor 10 has a length in a direction connecting the pair of end faces 15. The direction L is arranged on the main surface of the wiring board 2 so as to face the direction along the main surface of the wiring board 2. That is, any of the rectangular side surfaces 16 and 17 including the long side and the short side is the facing surface facing the main surface of the wiring board 2. Further, a sealing resin layer 5 is formed on the main surface of the wiring board 2 so as to embed the laminated ceramic capacitor 10 in this state.

The wiring board 2 is made of an insulating substrate having a conductive pattern formed on at least one of the pair of main surfaces. As the material of the wiring board 2, a resin material such as epoxy resin or a ceramic material such as alumina, or a material to which a filler made of an inorganic material or an organic material, a woven cloth, or the like is added can be used. .. Generally, as the wiring board 2, a glass epoxy board in which a glass woven fabric is added to a base material made of an epoxy resin is preferably used.

A pair of lands 3 are provided on the main surface of the wiring board 2 corresponding to the monolithic ceramic capacitor 10. Each of these pairs of lands 3 corresponds to a part of the above-mentioned conductive pattern, and is arranged so as to be located apart from each other.

Further, each of the pair of lands 3 is formed in a size corresponding to the pair of external electrodes 14 possessed by each of the laminated ceramic capacitors 10, and the wiring board 2 is formed with respect to the corresponding external electrodes 14. It contains facing parts along the normal direction of the main surface. As the material of the pair of lands 3, various conductive materials can be used, but in general, a metal material such as copper foil is preferably used.

The pair of external electrodes 14 of each of the multilayer ceramic capacitors 10 and the pair of lands 3 provided on the wiring board 2 are bonded by a conductive bonding member 4, respectively. As the joining member 4, for example, a conductive adhesive or solder can be used. Here, when a conductive adhesive is used as the joining member 4, the resin component contained in the conductive adhesive exerts the effect of absorbing the vibration generated in the laminated ceramic capacitor 10, so that the laminated ceramic capacitor 10 is used. It becomes possible to effectively attenuate the vibration propagating from the outside.

The sealing resin layer 5 is located so as to cover the main surface of the wiring board 2 in the portion where the laminated ceramic capacitor 10 is mounted, and the laminated ceramic capacitor 10 is embedded on the main surface of the wiring board 2. ing. More specifically, the sealing resin layer 5 is provided so as to cover the main surface of the wiring board 2, the surface of the land 3 provided on the wiring board 2, the surface of the joining member 4, and the surface of the laminated ceramic capacitor 10. This prevents the surface of these members from being exposed to the outside of the circuit module. It is preferable that the space between the wiring board 2 and the laminated ceramic capacitor 10 and the space between the pair of lands 3 and the pair of joining members 4 are embedded by the sealing resin layer 5. The space does not necessarily have to be embedded by the sealing resin layer 5, and the space may only be surrounded by the sealing resin layer 5.

The material of the sealing resin layer 5 is not particularly limited, and various thermoplastic resin materials, thermosetting resin materials, and the like can be used. Further, fillers and the like made of various materials may be added to the sealing resin layer 5. From the viewpoint of reliability of the circuit module, it is preferable that the difference in linear expansion coefficient between the wiring board 2 and various electronic components mounted on the wiring board 2 is small, and when the above-mentioned glass epoxy board is used as the wiring board 2. Usually, an epoxy resin is used as the sealing resin layer 5. Further, although not shown, a member such as a conductive layer may be separately provided on the surface of the sealing resin layer 5.

When assembling the multilayer ceramic capacitor 10 to the circuit module, first, a conductive adhesive or a solder paste is applied on a pair of lands 3 provided in advance on the wiring board 2 by screen printing or the like, and then the laminated ceramic is applied thereto. With the capacitors 10 mounted, they are charged into the reflow furnace. As a result, a fillet is formed on the joining member 4, and the monolithic ceramic capacitor 10 is mounted on the wiring board 2. After that, the circuit module is manufactured by forming the sealing resin layer 5 on the main surface of the wiring board 2 on which the monolithic ceramic capacitor 10 is mounted by transfer molding, potting, or the like.

Here, as shown in FIGS. 5A and 5B, in the first mounting embodiment 10 (H), the dielectric layer 12 and the internal electrode layer 13 in the laminated body 11 of the laminated ceramic capacitor 10 Laminated so that the thickness direction T, which is the laminating direction of, faces a direction that does not follow the main surface of the wiring board 2 (that is, the thickness direction T of the laminated ceramic capacitor 10 is orthogonal to the main surface of the wiring board 2). The ceramic capacitor 10 is arranged on the wiring board 2. As a result, in the first mounting mode 10 (H), one of the pair of thickness direction side surfaces 16 located relative to each other in the thickness direction T of the laminated ceramic capacitor 10 faces the facing surface 16a facing the wiring board 2. Will be.

On the other hand, as shown in FIGS. 6 (A) and 6 (B), in the second mounting mode 10 (V), the dielectric layer 12 and the internal electrode layer 13 in the laminated body 11 of the laminated ceramic capacitor 10 Laminating so that the thickness direction T, which is the laminating direction, faces the direction along the main surface of the wiring board 2 (that is, the thickness direction T of the laminated ceramic capacitor 10 is positioned parallel to the main surface of the wiring board 2). The ceramic capacitor 10 is arranged on the wiring board 2. As a result, in the second mounting mode 10 (V), one of the pair of widthwise side surfaces 17 located relative to each other in the widthwise direction W of the laminated ceramic capacitor 10 faces the facing surface 17a facing the wiring board 2. Will be.

7 to 9 are schematic views showing various layout patterns when two multilayer ceramic capacitors are arranged in close proximity to each other. Here, FIGS. 7 (A) to 7 (C) are schematic views showing the first to third layout patterns belonging to the first layout group, respectively, and FIGS. 8 (A) to 8 (C) are diagrams. 9 (A) to 9 (D) are schematic views showing the fourth to sixth layout patterns belonging to the second layout group, respectively, and FIGS. 9 (A) to 9 (D) show the seventh to tenth layout patterns belonging to the third layout group, respectively. It is a schematic diagram. Next, with reference to FIGS. 7 to 9, details of various layout patterns when two multilayer ceramic capacitors are arranged close to each other will be described, and when the layout pattern is adopted, these 2 of the circuit module will be described. The magnitude of the vibration generated in the region R in which the multilayer ceramic capacitors are arranged will be described. Here, the above-mentioned "neighborhood" means a range in which the distance between the two ceramic capacitors is preferably 1.0 [mm] or less. In FIGS. 7 to 9, the sealing resin layer 5 is not shown.

As shown in FIGS. 7A to 7C, the first to third layout patterns LP1 to LP3 belonging to the first layout group are all along the length direction L of the two multilayer ceramic capacitors. These two multilayer ceramic capacitors are arranged so that the axes are located parallel to each other at a distance on the main surface of the wiring board 2.

In the first layout pattern LP1 shown in FIG. 7A, both of the two multilayer ceramic capacitors are mounted in the above-mentioned first mounting mode 10 (H). In this case, one of the pair of widthwise side surfaces 17 of one laminated ceramic capacitor faces one of the pair of widthwise side surfaces 17 of the other laminated ceramic capacitor via the sealing resin layer 5.

When the first layout pattern LP1 is used, a slightly large distortion (see arrow ARL) along the length direction _L generated by one laminated ceramic capacitor in the X-axis direction shown in the figure and the other lamination are performed. Slightly large strains along the length direction _L (see arrow ARL) generated in the ceramic capacitor act to amplify each other's vibrations in the region R, and the vibrations in the X-axis direction become considerably large. Further, in the case of the first layout pattern LP1, a slightly large distortion along the width direction _W generated by one laminated ceramic capacitor in the Y-axis direction shown in the figure (see arrow ARW) and the other. Slightly large strains along the width direction _W (see arrow ARW) that occur in the multilayer ceramic capacitor of No. 1 act to amplify each other's vibrations in the region R, but the vibrations in the Y-axis direction are relatively small. It is suppressed.

In the second layout pattern LP2 shown in FIG. 7B, both of the two multilayer ceramic capacitors are mounted in the second mounting mode 10 (V) described above. In this case, one of the pair of thickness-direction side surfaces 16 of one laminated ceramic capacitor faces one of the pair of thickness-direction side surfaces 16 of the other laminated ceramic capacitor via the sealing resin layer 5.

In the case of the second layout pattern LP2, in the X-axis direction shown in the figure, a slightly large distortion (see arrow ARL) along the length direction _L generated by one laminated ceramic capacitor and the other lamination Slightly large strains along the length direction _L (see arrow ARL) generated in the ceramic capacitor act to amplify each other's vibrations in the region R, and the vibrations in the X-axis direction become considerably large. Further, in the case of the second layout pattern LP2, a significantly large distortion (see arrow ART) along the thickness direction _T generated by one laminated ceramic capacitor in the Y-axis direction shown in the figure and the other. Remarkably large strains along the thickness direction _T (see arrow ART) generated in the multilayer ceramic capacitor of No. 1 act to amplify each other's vibrations in the region R, and the vibrations in the Y-axis direction become extremely large. ..

In the third layout pattern LP3 shown in FIG. 7C, one of the two multilayer ceramic capacitors is mounted in the second mounting mode 10 (V) described above, and the two multilayer ceramic capacitors are mounted. The other of them is mounted in the first mounting mode 10 (H) described above. In this case, one of the pair of thickness-oriented side surfaces 16 of one laminated ceramic capacitor faces one of the pair of width-oriented side surfaces 17 of the other laminated ceramic capacitor via the sealing resin layer 5.

In the case of the third layout pattern LP3, in the X-axis direction shown in the figure, a slightly large distortion (see arrow ARL) along the length direction _L generated by one laminated ceramic capacitor and the other lamination Slightly large strains along the length direction _L (see arrow ARL) generated in the ceramic capacitor act to amplify each other's vibrations in the region R, and the vibrations in the X-axis direction become considerably large. Further, in the case of the third layout pattern LP3, a significantly large distortion (see arrow ART) along the thickness direction _T generated by one laminated ceramic capacitor in the Y-axis direction shown in the figure and the other. Slightly large strains along the width direction _W (see arrow ARW) generated in the multilayer ceramic capacitor of No. 1 act to cancel each other's vibrations in the region R, and the vibrations in the Y-axis direction are considerably small. It is suppressed.

As is clear from the above, among the first to third layout patterns LP1 to LP3 belonging to the first layout group, the third layout pattern LP3, in which the vibration is partially canceled in the region R, suppresses the vibration. It can be said that it is suitable from the viewpoint of

As shown in FIGS. 8A to 8C, the fourth to sixth layout patterns LP4 to LP6 belonging to the second layout group are all along the length direction L of the two multilayer ceramic capacitors. These two multilayer ceramic capacitors are arranged so that the axes are located on the same straight line with each other on the main surface of the wiring board 2.

In the fourth layout pattern LP4 shown in FIG. 8A, both of the two multilayer ceramic capacitors are mounted in the above-described first mounting mode 10 (H). In this case, one of the pair of end faces 15 of one laminated ceramic capacitor faces one of the pair of end faces 15 of the other laminated ceramic capacitor via the sealing resin layer 5.

In the case of the fourth layout pattern LP4, in the X-axis direction shown in the figure, a slightly large distortion (see arrow ARL) along the length direction _L generated by one laminated ceramic capacitor and the other lamination Slightly large strains along the length direction _L (see arrow ARL) generated in the ceramic capacitor act to amplify each other's vibrations in the region R, and the vibrations in the X-axis direction become considerably large. Further, in the case of the fourth layout pattern LP4, a slightly large distortion along the width direction _W generated by one laminated ceramic capacitor in the Y-axis direction shown in the figure (see arrow ARW) and the other Slightly large strains along the width direction _W (see arrow ARW) that occur in the multilayer ceramic capacitor of No. 1 act to amplify each other's vibrations in the region R, but the vibrations in the Y-axis direction are relatively small. It is suppressed.

In the fifth layout pattern LP5 shown in FIG. 8B, both of the two multilayer ceramic capacitors are mounted in the second mounting mode 10 (V) described above. In this case, one of the pair of end faces 15 of one laminated ceramic capacitor faces one of the pair of end faces 15 of the other laminated ceramic capacitor via the sealing resin layer 5.

In the case of the fifth layout pattern LP5, in the X-axis direction shown in the figure, a slightly large distortion (see arrow ARL) along the length direction _L generated by one laminated ceramic capacitor and the other lamination are performed. Slightly large strains along the length direction _L (see arrow ARL) generated in the ceramic capacitor act to amplify each other's vibrations in the region R, and the vibrations in the X-axis direction become considerably large. Further, in the case of the fifth layout pattern LP5, a significantly large distortion (see arrow ART) along the thickness direction _T generated by one laminated ceramic capacitor in the Y-axis direction shown in the figure and the other. Remarkably large strains along the thickness direction _T (see arrow ART) generated in the multilayer ceramic capacitor of No. 1 act to amplify each other's vibrations in the region R, and the vibrations in the Y-axis direction become extremely large. ..

In the sixth layout pattern LP6 shown in FIG. 8C, one of the two multilayer ceramic capacitors is mounted in the second mounting mode 10 (V) described above, and the two multilayer ceramic capacitors are mounted. The other of them is mounted in the first mounting mode 10 (H) described above. In this case, one of the pair of end faces 15 of one laminated ceramic capacitor faces one of the pair of end faces 15 of the other laminated ceramic capacitor via the sealing resin layer 5.

In the case of the sixth layout pattern LP6, in the X-axis direction shown in the figure, a slightly large distortion (see arrow ARL) along the length direction _L generated by one laminated ceramic capacitor and the other lamination Slightly large strains along the length direction _L (see arrow ARL) generated in the ceramic capacitor act to amplify each other's vibrations in the region R, and the vibrations in the X-axis direction become considerably large. Further, in the case of the sixth layout pattern LP6, in the Y-axis direction shown in the figure, a significantly large distortion along the thickness direction _T generated by one laminated ceramic capacitor (see arrow ART) and the other. Slightly large strains along the width direction _W (see arrow ARW) generated in the multilayer ceramic capacitor of No. 1 act to cancel each other's vibrations in the region R, and the vibrations in the Y-axis direction are considerably small. It is suppressed.

As is clear from the above, among the 4th to 6th layout patterns LP4 to LP6 belonging to the 2nd layout group, the 6th layout pattern LP6 in which the vibration is partially canceled in the region R suppresses the vibration. It can be said that it is suitable from the viewpoint of

As shown in FIGS. 9A to 9D, the seventh to tenth layout patterns LP7 to LP10 belonging to the third layout group are all along the length direction L of the two multilayer ceramic capacitors. These two multilayer ceramic capacitors are arranged so that the axes are orthogonal to each other on the main surface of the wiring board 2.

In the seventh layout pattern LP7 shown in FIG. 9A, both of the two multilayer ceramic capacitors are mounted in the first mounting mode 10 (H) described above. In this case, one of the pair of end faces 15 of one laminated ceramic capacitor faces one of the pair of widthwise side surfaces 17 of the other laminated ceramic capacitor via the sealing resin layer 5.

In the case of the 7th layout pattern LP7, a slightly large distortion (see arrow ARW) along the width direction _W generated by one laminated ceramic capacitor in the X-axis direction shown in the figure and the other lamination Although a slightly large strain (see arrow ARL) along the length direction _L generated by the ceramic capacitor acts to amplify each other's vibrations in the region R, the vibrations in the X-axis direction are suppressed to be relatively small. To. Further, in the case of the 7th layout pattern LP7, a slightly large distortion (see arrow ARL) along the length direction _L generated by one laminated ceramic capacitor in the Y-axis direction shown in the figure and the other Slightly large strains along the width direction _W (see arrow ARW) that occur in the monolithic ceramic capacitors of the above act to amplify each other's vibrations in the region R, but the vibrations in the X-axis direction are relatively small. It is suppressed.

In the eighth layout pattern LP8 shown in FIG. 9B, both of the two multilayer ceramic capacitors are mounted in the second mounting mode 10 (V) described above. In this case, one of the pair of end faces 15 of one laminated ceramic capacitor faces one of the pair of side surfaces 16 in the thickness direction of the other laminated ceramic capacitor via the sealing resin layer 5.

In the case of the eighth layout pattern LP8, a significantly large distortion (see arrow ART) along the thickness direction _T generated by one laminated ceramic capacitor in the X-axis direction shown in the figure and the other lamination are performed. Slightly large strains along the length direction _L (see arrow ARL) generated in the ceramic capacitor act to cancel each other's vibrations in the region R, and the vibrations in the X-axis direction are suppressed to be significantly smaller. .. Further, in the case of the eighth layout pattern LP8, in the Y-axis direction shown in the figure, a slightly large distortion along the length direction _L generated by one laminated ceramic capacitor (see arrow ARL) and the other. Remarkably large strains along the thickness direction _T (see arrow ART) generated in the multilayer ceramic capacitor of No. 1 act to cancel each other's vibrations in the region R, and the vibrations in the Y-axis direction are suppressed to be significantly small. Will be done.

In the ninth layout pattern LP9 shown in FIG. 9C, one of the two multilayer ceramic capacitors is mounted in the second mounting mode 10 (V) described above, and the two multilayer ceramic capacitors are mounted. The other of them is mounted in the first mounting mode 10 (H) described above. In this case, one of the pair of end faces 15 of one laminated ceramic capacitor faces one of the pair of widthwise side surfaces 17 of the other laminated ceramic capacitor via the sealing resin layer 5.

In the case of the 9th layout pattern LP9, a significantly large distortion (see arrow ART) along the thickness direction _T generated by one laminated ceramic capacitor in the X-axis direction shown in the figure and the other lamination are performed. Slightly large strains along the length direction _L (see arrow ARL) generated in the ceramic capacitor act to cancel each other's vibrations in the region R, and the vibrations in the X-axis direction are suppressed to be significantly smaller. .. Further, in the case of the 9th layout pattern LP9, in the Y-axis direction shown in the figure, a slightly large distortion along the length direction _L generated by one laminated ceramic capacitor (see arrow ARL) and the other. Slightly large strains along the width direction _W (see arrow ARW) that occur in the multilayer ceramic capacitor of No. 1 act to amplify each other's vibrations in the region R, but the vibrations in the Y-axis direction are relatively small. It is suppressed.

In the tenth layout pattern LP10 shown in FIG. 9D, one of the two multilayer ceramic capacitors is mounted in the first mounting mode 10 (H) described above, and the two multilayer ceramic capacitors are mounted. The other of them is mounted in the second mounting mode 10 (V) described above. In this case, one of the pair of end faces 15 of one laminated ceramic capacitor faces one of the pair of side surfaces 16 in the thickness direction of the other laminated ceramic capacitor via the sealing resin layer 5.

In the case of the tenth layout pattern LP10, a slightly large distortion (see arrow ARW) along the width direction _W generated by one laminated ceramic capacitor in the X-axis direction shown in the figure and the other lamination are performed. Although a slightly large strain (see arrow ARL) along the length direction _L generated by the ceramic capacitor acts to amplify each other's vibrations in the region R, the vibrations in the X-axis direction are suppressed to be relatively small. To. Further, in the case of the tenth layout pattern LP10, a slightly large distortion (see arrow ARL) along the length direction _L generated by one laminated ceramic capacitor in the Y-axis direction shown in the figure and the other Remarkably large strains along the thickness direction _T (see arrow ART) generated in the multilayer ceramic capacitor of No. 1 act to cancel each other's vibrations in the region R, and the vibrations in the Y-axis direction are suppressed to be significantly small. Will be done.

As is clear from the above, among the 7th to 10th layout patterns LP7 to LP10 belonging to the 3rd layout group, the 8th to 10th layout patterns LP8 to LP10 in which the vibration is canceled out at least in a part in the region R are included. It can be said that it is suitable from the viewpoint of suppressing vibration. In particular, in the eighth layout pattern LP8, vibrations cancel out significantly in both the X-axis direction and the Y-axis direction in the region R, and thus this can be said to be particularly suitable from the viewpoint of suppressing vibrations.

On the other hand, for the 7th layout pattern LP7 belonging to the 3rd layout group, although the vibration is not canceled out in the region R, the degree of amplified vibration is relatively small, and the 7th layout pattern LP7 also vibrates. It can be said that it is suitable from the viewpoint of suppressing the above.

In any of the layout patterns belonging to the third layout group, the length directions L of the two multilayer ceramic capacitors are oriented in different directions in the direction along the main surface of the wiring board, so that they are in the length directions L of each other. The slightly large distortion along the line is not related to amplifying the vibration. Further, in any of the layout patterns belonging to the third layout group, the thickness directions T of the two multilayer ceramic capacitors are oriented in different directions from each other, so that a significantly large distortion along the thickness direction T causes vibration. There is no relationship to amplify. Therefore, from the viewpoint of suppressing vibration, it can be said that the layout pattern belonging to the third layout group is a more suitable layout pattern than the layout pattern belonging to the first and second layout groups.

Therefore, based on the above considerations, when two multilayer ceramic capacitors are placed close to each other, one of the pair of end faces 15 of one multilayer ceramic capacitor is a pair of side surfaces (a pair of thicknesses) of the other multilayer ceramic capacitor. It can be said that it is preferable to arrange these two multilayer ceramic capacitors so as to face each other with the sealing resin layer 5 interposed therebetween (including the directional side surface 16 and the pair of widthwise side surfaces 17).

Here, when two multilayer ceramic capacitors are arranged close to each other, it is particularly preferable to adopt the eighth layout pattern LP8 from the viewpoint of suppressing vibration, as described above. Taking this point into consideration, when three or more multilayer ceramic capacitors are arranged in close proximity, two of these multilayer ceramic capacitors are mounted in the second mounting mode 10 (V) according to the layout pattern LP8. Further, it is preferable to mount the remaining one or more multilayer ceramic capacitors in the first mounting mode 10 (H) so as to be close to these two multilayer ceramic capacitors.

With this configuration, the vibrations that could not be offset by the two multilayer ceramic capacitors mounted according to the eighth layout pattern LP8 are further generated by the remaining one or more multilayer ceramic capacitors in the X-axis direction in the region R and in the region R. Since it is possible to cancel each other in both the Y-axis directions, a high vibration suppression effect can be obtained.

Based on the above findings, in the following, in a circuit module including a plurality of monolithic ceramic capacitors, attention will be paid to a group of monolithic ceramic capacitors composed of a plurality of specific monolithic ceramic capacitors included in the plurality of monolithic ceramic capacitors. The circuit module according to the first to twelfth configuration examples in which the generation of vibration is suppressed by applying a characteristic layout to the mounting position of a plurality of multilayer ceramic capacitors included in the ceramic capacitor group will be described in detail.

(First configuration example)
10 and 11 are schematic perspective views and schematic plan views showing the layout of the multilayer ceramic capacitor provided in the circuit module according to the first configuration example based on the present embodiment. Further, FIG. 12 is a schematic cross-sectional view taken along the line XII-XII shown in FIG. 11 of the circuit module shown in FIGS. 10 and 11, and FIG. 13 includes a laminated ceramic capacitor shown in FIGS. 10 to 12. It is a figure which shows the circuit composition example of a circuit. In addition, in FIG. 11, the illustration of the sealing resin layer 5 is omitted.

In this first configuration example, as a plurality of multilayer ceramic capacitors included in the above-mentioned multilayer ceramic capacitor group, the same design specifications (same) that are electrically connected in series or in parallel via a conductive pattern provided on a wiring board. The focus is on two monolithic ceramic capacitors (capacity and same size). The layout pattern of the two multilayer ceramic capacitors in the circuit module according to the first configuration example matches the seventh layout pattern LP7 belonging to the above-mentioned third layout group.

As shown in FIGS. 10 to 13, in the circuit module 1A according to the first configuration example, the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B have a conductive pattern provided on the wiring board 2. They are electrically connected in series or in parallel to each other via a certain land 3 and wirings 6A to 6C, and are electrically connected to the same power source 7 and electrically connected to the ground terminal GND. That is, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are connected in series or in parallel to the same power supply line.

The circuit configuration shown in FIG. 13A shows a case where the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are electrically connected in series. In this case, one of the pair of external electrodes 14 of the first laminated ceramic capacitor 10A and one of the pair of external electrodes 14 of the second laminated ceramic capacitor 10B are electrically connected via the land 3 and the wiring 6C. The other of the pair of external electrodes 14 of the first laminated ceramic capacitor 10A and the power supply 7 are electrically connected via the land 3 and the wiring 6A, and the pair of the second laminated ceramic capacitors 10B are electrically connected. The other of the external electrodes 14 and the ground terminal GND are electrically connected via the land 3 and the wiring 6B.

The circuit configuration shown in FIG. 13B shows a case where the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are electrically connected in parallel. In this case, one of the pair of external electrodes 14 of the first laminated ceramic capacitor 10A, one of the pair of external electrodes 14 of the second laminated ceramic capacitor 10B, and the power supply 7 are connected to the land 3 and the wiring. Electrically connected via 6A, the other of the pair of external electrodes 14 of the first multilayer ceramic capacitor 10A, the other of the pair of external electrodes 14 of the second multilayer ceramic capacitor 10B, and the ground terminal GND. Is electrically connected via the land 3 and the wiring 6B. That is, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are connected in parallel to the same power supply line. In other words, when viewed in an equivalent circuit, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are connected to the same node.

As shown in FIGS. 10 to 12, both the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are mounted according to the first mounting mode 10 (H) described above. That is, the rectangular side surface 16 in the thickness direction having the long side and the short side of each of the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B faces the facing surface 16a facing the main surface of the wiring board 2. It has become.

The facing surfaces 16a of the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B each have a rectangular parallelepiped shape in both the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B, and further, L in the length direction thereof. Is mounted on the wiring board 2 so as to be parallel to the main surface of the wiring board 2, and both have a rectangular shape having a pair of short sides and a pair of long sides.

Here, in the circuit module 1A according to the first configuration example, the direction in which the long side of the facing surface 16a of the first laminated ceramic capacitor 10A extends and the long side of the facing surface 16a of the second laminated ceramic capacitor 10B Is orthogonal to the extending direction, and one of the pair of end faces 15 of the first laminated ceramic capacitor 10A is attached to one of the pair of widthwise side surfaces 17 of the second laminated ceramic capacitor 10B. The first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are mounted on the wiring board 2 so as to face each other.

Preferably, when viewed from the main surface of the wiring board 2, the axis parallel to the length direction L passing through the center of the first laminated ceramic capacitor 10A is configured to penetrate the second laminated ceramic capacitor 10B. Further, preferably, when viewed from the main surface of the wiring board 2, the axis line parallel to the width direction W passing through the center of the second laminated ceramic capacitor 10B is configured to penetrate the first laminated ceramic capacitor 10A. Further, more preferably, the axis parallel to the length direction L passing through the center of the first laminated ceramic capacitor 10A and the axis parallel to the width direction W passing through the center of the second laminated ceramic capacitor 10B coincide with each other. Configure.

Here, the direction parallel to the main surface of the wiring board 2 and orthogonal to the length direction L of the first laminated ceramic capacitor 10A is defined as the X-axis direction, and is parallel to the main surface of the wiring board 2 and the first laminated ceramic. The direction parallel to the length direction L of the capacitor 10A is defined as the Y-axis direction. At this time, the width direction W of the first laminated ceramic capacitor 10A and the length direction L of the second laminated ceramic capacitor 10B face the same X-axis direction, and the length direction L of the first laminated ceramic capacitor 10A and the second. The width direction W of the multilayer ceramic capacitor 10B faces the same Y-axis direction.

In this case, the vibration mode caused by the distortion along the width direction W of the first laminated ceramic capacitor 10A (see the arrow VMA _W shown in FIG. 11) and the length direction L of the second laminated ceramic capacitor 10B. The vibration modes caused by the strain (see the arrow VMB _L shown in FIG. 11) are matched so as to face each other in the same direction along the X-axis direction of the circuit module 1A, and the first laminated ceramic is used. Vibration mode due to distortion along the length direction L of the capacitor 10A (see arrow VMA _L shown in FIG. 11) and vibration mode due to distortion along the width direction W of the second laminated ceramic capacitor 10B (FIG. 11). (Refer to the arrow VMB _W shown in 11) coincides with each other so as to face the same direction along the Y-axis direction of the circuit module 1A.

Therefore, as mentioned in the description column of the 7th layout pattern LP7 belonging to the 3rd layout group described above, it is caused by the distortion generated in the 1st laminated ceramic capacitor 10A and the 2nd laminated ceramic capacitor 10B when the voltage is applied. It is possible to prevent the vibration of the circuit module 1A generated from being extremely amplified. As a result, the generation of noise can be suppressed, and the malfunction of other elements can be prevented.

(Second configuration example)
FIG. 14 is a schematic plan view showing the layout of the multilayer ceramic capacitor provided in the circuit module according to the second configuration example based on the present embodiment, and FIG. 15 is a schematic plan view of the circuit module shown in FIG. It is a schematic cross-sectional view along the XV-XV line shown in. In FIG. 14, the sealing resin layer 5 is not shown.

This second configuration example matches the eighth layout pattern LP8 belonging to the above-mentioned third layout group. Specifically, as shown in FIGS. 14 and 15, in the circuit module 1B according to the second configuration example, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are both described above. 2 It is different from the first configuration example in that it is mounted in the mounting mode 10 (V), and has the same configuration as the first configuration example in other respects.

That is, the rectangular widthwise side surface 17 including the long side and the short side of the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B becomes a facing surface 17a located facing the main surface of the wiring board 2. There is. As a result, one of the pair of end faces 15 of the first laminated ceramic capacitor 10A faces one of the pair of side surfaces 16 in the thickness direction of the second laminated ceramic capacitor 10B via the sealing resin layer 5.

Here, the direction parallel to the main surface of the wiring board 2 and orthogonal to the length direction L of the first laminated ceramic capacitor 10A is defined as the X-axis direction, and is parallel to the main surface of the wiring board 2 and the first laminated ceramic. The direction parallel to the length direction L of the capacitor 10A is defined as the Y-axis direction. At this time, the thickness direction T of the first laminated ceramic capacitor 10A and the length direction L of the second laminated ceramic capacitor 10B face the same X-axis direction, and the length direction L of the first laminated ceramic capacitor 10A and the second. The thickness direction T of the monolithic ceramic capacitor 10B faces the same Y-axis direction.

In this case, the vibration mode caused by the distortion of the first laminated ceramic capacitor 10A along the thickness direction _T (see the arrow VMAT shown in FIG. 14) and along the length direction L of the second laminated ceramic capacitor 10B. The vibration modes caused by the strain (see the arrow VMB _L shown in FIG. 14) are matched so as to face each other in the same direction along the X-axis direction of the circuit module 1B, and the first laminated ceramic is used. Vibration mode due to distortion along the length direction L of the capacitor 10A (see arrow VMA _L shown in FIG. 14) and vibration mode due to distortion along the thickness direction T of the second laminated ceramic capacitor 10B (FIG. 14). (See the arrow VMB _T shown in 14) coincide with each other so as to face the same direction along the Y-axis direction of the circuit module 1B.

Therefore, as mentioned in the description column of the eighth layout pattern LP8 belonging to the third layout group described above, it is caused by the distortion generated in the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B when a voltage is applied. The vibration of the circuit module 1A generated is canceled out in both the X-axis direction and the Y-axis direction. As a result, the generation of noise can be suppressed, and the malfunction of other elements can be prevented.

Further, in the case of the above configuration, one end surface 15 of the first laminated ceramic capacitor 10A and one side surface 16 in the thickness direction of the second laminated ceramic capacitor 10B are arranged to face each other in the Y-axis direction. Therefore, the propagation directions of the vibration modes generated along the Y-axis direction face each other, and the vibration canceling action can be obtained more efficiently.

(Third configuration example)
FIG. 16 is a schematic plan view showing the layout of the multilayer ceramic capacitor provided in the circuit module according to the third configuration example based on the present embodiment, and FIG. 17 is a schematic plan view of the circuit module shown in FIG. It is a schematic cross-sectional view along the line XVII-XVII shown in. In addition, in FIG. 16, the illustration of the sealing resin layer 5 is omitted.

This third configuration example matches the ninth layout pattern LP9 belonging to the above-mentioned third layout group. Specifically, as shown in FIGS. 16 and 17, in the circuit module 1C according to the third configuration example, the first multilayer ceramic capacitor 10A is mounted in the second mounting mode 10 (V) described above. The second multilayer ceramic capacitor 10B is different from the first configuration example in that it is mounted in the first mounting mode 10 (H) described above, and is the same as the first configuration example in other respects. It is configured.

That is, the rectangular side surface 17 in the width direction including the long side and the short side of the first laminated ceramic capacitor 10A is a facing surface 17a located facing the main surface of the wiring board 2, and the second laminated ceramic capacitor. The rectangular side surface 16 in the thickness direction including the long side and the short side of 10B is a facing surface 16a located facing the main surface of the wiring board 2. As a result, one of the pair of end faces 15 of the first laminated ceramic capacitor 10A faces one of the pair of widthwise side surfaces 17 of the second laminated ceramic capacitor 10B via the sealing resin layer 5.

Here, the direction parallel to the main surface of the wiring board 2 and orthogonal to the length direction L of the first laminated ceramic capacitor 10A is defined as the X-axis direction, and is parallel to the main surface of the wiring board 2 and the first laminated ceramic. The direction parallel to the length direction L of the capacitor 10A is defined as the Y-axis direction. At this time, the thickness direction T of the first laminated ceramic capacitor 10A and the length direction L of the second laminated ceramic capacitor 10B face the same X-axis direction, and the length direction L of the first laminated ceramic capacitor 10A and the second. The width direction W of the multilayer ceramic capacitor 10B faces the same Y-axis direction.

In this case, the vibration mode caused by the distortion along the thickness direction _T of the first laminated ceramic capacitor 10A (see the arrow VMAT shown in FIG. 16) and along the length direction L of the second laminated ceramic capacitor 10B. The vibration modes caused by the strain (see the arrow VMB _L shown in FIG. 16) are matched so as to face each other in the same direction along the X-axis direction of the circuit module 1C, and the first laminated ceramic is used. Vibration mode due to distortion along the length direction L of the capacitor 10A (see arrow VMA _L shown in FIG. 16) and vibration mode due to distortion along the width direction W of the second laminated ceramic capacitor 10B (FIG. 16). (Refer to the arrow VMB _W shown in 16) coincides with each other so as to face the same direction along the Y-axis direction of the circuit module 1C.

Therefore, as mentioned in the description column of the 9th layout pattern LP9 belonging to the 3rd layout group described above, it is caused by the distortion generated in the 1st multilayer ceramic capacitor 10A and the 2nd multilayer ceramic capacitor 10B when the voltage is applied. The vibration of the circuit module 1A generated is canceled out in the X-axis direction. As a result, the generation of noise can be suppressed, and the malfunction of other elements can be prevented.

(Fourth configuration example)
FIG. 18 is a schematic plan view showing the layout of the multilayer ceramic capacitor provided in the circuit module according to the fourth configuration example based on the present embodiment, and FIG. 19 is a schematic plan view of the circuit module shown in FIG. It is a schematic cross-sectional view along the XIX-XIX line shown in. In FIG. 18, the sealing resin layer 5 is not shown.

This fourth configuration example matches the tenth layout pattern LP10 belonging to the above-mentioned third layout group. Specifically, as shown in FIGS. 18 and 19, in the circuit module 1D according to the fourth configuration example, the first multilayer ceramic capacitor 10A is mounted in the first mounting mode 10 (H) described above. The second multilayer ceramic capacitor 10B is different from the first configuration example in that it is mounted in the second mounting mode 10 (V) described above, and is the same as the first configuration example in other respects. It is configured.

That is, the rectangular side surface 16 in the thickness direction including the long side and the short side of the first laminated ceramic capacitor 10A is a facing surface 16a located facing the main surface of the wiring board 2, and the second laminated ceramic capacitor. The rectangular side surface 17 in the width direction including the long side and the short side of 10B is a facing surface 17a located facing the main surface of the wiring board 2. As a result, one of the pair of end faces 15 of the first laminated ceramic capacitor 10A faces one of the pair of side surfaces 16 in the thickness direction of the second laminated ceramic capacitor 10B via the sealing resin layer 5.

Here, the direction parallel to the main surface of the wiring board 2 and orthogonal to the length direction L of the first laminated ceramic capacitor 10A is defined as the X-axis direction, and is parallel to the main surface of the wiring board 2 and the first laminated ceramic. The direction parallel to the length direction L of the capacitor 10A is defined as the Y-axis direction. At this time, the width direction W of the first laminated ceramic capacitor 10A and the length direction L of the second laminated ceramic capacitor 10B face the same X-axis direction, and the length direction L of the first laminated ceramic capacitor 10A and the second. The thickness direction T of the monolithic ceramic capacitor 10B faces the same Y-axis direction.

In this case, the vibration mode caused by the distortion along the width direction W of the first laminated ceramic capacitor 10A (see the arrow VMA _W shown in FIG. 18) and the length direction L of the second laminated ceramic capacitor 10B. The vibration modes caused by the strain (see the arrow VMB _L shown in FIG. 18) are matched so as to face each other in the same direction along the X-axis direction of the circuit module 1D, and the first laminated ceramic is used. Vibration mode due to distortion along the length direction L of the capacitor 10A (see arrow VMA _L shown in FIG. 18) and vibration mode due to distortion along the thickness direction T of the second laminated ceramic capacitor 10B (FIG. 18). (See the arrow VMB _T shown in 18) coincide with each other so as to face the same direction along the Y-axis direction of the circuit module 1D.

Therefore, as mentioned in the description column of the tenth layout pattern LP10 belonging to the third layout group described above, it is caused by the distortion generated in the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B when the voltage is applied. The vibration of the circuit module 1A generated is canceled out in the Y-axis direction. As a result, the generation of noise can be suppressed, and the malfunction of other elements can be prevented.

Further, in the case of the above configuration, one end surface 15 of the first laminated ceramic capacitor 10A and one side surface 16 in the thickness direction of the second laminated ceramic capacitor 10B are arranged to face each other in the Y-axis direction. Therefore, the propagation directions of the vibration modes generated along the Y-axis direction face each other, and the vibration canceling action can be obtained more efficiently.

(5th configuration example)
FIG. 20 is a schematic plan view showing the layout of the multilayer ceramic capacitor provided in the circuit module according to the fifth configuration example based on the present embodiment. In FIG. 20, the sealing resin layer 5 is not shown.

In the fifth configuration example, the same design specifications (same) are electrically connected in series or in parallel via a conductive pattern provided on a wiring board as a plurality of multilayer ceramic capacitors included in the above-mentioned multilayer ceramic capacitor group. The focus is on three monolithic ceramic capacitors (capacity and same size). The three multilayer ceramic capacitors in the circuit module according to the fifth configuration example are electrically connected to each other in series or in parallel, as in the case of the first configuration example.

As shown in FIG. 20, in the circuit module 1E according to the fifth configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C are each described in the first mounting mode 10 described above. It is mounted in either (H) or the second mounting mode 10 (V). Specifically, the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, and the third laminated ceramic capacitor 10C have their respective length directions L parallel to the main surface of the wiring board 2, and their respective width directions. It is mounted on the wiring board 2 so that either W or the thickness direction T is parallel to the normal direction (Z-axis direction shown in the figure) of the main surface of the wiring board 2. Further, the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B are arranged so as to be adjacent to each other, and the first laminated ceramic capacitor 10A and the third laminated ceramic capacitor 10C are adjacent to each other. It is arranged so that it is located.

In this configuration, one of the pair of end faces 15 of the first laminated ceramic capacitor 10A is a pair of side surfaces (a pair of thickness direction side surfaces 16 and a pair of width directions) of the second laminated ceramic capacitor 10B. One of the side surfaces (including the side surface 17) is opposed to the sealing resin layer 5 via the sealing resin layer 5, and the other of the pair of end faces 15 of the first laminated ceramic capacitor 10A is the third laminated ceramic capacitor 10C. It faces one of the pair of side surfaces (including the pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17) via the sealing resin layer 5.

Therefore, in the fifth configuration example, the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B located adjacent to each other are the seventh to tenth layout patterns LP7 to LP10 in the above-mentioned third layout group. The first laminated ceramic capacitor 10A and the third laminated ceramic capacitor 10C located adjacent to each other have the same positional relationship as described above, and the seventh to tenth layout patterns LP7 to LP10 in the above-mentioned third layout group are used. It will have a positional relationship like this.

Therefore, by adopting this configuration, the vibration of the circuit module 1E caused by the distortion generated in the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, and the third laminated ceramic capacitor 10C when the voltage is applied is in the region. It can be suppressed in R, and as a result, the generation of noise can be suppressed and the malfunction of other elements can be prevented.

Here, the circuit module 1E is manufactured by aligning the stacking directions of the dielectric layer 12 and the internal electrode layer 13 in each of the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, and the third laminated ceramic capacitor 10C in the same direction. From the viewpoint of suppressing the vibration generated in the circuit module 1E while facilitating the above, for example, referring to FIG. 20, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C are used, respectively. It is preferable to mount the capacitor in the second mounting mode 10 (V) described above.

On the other hand, from the viewpoint of maximally suppressing the vibration generated in the circuit module 1E, for example, with reference to FIG. 20, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are respectively described in the second mounting embodiment 10 (1) described above. It is preferable to mount the third multilayer ceramic capacitor 10C in V) and mount it in the first mounting mode 10 (H) described above.

(6th configuration example)
FIG. 21 is a schematic plan view showing the layout of the multilayer ceramic capacitor provided in the circuit module according to the sixth configuration example based on the present embodiment. In FIG. 21, the sealing resin layer 5 is not shown.

In this sixth configuration example, as a plurality of multilayer ceramic capacitors included in the above-mentioned multilayer ceramic capacitor group, the same design specifications (same) that are electrically connected in series or in parallel via a conductive pattern provided on a wiring board. The focus is on three monolithic ceramic capacitors (capacity and same size). The three multilayer ceramic capacitors in the circuit module according to the sixth configuration example are electrically connected to each other in series or in parallel, as in the case of the first configuration example.

As shown in FIG. 21, in the circuit module 1F according to the sixth configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C are each described in the first mounting mode 10 described above. It is mounted in either (H) or the second mounting mode 10 (V). Specifically, the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, and the third laminated ceramic capacitor 10C have their respective length directions L parallel to the main surface of the wiring board 2, and their respective width directions. It is mounted on the wiring board 2 so that either W or the thickness direction T is parallel to the normal direction (Z-axis direction shown in the figure) of the main surface of the wiring board 2. Further, the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B are arranged so as to be adjacent to each other, and the second laminated ceramic capacitor 10B and the third laminated ceramic capacitor 10C are adjacent to each other. It is arranged so that it is located.

In this configuration, one of the pair of end faces 15 of the first laminated ceramic capacitor 10A is a pair of side surfaces (a pair of thickness direction side surfaces 16 and a pair of width directions) of the second laminated ceramic capacitor 10B. One of the pair of end faces 15 of the third laminated ceramic capacitor 10C is opposed to one of the side surfaces (including the side surface 17) via the sealing resin layer 5, and the second laminated ceramic capacitor 10B is used. It faces the other of the pair of side surfaces (including the pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17) via the sealing resin layer 5.

Therefore, in the sixth configuration example, the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B located adjacent to each other are the seventh to tenth layout patterns LP7 to LP10 in the above-mentioned third layout group. The second laminated ceramic capacitor 10B and the third laminated ceramic capacitor 10C located adjacent to each other have the same positional relationship as described above, and the seventh to tenth layout patterns LP7 to LP10 in the above-mentioned third layout group are used. It will have a positional relationship like this.

Therefore, by adopting this configuration, the vibration of the circuit module 1F caused by the distortion generated in the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, and the third laminated ceramic capacitor 10C when the voltage is applied is in the region. It can be suppressed in R, and as a result, the generation of noise can be suppressed and the malfunction of other elements can be prevented.

Here, the circuit module 1F is manufactured by aligning the stacking directions of the dielectric layer 12 and the internal electrode layer 13 in each of the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, and the third laminated ceramic capacitor 10C in the same direction. From the viewpoint of suppressing the vibration generated in the circuit module 1F while facilitating the above, for example, referring to FIG. 21, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C are used, respectively. It is preferable to mount the capacitor in the second mounting mode 10 (V) described above.

On the other hand, from the viewpoint of maximally suppressing the vibration generated in the circuit module 1F, for example, with reference to FIG. 21, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are respectively described in the second mounting embodiment 10 (1) described above. It is preferable to mount the third multilayer ceramic capacitor 10C in V) and mount it in the first mounting mode 10 (H) described above.

(7th configuration example)
FIG. 22 is a schematic plan view showing the layout of the multilayer ceramic capacitor provided in the circuit module according to the seventh configuration example based on the present embodiment. In FIG. 22, the sealing resin layer 5 is not shown.

This seventh configuration example has the same design specifications (same) that are electrically connected in series or in parallel via a conductive pattern provided on a wiring board as a plurality of multilayer ceramic capacitors included in the above-mentioned multilayer ceramic capacitor group. The focus is on three monolithic ceramic capacitors (capacity and same size). The three multilayer ceramic capacitors in the circuit module according to the seventh configuration example are electrically connected to each other in series or in parallel, as in the case of the first configuration example.

As shown in FIG. 22, in the circuit module 1G according to the seventh configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C are each described in the first mounting mode 10 described above. It is mounted in either (H) or the second mounting mode 10 (V). Specifically, the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, and the third laminated ceramic capacitor 10C have their respective length directions L parallel to the main surface of the wiring board 2, and their respective width directions. It is mounted on the wiring board 2 so that either W or the thickness direction T is parallel to the normal direction (Z-axis direction shown in the figure) of the main surface of the wiring board 2. Further, the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, and the third laminated ceramic capacitor 10C are arranged so as to be adjacent to each other.

In this configuration, one of the pair of end faces 15 of the first laminated ceramic capacitor 10A is a pair of side surfaces (a pair of thickness direction side surfaces 16 and a pair of width directions) of the second laminated ceramic capacitor 10B. One of the pair of end faces 15 of the third laminated ceramic capacitor 10C is opposed to one of the side surfaces (including the side surface 17) via the sealing resin layer 5, and the second laminated ceramic capacitor 10B is used. It faces the above one of the pair of side surfaces (including the pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17) via the sealing resin layer 5.

Therefore, in the seventh configuration example, the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B located adjacent to each other are the seventh to tenth layout patterns LP7 to LP10 in the above-mentioned third layout group. The third laminated ceramic capacitor 10C and the second laminated ceramic capacitor 10B located adjacent to each other have the same positional relationship as described above, and the seventh to tenth layout patterns LP7 to LP10 in the above-mentioned third layout group are used. It will have a positional relationship like this.

Therefore, by adopting this configuration, the vibration of the circuit module 1G caused by the distortion generated in the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, and the third laminated ceramic capacitor 10C when the voltage is applied is in the region. It can be suppressed in R, and as a result, the generation of noise can be suppressed and the malfunction of other elements can be prevented.

Here, the circuit module 1G is manufactured by aligning the stacking directions of the dielectric layer 12 and the internal electrode layer 13 in each of the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, and the third laminated ceramic capacitor 10C in the same direction. From the viewpoint of suppressing the vibration generated in the circuit module 1G while facilitating the above, for example, referring to FIG. 22, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C are used, respectively. It is preferable to mount the capacitor in the second mounting mode 10 (V) described above.

On the other hand, from the viewpoint of maximally suppressing the vibration generated in the circuit module 1G, for example, with reference to FIG. 22, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are respectively described in the second mounting mode 10 (2) described above. It is preferable to mount the third multilayer ceramic capacitor 10C in V) and mount it in the first mounting mode 10 (H) described above.

(8th configuration example)
FIG. 23 is a schematic plan view showing the layout of the multilayer ceramic capacitor provided in the circuit module according to the eighth configuration example based on the present embodiment. In FIG. 23, the sealing resin layer 5 is not shown.

This eighth configuration example is the same design specification (same) that is electrically connected in series or in parallel via a conductive pattern provided on a wiring board as a plurality of multilayer ceramic capacitors included in the above-mentioned multilayer ceramic capacitor group. The focus is on four monolithic ceramic capacitors (capacity and same size). The four monolithic ceramic capacitors in the circuit module according to the eighth configuration example are electrically connected to each other in series or in parallel, as in the case of the first configuration example.

As shown in FIG. 23, in the circuit module 1H according to the eighth configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D are respectively. It is mounted in either the first mounting mode 10 (H) or the second mounting mode 10 (V) described above. Specifically, the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, the third laminated ceramic capacitor 10C, and the fourth laminated ceramic capacitor 10D have their respective length directions L parallel to the main surface of the wiring board 2. At the same time, it is mounted on the wiring board 2 so that either the width direction W or the thickness direction T is parallel to the normal direction of the main surface of the wiring board 2 (Z-axis direction shown in the figure). There is. Further, the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, the third laminated ceramic capacitor 10C, and the fourth laminated ceramic capacitor 10D are arranged so as to be adjacent to each other. More specifically, in the first laminated ceramic capacitor 10A and the third laminated ceramic capacitor 10C, the axes along the length direction L thereof are located parallel to each other on the main surface of the wiring board 2 at a distance. The second laminated ceramic capacitor 10B and the fourth laminated ceramic capacitor 10D are arranged so that their axes along the length direction L are aligned with each other on the main surface of the wiring board 2. It is arranged so that it will be different.

In this configuration, one of the pair of end faces 15 of the first laminated ceramic capacitor 10A is a pair of side surfaces (a pair of thickness direction side surfaces 16 and a pair of width directions) of the second laminated ceramic capacitor 10B. One of the pair of end faces 15 of the third laminated ceramic capacitor 10C is opposed to one of the side surfaces (including the side surface 17) via the sealing resin layer 5, and the fourth laminated ceramic capacitor 10D is used. It faces one of the pair of side surfaces (including the pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17) via the sealing resin layer 5.

Therefore, in the eighth configuration example, the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B located adjacent to each other, and the third laminated ceramic capacitor 10C and the fourth laminated ceramic capacitor 10D located adjacent to each other are used. , Each of which has a positional relationship such as the 7th to 10th layout patterns LP7 to LP10 in the above-mentioned third layout group.

Therefore, by adopting this configuration, it occurs due to the distortion generated in the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D when a voltage is applied. The vibration of the circuit module 1H can be suppressed in the region R, and as a result, the generation of noise can be suppressed and the malfunction of other elements can be prevented.

Here, the stacking directions of the dielectric layer 12 and the internal electrode layer 13 in each of the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, the third laminated ceramic capacitor 10C, and the fourth laminated ceramic capacitor 10D are aligned in the same direction. From the viewpoint of facilitating the manufacture of the circuit module 1H and suppressing the vibration generated in the circuit module 1H, for example, with reference to FIG. 23, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the second It is preferable to mount the three multilayer ceramic capacitors 10C and the fourth multilayer ceramic capacitor 10D in the second mounting mode 10 (V) described above, respectively.

On the other hand, from the viewpoint of maximally suppressing the vibration generated in the circuit module 1H, for example, with reference to FIG. 23, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are respectively described in the second mounting embodiment 10 (1) described above. It is preferable to mount the third laminated ceramic capacitor 10C and the fourth laminated ceramic capacitor 10D according to the first mounting mode 10 (H) described above, respectively.

(9th configuration example)
FIG. 24 is a schematic plan view showing the layout of the multilayer ceramic capacitor provided in the circuit module according to the ninth configuration example based on the present embodiment. In addition, in FIG. 24, the illustration of the sealing resin layer 5 is omitted.

This ninth configuration example is the same design specification (same) that is electrically connected in series or in parallel via a conductive pattern provided on a wiring board as a plurality of multilayer ceramic capacitors included in the above-mentioned multilayer ceramic capacitor group. The focus is on four monolithic ceramic capacitors (capacity and same size). The four monolithic ceramic capacitors in the circuit module according to the ninth configuration example are electrically connected to each other in series or in parallel, as in the case of the first configuration example.

As shown in FIG. 24, in the circuit module 1I according to the ninth configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D are respectively. It is mounted in either the first mounting mode 10 (H) or the second mounting mode 10 (V) described above. Specifically, the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, the third laminated ceramic capacitor 10C, and the fourth laminated ceramic capacitor 10D have their respective length directions L parallel to the main surface of the wiring board 2. At the same time, it is mounted on the wiring board 2 so that either the width direction W or the thickness direction T is parallel to the normal direction of the main surface of the wiring board 2 (Z-axis direction shown in the figure). There is. Further, the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, the third laminated ceramic capacitor 10C, and the fourth laminated ceramic capacitor 10D are arranged so as to be adjacent to each other. More specifically, in the first laminated ceramic capacitor 10A and the third laminated ceramic capacitor 10C, the axes along the length direction L thereof are located parallel to each other on the main surface of the wiring board 2 at a distance. The second laminated ceramic capacitor 10B and the fourth laminated ceramic capacitor 10D are arranged so that their axes along the length direction L are parallel to each other on the main surface of the wiring board 2. It is arranged so that it will be different.

In this configuration, one of the pair of end faces 15 of the first laminated ceramic capacitor 10A is a pair of side surfaces (a pair of thickness direction side surfaces 16 and a pair of width directions) of the second laminated ceramic capacitor 10B. One of the pair of end faces 15 of the second laminated ceramic capacitor 10B is opposed to one of the side surfaces (including the side surface 17) via the sealing resin layer 5, and the third laminated ceramic capacitor 10C is used. It faces one of the pair of side surfaces (including the pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17) via the sealing resin layer 5. Further, one of the pair of end faces 15 of the third laminated ceramic capacitor 10C is one of the pair of side surfaces (including the pair of thickness direction side surfaces 16 and the pair of width direction side surfaces 17) of the fourth laminated ceramic capacitor 10D. One of the pair of end faces 15 of the fourth laminated ceramic capacitor 10D is opposed to one of them via the sealing resin layer 5, and one of the pair of side surfaces (a pair of side surfaces) of the first laminated ceramic capacitor 10A is present. It faces one of the side surfaces 16 in the thickness direction and the pair of side surfaces 17 in the width direction via the sealing resin layer 5.

Therefore, in the ninth configuration example, the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B located adjacent to each other, the second laminated ceramic capacitor 10B and the third laminated ceramic capacitor 10C located adjacent to each other, and adjacent to each other. The third laminated ceramic capacitor 10C and the fourth laminated ceramic capacitor 10D located adjacent to each other, and the fourth laminated ceramic capacitor 10D and the first laminated ceramic capacitor 10A located adjacent to each other are the third of the above-mentioned third layout groups. The 7th to 10th layout patterns have a positional relationship such as LP7 to LP10.

Therefore, by adopting this configuration, it occurs due to the distortion generated in the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D when a voltage is applied. The vibration of the circuit module 1I can be suppressed in the region R, and as a result, the generation of noise can be suppressed and the malfunction of other elements can be prevented.

Here, the stacking directions of the dielectric layer 12 and the internal electrode layer 13 in each of the first laminated ceramic capacitor 10A, the second laminated ceramic capacitor 10B, the third laminated ceramic capacitor 10C, and the fourth laminated ceramic capacitor 10D are aligned in the same direction. From the viewpoint of facilitating the manufacture of the circuit module 1I and suppressing the vibration generated in the circuit module 1I, for example, referring to FIG. 24, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the second It is preferable to mount the three multilayer ceramic capacitors 10C and the fourth multilayer ceramic capacitor 10D in the second mounting mode 10 (V) described above, respectively.

On the other hand, from the viewpoint of maximally suppressing the vibration generated in the circuit module 1I, for example, with reference to FIG. 24, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are respectively described in the second mounting mode 10 (2) described above. It is preferable to mount the third laminated ceramic capacitor 10C and the fourth laminated ceramic capacitor 10D according to the first mounting mode 10 (H) described above, respectively.

(10th configuration example)
FIG. 25 is a schematic plan view showing the layout of the multilayer ceramic capacitor and the IC provided in the circuit module according to the tenth configuration example. In addition, in FIG. 25, the illustration of the sealing resin layer 5 is omitted.

As shown in FIG. 25, the circuit module 1J according to the tenth configuration example is mounted on the wiring board 2, the IC (Integrated Circuit) 20 as an integrated circuit element mounted on the wiring board 2, and the wiring board 2. This includes a capacitor element group consisting of two multilayer ceramic capacitors 10 for decoupling connected to the IC and a sealing resin layer (not shown), and the laminated ceramic for the two decouplings. In the layout of the capacitor 10, any one of the layouts of the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B shown in the circuit modules 1A to 1D according to the first to fourth configuration examples described above (that is, the third layout described above). Any of the 7th to 10th layout patterns LP7 to LP10) of the layout group is applied. Here, the two laminated ceramic capacitors 10 for decoupling have different capacities from each other, and both are embedded on the wiring board 2 by a sealing resin layer (not shown) described above.

More specifically, the IC 20 has a plurality of terminals for performing input / output with an external circuit, and the plurality of terminals include a power supply terminal 21 and a ground terminal 22. The two multilayer ceramic capacitors 10 for decoupling described above are arranged side by side in the vicinity of the IC 20 on the main surface of the wiring board 2 on which the IC 20 is mounted, along a direction parallel to the main surface.

Each of the lands 3 connected to the external electrodes of each of the two decoupling multilayer ceramic capacitors 10 via the bonding member 4 is associated with the power supply terminal 21 and the ground terminal 22 of the IC 20 via wiring. It is connected. As a result, the two monolithic ceramic capacitors 10 for decoupling are electrically connected in parallel between the power supply terminal 21 and the ground terminal 22.

Here, the monolithic ceramic capacitor for decoupling is connected between the power supply line and the ground in order to suppress fluctuations in the power supply voltage and interference between circuits. The decoupling circuit composed of the monolithic ceramic capacitor for the decoupling has a plurality of different capacities between the power supply line and the ground so that a high noise absorption effect can be exhibited in a wide frequency range. It is generally configured by connecting the multilayer ceramic capacitors of the above in parallel electrically. As the IC to which the decoupling circuit is attached, various types are assumed, and examples thereof include a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and an APU (Accelerated Processing Unit).

As described above, in the circuit module 1J according to the tenth configuration example, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B shown in the circuit modules 1A to 1D according to the first to fourth configuration examples. One of the layouts is applied to the layout of the two monolithic ceramic capacitors 10 for decoupling. With such a configuration, the detailed description thereof will be repeated, so that the detailed description thereof will be omitted, but the vibration generated in the region R in which the multilayer ceramic capacitors 10 for these two decouplings are arranged can be suppressed, and as a result. As a result, the generation of noise can be reduced.

Further, as described above, by arranging these two monolithic ceramic capacitors 10 for coupling in the vicinity of the IC 20, not only the size of the circuit module 1J can be prevented from increasing, but also the size of the circuit module 1J is formed on the wiring board 2. The loop inductance of the circuit can also be reduced.

Therefore, by adopting the configuration like the circuit module 1J according to the tenth configuration example to configure the decoupling circuit, it is possible to suppress the generation of noise while preventing the electronic device from becoming large in size. Here, in the tenth configuration example, the case where the two laminated ceramic capacitors 10 for decoupling and the IC 20 are arranged so as to be aligned on the same straight line is illustrated, but the two laminated ceramics for decoupling are illustrated. The direction in which the capacitors 10 are lined up may be arranged so as to intersect the direction in which the IC 20 and the capacitor element group composed of the two monolithic ceramic capacitors 10 for decoupling are lined up.

(11th configuration example)
FIG. 26 is a schematic plan view showing the layout of the multilayer ceramic capacitor and the IC provided in the circuit module according to the eleventh configuration example. In FIG. 26, the sealing resin layer 5 is not shown.

As shown in FIG. 26, the circuit module 1K according to the eleventh configuration example is connected to the wiring board 2, the IC 20 mounted on the wiring board 2, and the IC by being mounted on the wiring board 2. It includes a capacitor element group composed of one multilayer ceramic capacitor 10 for decoupling and a sealing resin layer (not shown), and the layout of the three multilayer ceramic capacitors 10 for decoupling includes the fifth described above. The layout of the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor 10C shown in the circuit module 1E according to the configuration example is applied. Here, the three laminated ceramic capacitors 10 for decoupling are composed of a combination of large-capacity, medium-capacity, and small-capacity capacitors, all of which are wrapped by the above-mentioned sealing resin layer (not shown) on the wiring board 2. It is buried.

More specifically, as in the case of the tenth configuration example described above, the IC 20 has a plurality of terminals for input / output with an external circuit, and the plurality of terminals have a power supply terminal 21. And the ground terminal 22 are included. The three multilayer ceramic capacitors 10 for decoupling described above are arranged side by side in the vicinity of the IC 20 on the main surface of the wiring board 2 on which the IC 20 is mounted, along a direction parallel to the main surface.

Each of the lands 3 connected to the external electrodes of each of the three decoupling multilayer ceramic capacitors 10 via the bonding member 4 is associated with the power supply terminal 21 and the ground terminal 22 of the IC 20 via wiring. It is connected. As a result, the three monolithic ceramic capacitors 10 for decoupling are electrically connected in parallel between the power supply terminal 21 and the ground terminal 22.

As described above, in the circuit module 1K according to the eleventh configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor shown in the circuit module 1E according to the fifth configuration example are shown. The layout of 10C is applied to the layout of the three monolithic ceramic capacitors 10 for decoupling. With such a configuration, the detailed description thereof will be repeated and will be omitted, but the vibration generated in the region R in which the multilayer ceramic capacitors 10 for these three decouplings are arranged can be suppressed, and as a result. As a result, the generation of noise can be reduced.

Further, as described above, by arranging these three monolithic ceramic capacitors 10 for inductance in the vicinity of the IC 20, not only the size of the circuit module 1K can be prevented from being increased, but also the circuit module 1K is formed on the wiring board 2. The loop inductance of the circuit can also be reduced.

Therefore, by adopting a configuration such as the circuit module 1K according to the eleventh configuration example to configure the decoupling circuit, it is possible to suppress the generation of noise while preventing the increase in size of the electronic device. Here, in the eleventh configuration example, the case where the three laminated ceramic capacitors 10 for decoupling and the IC 20 are arranged so as to be aligned on the same straight line is illustrated, but the three laminated ceramics for decoupling are illustrated. The direction in which the capacitors 10 are lined up may be arranged so as to intersect the direction in which the IC 20 and the capacitor element group composed of the three monolithic ceramic capacitors 10 for decoupling are lined up.

(12th configuration example)
FIG. 27 is a schematic plan view showing the layout of the multilayer ceramic capacitor and the IC provided in the circuit module according to the twelfth configuration example. In addition, in FIG. 27, the illustration of the sealing resin layer 5 is omitted.

As shown in FIG. 27, the circuit module 1L according to the twelfth configuration example is connected to the wiring board 2, the IC 20 mounted on the wiring board 2, and the IC by being mounted on the wiring board 2. It includes a capacitor element group composed of one multilayer ceramic capacitor 10 for decoupling and a sealing resin layer (not shown), and the layout of the four multilayer ceramic capacitors 10 for decoupling includes the ninth described above. The layout of the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, the third multilayer ceramic capacitor 10C, and the fourth multilayer ceramic capacitor 10D shown in the circuit module 1I according to the configuration example is applied. Here, the four laminated ceramic capacitors 10 for decoupling are composed of a combination of large-capacity, medium-capacity, and small-capacity capacitors, and the large-capacity capacitor is supported by two laminated ceramic capacitors 10 having the same capacity. The medium-capacity and small-capacity capacitors are each supported by one monolithic ceramic capacitor 10. The four monolithic ceramic capacitors 10 for decoupling are all embedded on the wiring board 2 by a sealing resin layer (not shown) described above.

More specifically, as in the case of the tenth configuration example described above, the IC 20 has a plurality of terminals for input / output with an external circuit, and the plurality of terminals have a power supply terminal 21. And the ground terminal 22 are included. The four multilayer ceramic capacitors 10 for decoupling described above are arranged side by side in the vicinity of the IC 20 on the main surface of the wiring board 2 on which the IC 20 is mounted, along a direction parallel to the main surface.

Each of the lands 3 connected to the external electrodes of each of the four decoupling multilayer ceramic capacitors 10 via the bonding member 4 is associated with the power supply terminal 21 and the ground terminal 22 of the IC 20 via wiring. It is connected. As a result, the four monolithic ceramic capacitors 10 for decoupling are electrically connected in parallel between the power supply terminal 21 and the ground terminal 22.

As described above, in the circuit module 1L according to the twelfth configuration example, the first multilayer ceramic capacitor 10A, the second multilayer ceramic capacitor 10B, and the third multilayer ceramic capacitor shown in the circuit module 1I according to the ninth configuration example. The layout of the 10C and the fourth multilayer ceramic capacitor 10D is applied to the layout of the four multilayer ceramic capacitors 10 for decoupling. With such a configuration, the detailed description thereof will be repeated, so that the detailed description thereof will be omitted, but the vibration generated in the region R in which the multilayer ceramic capacitors 10 for these four decouplings are arranged can be suppressed, and as a result. As a result, the generation of noise can be reduced.

Further, as described above, by arranging these four monolithic ceramic capacitors 10 for inductance in the vicinity of the IC 20, not only the size of the circuit module 1L can be prevented from increasing, but also the size of the circuit module 1L is formed on the wiring board 2. The loop inductance of the circuit can also be reduced.

Therefore, by adopting a configuration like the circuit module 1L according to the twelfth configuration example to configure the decoupling circuit, it is possible to suppress the generation of noise while preventing the electronic device from becoming large in size.

(Verification test)
Hereinafter, the verification test conducted to confirm the effect of the present invention will be described. As a verification test, by changing the mounting layout of the laminated ceramic capacitor on the wiring board and changing the mounting mode of the laminated ceramic capacitor on the wiring board, the sound pressure level of the noise generated when the voltage is applied can be adjusted. The first and second verification tests were carried out to verify whether such changes occur.

(1st verification test)
FIG. 28 is a diagram showing the mounting layout of the multilayer ceramic capacitors according to Comparative Examples 1 and 2 and Examples 1 and 2 verified in the first verification test. In addition, in FIG. 28, the illustration of the sealing resin layer is omitted. In the first verification test, a circuit module to which the mounting layout of the monolithic ceramic capacitor shown in FIGS. 28 (A) to 28 (D) was applied was prepared as a sample, and a voltage was actually applied to each of these samples. The sound pressure level of the noise generated at that time was actually measured.

Of the samples prepared in the first verification test, the sample according to Comparative Example 1 (see FIG. 28 (A)) and the sample according to Example 1 (see FIG. 28 (C)) are both included in the sample. The two monolithic ceramic capacitors 10 are mounted according to the first mounting mode 10 (H) described above, and the sample according to Comparative Example 2 (see FIG. 28B) and the sample according to Example 2 (FIG. 2). 28 (D)) is a mounting of the two multilayer ceramic capacitors 10 included in the sample in the second mounting mode 10 (V) described above.

As shown in FIG. 28 (A), the mounting layout according to Comparative Example 1 is the fourth layout pattern LP4 of the second layout group described above, and the length direction L of the two multilayer ceramic capacitors 10 is L. It is mounted so as to match the X-axis direction of the wiring board 2 and the width direction W of the two multilayer ceramic capacitors 10 to match the Y-axis direction of the wiring board 2.

As shown in FIG. 28B, the mounting layout according to Comparative Example 2 is the fifth layout pattern LP5 of the second layout group described above, and the length direction L of the two multilayer ceramic capacitors 10 is L. It is mounted so as to match the X-axis direction of the wiring board 2 and the thickness direction T of the two multilayer ceramic capacitors 10 to match the Y-axis direction of the wiring board 2.

As shown in FIG. 28C, the mounting layout according to the first embodiment is the seventh layout pattern LP7 (that is, the mounting layout as in the first configuration example) of the third layout group described above. The width direction W of one multilayer ceramic capacitor 10 and the length direction L of the other multilayer ceramic capacitor 10 match the X-axis direction of the wiring board 2, and the length direction L of one of the multilayer ceramic capacitors 10 It is mounted so that the width direction W of the other multilayer ceramic capacitor 10 coincides with the Y-axis direction of the wiring board 2. One of the pair of axial end faces of the one laminated ceramic capacitor 10 faces one of the pair of widthwise end faces of the other laminated ceramic capacitor 10 via the sealing resin layer. ..

As shown in FIG. 28 (D), the mounting layout according to the second embodiment is the eighth layout pattern LP8 (that is, the mounting layout as in the second configuration example) of the third layout group described above. The thickness direction T of one laminated ceramic capacitor 10 and the length direction L of the other laminated ceramic capacitor 10 match the X-axis direction of the wiring board 2, and the length direction L of the one laminated ceramic capacitor 10 It is mounted so that the thickness direction T of the other multilayer ceramic capacitor 10 coincides with the Y-axis direction of the wiring board 2. One of the pair of axial end faces of the one laminated ceramic capacitor 10 faces one of the pair of thickness direction end faces of the other laminated ceramic capacitor 10 via the sealing resin layer. ..

The monolithic ceramic capacitors 10 used in Comparative Examples 1 and 2 and Examples 1 and 2 all had the same design specifications. More specifically, the external dimensions of the multilayer ceramic capacitor 10 in the length direction L, the external dimensions in the width direction W, and the external dimensions in the thickness direction T are 1.0 [mm] × 0.5 [mm] × 0.5. It is [mm] and the capacitance is 2.2 [μF]. Further, in Comparative Examples 1 and 2 and Examples 1 and 2, a plurality of multilayer ceramic capacitors 10 were all electrically connected in parallel. As the wiring board 2, a glass epoxy board having a thickness of 0.8 [mm] is used, and each of the plurality of laminated ceramic capacitors 10 has a thickness of 0.8 [mm] as the sealing resin layer 5. It was embedded with an epoxy resin layer.

FIG. 29 is a schematic diagram showing a method of measuring the sound pressure level of noise in the first verification test. As shown in FIG. 29, when actually measuring the sound pressure level of noise, the sample S is installed in the anechoic box 200, and in this state, the AC voltage of 2 [Vpp] is 4.5 to the multilayer ceramic capacitor 10. It was applied at a frequency in the range of [kHz] to 5.0 [kHz], and the maximum value of the noise generated at that time was measured.

To measure the sound pressure level of noise, the sound collecting microphone 210 is placed facing the sample S in the soundless box 200, and the sound emitted from the sample S is collected by the sound collecting microphone 210 and the sound collecting meter 220. The sound was made, and based on this, the sound pressure level was analyzed using the FFT analyzer 230.

When measuring the noise pressure level, the noise pressure level due to vibration along the X-axis direction of the wiring board 2 and the noise sound pressure level due to vibration along the Y-axis direction of the wiring board 2 are determined. As the wiring board 2 in each sample, a board having a rectangular shape including a long side and a short side was used so that it could be measured individually. That is, in each of Comparative Examples 1 and 2 and Examples 1 and 2, in the direction of the long side of the wiring board 2 having a rectangular shape for measuring the sound pressure level of noise due to vibration along the X-axis direction. Prepared ones that match the X-axis direction and the size of the mounting area of the multilayer ceramic capacitor 10 in the Y-axis direction and the length in the short side direction of the wiring board 2 having a rectangular shape, and along the Y-axis direction. For measuring the sound pressure level of noise due to vibration, the Y-axis direction is matched with the long side direction of the wiring board 2 having a rectangular shape, and the size and rectangular shape of the mounting area of the laminated ceramic capacitor 10 in the X-axis direction. It was decided to prepare ones that match the length in the short side direction of the wiring board 2 having the above, and to measure the sound pressure level of noise for each of them.

FIG. 30 is a graph showing the results of the first verification test. In the graph shown in FIG. 30, the horizontal axis represents the sound pressure level [dB] of noise due to vibration along the X-axis direction, and the vertical axis represents the sound pressure level [dB] of noise due to vibration along the Y-axis direction. ] Is represented.

As shown in FIG. 30, in the relationship between Comparative Example 1 and Examples 1 and 2, in Examples 1 and 2 to which the present invention is applied, the X-axis is compared with Comparative Example 1 to which the present invention is not applied. It was confirmed that the sound pressure level of noise was significantly reduced in the direction, and in the relationship between Comparative Example 2 and Examples 1 and 2, the present invention was applied in Examples 1 and 2 to which the present invention was applied. It was confirmed that the sound pressure level of noise was significantly reduced in both the X-axis direction and the Y-axis direction as compared with Comparative Example 2 which was not performed. In particular, in the relationship between Comparative Example 2 and Examples 1 and 2, in Examples 1 and 2 to which the present invention is applied, noise noise is heard in the Y-axis direction as compared with Comparative Example 2 to which the present invention is not applied. The pressure level is significantly reduced.

Further, in the relationship between Example 1 and Example 2, in Example 2 to which the present invention is applied, noise is generated in both the X-axis direction and the Y-axis direction as compared with Example 1 to which the present invention is applied. It was confirmed that the sound pressure level was significantly reduced.

Based on the first verification test described above, it can be said that it has been experimentally confirmed that the transmission of vibration is suppressed and the noise can be reduced as a result by applying the present invention.

(2nd verification test)
FIG. 31 is a diagram showing the mounting layout of the multilayer ceramic capacitors according to Comparative Example 3 and Examples 3 and 4 verified in the second verification test. In addition, in FIG. 31, the illustration of the sealing resin layer is omitted. In the second verification test, a circuit module to which the mounting layout of the multilayer ceramic capacitor shown in FIGS. 31 (A) to 31 (C) was applied was prepared as a sample, and a voltage was actually applied to each of these samples. The sound pressure level of the noise generated at that time was actually measured.

The samples prepared in the second verification test are all three multilayer ceramic capacitors included in the sample mounted in the above-mentioned second mounting mode 10 (V).

As shown in FIG. 31 (A), in the mounting layout according to Comparative Example 3, the length direction L of the three laminated ceramic capacitors 10 matches the X-axis direction of the wiring board 2, and the three laminated ceramic capacitors It is mounted so that the width direction W of 10 coincides with the Y-axis direction of the wiring board 2. The length L of the three multilayer ceramic capacitors 10 is configured to be located on the same straight line with each other.

As shown in FIG. 31B, the mounting layout according to the third embodiment is the same as that of the fifth configuration example, and the one multilayer ceramic capacitor 10 remains L in the length direction 2 The thickness direction T of the laminated ceramic capacitors 10 matches the X-axis direction of the wiring board 2, and the thickness direction T of the one laminated ceramic capacitor 10 and the length direction L of the two laminated ceramic capacitors 10. Is mounted so as to match the Y-axis direction of the wiring board 2. One of the pair of axial end faces of the one laminated ceramic capacitor 10 is sealed in one of the pair of thickness direction end faces of one of the two laminated ceramic capacitors 10. The other of the pair of axial end faces of the one laminated ceramic capacitor 10 facing each other via the resin layer is the pair of thicknesses of the remaining one of the two laminated ceramic capacitors 10. It faces one of the directional end faces via a sealing resin layer.

As shown in FIG. 31C, the mounting layout according to the fourth embodiment is the same as that of the seventh configuration example, and the two multilayer ceramic capacitors 10 have a thickness direction T and the remaining one. The length direction L of the multilayer ceramic capacitor 10 matches the X-axis direction of the wiring board 2, and the length direction L of the two multilayer ceramic capacitors 10 and the thickness direction T of the one multilayer ceramic capacitor 10 Is mounted so as to match the Y-axis direction of the wiring board 2. It should be noted that one of the pair of axial end faces of each of the two laminated ceramic capacitors 10 has a sealing resin layer on one of the pair of thickness direction end faces of the one laminated ceramic capacitor 10. Facing via.

The monolithic ceramic capacitors 10 used in Comparative Examples 3 and 3 and 4 had the same design specifications. More specifically, the external dimensions of the multilayer ceramic capacitor 10 in the length direction L, the external dimensions in the width direction W, and the external dimensions in the thickness direction T are 1.0 [mm] × 0.5 [mm] × 0.5. It is [mm] and the capacitance is 2.2 [μF]. Further, in Comparative Example 3 and Examples 3 and 4, a plurality of multilayer ceramic capacitors 10 were all electrically connected in parallel. Further, a glass epoxy board having a thickness of 0.8 [mm] is used as the wiring board 2, and the plurality of laminated ceramic capacitors 10 all have a thickness of 0.8 [mm] as the sealing resin layer 5. It was embedded with an epoxy resin layer. In the second verification test, the sound pressure level of the noise generated in the sample was actually measured by using the same measurement method as the measurement method of the noise pressure level shown in the first verification test described above.

FIG. 32 is a graph showing the results of the second verification test. In the graph shown in FIG. 32, the horizontal axis represents the sound pressure level [dB] of noise due to vibration along the X-axis direction, and the vertical axis represents the sound pressure level [dB] of noise due to vibration along the Y-axis direction. ] Is represented.

As shown in FIG. 32, in the relationship between Comparative Example 3 and Examples 3 and 4, in Examples 3 and 4 to which the present invention is applied, the Y-axis is compared with Comparative Example 3 to which the present invention is not applied. It was confirmed that the sound pressure level of noise was significantly reduced in the direction. In particular, in the relationship between Comparative Example 3 and Example 3, in Example 3 to which the present invention is applied, the sound pressure level of noise in the Y-axis direction is much higher than that in Comparative Example 3 to which the present invention is not applied. It is significantly reduced.

Based on the second verification test described above, it can be said that it has been experimentally confirmed that the transmission of vibration can be suppressed and the noise can be reduced as a result by applying the present invention.

(Third verification test)
FIG. 33 is a diagram showing a mounting layout of the multilayer ceramic capacitors according to Examples 5 to 8 verified in the third verification test. FIG. 34 is a diagram showing a mounting layout of the multilayer ceramic capacitor according to Examples 9 and 10 verified in the third verification test. In addition, in FIGS. 33 and 34, the illustration of the sealing resin layer is omitted. In the third verification test, a circuit module to which the mounting layout of the multilayer ceramic capacitor shown in FIGS. 33 (A) to 33 (D) and FIGS. 34 (A) and 34 (B) was applied was prepared as a sample, and these samples were prepared. A voltage was actually applied to each of the above, and the sound pressure level of the noise generated at that time was actually measured.

Among the samples prepared in the third verification test, the sample according to Example 5 (see FIG. 33 (A)), the sample according to Example 8 (see FIG. 33 (D)), and the sample according to Example 9 (see FIG. 33 (D)). In both the sample according to FIG. 34 (A) and the sample according to the tenth embodiment (see FIG. 34 (B)), two of the four monolithic ceramic capacitors 10 included in the sample are mounted in the first mounting mode described above. It is mounted in 10 (H), and the remaining two are mounted in the second mounting mode 10 (V) described above. In the sample according to the sixth embodiment (see FIG. 33B), the four multilayer ceramic capacitors 10 included in the sample are mounted in the second mounting mode 10 (V) described above. In the sample according to the seventh embodiment (see FIG. 33C), the four multilayer ceramic capacitors 10 included in the sample are mounted in the above-mentioned first mounting mode 10 (H).

As shown in FIGS. 33 (A) to 33 (D), the mounting layout according to the fifth to eighth embodiments is the same as the ninth configuration example shown in FIG. 24.

As shown in FIGS. 24 and 33 (A), in the mounting layout according to the fifth embodiment, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are mounted in the second mounting mode 10 (V). , The third multilayer ceramic capacitor 10C and the fourth multilayer ceramic capacitor 10D are mounted in the first mounting mode 10 (H).

As shown in FIGS. 24 and 33 (B), in the mounting layout according to the sixth embodiment, the first laminated ceramic capacitor 10A to the fourth laminated ceramic capacitor 10D are mounted in the second mounting mode 10 (V). ..

As shown in FIGS. 24 and 33 (C), in the mounting layout according to the seventh embodiment, the first laminated ceramic capacitor 10A to the fourth laminated ceramic capacitor 10D are mounted in the first mounting mode 10 (H). ..

As shown in FIGS. 24 and 33 (D), in the mounting layout according to the eighth embodiment, the second laminated ceramic capacitor 10B and the fourth laminated ceramic capacitor 10D are mounted in the second mounting mode 10 (V). , The first multilayer ceramic capacitor 10A and the third multilayer ceramic capacitor 10C are mounted in the first mounting mode 10 (H).

As shown in FIG. 34 (A), the mounting layout according to the ninth embodiment is the mounting layout as in the eighth configuration example shown in FIG. 23. As shown in FIGS. 23 and 34 (A), in the mounting layout according to the ninth embodiment, the first multilayer ceramic capacitor 10A and the second multilayer ceramic capacitor 10B are mounted in the second mounting mode 10 (V). , The third multilayer ceramic capacitor 10C and the fourth multilayer ceramic capacitor 10D are mounted in the first mounting mode 10 (H).

As shown in FIG. 34 (B), in the mounting layout according to the tenth embodiment, the relationship between the first configuration example shown in FIG. 11 and the second configuration example shown in FIG. 14 is related to the fourth configuration example shown in FIG. It is an implementation layout that is combined so that it holds true. As shown in FIG. 34 (B), in the mounting layout according to the tenth embodiment, the first laminated ceramic capacitor 10A and the second laminated ceramic capacitor 10B are mounted in the second mounting mode 10 (V), and the third The multilayer ceramic capacitor 10C and the fourth multilayer ceramic capacitor 10D are mounted in the first mounting mode 10 (H).

The monolithic ceramic capacitors 10 used in Examples 5 to 10 all had the same design specifications. More specifically, the external dimensions of the multilayer ceramic capacitor 10 in the length direction L, the external dimensions in the width direction W, and the external dimensions in the thickness direction T are 1.0 [mm] × 0.5 [mm] × 0.5. It is [mm] and the capacitance is 2.2 [μF]. Further, in Examples 5 to 8, a plurality of multilayer ceramic capacitors 10 were all electrically connected in parallel. Further, a glass epoxy board having a thickness of 0.8 [mm] is used as the wiring board 2, and the plurality of laminated ceramic capacitors 10 all have a thickness of 0.8 [mm] as the sealing resin layer 5. It was embedded with an epoxy resin layer. In the third verification test, the sound pressure level of the noise generated in the sample was actually measured by using the same measurement method as the measurement method of the noise pressure level shown in the first verification test described above.

FIG. 35 is a graph showing the results of the third verification test. In the graph shown in FIG. 35, the horizontal axis represents the sound pressure level [dB] of noise due to vibration along the X-axis direction, and the vertical axis represents the sound pressure level [dB] of noise due to vibration along the Y-axis direction. ] Is represented.

As shown in FIG. 35, in the relationship between Examples 5, 9 and 10 and Examples 6, 7 and 8, in Examples 5, 9 and 10 are noise sounds as compared with Examples 6, 7 and 8. It was confirmed that the pressure level was significantly reduced. However, also in Examples 6, 7 and 8, four monolithic ceramic capacitors 10 are arranged as compared with the sound pressure level of noise shown in FIG. 32 of Comparative Example 3 in which three monolithic ceramic capacitors 10 are arranged. Despite this, the sound pressure level of noise was reduced.

Based on the third verification test described above, it can be said that it has been experimentally confirmed that the transmission of vibration can be suppressed and the noise can be reduced as a result by applying the present invention.

In some of the first to twelfth configuration examples based on the above-described embodiment of the present invention, the monolithic ceramic capacitor mounted in the first mounting mode 10 (H) described above and the second mounting mode described above are used. An example is shown in which a monolithic ceramic capacitor mounted at 10 (V) is mixed. However, depending on whether the mounting mode of the monolithic ceramic capacitor is the first mounting mode 10 (H) described above or the second mounting mode 10 (V) described above, the monolithic ceramic capacitor prepared at the time of mounting is used. Is different. Therefore, in order to facilitate the preparation of the multilayer ceramic capacitor, the mounting mode of the plurality of multilayer ceramic capacitors mounted on the circuit module is either the first mounting mode 10 (H) or the second mounting mode 10 (V). It is preferable to adopt a configuration example arranged on one side.

Further, the layout of the multilayer ceramic capacitor shown in the circuit module according to the first to twelfth configuration examples based on the above-described embodiment of the present invention reduces noise without being limited by the capacity and size of the multilayer ceramic capacitor. It is a layout that can be done. However, since the sound pressure level of noise usually tends to increase as the capacity of the monolithic ceramic capacitor increases, the present invention has a capacity of at least one of the monolithic ceramic capacitors assembled in the circuit module. It can be suitably applied when it is [μF] or more, and it can be particularly preferably applied when it is 10 [μF] or more.

Further, in the tenth to twelfth configuration examples based on the above-described embodiment of the present invention, the case where the present invention is applied to the multilayer ceramic capacitor group constituting the decoupling circuit is exemplified, but the present invention is described. Of course, it can also be applied to a group of multilayer ceramic capacitors included in circuits of other applications connected to a line containing an audible frequency component (20 [Hz] to 20 [kHz]) where voltage fluctuations can occur.

Further, in the first to ninth configuration examples based on the above-described embodiment of the present invention, a plurality of multilayer ceramic capacitors electrically connected in series or in parallel have the same design specifications (same capacity and same size). ), But these plurality of multilayer ceramic capacitors may have different design specifications.

Further, as described above, the present invention is not limited to the mounting structure of the laminated ceramic capacitor as exemplified in the above-described embodiment of the present invention, and the present invention is not limited to the laminated metallized film capacitor. It can also be applied to the mounting structure of other types of capacitor elements represented.

Here, as an example to which the present invention can be suitably applied, one capacitor element is substituted with two or more capacitor elements, and the two substituted capacitor elements are electrically connected in parallel. The above is an example of applying the present invention. In this case, not only the vibration generated in the circuit module can be reduced by substituting with a capacitor element having a smaller capacity and a smaller size, but also the vibration of the circuit module can be suppressed by the vibration suppressing effect which is the effect of the present invention described above. Can be further reduced, and as a result, significant noise reduction becomes possible. For example, by substituting a capacitor element having a capacitance of 10 [μF] with two capacitor elements having a capacitance of 4.7 [μF], it is possible to significantly reduce noise without significantly increasing the mounting area. Become.

Further, the characteristic configurations shown in the first to twelfth configuration examples based on the above-described embodiment of the present invention can be naturally combined with each other as long as the gist of the present invention is not deviated.

As described above, the above-described embodiment disclosed this time is an example in all respects and is not limiting. The technical scope of the present invention is defined by the scope of claims and includes all modifications within the meaning and scope equivalent to the description of the scope of claims.

1A to 1L circuit module, 2 wiring board, 3 lands, 4 bonding members, 5 sealing resin layer, 6A to 6C wiring, 7 power supply, 10, 10A to 10D multilayer ceramic capacitor, 11 laminate, 12 dielectric layer, 13 Internal electrode layer, 14 external electrodes, 15 end face, 16 thickness direction side surface, 16a facing surface, 17 width direction side surface, 17a facing surface, 18 corners, 20 IC, 21 power supply terminal, 22 ground terminal, 200 soundless box, 210 Sound collector microphone, 220 sound collector, 230 FFT analyzer.

Claims (1)

A first capacitor element, a second capacitor element, and a third capacitor element including a rectangular parallelepiped-shaped laminate including dielectric layers and internal electrode layers alternately laminated along the stacking direction.
A wiring board including a main surface on which the first capacitor element, the second capacitor element, and the third capacitor element are mounted, and
A mounting structure of a capacitor element including the first capacitor element, the second capacitor element, and a sealing resin layer for embedding the third capacitor element.
The laminated body has a width direction orthogonal to the laminating direction and a length direction orthogonal to each of the laminating direction and the width direction.
The first capacitor element, the second capacitor element, and the third capacitor element are electrically connected in series or in parallel via a conductive pattern provided on the wiring board.
The surfaces of the first capacitor element, the second capacitor element, and the third capacitor element facing the wiring board have short sides and long sides.
Each of the first capacitor element, the second capacitor element, and the third capacitor element is relative to a pair of end faces located relative to each other in the direction in which the long side extends and in the direction in which the short side extends. It has a pair of side surfaces positioned so as to be spaced apart from each other on the outer surface of the laminated body, and has a pair of external electrodes.
Each of the first capacitor element, the second capacitor element, and the external electrode included in the third capacitor element is a bonding member conductive to a land provided on the wiring board corresponding to each of the external electrodes. Each is joined via
One of the pair of end faces of the first capacitor element, the pair of end faces of the second capacitor element, and the pair of end faces of the third capacitor element is the pair of the first capacitor element. The side surface, the pair of side surfaces of the second capacitor element, and any one of the pair of side surfaces of the third capacitor element face each other via the sealing resin layer.
The remaining one of the pair of end faces of the first capacitor element, the pair of end faces of the second capacitor element, and the pair of end faces of the third capacitor element is the surface of the first capacitor element. The pair of side surfaces, the pair of side surfaces of the second capacitor element, and the pair of side surfaces of the third capacitor element face each other via the sealing resin layer.
One of the pair of end faces of the first capacitor element and one of the pair of end faces of the third capacitor element are sealed on one of the pair of side surfaces of the second capacitor element. Facing each other via the waterproof resin layer ,
The stacking direction of the first capacitor element and the stacking direction of the second capacitor element are both oriented along the main surface of the wiring board.
The stacking direction of the third capacitor element is oriented so as not to follow the main surface of the wiring board.
A mounting structure for a capacitor element , wherein the length direction of each of the first capacitor element, the second capacitor element, and the third capacitor element is oriented along the main surface of the wiring board .

Images