JP2014183173A - Circuit board and mounting method for capacitor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board that is able to reduce noise while preventing thickness increase.SOLUTION: In a circuit board 1A, a plurality of multilayer ceramic capacitors 10A1, 10A2 of approximately rectangular parallelepiped shape are mounted on a wiring board 2. The multilayer ceramic capacitors 10A1, 10A2 are arranged adjacent to each other along a direction parallel to the principal surface of the wiring board 2. The respective directions in which the opposite faces of the multilayer ceramic capacitors 10A1, 10A2 are distorted during the application of voltage thereto are opposite to each other. The total of the amounts of distortion that occur in the multilayer ceramic capacitors 10A1, 10A2 is always almost constant in the direction in which the multilayer ceramic capacitors 10A1, 10A2 are arranged.

Description

  The present invention relates to a circuit board in which a plurality of substantially rectangular parallelepiped capacitor elements are mounted on a wiring board, and a method of mounting a capacitor element when mounting a plurality of substantially rectangular parallelepiped capacitor elements on a wiring board.

In recent years, with the increase in performance of electronic devices, the capacity of multilayer ceramic capacitors as electronic components has been increasing. In a large-capacity multilayer ceramic capacitor, a ceramic material having a high dielectric constant such as barium titanate (BaTiO ₃ ) is used as a dielectric material.

  Since these high dielectric constant ceramic materials have piezoelectricity and electrostrictive properties, in a multilayer ceramic capacitor including a dielectric made of a high dielectric constant ceramic material, when a voltage is applied, it is mechanical. Distortion will occur.

  Therefore, when an AC voltage or a DC voltage on which an AC component is superimposed is applied to a large-capacity multilayer ceramic capacitor mounted on a wiring board, vibration is generated due to mechanical distortion generated in the ceramic material. As a result, the vibration is propagated to the wiring board, causing the circuit board to vibrate.

  Here, when the circuit board vibrates at a frequency of 20 [Hz] to 20 [kHz], which is an audible frequency range, due to the propagated vibration, so-called “acoustic noise” is generated. Become.

  Various techniques for reducing the noise have been proposed, and one of them is disclosed in Japanese Patent Laid-Open No. 2000-233203 (Patent Document 1). In the technique disclosed in Patent Document 1, a pair of multilayer ceramic capacitors having equivalent specifications are mounted symmetrically on corresponding positions on the front and back surfaces of the wiring board, and propagated from one multilayer ceramic capacitor to the wiring board. Noise is reduced by causing the vibration and vibration propagated from the other multilayer ceramic capacitor to the wiring board to cancel each other.

JP 2000-23320 A

  However, when the technique disclosed in Patent Document 1 is applied, as a result, the multilayer ceramic capacitor is mounted on the front and back surfaces of the wiring board, which inevitably increases the thickness of the circuit board. There is a risk that the electronic equipment will be enlarged.

  Further, the technique disclosed in Patent Document 1 can be applied only when the multilayer ceramic capacitor can be mounted on the front and back surfaces of the wiring board. In the circuit design of an electronic circuit or the structure design of an electronic device. When a multilayer ceramic capacitor can be mounted only on one side of the wiring board, it cannot be applied in the first place.

  Therefore, the present invention has been made in view of the above-described problems, and an object thereof is to provide a circuit board capable of reducing noise while preventing an increase in thickness, and the thickness of the circuit board is increased. It is an object of the present invention to provide a method for mounting a capacitor element that can prevent noise and reduce noise.

  A circuit board according to the present invention is formed by mounting a plurality of substantially rectangular parallelepiped capacitor elements on a wiring board having a laminate composed of dielectric layers and internal electrode layers that are alternately laminated along a predetermined direction. . The plurality of capacitor elements include a capacitor element group including a plurality of capacitor elements arranged in the vicinity along a direction parallel to the main surface of the wiring board. The main surfaces of the plurality of capacitor elements included in the capacitor element group facing the wiring board are all substantially rectangular. The plurality of capacitor elements included in the capacitor element group are located on a straight line extending along a direction parallel to any one side of the main surface of one capacitor element of the plurality of capacitor elements. Yes. Among the plurality of capacitor elements included in the capacitor element group, directions of distortion generated when a voltage is applied on an opposing surface of adjacent capacitor elements are opposite to each other, and the plurality of capacitors included in the capacitor element group The total amount of distortion generated in the plurality of capacitor elements in the direction in which the elements are arranged is always substantially constant.

  In the circuit board according to the present invention, the main surface of the plurality of capacitor elements included in the capacitor element group is preferably a substantially rectangular shape having a pair of short sides and a pair of long sides, In that case, it is preferable that the plurality of capacitor elements included in the capacitor element group have external electrodes at both ends along a direction parallel to the long side of each main surface. In that case, each of the external electrodes is preferably electrically connected to a land provided corresponding to the wiring board via a conductive bonding member.

  The circuit board according to the present invention may include a plurality of the capacitor element groups. In that case, all the capacitor elements included in the plurality of capacitor element groups are arranged in a straight line in the vicinity. It is preferable.

  The circuit board according to the present invention may include a plurality of the capacitor element groups. In that case, all the capacitor elements included in the plurality of capacitor element groups are arranged in a matrix in the vicinity. It is preferable.

  In the circuit board according to the present invention, it is preferable that the stacking directions of the stacked bodies included in each of the plurality of capacitor elements included in the capacitor element group are all in the same direction.

  In the circuit board according to the present invention, the capacitor element group is preferably composed of a pair of capacitor elements having equivalent specifications. In that case, it is preferable that the sum of absolute values of voltages applied to the pair of capacitor elements is always substantially constant.

  A mounting method for a capacitor element according to the present invention is for mounting a plurality of substantially rectangular parallelepiped capacitor elements on a wiring board having a laminate composed of dielectric layers and internal electrode layers alternately stacked along a predetermined direction. Is the method. The plurality of capacitor elements include a capacitor element group including a plurality of capacitor elements that are arranged in the vicinity along a direction parallel to the main surface of the wiring board. The main surfaces of the plurality of capacitor elements included in the capacitor element group that face the wiring board are all formed in a substantially rectangular shape. The plurality of capacitor elements included in the capacitor element group are positioned on a straight line extending along a direction parallel to any one side of the main surface of one capacitor element of the plurality of capacitor elements. Is to be arranged. The capacitor element mounting method according to the present invention is such that, among the plurality of capacitor elements included in the capacitor element group, the directions of distortion generated when a voltage is applied on opposite surfaces of adjacent capacitor elements are opposite to each other. The plurality of capacitor elements are mounted on the wiring board so that the total amount of distortion generated in the plurality of capacitor elements is always substantially constant in the direction in which the plurality of capacitor elements included in the capacitor element group are arranged. It is characterized by that.

  In the capacitor element mounting method according to the present invention, the principal surfaces of the plurality of capacitor elements included in the capacitor element group are formed in a substantially rectangular shape having a pair of short sides and a pair of long sides. In this case, the plurality of capacitor elements included in the capacitor element group have external electrodes at both ends along the direction parallel to the long side of each of the main surfaces. It is preferable. In that case, when mounting the plurality of capacitor elements included in the capacitor element group on the wiring board, each of the external electrodes corresponds to the wiring board. It may be further characterized in that each of the lands provided is electrically connected via a conductive bonding member.

  In the capacitor element mounting method according to the present invention, when there are a plurality of capacitor element groups, all the capacitor elements included in the plurality of capacitor element groups are arranged in a straight line in the vicinity. It may be further characterized in that all the capacitor elements are mounted on the wiring board.

  The capacitor element mounting method according to the present invention is such that when there are a plurality of capacitor element groups, all the capacitor elements included in the plurality of capacitor element groups are arranged in a matrix in the vicinity. It may be further characterized in that all the capacitor elements are mounted on the wiring board.

  The capacitor element mounting method according to the present invention includes a plurality of capacitor elements such that each of the plurality of capacitor elements included in the capacitor element group has a stacked direction of the stacked body facing the same direction. May be further mounted on the wiring board.

  The capacitor element mounting method according to the present invention may be further characterized in that the capacitor element group is composed of a pair of capacitor elements having equivalent specifications. In such a case, the capacitor element mounting method according to the present invention may be configured so that the sum of absolute values of voltages applied to the pair of capacitor elements is always substantially constant. It may be further characterized by being mounted on a wiring board.

  ADVANTAGE OF THE INVENTION According to this invention, it can be set as the circuit board which can reduce a noise, preventing the increase in thickness, and the mounting method of the capacitor | condenser element which can prevent the increase in the thickness of a circuit board and can reduce a noise It can be.

1 is a perspective view of a multilayer ceramic capacitor provided on a circuit board in an embodiment of the present invention. It is sectional drawing along the II-II line shown in FIG. 1 of the multilayer ceramic capacitor shown in FIG. It is sectional drawing along the III-III line | wire shown in FIG. 1 of the multilayer ceramic capacitor shown in FIG. It is a figure which shows the result of having simulated the distortion which arises at the time of a voltage application to the laminated body of the laminated ceramic capacitor shown in FIG. It is a model front view which shows the 1st mounting structure which mounted the multilayer ceramic capacitor shown in FIG. 1 with respect to the wiring board. It is a schematic side view which shows the 1st mounting structure which mounted the multilayer ceramic capacitor shown in FIG. 1 with respect to the wiring board. It is a model front view which shows the 2nd mounting structure which mounted the multilayer ceramic capacitor shown in FIG. 1 with respect to the wiring board. It is a schematic side view which shows the 2nd mounting structure which mounted the multilayer ceramic capacitor shown in FIG. 1 with respect to the wiring board. It is a schematic perspective view which shows the layout of the multilayer ceramic capacitor with which the circuit board based on the 1st structural example was equipped. It is a figure which shows an example of the waveform of the voltage applied to the multilayer ceramic capacitor with which the circuit board which concerns on a 1st structural example was equipped. It is the figure which showed typically the change of the stress which arises in the circuit board which concerns on a 1st structural example, and the multilayer ceramic capacitor with which it was equipped with time. It is a figure which shows another example of the waveform of the voltage applied to the multilayer ceramic capacitor with which the circuit board which concerns on a 1st structural example was equipped. It is a figure which shows another example of the waveform of the voltage applied to the multilayer ceramic capacitor with which the circuit board which concerns on a 1st structural example was equipped. It is the figure which showed typically the layout of the multilayer ceramic capacitor with which the circuit board based on the 2nd structural example was equipped, and the change of the stress with time which arises in the said multilayer ceramic capacitor. It is the figure which showed typically the layout of the multilayer ceramic capacitor with which the circuit board based on the 3rd structural example was equipped. It is the figure which showed typically the layout of the multilayer ceramic capacitor with which the circuit board based on the 4th structural example was equipped, and the change of the stress with time which arises in the said multilayer ceramic capacitor. It is the figure which showed typically the layout of the multilayer ceramic capacitor with which the circuit board based on the 5th structural example was equipped, and the change of the stress with time which arises in the said multilayer ceramic capacitor. It is the figure which showed typically the layout of the multilayer ceramic capacitor with which the circuit board based on the 6th structural example was equipped. It is the figure which showed typically the layout of the multilayer ceramic capacitor with which the circuit board based on the 7th structural example was equipped, and the change of the stress with time which arises in the said multilayer ceramic capacitor. It is a figure which shows an example of the waveform of the voltage applied to the multilayer ceramic capacitor with which the circuit board based on the 7th structural example was equipped. It is the figure which showed typically the layout of the multilayer ceramic capacitor with which the circuit board based on the 8th structural example was equipped, and the change of the stress with time which arises in the said multilayer ceramic capacitor. It is a figure which shows an example of the waveform of the voltage applied to the multilayer ceramic capacitor with which the circuit board based on the 8th structural example was equipped.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Examples of the capacitor element to which the present invention is applied include a multilayer ceramic capacitor using a ceramic material as a dielectric material and a multilayer metallized film capacitor using a resin film as a dielectric material. In the embodiment shown in FIG. 1, the multilayer ceramic capacitor will be described as an example. In the following embodiments, the same or common parts are denoted by the same reference numerals in the drawings, and description thereof will not be repeated.

  FIG. 1 is a perspective view of a multilayer ceramic capacitor provided on a circuit board according to an embodiment of the present invention. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along the line II-II shown in FIG. 1, and FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. FIG. First, with reference to these FIG. 1 thru | or FIG. 3, the multilayer ceramic capacitor with which the circuit board in this Embodiment is equipped is demonstrated.

  As shown in FIGS. 1 to 3, the multilayer ceramic capacitor 10 is an electronic component having a substantially rectangular parallelepiped shape as a whole, and includes a multilayer body 11 and a pair of external electrodes 14.

  As shown in FIGS. 2 and 3, the multilayer body 11 includes dielectric layers 12 and internal electrode layers 13 that are alternately laminated along a predetermined direction. Dielectric layer 12 is formed of, for example, a ceramic material mainly composed of barium titanate. In addition, the dielectric layer 12 may contain a Mn compound, Mg compound, Si compound, Co compound, Ni compound, rare earth compound, or the like as a subcomponent of a ceramic powder that is a raw material of a ceramic sheet described later. On the other hand, the internal electrode layer 13 is formed of a metal material typified by Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or the like.

  The laminate 11 is prepared by preparing a plurality of material sheets on which a conductive paste to be the internal electrode layer 13 is printed on the surface of a ceramic sheet (so-called green sheet) to be the dielectric layer 12, and laminating the plurality of material sheets. Manufactured by crimping and firing.

The material of the dielectric layer 12 is not limited to the above-mentioned ceramic material mainly composed of barium titanate, and other high dielectric constant ceramic materials (for example, CaTiO ₃ , SrTiO ₃ , CaZrO _3, etc.) are mainly used. May be selected as the material of the dielectric layer 12. Further, the material of the internal electrode layer 13 is not limited to the metal material described above, and other conductive materials may be selected as the material of the internal electrode layer 13.

  As shown in FIGS. 1 and 2, the pair of external electrodes 14 are provided so as to be separated from each other so as to cover the surfaces of both end portions in a predetermined direction of the multilayer body 11. The pair of external electrodes 14 are each composed of a conductive film.

  The pair of external electrodes 14 is composed of a laminated film of a sintered metal layer and a plating layer, for example. A sintered metal layer is formed by baking pastes, such as Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, for example. A plating layer is comprised by the Ni plating layer and the Sn plating layer which covers this, for example. Instead of this, the plated layer may be a Cu plated layer or an Au plated layer. Further, the pair of external electrodes 14 may be constituted only by a plating layer.

  Further, a conductive resin paste can be used as the pair of external electrodes 14. When a conductive resin paste is used as the pair of external electrodes 14, the resin component contained in the conductive resin paste exhibits an effect of absorbing vibration generated in the multilayer body 11, so that it propagates from the multilayer body 11 to the outside. It is possible to effectively attenuate the vibrations that occur, which is advantageous in reducing noise.

  As shown in FIG. 2, one of the pair of internal electrode layers 13 adjacent to each other with the dielectric layer 12 sandwiched in the stacking direction is connected to one of the pair of external electrodes 14 inside the multilayer ceramic capacitor 10. The other of the pair of internal electrode layers 13 that are electrically connected and are adjacent to each other with the dielectric layer 12 sandwiched in the stacking direction is the other of the pair of external electrodes 14 in the multilayer ceramic capacitor 10. Is electrically connected. As a result, a plurality of capacitor elements are electrically connected in parallel between the pair of external electrodes 14.

  Here, as shown in FIGS. 1 to 3, the direction in which the pair of external electrodes 14 are arranged is defined as the length direction L of the multilayer ceramic capacitor 10, and the dielectric layer 12 and the internal electrode layer 13 in the multilayer body 11 are defined. When the stacking direction is defined as the thickness direction T, and the direction perpendicular to both the length direction L and the thickness direction T is defined as the width direction W, the multilayer ceramic capacitor 10 in the present embodiment is It has an elongated, substantially rectangular parallelepiped shape that is configured such that the outer dimension along it is the longest.

  As typical values of the outer dimension in the length direction L and the outer dimension in the width direction W of the multilayer ceramic capacitor 10, for example, 3.2 [mm] × 1.6 [mm], 2.0 [mm] × 1 .25 [mm], 1.6 [mm] × 0.8 [mm], 1.0 [mm] × 0.5 [mm], 0.8 [mm] × 0.4 [mm],. Examples include 6 [mm] × 0.3 [mm], 0.4 [mm] × 0.2 [mm], and the like.

  Of the six main surfaces of the substantially rectangular parallelepiped multilayer ceramic capacitor 10, a pair of main surfaces positioned relative to each other in the length direction L are defined as the length direction end surfaces 15, and positioned relative to each other in the thickness direction T. A pair of principal surfaces is defined as a thickness direction end surface 16 and a pair of principal surfaces positioned relative to each other in the width direction W is defined as a width direction end surface 17, and the terminology will be used in the following description.

  FIG. 4 is a diagram showing a result of simulating distortion generated when a voltage is applied to the multilayer ceramic capacitor body shown in FIG. Next, with reference to this FIG. 4, the distortion which may arise in the multilayer ceramic capacitor with which the circuit board in this Embodiment is equipped is demonstrated.

  When an AC voltage or a DC voltage on which an AC component is superimposed is applied to the pair of external electrodes 14 of the multilayer ceramic capacitor 10 described above, mechanical distortion as shown in FIG. This is a distortion of the multilayer ceramic capacitor 10.

As shown in FIG. 4, when a voltage is applied, the laminate 11 along the thickness direction T is significantly distorted outwardly as indicated by an arrow AR _T in the figure. Accordingly, the arrow AR _W laminate 11 along the length L is in the arrow largely distorted inward as indicated by AR _L, also laminated body 11 in the drawing along the width direction W in the drawing As shown in, it is distorted inward. On the other hand, almost no distortion occurs in the corner portion 18 of the laminated body 11 having an elongated, substantially rectangular parallelepiped shape.

  Therefore, in the multilayer ceramic capacitor 10, the same distortion occurs when a voltage is applied, and the above-described distortion repeatedly occurs in accordance with the period of the voltage applied to the multilayer ceramic capacitor 10. . As a result, in the circuit board provided with the multilayer ceramic capacitor 10, the multilayer ceramic capacitor 10 serves as a vibration source, and the circuit board vibrates as a result of propagation of the vibration to the wiring board, resulting in noise. .

  Here, as the mounting structure of the multilayer ceramic capacitor 10 in the present embodiment, two types of structures, a first mounting structure and a second mounting structure described later, are assumed. The first mounting structure is a mounting structure in which the multilayer ceramic capacitor 10 is mounted on the wiring board so that the thickness direction T of the multilayer ceramic capacitor 10 is substantially parallel to the normal direction of the mounting surface of the circuit board. The structure is a mounting structure in which the multilayer ceramic capacitor 10 is mounted on the wiring board so that the thickness direction T of the multilayer ceramic capacitor 10 is substantially orthogonal to the normal direction of the mounting surface of the circuit board.

  5 and 6 are a schematic front view and a schematic side view showing a first mounting structure in which the multilayer ceramic capacitor shown in FIG. 1 is mounted on a wiring board. 7 and 8 are a schematic front view and a schematic side view showing a second mounting structure in which the multilayer ceramic capacitor shown in FIG. 1 is mounted on a wiring board. Next, with reference to FIGS. 5 to 8, the mechanism in which the distortion of the multilayer ceramic capacitor causes vibration in the circuit board in each case where the first mounting structure and the second mounting structure are adopted will be described in more detail. To do.

  In the following, in order to distinguish between the multilayer ceramic capacitor 10 mounted on the wiring board in the first mounting structure and the multilayer ceramic capacitor 10 mounted on the wiring board in the second mounting structure, the former multilayer capacitor is used. The ceramic capacitor is represented by reference numeral 10A, and the latter multilayer ceramic capacitor is represented by reference numeral 10B.

  As shown in FIGS. 5 to 8, the wiring substrate 2 is made of an insulating substrate having a conductive pattern formed on at least one of the pair of main surfaces. As a material of the wiring board 2, a material made of a resin material such as an epoxy resin, a ceramic material such as alumina, or a material in which a filler or a woven fabric made of an inorganic material or an organic material is added, or the like can be used. . Generally, as the wiring board 2, a glass epoxy board in which a glass woven fabric is added to a base material made of an epoxy resin is preferably used.

  A pair of lands 3 are provided on the main surface of the wiring board 2 so as to be spaced apart from each other. The pair of lands 3 correspond to a part of the conductive pattern described above and have a size corresponding to the pair of external electrodes 14 of the multilayer ceramic capacitors 10A and 10B. In addition, as a material of a pair of land 3, various conductive materials can be utilized, but generally metal materials, such as copper foil, are utilized suitably.

  The pair of external electrodes 14 of the multilayer ceramic capacitors 10 </ b> A and 10 </ b> B and the pair of lands 3 provided on the wiring board 2 are joined by a conductive joining member 6. As the joining member 6, for example, a conductive adhesive or solder can be used. Here, when a conductive adhesive is used as the joining member 6, the resin component contained in the conductive adhesive exhibits an effect of absorbing vibrations generated in the multilayer ceramic capacitors 10 </ b> A and 10 </ b> B. It becomes possible to effectively attenuate the vibration propagating from the capacitors 10A and 10B to the outside, which is advantageous in reducing noise.

  When the multilayer ceramic capacitors 10A and 10B are mounted on the wiring board 2, a conductive adhesive or solder paste is applied to the lands 3 provided in advance on the wiring board 2 by screen printing or the like, and the multilayer ceramic capacitor 10A is applied thereon. , 10B is placed in a reflow furnace. As a result, fillets are formed on the joining member 6, and the multilayer ceramic capacitors 10 </ b> A and 10 </ b> B are mounted on the wiring board 2.

  As shown in FIGS. 5 and 6, when the first mounting structure is adopted, the thickness direction T of the multilayer ceramic capacitor 10 </ b> A is located so as to be substantially orthogonal to the main surface of the wiring substrate 2, and The length direction L and the width direction W of the multilayer ceramic capacitor 10A are positioned so as to be substantially parallel to the surface. As a result, one of the pair of thickness direction end faces 16 of the multilayer ceramic capacitor 10 </ b> A is located facing the main surface of the wiring board 2.

As shown in FIG. 5, when a voltage multilayer ceramic capacitor 10A in this state is applied, greatly distorted inward as shown laminate 11 by an arrow AR _L in the figure, the laminated ceramic along with this A compressive stress acts inward on the pair of longitudinal end faces 15 of the capacitor 10A. Therefore, the multilayer ceramic capacitor 10A is compressed along the length direction L in the direction in which the length direction end faces 15 approach each other.

  As a result, the stress also acts on the wiring board 2 through the bonding member 6 bonded to the external electrode 14 and the land 3 bonded to the bonding member 6, and the direction indicated by the arrow A1 in FIG. The wiring board 2 bends toward the surface. At that time, since the wiring board 2 bends in the direction of the arrow A1 as described above at the positions on both outer sides of the multilayer ceramic capacitor 10A along the length direction L of the multilayer ceramic capacitor 10A, The portion of the wiring board 2 facing the ceramic capacitor 10A bends in the direction indicated by the arrow A2 in FIG.

Further, as shown in FIG. 6, when a voltage is applied to the multilayer ceramic capacitor 10A, the portion where the external electrodes 14 are provided in the laminated body 11, inward as indicated by an arrow AR _W in the drawings with distorted, distortion outward as indicated by an arrow AR _T in the figure, together with the compressive stress acts toward the inside pair of widthwise end face 17 of the multilayer ceramic capacitor 10A accordingly, the multilayer ceramic capacitor An extensional stress acts outwardly on the pair of thickness direction end faces 16 of 10A. Therefore, the portion of the multilayer ceramic capacitor 10A where the external electrode 14 is provided is compressed along the width direction W in the direction in which the width direction end faces 17 approach each other, and the thickness direction end faces 16 along the thickness direction T are mutually compressed. Extends away from you.

  As a result, stress also acts on the wiring board 2 via the bonding member 6 bonded to the external electrode 14 and the land 3 bonded to the bonding member 6, and the arrows A 3 and A 4 in FIG. The wiring board 2 bends in the direction shown.

  On the other hand, when the voltage applied to the multilayer ceramic capacitor 10A is removed, all the distortions that have occurred in the multilayer ceramic capacitor 10A are also removed. It will return to its original state.

  Therefore, the wiring board 2 is repeatedly deformed between the bent state and the unbent state based on the mechanism described above in accordance with the period of the voltage applied to the multilayer ceramic capacitor 10A. As a result, the circuit board vibrates periodically, and noise is generated as a result when no measures are taken.

  As shown in FIGS. 7 and 8, when the second mounting structure is adopted, the width direction W of the multilayer ceramic capacitor 10 </ b> B is positioned so as to be substantially orthogonal to the main surface of the wiring board 2. The length direction L and the thickness direction T of the multilayer ceramic capacitor 10B are positioned so as to be substantially parallel to the surface. Thereby, one of the pair of width direction end faces 17 of the multilayer ceramic capacitor 10 </ b> B is positioned to face the main surface of the wiring board 2.

As shown in FIG. 7, when a voltage is applied to the multilayer ceramic capacitor 10B in this state, the laminated body 11 is greatly distorted inward as indicated by an arrow AR _L in the figure, the laminated ceramic along with this A compressive stress acts inward on the pair of longitudinal end faces 15 of the capacitor 10B. Therefore, the multilayer ceramic capacitor 10B is compressed along the length direction L in the direction in which the length direction end faces 15 approach each other.

  As a result, stress is also applied to the wiring board 2 through the bonding member 6 bonded to the external electrode 14 and the land 3 bonded to the bonding member 6, and the direction indicated by the arrow B1 in FIG. The wiring board 2 bends toward the surface. At that time, since the wiring board 2 bends in the direction of the arrow B1 as described above at the positions on both outer sides of the multilayer ceramic capacitor 10B along the length direction L of the multilayer ceramic capacitor 10B. The portion of the wiring board 2 facing the ceramic capacitor 10B bends in the direction indicated by the arrow B2 in FIG.

Further, as shown in FIG. 8, when a voltage is applied to the multilayer ceramic capacitor 10B, a portion external electrodes 14 are provided in the laminated body 11, inward as indicated by an arrow AR _W in the drawings with distorted, distortion outward as indicated by an arrow AR _T in the figure, together with the compressive stress acts toward the inside pair of widthwise end face 17 of the multilayer ceramic capacitor 10B accordingly, the multilayer ceramic capacitor An extensional stress acts on the pair of thickness direction end faces 16 of 10B toward the outside. Therefore, the portion of the multilayer ceramic capacitor 10B where the external electrode 14 is provided is compressed along the width direction W in the direction in which the width direction end faces 17 approach each other, and the thickness direction end faces 16 are aligned with each other along the thickness direction T. Extends away from you.

  As a result, stress also acts on the wiring board 2 via the bonding member 6 bonded to the external electrode 14 and the land 3 bonded to the bonding member 6, and the arrows A 3 and A 4 in FIG. The wiring board 2 bends in the direction shown.

  On the other hand, when the voltage applied to the multilayer ceramic capacitor 10B is removed, all the distortion generated in the multilayer ceramic capacitor 10B is also removed. It will return to its original state.

  Therefore, the wiring board 2 is repeatedly deformed between the bent state and the unbent state based on the mechanism described above in accordance with the period of the voltage applied to the multilayer ceramic capacitor 10B. As a result, the circuit board vibrates periodically, and noise is generated as a result when no measures are taken.

  Therefore, the mounting method of the circuit board and the multilayer ceramic capacitor in the present embodiment is based on a plurality of specific multilayer ceramic capacitors included in the multilayer ceramic capacitors when the multilayer ceramic capacitors are mounted on the wiring board. By paying attention to the multilayer ceramic capacitor group and adopting a layout that takes into account the magnitude and direction of distortion that will occur when a voltage is applied to multiple multilayer ceramic capacitors included in the multilayer ceramic capacitor group The noise is reduced while avoiding an increase in the thickness of the circuit board.

(First configuration example)
FIG. 9 is a schematic perspective view showing a layout of the multilayer ceramic capacitor provided in the circuit board according to the first configuration example based on the present embodiment, and FIG. 10 is a circuit diagram according to the first configuration example. It is a figure which shows an example of the waveform of the voltage applied to the provided multilayer ceramic capacitor. FIG. 11 is a diagram schematically showing a change in stress over time generated in the circuit board according to the first configuration example and the multilayer ceramic capacitor provided in the circuit board.

  11A shows only the stress generated in the direction in which the plurality of multilayer ceramic capacitors are arranged among the stresses generated at time tx shown in FIG. 10, and FIG. 11B shows the stress generated in FIG. Of the stresses generated at the time ty shown, only the stresses generated in the direction in which the plurality of multilayer ceramic capacitors are arranged are shown.

  This first configuration example focuses on a pair of multilayer ceramic capacitors having the same specifications as the plurality of multilayer ceramic capacitors included in the above-described multilayer ceramic capacitor group.

  As shown in FIG. 9, FIG. 11A and FIG. 11B, the circuit board 1A according to the first configuration example is a pair of monolithic ceramic capacitors in the region R of the circuit board 1A. Multilayer ceramic capacitor 10 </ b> A <b> 1 and second multilayer ceramic capacitor 10 </ b> A <b> 2 are arranged side by side along a direction parallel to the main surface of wiring substrate 2. Here, the “vicinity” mentioned above means a range of about 1/10 of the wavelength of vibration propagated to the wiring board 2. More preferably, the first monolithic ceramic capacitor 10A1 and the second monolithic ceramic capacitor 10A2 include other elements (in addition to other monolithic ceramic capacitors, other electronic components other than the monolithic ceramic capacitors are also included in the other elements). Are arranged side by side with no interposition. The first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 are both mounted on the wiring board 2 using the first mounting structure described above.

  More specifically, as shown in FIGS. 11 (A) and 11 (B), among the thickness direction end face 16 of the first multilayer ceramic capacitor 10A1 and the thickness direction end face 16 of the second multilayer ceramic capacitor 10A2, the wiring board 2 Since both the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 have a substantially rectangular parallelepiped shape, both end faces facing each other have a substantially rectangular shape having a pair of short sides and a pair of long sides. The first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 are arranged next to each other so as to be positioned on a straight line 100 extending in a direction parallel to the long side. ing. In the first configuration example, the length direction L of the first multilayer ceramic capacitor 10A1 and the length direction L of the second multilayer ceramic capacitor 10A2 are arranged so as to face the same direction.

In this case, the opposing surfaces of the pair of adjacent first multilayer ceramic capacitor 10A1 and second multilayer ceramic capacitor 10A2 are one of the pair of longitudinal end faces 15 of the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor. It is comprised by one of a pair of length direction end surface 15 of 10A2. Therefore, the orientation of the distortion generated by these opposing surfaces when a voltage is applied becomes opposite to each other as indicated by arrows AR _L in the figure.

  As shown in FIG. 9, the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 mounted on the wiring board 2 are electrically connected to the signal source 5 via lands 3 and wirings 4 provided on the wiring board 2, respectively. Connected. The signal source 5 may be provided in the circuit board 1A, or may be provided outside the circuit board 1A. Here, a signal generated by the signal source 5 electrically connected to the first multilayer ceramic capacitor 10A1, and a signal generated by the signal source 5 electrically connected to the second multilayer ceramic capacitor 10A2. Are different from each other.

  Specifically, as shown in FIG. 10, the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1 is 0 [V] and + V at every predetermined timing (time t1, t2, t3,...). The voltage waveform applied to the second multilayer ceramic capacitor 10A2 is 180 degrees with the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1. A rectangular wave whose voltage is switched between + V [V] and 0 [V] at every predetermined timing (time t1, t2, t3,...) With a phase difference. That is, in the first configuration example, the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1 and the waveform of the voltage applied to the second multilayer ceramic capacitor 10A2 have the same amplitude and opposite phases. Therefore, the sum of the absolute value of the voltage applied to the first multilayer ceramic capacitor 10A1 and the absolute value of the voltage applied to the second multilayer ceramic capacitor 10A2 is always substantially constant.

  Therefore, as shown in FIG. 11 (A), at time tx, only the first multilayer ceramic capacitor 10A1 is distorted, and the second multilayer ceramic capacitor 10A2 is not distorted. As shown, at time ty, distortion occurs only in the second multilayer ceramic capacitor 10A2, and no distortion occurs in the first multilayer ceramic capacitor 10A1.

  Here, as described above, since the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 have the same specifications, their capacitances are the same, and the first multilayer ceramic capacitor 10A1 and Since the waveform of the voltage applied to the second multilayer ceramic capacitor 10A2 has the same amplitude and the opposite phase, the vibration wave generated in the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 as the vibration source. Also have the same amplitude and opposite phase. Therefore, the total amount of distortion generated in the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 is always kept substantially constant.

  As a result, the bending in the direction in which the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 are arranged, which occurs in the wiring board 2 due to the propagation of vibrations generated in the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2, is transmitted. The deformation (that is, the bending deformation along the direction indicated by the arrow C in FIGS. 11A and 11B) causes the region R in the vicinity of the mounting position of the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2. In the inside, since the amount of bending is always constant, the wiring board 2 of the part is kept in a state of being bent constantly without substantially vibrating.

  The above-mentioned “the sum of absolute values of applied voltages is always substantially constant” or “the sum of distortion amounts is always substantially constant” means that the difference in vibration propagating from each multilayer ceramic capacitor to the wiring board is filled. It means that it is constant within the range (hereinafter the same).

  Therefore, by using the circuit board 1A according to the first configuration example, vibration generated in the wiring board 2 is reduced. As a result, noise can be reduced without increasing the thickness of the circuit board 1A. Can do. In addition, since the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 are not mounted on the front and back surfaces of the wiring board 2, the application is possible even when an electronic component can be mounted only on one side of the wiring board 2. It is possible to reduce noise while ensuring a high degree of design freedom.

  In the first configuration example, the voltage applied to the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 is illustrated as a rectangular wave having the same amplitude and opposite phase. If the waveforms are in a complementary relationship, the sum of the amount of distortion generated in the first multilayer ceramic capacitor 10A1 and the amount of strain generated in the second multilayer ceramic capacitor 10A2 can be made substantially constant at all times. Hereinafter, an example thereof will be specifically exemplified.

  12 and 13 are diagrams showing another example and still another example of the waveform of the voltage applied to the multilayer ceramic capacitor provided in the circuit board according to the first configuration example.

  In the example shown in FIG. 12, the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1 is −V [V] and + V [V] at predetermined timings (time t1, t2, t3,...). The waveform of the voltage applied to the second multilayer ceramic capacitor 10A2 is predetermined with a phase difference of 180 degrees from the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1. Are square waves whose voltage is switched between + V [V] and -V [V] at each timing (time t1, t2, t3,...). That is, the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1 and the waveform of the voltage applied to the second multilayer ceramic capacitor 10A2 have the same amplitude and opposite phases. The sum of the absolute value of the voltage applied to the multilayer ceramic capacitor 10A1 and the absolute value of the voltage applied to the second multilayer ceramic capacitor 10A2 is always substantially constant.

  Even in such a configuration, since the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1 and the waveform of the voltage applied to the second multilayer ceramic capacitor 10A2 are in a complementary relationship, the first The sum of the amount of strain generated in the multilayer ceramic capacitor 10A1 and the amount of strain generated in the second multilayer ceramic capacitor 10A2 can be made substantially constant at all times.

  In the example shown in FIG. 13, the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1 peaks at 0 V [V] and + V [V] at a predetermined timing (time t1, t2, t3,...). The voltage waveform applied to the second multilayer ceramic capacitor 10A2 has a predetermined timing (time t1) with a phase difference of 180 degrees from the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1. , T2, t3,...) Is a sine wave having peaks at + V [V] and 0 [V].

  Even in such a configuration, since the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1 and the waveform of the voltage applied to the second multilayer ceramic capacitor 10A2 are in a complementary relationship, the first The sum of the amount of strain generated in the multilayer ceramic capacitor 10A1 and the amount of strain generated in the second multilayer ceramic capacitor 10A2 can be made substantially constant at all times.

(Second configuration example)
FIG. 14 is a diagram schematically showing a layout of the multilayer ceramic capacitor provided on the circuit board according to the second configuration example and a change in stress over time generated in the multilayer ceramic capacitor.

  Similar to the first configuration example, the second configuration example focuses on a pair of multilayer ceramic capacitors having the same specifications as the plurality of multilayer ceramic capacitors included in the multilayer ceramic capacitor group described above.

  As shown in FIGS. 14A and 14B, in the circuit board 1B according to the second configuration example, a first multilayer ceramic capacitor which is a pair of multilayer ceramic capacitors in the region R of the circuit board 1B. 10A1 and second multilayer ceramic capacitor 10A2 are arranged in the vicinity along the direction parallel to the main surface of wiring board 2. Here, the “vicinity” mentioned above means a range of about 1/10 of the wavelength of vibration propagated to the wiring board 2. More preferably, the first monolithic ceramic capacitor 10A1 and the second monolithic ceramic capacitor 10A2 include other elements (in addition to other monolithic ceramic capacitors, other electronic components other than the monolithic ceramic capacitors are also included in the other elements). Are arranged side by side with no interposition. The first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 are both mounted on the wiring board 2 using the first mounting structure described above.

  More specifically, as shown in FIGS. 14 (A) and 14 (B), among the thickness direction end face 16 of the first multilayer ceramic capacitor 10A1 and the thickness direction end face 16 of the second multilayer ceramic capacitor 10A2, the wiring board 2 Since both the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 have a substantially rectangular parallelepiped shape, both end faces facing each other have a substantially rectangular shape having a pair of short sides and a pair of long sides. The first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 are arranged next to each other so as to be positioned on a straight line 101 extending in a direction parallel to the short side of these. ing. In the second configuration example, the width direction W of the first multilayer ceramic capacitor 10A1 and the width direction W of the second multilayer ceramic capacitor 10A2 are arranged to face the same direction.

  In this case, the opposing surfaces of the pair of adjacent first multilayer ceramic capacitor 10A1 and second multilayer ceramic capacitor 10A2 are one of the pair of width direction end faces 17 of the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2. And one of the pair of width direction end faces 17. For this reason, the directions of distortion generated on these facing surfaces when a voltage is applied are opposite to each other.

  Here, also in the second configuration example, similarly to the first configuration example described above, the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 are connected to the signal source 5 that generates different signals, The waveform of the voltage applied to the first multilayer ceramic capacitor 10A1 and the waveform of the voltage applied to the second multilayer ceramic capacitor 10A2 are as shown in FIG. Therefore, the total amount of distortion generated in the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 is always kept substantially constant.

  As a result, the bending in the direction in which the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 are arranged, which occurs in the wiring board 2 due to the propagation of vibrations generated in the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2, is transmitted. The deformation (that is, the bending deformation along the direction indicated by the arrow D in FIGS. 14A and 14B) is a region R in the vicinity of the mounting position of the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2. In the inside, since the amount of bending is always constant, the wiring board 2 of the part is kept in a state of being bent constantly without substantially vibrating.

  Therefore, by using the circuit board 1B according to the second configuration example, the vibration generated in the wiring board 2 is reduced as in the first configuration example. As a result, the thickness of the circuit board 1B is reduced. Noise can be reduced without increasing it.

(Third configuration example)
FIG. 15 is a diagram schematically showing the layout of the multilayer ceramic capacitor provided on the circuit board according to the third configuration example.

  As in the first and second configuration examples, the third configuration example focuses on a pair of multilayer ceramic capacitors having the same specifications as the plurality of multilayer ceramic capacitors included in the multilayer ceramic capacitor group described above. By combining a plurality of the multilayer ceramic capacitor groups, the first configuration example and the second configuration example are combined.

  As shown in FIG. 15, in the circuit board 1 </ b> C according to the third configuration example, a pair of multilayer ceramic capacitors as in the first configuration example are arranged adjacent to each other so as to be positioned on a straight line 100. A plurality of multilayer ceramic capacitor groups arranged in a straight line along a straight line 100, and a pair of multilayer ceramic capacitors as in the second configuration example are positioned on the straight line 101. Thus, a multilayer ceramic capacitor group is configured by being arranged adjacent to each other, and a plurality of the multilayer ceramic capacitor groups are further arranged in a straight line along the straight line 101.

  As a result, in the circuit board 1C according to the third configuration example, the individual multilayer ceramic capacitor groups are arranged in a matrix (matrix) on the mounting surface of the circuit board 1C. The individual multilayer ceramic capacitors 10A are also arranged in a matrix (matrix) on the mounting surface of the circuit board 1C. Each of the multilayer ceramic capacitors 10A is mounted on the wiring board 2 by adopting the first mounting structure described above.

  When configured in this way, the laminated ceramic capacitors 10A adjacent in the row direction or the column direction are connected to each other between the first laminated ceramic capacitor 10A1 and the second laminated ceramic capacitor 10A2 in the first configuration example or the second configuration example described above. Will have a relationship.

  Therefore, by using the circuit board 1C according to the third configuration example, vibration is reduced in the entire wiring board 2 in the portion where the multilayer ceramic capacitor 10A arranged in a matrix is located. Noise can be reduced without increasing the thickness of the circuit board 1C.

(Fourth configuration example)
FIG. 16 is a diagram schematically showing the layout of the multilayer ceramic capacitor provided on the circuit board according to the fourth configuration example and the change in stress over time generated in the multilayer ceramic capacitor.

  Similar to the first configuration example, the fourth configuration example focuses on a pair of multilayer ceramic capacitors having the same specifications as the plurality of multilayer ceramic capacitors included in the multilayer ceramic capacitor group described above.

  As shown in FIGS. 16A and 16B, when the circuit board 1D according to the fourth configuration example is compared with the circuit board 1A according to the first configuration example described above, a first multilayer ceramic capacitor is provided. 10B1 and the second multilayer ceramic capacitor 10B2 are different from each other only in that the second mounting structure described above is adopted and the wiring board 2 is mounted.

  In this case, the opposing surfaces of the pair of adjacent first multilayer ceramic capacitor 10B1 and second multilayer ceramic capacitor 10B2 are one of the pair of width direction end surfaces 17 of the first multilayer ceramic capacitor 10B1 and the second multilayer ceramic capacitor 10B2. And one of the pair of width direction end faces 17. For this reason, the directions of distortion generated on these facing surfaces when a voltage is applied are opposite to each other.

  Here, also in the fourth configuration example, similarly to the first configuration example described above, the first multilayer ceramic capacitor 10B1 and the second multilayer ceramic capacitor 10B2 are connected to the signal source 5 that generates different signals, respectively. The waveform of the voltage applied to the first multilayer ceramic capacitor 10B1 and the waveform of the voltage applied to the second multilayer ceramic capacitor 10B2 are as shown in FIG. Therefore, the total amount of distortion generated in the first multilayer ceramic capacitor 10B1 and the second multilayer ceramic capacitor 10B2 is always kept substantially constant.

  As a result, the bending in the direction in which the first multilayer ceramic capacitor 10B1 and the second multilayer ceramic capacitor 10B2 are arranged, which occurs in the wiring board 2 due to the propagation of vibrations generated in the first multilayer ceramic capacitor 10B1 and the second multilayer ceramic capacitor 10B2. The deformation (that is, the bending deformation along the direction indicated by the arrow C in FIGS. 16A and 16B) causes the region R in the vicinity of the mounting position of the first multilayer ceramic capacitor 10B1 and the second multilayer ceramic capacitor 10B2. In the inside, since the amount of bending is always constant, the wiring board 2 of the part is kept in a state of being bent constantly without substantially vibrating.

  Therefore, by using the circuit board 1D according to the fourth configuration example, the vibration generated in the wiring board 2 is reduced as in the first configuration example. As a result, the thickness of the circuit board 1D is reduced. Noise can be reduced without increasing it.

(Fifth configuration example)
FIG. 17 is a diagram schematically showing the layout of the multilayer ceramic capacitor provided on the circuit board according to the fifth configuration example and the change in stress over time generated in the multilayer ceramic capacitor.

  Similar to the second configuration example, the fifth configuration example focuses on a pair of multilayer ceramic capacitors having the same specifications as the plurality of multilayer ceramic capacitors included in the multilayer ceramic capacitor group described above.

  As shown in FIGS. 17A and 17B, the circuit board 1E according to the fifth configuration example has a first multilayer ceramic capacitor when compared with the circuit board 1B according to the second configuration example described above. 10B1 and the second multilayer ceramic capacitor 10B2 are different from each other only in that the second mounting structure described above is adopted and the wiring board 2 is mounted.

  In this case, the opposing surfaces of the pair of adjacent first multilayer ceramic capacitor 10B1 and second multilayer ceramic capacitor 10B2 are one of the pair of thickness direction end faces 16 of the first multilayer ceramic capacitor 10B1 and the second multilayer ceramic capacitor 10B2. And one of the pair of thickness direction end faces 16. For this reason, the directions of distortion generated on these facing surfaces when a voltage is applied are opposite to each other.

  Here, also in the fifth configuration example, similarly to the first configuration example described above, the first multilayer ceramic capacitor 10B1 and the second multilayer ceramic capacitor 10B2 are connected to the signal source 5 that generates different signals, respectively. The waveform of the voltage applied to the first multilayer ceramic capacitor 10B1 and the waveform of the voltage applied to the second multilayer ceramic capacitor 10B2 are as shown in FIG. Therefore, the total amount of distortion generated in the first multilayer ceramic capacitor 10B1 and the second multilayer ceramic capacitor 10B2 is always kept substantially constant.

  As a result, the bending in the direction in which the first multilayer ceramic capacitor 10B1 and the second multilayer ceramic capacitor 10B2 are arranged, which occurs in the wiring board 2 due to the propagation of vibrations generated in the first multilayer ceramic capacitor 10B1 and the second multilayer ceramic capacitor 10B2. The deformation (that is, the bending deformation along the direction indicated by the arrow D in FIGS. 17A and 17B) is a region R in the vicinity of the mounting position of the first multilayer ceramic capacitor 10B1 and the second multilayer ceramic capacitor 10B2. In the inside, since the amount of bending is always constant, the wiring board 2 of the part is kept in a state of being bent constantly without substantially vibrating.

  Therefore, by using the circuit board 1E according to the fifth configuration example, the vibration generated in the wiring board 2 is reduced as in the first configuration example. As a result, the thickness of the circuit board 1E is reduced. Noise can be reduced without increasing it.

(Sixth configuration example)
FIG. 18 is a diagram schematically showing the layout of the multilayer ceramic capacitor provided on the circuit board according to the sixth configuration example.

  The sixth configuration example, like the fourth configuration example and the fifth configuration example, pays attention to a pair of multilayer ceramic capacitors having the same specifications as the plurality of multilayer ceramic capacitors included in the multilayer ceramic capacitor group described above. A plurality of the multilayer ceramic capacitor groups are provided to combine the fourth configuration example and the fifth configuration example.

  As shown in FIG. 18, in the circuit board 1 </ b> F according to the sixth configuration example, a pair of multilayer ceramic capacitors as in the fourth configuration example are arranged adjacent to each other so as to be positioned on a straight line 100. A plurality of multilayer ceramic capacitor groups arranged in a straight line along the straight line 100, and a pair of multilayer ceramic capacitors as in the fifth configuration example are positioned on the straight line 101. Thus, a multilayer ceramic capacitor group is configured by being arranged adjacent to each other, and a plurality of the multilayer ceramic capacitor groups are further arranged in a straight line along the straight line 101.

  As a result, in the circuit board 1F according to the sixth configuration example, the individual multilayer ceramic capacitor groups are arranged in a matrix (matrix) on the mounting surface of the circuit board 1F. The individual multilayer ceramic capacitors 10B are also arranged in a matrix (matrix) on the mounting surface of the circuit board 1F. Each of the multilayer ceramic capacitors 10B is mounted on the wiring board 2 using the above-described second mounting structure.

  When configured in this way, the laminated ceramic capacitors 10B adjacent in the row direction or the column direction are arranged such that the first laminated ceramic capacitor 10B1 and the second laminated ceramic capacitor 10B2 in the fourth configuration example or the fifth configuration example described above. Will have a relationship.

  Therefore, by using the circuit board 1F according to the sixth configuration example, vibration is reduced in the entire wiring board 2 in a portion where the multilayer ceramic capacitor 10B arranged in a matrix is located. Noise can be reduced without increasing the thickness of the circuit board 1F.

(Seventh configuration example)
FIG. 19 is a diagram schematically showing the layout of the multilayer ceramic capacitor provided on the circuit board according to the seventh configuration example and the change in stress over time generated in the multilayer ceramic capacitor. FIG. 20 is a diagram illustrating an example of a waveform of a voltage applied to the multilayer ceramic capacitor provided in the circuit board according to the seventh configuration example.

  The seventh configuration example focuses on three multilayer ceramic capacitors having the same specifications as the plurality of multilayer ceramic capacitors included in the above-described multilayer ceramic capacitor group.

  As shown in FIGS. 19A and 19B, in the circuit board 1G according to the seventh configuration example, the first multilayer ceramic capacitor which is three multilayer ceramic capacitors in the region R of the circuit board 1G. 10A1, second multilayer ceramic capacitor 10A2 and third multilayer ceramic capacitor 10A3 are arranged side by side along a direction parallel to the main surface of wiring board 2. Here, the “vicinity” mentioned above means a range of about 1/10 of the wavelength of vibration propagated to the wiring board 2. More preferably, the first multilayer ceramic capacitor 10A1, the second multilayer ceramic capacitor 10A2, and the third multilayer ceramic capacitor 10A3 are other elements (including other multilayer ceramic capacitors as well as multilayer ceramic capacitors). (Including other electronic components other than the above) are arranged side by side without interposition. The first multilayer ceramic capacitor 10A1, the second multilayer ceramic capacitor 10A2, and the third multilayer ceramic capacitor 10A3 are all mounted on the wiring board 2 using the first mounting structure described above.

  More specifically, as shown in FIGS. 19A and 19B, the thickness direction end face 16 of the first multilayer ceramic capacitor 10A1, the thickness direction end face 16 of the second multilayer ceramic capacitor 10A2, and the third multilayer ceramic capacitor. 10A3, the end face facing the wiring substrate 2 has a substantially rectangular parallelepiped shape because each of the first multilayer ceramic capacitor 10A1, the second multilayer ceramic capacitor 10A2, and the third multilayer ceramic capacitor 10A3 has a substantially rectangular parallelepiped shape. It has a substantially rectangular shape having a pair of short sides and a pair of long sides, and is located on a straight line 100 extending in a direction parallel to the long sides of the first multilayer ceramic capacitor 10A1. The first multilayer ceramic capacitor 10A1, the second multilayer ceramic capacitor 10A2, and the first Multilayer ceramic capacitor 10A3 are arranged side by side next to each other.

  Here, in the seventh configuration example, the length direction L of the first multilayer ceramic capacitor 10A1, the width direction W of the second multilayer ceramic capacitor 10A2, and the width direction W of the third multilayer ceramic capacitor 10A3 are mutually different. They are arranged to face the same direction.

In this case, the opposing surfaces of the adjacent first multilayer ceramic capacitor 10A1 and second multilayer ceramic capacitor 10A2 are either one of the pair of longitudinal end faces 15 of the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2. This is constituted by one of the pair of width direction end faces 17. The opposing surfaces of the adjacent second multilayer ceramic capacitor 10A2 and third multilayer ceramic capacitor 10A3 are either one of the pair of width direction end faces 17 of the second multilayer ceramic capacitor 10A2 and the pair of second multilayer ceramic capacitor 10A2. This is constituted by one of the width direction end faces 17. Therefore, the orientation of the distortion generated by these opposing surfaces at the time of voltage application is an arrow AR _L, becomes opposite to each other as shown AR _W in the figure.

  As shown in FIG. 20, the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1 is 0 [V] and + V [V] at every predetermined timing (time t1, t2, t3,...). The waveform of the voltage applied to the second multilayer ceramic capacitor 10A2 and the third multilayer ceramic capacitor 10A3 is 180 degrees with the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1. Is a rectangular wave whose voltage is switched between + V [V] and 0 [V] at every predetermined timing (time t1, t2, t3,...). That is, in the first configuration example, the amplitude of the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1 and the waveform of the voltage applied to the second multilayer ceramic capacitor 10A2 and the third multilayer ceramic capacitor 10A3 The same and opposite phase.

  Therefore, as shown in FIG. 19A, at time tx, distortion occurs only in the first multilayer ceramic capacitor 10A1, and no distortion occurs in the second multilayer ceramic capacitor 10A2 and the third multilayer ceramic capacitor 10A3. As shown in FIG. 19B, at time ty, distortion occurs only in the second multilayer ceramic capacitor 10A2 and the third multilayer ceramic capacitor 10A3, and no distortion occurs in the first multilayer ceramic capacitor 10A1. Become.

  Here, referring to FIG. 4, the amount of strain generated when a voltage is applied to a multilayer ceramic capacitor having a substantially rectangular parallelepiped shape is different in the length direction L and the width direction W, and the strain amount in the length direction L is generally a width. It becomes larger than the distortion amount in the direction W. Therefore, by adopting the layout as described above, the total amount of distortion generated in the first multilayer ceramic capacitor 10A1, the second multilayer ceramic capacitor 10A2, and the third multilayer ceramic capacitor 10A3 can always be kept substantially constant.

  As a result, the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic that are generated in the wiring board 2 due to the propagation of vibrations generated in the first multilayer ceramic capacitor 10A1, the second multilayer ceramic capacitor 10A2, and the third multilayer ceramic capacitor 10A3. The bending deformation in the direction in which the capacitor 10A2 and the third multilayer ceramic capacitor 10A3 are arranged (that is, the bending deformation along the direction indicated by the arrow E in FIGS. 19A and 19B) is the first multilayer ceramic capacitor 10A1. In the region R in the vicinity of the mounting position of the second multilayer ceramic capacitor 10A2 and the third multilayer ceramic capacitor 10A3, the amount of flexure is always constant, so that the wiring board 2 of the part is flexibly steadily without substantially vibrating. Keeping up To become.

  Therefore, by using the circuit board 1G according to the seventh configuration example, vibration generated in the wiring board 2 is reduced, and as a result, noise can be reduced without increasing the thickness of the circuit board 1G. Can do.

(Eighth configuration example)
FIG. 21 is a diagram schematically showing the layout of the multilayer ceramic capacitor provided on the circuit board according to the eighth configuration example and the change in stress over time generated in the multilayer ceramic capacitor. FIG. 22 is a diagram illustrating an example of a waveform of a voltage applied to the multilayer ceramic capacitor provided in the circuit board according to the eighth configuration example.

  The eighth configuration example focuses on a pair of multilayer ceramic capacitors having different specifications as a plurality of multilayer ceramic capacitors included in the above-described multilayer ceramic capacitor group.

  As shown in FIGS. 21A and 21B, in the circuit board 1H according to the eighth configuration example, the first multilayer ceramic capacitor which is a pair of multilayer ceramic capacitors in the region R of the circuit board 1H. 10A1 and second multilayer ceramic capacitor 10A2 are arranged in the vicinity along the direction parallel to the main surface of wiring board 2. Here, the “vicinity” mentioned above means a range of about 1/10 of the wavelength of vibration propagated to the wiring board 2. More preferably, the first monolithic ceramic capacitor 10A1 and the second monolithic ceramic capacitor 10A2 include other elements (in addition to other monolithic ceramic capacitors, other electronic components other than the monolithic ceramic capacitors are also included in the other elements). Are arranged side by side with no interposition. The first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 are both mounted on the wiring board 2 using the first mounting structure described above.

  More specifically, as shown in FIGS. 21A and 21B, of the thickness direction end face 16 of the first multilayer ceramic capacitor 10A1 and the thickness direction end face 16 of the second multilayer ceramic capacitor 10A2, the wiring board 2 Since both the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 have a substantially rectangular parallelepiped shape, both end faces facing each other have a substantially rectangular shape having a pair of short sides and a pair of long sides. The first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 are arranged next to each other so as to be positioned on a straight line 100 extending in a direction parallel to the long side. ing.

  Here, in the eighth configuration example, the length direction L of the first multilayer ceramic capacitor 10A1 and the width direction W of the second multilayer ceramic capacitor 10A2 are arranged to face the same direction.

In this case, the opposing surfaces of the adjacent first multilayer ceramic capacitor 10A1 and second multilayer ceramic capacitor 10A2 are either one of the pair of longitudinal end faces 15 of the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2. This is constituted by one of the pair of width direction end faces 17. Therefore, the orientation of the distortion generated by these opposing surfaces at the time of voltage application is an arrow AR _L, becomes opposite to each other as shown AR _W in the figure.

  As shown in FIG. 22, the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1 is 0 [V] and + V [V] at predetermined timings (time t1, t2, t3,...). The waveform of the voltage applied to the second multilayer ceramic capacitor 10A2 and the third multilayer ceramic capacitor 10A3 is 180 degrees with the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1. Is a rectangular wave whose voltage is switched between + VA [V] and 0 [V] at predetermined timings (time t1, t2, t3,...). Here, the voltage value + VA [V] applied to the second multilayer ceramic capacitor 10A2 is larger than the voltage value + V [V] applied to the first multilayer ceramic capacitor 10A1. That is, in the first configuration example, the amplitude of the waveform of the voltage applied to the first multilayer ceramic capacitor 10A1 and the waveform of the voltage applied to the second multilayer ceramic capacitor 10A2 and the third multilayer ceramic capacitor 10A3 It has a different antiphase.

  Here, referring to FIG. 4, the amount of strain generated when a voltage is applied to a multilayer ceramic capacitor having a substantially rectangular parallelepiped shape is different in the length direction L and the width direction W, and the strain amount in the length direction L is generally a width. It becomes larger than the distortion amount in the direction W. Therefore, as described above, the voltage value applied to the second multilayer ceramic capacitor 10A2 is made larger than the voltage value applied to the first multilayer ceramic capacitor 10A1, thereby the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor. The total amount of distortion generated in 10A2 and the third multilayer ceramic capacitor 10A3 can always be kept substantially constant.

  Therefore, as shown in FIG. 21A, at time tx, only the first multilayer ceramic capacitor 10A1 is distorted, and the second multilayer ceramic capacitor 10A2 is not distorted. As shown, at time ty, distortion occurs only in the second multilayer ceramic capacitor 10A, and no distortion occurs in the first multilayer ceramic capacitor 10A1.

  As a result, the bending in the direction in which the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2 are arranged, which occurs in the wiring board 2 due to the propagation of vibrations generated in the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2, is transmitted. The deformation (that is, the bending deformation along the direction indicated by the arrow F in FIGS. 21A and 21B) causes the region R in the vicinity of the mounting position of the first multilayer ceramic capacitor 10A1 and the second multilayer ceramic capacitor 10A2. In the inside, since the amount of bending is always constant, the wiring board 2 of the part is kept in a state of being bent constantly without substantially vibrating.

  Therefore, by using the circuit board 1H according to the eighth configuration example, vibration generated in the wiring board 2 is reduced. As a result, noise can be reduced without increasing the thickness of the circuit board 1H. Can do.

  As described above, in circuit boards 1A to 1H according to the present embodiment, any of the plurality of multilayer ceramic capacitors included in the multilayer ceramic capacitor group is generated when a voltage is applied to the opposing surface of the adjacent multilayer ceramic capacitor. The direction of strain to be reversed is opposite to each other, and the total amount of strain generated in the plurality of multilayer ceramic capacitors in the direction in which the plurality of multilayer ceramic capacitors included in the multilayer ceramic capacitor group is aligned is always substantially constant. Has been.

  Also, the mounting method of the multilayer ceramic capacitor in the present embodiment is to mount a plurality of multilayer ceramic capacitors on the wiring board so as to satisfy the above conditions, and among the plurality of multilayer ceramic capacitors included in the multilayer ceramic capacitor group In addition, the directions of distortion generated when applying voltage are opposite to each other on the opposing surfaces of the adjacent multilayer ceramic capacitors, and the plurality of multilayer ceramic capacitors included in the multilayer ceramic capacitor group are arranged in the direction in which the multilayer ceramic capacitors are aligned. The plurality of multilayer ceramic capacitors are mounted on a wiring board so that the total amount of distortion generated is always substantially constant.

  As a result, vibration generated in the wiring board 2 is reduced, and as a result, noise can be reduced without increasing the thickness of the circuit boards 1A to 1H.

  In order to easily realize a layout that satisfies the above conditions, the stacking direction (that is, the thickness direction T) of the multilayer body included in each of the multilayer ceramic capacitors included in the multilayer ceramic capacitor group is the same direction. It is preferable that individual multilayer ceramic capacitors are mounted so as to face.

  The above-described embodiment disclosed herein is illustrative in all respects and is not restrictive. The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1A to 1H circuit board, 2 wiring boards, 3 lands, 4 wirings, 5 signal sources, 6 joint members, 10, 10A, 10A1 to 10A3, 10B, 10B1, 10B2 laminated ceramic capacitors, 11 laminated bodies, 12 dielectric layers, 13 internal electrode layers, 14 external electrodes, 15 lengthwise end faces, 16 thickness direction end faces, 17 width direction end faces, 18 corners.

Claims (14)

A circuit board in which a plurality of substantially rectangular parallelepiped capacitor elements having a laminate composed of dielectric layers and internal electrode layers alternately laminated along a predetermined direction are mounted on a wiring board,
The plurality of capacitor elements include a capacitor element group consisting of a plurality of capacitor elements arranged in the vicinity along a direction parallel to the main surface of the wiring board,
The main surfaces of the plurality of capacitor elements included in the capacitor element group that face the wiring board are all substantially rectangular.
The plurality of capacitor elements included in the capacitor element group are located on a straight line extending along a direction parallel to any one side of the principal surface of one capacitor element of the plurality of capacitor elements. And
Among the plurality of capacitor elements included in the capacitor element group, the directions of distortion generated when a voltage is applied on the opposing surfaces of adjacent capacitor elements are opposite to each other.
A circuit board in which a total amount of distortion generated in the plurality of capacitor elements in a direction in which the plurality of capacitor elements included in the capacitor element group is arranged is always substantially constant. The main surface of the plurality of capacitor elements included in the capacitor element group is a substantially rectangular shape having a pair of short sides and a pair of long sides,
The plurality of capacitor elements included in the capacitor element group have external electrodes at both ends along a direction parallel to the long side of each main surface,
The circuit board according to claim 1, wherein each of the external electrodes is electrically connected to a land provided corresponding to the wiring board via a conductive bonding member. A plurality of the capacitor element groups are provided,
The circuit board according to claim 1, wherein all capacitor elements included in the plurality of capacitor element groups are arranged in a straight line in the vicinity. A plurality of the capacitor element groups are provided,
The circuit board according to claim 1, wherein all the capacitor elements included in the plurality of capacitor element groups are arranged in a matrix in the vicinity.   5. The circuit board according to claim 1, wherein the lamination direction of each of the plurality of capacitor elements included in the capacitor element group is directed in the same direction. 6.   The circuit board according to claim 1, wherein the capacitor element group includes a pair of capacitor elements having equivalent specifications.   The circuit board according to claim 6, wherein a sum of absolute values of voltages applied to the pair of capacitor elements is always substantially constant. A capacitor element mounting method for mounting a plurality of substantially rectangular parallelepiped capacitor elements on a wiring board having a laminate composed of dielectric layers and internal electrode layers alternately laminated along a predetermined direction,
The plurality of capacitor elements include a capacitor element group consisting of a plurality of capacitor elements that are arranged in the vicinity along a direction parallel to the main surface of the wiring board,
The principal surfaces that face the wiring board of the plurality of capacitor elements included in the capacitor element group are all formed in a substantially rectangular shape,
The plurality of capacitor elements included in the capacitor element group are positioned on a straight line extending along a direction parallel to any one side of the principal surface of one capacitor element of the plurality of capacitor elements. Are arranged in the
Among the plurality of capacitor elements included in the capacitor element group, directions of distortion generated when a voltage is applied on opposite surfaces of adjacent capacitor elements are opposite to each other, and the plurality of capacitors included in the capacitor element group A mounting method for a capacitor element, wherein the plurality of capacitor elements are mounted on the wiring board so that the total amount of distortion generated in the plurality of capacitor elements is always substantially constant in the direction in which the elements are arranged. The main surfaces of the plurality of capacitor elements included in the capacitor element group are formed in a substantially rectangular shape having a pair of short sides and a pair of long sides,
The plurality of capacitor elements included in the capacitor element group have external electrodes at both ends along a direction parallel to the long side of each main surface,
When mounting the plurality of capacitor elements included in the capacitor element group on the wiring board, each of the external electrodes is electrically connected to a land provided corresponding to the wiring board via a conductive bonding member. The capacitor element mounting method according to claim 8, wherein the capacitor elements are connected to each other.   When there are a plurality of capacitor element groups, all the capacitor elements are mounted on the wiring board so that all the capacitor elements included in the plurality of capacitor element groups are arranged linearly in the vicinity. 10. The method of mounting a capacitor element according to claim 8, wherein the capacitor element is mounted.   When there are a plurality of capacitor element groups, all the capacitor elements are mounted on the wiring board so that all the capacitor elements included in the plurality of capacitor element groups are arranged in a matrix in the vicinity. 10. The method of mounting a capacitor element according to claim 8, wherein the capacitor element is mounted.   The plurality of capacitor elements are mounted on the wiring board so that the stacking direction of the multilayer body included in each of the plurality of capacitor elements included in the capacitor element group faces the same direction. The method for mounting a capacitor element according to claim 8.   The method of mounting a capacitor element according to any one of claims 8 to 12, wherein the capacitor element group includes a pair of capacitor elements having equivalent specifications.   14. The capacitor element according to claim 13, wherein the pair of capacitor elements are mounted on the wiring board so that a sum of absolute values of voltages applied to the pair of capacitor elements is always substantially constant. How to implement

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