JP2017147435A5

JP2017147435A5 -

Info

Publication number: JP2017147435A5
Application number: JP2016224025A
Authority: JP
Filing date: 2016-11-17
Publication date: 2019-12-26
Anticipated expiration: 2036-11-17

Description

エミッタトレンチ部６０は、ダイオード部８０が形成された領域に設けられる。エミッタトレンチ部６０は、ループ型の形状と直線型の形状の両方を有してよい。また、本例のエミッタトレンチ部６０は、ダミートレンチ部３０およびゲートトレンチ部４０とトレンチ幅が対応するように設けられている。但し、エミッタトレンチ部６０の形状は、トランジスタ部７０およびダイオード部８０のレイアウトに応じて適宜変更されてよい。 Emitter trench portion 60 is provided in a region where diode portion 80 is formed. The emitter trench portion 60 may have both a loop shape and a linear shape. Further, the emitter trench portion 60 of this example is provided so that the trench width corresponds to the dummy trench portion 30 and the gate trench portion 40 . However, the shape of the emitter trench section 60 may be appropriately changed according to the layout of the transistor section 70 and the diode section 80.

なお、ダイオード部８０においては、ベース領域１４のおもて面にコンタクト領域１５を形成せず、ベース領域１４のみとしてもよい。これにより、ダイオード部８０において、ドリフト領域１８への少数キャリアの過剰な注入を抑制できる。 In the diode section 80, the contact region 15 may not be formed on the front surface of the base region 14 and only the base region 14 may be provided. Thus, excessive injection of minority carriers into drift region 18 in diode section 80 can be suppressed.

ダイオード部８０ａは、活性領域１０２の一端に設けられる。ダイオード部８０ｂは、ダイオード部８０ａが設けられた活性領域１０２の一端と異なる他端に設けられている。本例のダイオード部８０ｂは、ダイオード部８０ａが設けられた一端と対向する活性領域１０２の端部に設けられている。このように、ダイオード部８０は、活性領域１０２の端部に配置されることにより、活性領域１０２の一端側においてトランジスタ部７０と接することがない。よって、ダイオード部８０に照射するヘリウムにより、トランジスタ部７０に与える影響が小さくなる。 The diode section 80a is provided at one end of the active region 102. The diode section 80b is provided at the other end different from one end of the active region 102 where the diode section 80a is provided. The diode section 80b of this example is provided at an end of the active region 102 opposite to one end where the diode section 80a is provided. As described above, since the diode unit 80 is arranged at the end of the active region 102, the diode unit 80 does not contact the transistor unit 70 at one end of the active region 102. Therefore, the influence of helium irradiated on the diode unit 80 on the transistor unit 70 is reduced.

本例の蓄積層１６は、トランジスタ部７０およびダイオード部８０の両方に形成される。更に本例の蓄積層１６の少なくとも一部は、ウェル領域１７内に形成されている。つまり、蓄積層１６は、ゲートランナ４６が形成された領域にも、蓄積層１６が形成されている。よって、本例の蓄積層１６は、トランジスタ部７０、ダイオード部８０およびゲートランナ４６が形成された領域に形成されている。ここで、断面図において、ウェル領域１７に形成された蓄積層を蓄積層１６ａとし、ウェル領域１７以外に形成された蓄積層を蓄積層１６ｂとして示している。蓄積層１６ｂは、ベース領域１４に形成されている。蓄積層１６ｂは、実施例８および９の蓄積層１６と同様にＮ型の高濃度層である。蓄積層１６ａは、蓄積層１６ｂのようにＮ型となる必要はない。即ち、蓄積層１６ａは、蓄積層１６ｂと同一のプロセスで形成されてよいが、ウェル領域１７に形成されるのでＰ型のままであってよい。また、ウェル領域１７の蓄積層１６ａには、Ｎ型の不純物が含まれていてよい。ウェル領域１７におけるＮ型の不純物の化学的な濃度は、ウェル領域１７のＰ型の不純物の化学的な濃度より低い。これにより、半導体装置１００は、耐圧および耐量の低下を抑制できる。なお、ダイオード部８０に蓄積層１６を形成する場合、おもて面側のライフタイムキラー４７が省略されてもよい。 The storage layer 16 of this example is formed in both the transistor section 70 and the diode section 80. Further, at least a part of the accumulation layer 16 of the present example is formed in the well region 17. That is, the accumulation layer 16 is also formed in the region where the gate runner 46 is formed. Therefore, the accumulation layer 16 of the present example is formed in a region where the transistor section 70, the diode section 80, and the gate runner 46 are formed. Here, in the cross-sectional view, the storage layer formed in the well region 17 is shown as a storage layer 16a, and the storage layer formed outside the well region 17 is shown as a storage layer 16b. The storage layer 16b is formed in the base region 14. The storage layer 16b is an N-type high concentration layer, like the storage layers 16 of the eighth and ninth embodiments. The storage layer 16a does not need to be N-type unlike the storage layer 16b. That is, the accumulation layer 16a may be formed by the same process as that of the accumulation layer 16b, but may be P-type since it is formed in the well region 17. Also, the storage layer 16 a well region 17 may contain a N-type impurity. The chemical concentration of the N-type impurity in the well region 17 is lower than the chemical concentration of the P-type impurity in the well region 17. Thereby, the semiconductor device 100 can suppress a decrease in the withstand voltage and the withstand voltage. When the storage layer 16 is formed in the diode section 80, the lifetime killer 47 on the front side may be omitted.

Claims

A semiconductor substrate;
A transistor portion formed on the semiconductor substrate;
A diode portion formed on the semiconductor substrate and having a lifetime killer on a front surface side of the semiconductor substrate;
A semiconductor device, comprising: a gate runner provided between the transistor unit and the diode unit, and electrically connected to a gate of the transistor unit.

2. The semiconductor device according to claim 1, wherein the semiconductor substrate has a lifetime killer in at least a part of a region on a front surface side of the semiconductor substrate and below the gate runner. 3.

The semiconductor device according to claim 1, wherein the semiconductor substrate has a lifetime killer in an entire area below the gate runner on a front surface side of the semiconductor substrate.

The semiconductor substrate according to any one of claims 1 to 3, wherein the semiconductor substrate has a lifetime killer in at least a part of a region on the front side of the semiconductor substrate and closer to the transistor section than the gate runner. 13. The semiconductor device according to claim 1.

The semiconductor device according to claim 1, wherein a collector region of the transistor unit is formed in at least a part of a region below the gate runner.

The semiconductor device according to claim 1, wherein a collector region of the transistor portion is formed in an entire region below the gate runner.

The semiconductor device according to claim 1, wherein a collector region of the transistor unit is formed in at least a part of a region closer to the diode unit than the gate runner.

The semiconductor device according to claim 1, wherein a cathode region of the diode unit is not formed below the gate runner.

The semiconductor device according to claim 1, further comprising a well region having a conductivity type different from that of the semiconductor substrate and formed below the gate runner.

The transistor portion includes a gate trench portion formed on a front surface of the semiconductor substrate,
The semiconductor device according to claim 1, wherein at least a part of the gate trench portion is formed below the gate runner.

The semiconductor device according to claim 1, wherein the diode unit is disposed at an end of an active region of the semiconductor device.

The semiconductor device according to claim 1, wherein the diode unit is disposed at a corner of an active region of the semiconductor device.

The semiconductor device according to claim 1, wherein the diode unit surrounds the periphery of the transistor unit in a plan view.

The semiconductor device according to claim 1, wherein the transistor unit surrounds the periphery of the diode unit in a plan view.

Disposed adjacent to the transistor portion, and the temperature sensor for detecting a signal corresponding to the temperature of the transistor unit,
It said temperature sensor and is electrically connected through a sensor wiring, the semiconductor device according to any one of claims 1 to 14, the detection signal of the temperature sensor further comprises a temperature sensor terminal input.

The semiconductor device according to claim 15, wherein the diode unit has a separation region where at least one of the gate runner and the sensor wiring crosses the diode unit.

The semiconductor device according to claim 15, wherein the temperature sensor is disposed above a well region.

The semiconductor device according to claim 15, wherein the temperature sensor is surrounded by the transistor unit.

The diode unit includes:
A first diode region formed at one end of an active region of the semiconductor device;
The semiconductor device according to claim 15, further comprising: a second diode region formed at the other end of the active region facing the one end.

The semiconductor device according to claim 19, wherein the temperature sensor is provided between the first diode region and the second diode region.

A first conductivity type emitter region formed on the front surface of the semiconductor substrate;
A second conductivity type base region formed on the front surface of the semiconductor substrate and different from the first conductivity type;
A first conductivity type accumulation layer formed on the front surface side of the semiconductor substrate and having a higher concentration than an impurity concentration of the semiconductor substrate;
And an interlayer insulating film formed on the front surface of the semiconductor substrate.
A contact hole penetrating the interlayer insulating film corresponding to at least a part of the emitter region and the base region;
The semiconductor device according to any one of claims 1 to 20, wherein the storage layer is formed inside a region where the contact hole is formed in a direction in which a trench portion of the transistor portion extends.

22. The semiconductor device according to claim 21, wherein the storage layer is formed inside a region where the contact hole is formed in a direction in which a trench portion of the diode portion extends.

23. The semiconductor device according to claim 21, wherein the storage layer is formed in a region where the transistor unit, the diode unit, and the gate runner are formed.

24. The semiconductor device according to claim 21, wherein at least a part of the storage layer is formed in a well region.

The semiconductor device according to any one of claims 21 to 24, wherein the contact hole on the diode part side is formed apart from a well region in plan view.

The semiconductor device according to any one of claims 1 to 25, wherein at least a part of an end of the trench portion of the transistor portion is formed in a well region.