JP2017142774A - ネットワークオンチップ方法によるメモリバンクのためのファブリック相互接続 - Google Patents
ネットワークオンチップ方法によるメモリバンクのためのファブリック相互接続 Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1657—Access to multiple memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0647—Migration mechanisms
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/067—Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/22—Alternate routing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
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Abstract
Description
102 第1メモリバンク
104 第2メモリバンク
106 インターフェースロジック
108 サブアレイ
110 インタコネクタ
120 メモリバンクアーキテクチャスキーム
122 Hツリールーティングレイアウト
124 サブアレイ
126 ワイヤ
200 記憶装置
202 ネットワークオンチップアーキテクチャ
204 ノード
206 ルーター
208 メモリアレイ
210 リンク
220 先入れ先出し装置(FIFO)
222 データパケット交換ロジック
230 アグリゲータ
280 モジュレータ/デモジュレータ
Claims (31)
- 記憶装置において、
複数のノードであって、各ノードが、
複数のFIFOであって、各FIFOが多数のチャネルにわたるクロックドメインの個別細分化を可能にする複数のFIFO、
データパケット交換ロジック、及び
前記データパケット交換ロジックに動作可能なように接続される少なくとも1つのアグリゲータ
を含むルーターと、
ネットワークオンチップアーキテクチャを使用して各複数ノードの各ルーターを相互接続する複数のリンクと、
少なくとも1つのメモリアレイであって、少なくとも1つ前記メモリアレイがリンク経由で各ルーターに動作可能なように接続され、且つ、各メモリアレイが前記ルーター経由でアクセスされる少なくとも1つのメモリアレイと
を含む、複数のノードを含む、記憶装置。 - 各ルーターが少なくとも1つの隣接ルーターに動作可能なように接続される、請求項1に記載の記憶装置。
- 前記複数のノードが複数の行及び複数の列を形成する、請求項1に記載の記憶装置。
- 各ルーター中の利用可能なメモリの量が前記ルーターの一連のアドレスを定義する、請求項1に記載の記憶装置。
- 前記記憶装置が、第1層に配置されるレイアウトを有する前記複数のノードを含む第1ルーターメッシュをさらに含む、請求項1に記載の記憶装置。
- 前記第1ルーターメッシュの内部がX及びY方向にモザイク細工されて複数のN×Nメッシュを形成するタイルを含む、請求項5に記載の記憶装置。
- 前記複数のFIFOが少なくとも6個のFIFOである、請求項1に記載の記憶装置。
- 前記複数のFIFOが少なくとも10個のFIFOである、請求項1に記載の記憶装置。
- 各メモリアレイが並列にアクセスされ得る、請求項1に記載の記憶装置。
- 記憶装置全体に給電することなく各ルーターがデータパケットの経路に沿って連続的にアクセスされる、請求項1に記載の記憶装置。
- 各ノードが異なる周波数で動作する、請求項1に記載の記憶装置。
- 各ノードが別々の電圧で動作する、請求項1に記載の記憶装置。
- 前記別々の電圧がオンザフライで選択される、請求項12に記載の記憶装置。
- 各チャネルが独立の動作周波数で動作する、請求項1に記載の記憶装置。
- 各チャネルが全二重チャネルであり、且つ、各チャネルが異なる帯域幅で動作する、請求項1に記載の記憶装置。
- 前記複数のノードが格子図形にパターン化される、請求項1に記載の記憶装置。
- 前記アグリゲータが少なくとも1つのFIFOに動作可能なように接続される、請求項1に記載の記憶装置。
- 記憶装置において、
それぞれ複数のFIFOを含む複数のルーターと、
複数の知的財産コアであって、1つの知的財産コアが各ルーターに結合される複数の知的財産コアと、
ネットワークオンチップアーキテクチャスキームを利用して前記複数のルーターのうちの隣接ルーター同士を結合する少なくとも1つのリンクと
を含む少なくとも1つの相互接続メモリセルマトリックスを含む、記憶装置。 - 前記メモリセルマトリックスがダイ上に広がっている、請求項18に記載の記憶装置。
- 各ルーターが少なくとも6個のFIFOを含む、請求項18に記載の記憶装置。
- 各ルーターが5対のFIFOを含む、請求項18に記載の記憶装置。
- 前記記憶装置が固体メモリである、請求項18に記載の記憶装置。
- 各ルーターが、データパケットを送り出し、且つ、前記知的財産コアから取り出すデータパケット交換ロジックをさらに含む、請求項18に記載の記憶装置。
- 各ルーターが少なくとも1つのアグリゲータをさらに含み、且つ、前記アグリゲータが前記データパケット交換ロジックに動作可能なように接続される、請求項23に記載の記憶装置。
- 各ルーター中の利用可能なメモリの量が前記ルーターの一連のアドレスを定義する、請求項18に記載の記憶装置。
- 記憶装置において、
複数のルーターであって、各ルーターが複数のFIFO、データパケット交換ロジック、及び少なくとも1つのアグリゲータを含み、且つ、前記アグリゲータが少なくとも1つのFIFO及び前記データパケット交換ロジックに動作可能なように接続される複数のルーターと、
複数の知的財産コアであって、ネットワークオンチップアーキテクチャスキームを利用して1つの知的財産コアがリンク経由で各ルーターに結合される複数の知的財産コアと
を含む少なくとも1つの相互接続メモリセルマトリックスを含む、記憶装置。 - 前記メモリセルマトリックスがダイ上に広がっている、請求項26に記載の記憶装置。
- 各ルーターが少なくとも6個のFIFOを含む、請求項26に記載の記憶装置。
- 各ルーターが5対のFIFOを含む、請求項26に記載の記憶装置。
- 前記記憶装置が固体メモリである、請求項26に記載の記憶装置。
- 各ルーター中の利用可能なメモリの量が前記ルーターの一連のアドレスを定義する、請求項26に記載の記憶装置。
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US11165717B2 (en) | 2021-11-02 |
US11546272B2 (en) | 2023-01-03 |
CN107038133B (zh) | 2021-12-28 |
KR20170054259A (ko) | 2017-05-17 |
CN107038133A (zh) | 2017-08-11 |
KR101956855B1 (ko) | 2019-03-12 |
US20220014480A1 (en) | 2022-01-13 |
DE102016012739A1 (de) | 2017-04-27 |
JP6595437B2 (ja) | 2019-10-23 |
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