US8391281B2 - Router design for 3D network-on-chip - Google Patents

Router design for 3D network-on-chip Download PDF

Info

Publication number
US8391281B2
US8391281B2 US12/751,811 US75181110A US8391281B2 US 8391281 B2 US8391281 B2 US 8391281B2 US 75181110 A US75181110 A US 75181110A US 8391281 B2 US8391281 B2 US 8391281B2
Authority
US
United States
Prior art keywords
data
network
router
input
according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US12/751,811
Other versions
US20110243147A1 (en
Inventor
Bipul C. Paul
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba America Research Inc
Original Assignee
Toshiba America Research Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba America Research Inc filed Critical Toshiba America Research Inc
Priority to US12/751,811 priority Critical patent/US8391281B2/en
Assigned to TOSHIBA AMERICA RESEARCH, INC. reassignment TOSHIBA AMERICA RESEARCH, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PAUL, BIPUL C.
Publication of US20110243147A1 publication Critical patent/US20110243147A1/en
Application granted granted Critical
Publication of US8391281B2 publication Critical patent/US8391281B2/en
Application status is Active legal-status Critical
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/60Router architecture

Abstract

A network-on-chip router which includes an input buffer, an input controller connected to said input buffer, an arbiter connected to said input controller, a crossbar connected to said arbiter and said input buffer, and an output buffer connected to said crossbar. The network-on-chip router minimizes propagation time of data through the router by ensuring that the propagation delay of data through an input buffer is less than the combined propagation delay of data through an input controller and arbiter.

Description

FIELD OF THE INVENTION

The present invention relates, e.g., to high performance multi-core processors, and in preferred embodiments, asynchronous network-on-chip routers.

BACKGROUND

Routing design specific global on chip wires for system-on-chip (SOCs) can be costly and inefficient. Instead, on-chip routers have been developed to route packets. Network-on-chip (NOC) routers route packets of data to and from desired locations on an integrated circuit. The performance of NOC routers depends on the communication infrastructure built into the chip. Latency and throughput define the performance of an NOC router, and high performance NOC routers look to achieve low power consumption, high data rates, and minimal area usage.

Various router designs including both synchronous and asynchronous designs have been explored for network-on-chip (NOC) applications. Routing algorithms such as wormhole, virtual channel, etc., have also been extensively studied. While asynchronous routers are expected to perform better than synchronous routers in NOC applications, the design of asynchronous routers is far more complicated than the design of synchronous routers.

One the other hand, a wormhole routing algorithm, where a chain of data (also called flits) propagates through the network like a worm when a path is available, is easy to implement compared to a virtual channel router, but is less efficient than the latter under congestion conditions, and consequently reduces throughput.

In virtual channel routing, during congestion, the entire data chain (packet) needs to be stored inside a router to clear the channel for other incoming packets and hence, virtual channel routing is complicated to design and requires larger storage space. This additional storage space can increase power consumption and require more area on the chip. Further, various lengths and types of buffer implementations have been explored to store data inside a router. However, to maximize the network performance in terms of latency and throughput, these techniques need to be optimized through better designs and implementations.

SUMMARY

The preferred embodiments of the present invention improve upon the foregoing and other background technologies. In this disclosure, a full custom design of an asynchronous router suitable for 3 dimensional (3D) NOC topologies is explained. The 3D NOC router uses an optimized cascaded input buffer of optimal length instead of a typical FIFO (First-In-First-Out), in order to maximize performance while keeping the design simple. It also uses a pass transistor or transmission gate based crossbar to minimize the crossbar delay. This also consumes less area on the chip and less power. Although this design is suitable for a 3D NOC, it is applicable to any two dimensional (2D) NOC structure as well.

An advantage of the present 3D NOC router is low power consumption, reduced area on the chip, and low latency (due to asynchronous and full custom design). Further, no synchronization issues arise as the 3D NOC router uses an asynchronous design.

The asynchronous, 3D NOC router has been developed with a wormhole routing algorithm. The router uses cascaded latches for an input buffer to achieve a compact and low power design, while maintaining the maximum length of the buffer so that the data propagation delay is less than the combined delay of the input controller and the arbiter. This ensures that the input buffer delay does not affect the overall router delay.

The NOC router also uses a single stage output buffer, which besides providing extra storage, helps restore the full swing of data from the crossbar and provides signal boost to the output channel. Further, the NOC router uses a transmission or pass gate based crossbar switch for fast, compact and low-power router operation. Also, a logic gate based implementation of an adaptive routing algorithm realizes a fast, low power consumption and reduced area router.

According to an embodiment of the invention, a network-on-chip router includes an input buffer, an input controller connected to the input buffer, an arbiter connected to said input controller, a crossbar connected to the arbiter and said input buffer, and an output buffer connected to the crossbar.

According to another aspect of the invention, the propagation delay of data through the input buffer is lower than a combined propagation delay of data through the input controller and the arbiter.

According to another aspect of the invention, the input buffer comprises a first data latch and a second data latch arranged in series so that an output of the first data latch is an input of the second data latch.

The above and/or other aspects, features and/or advantages of various embodiments will be further appreciated in view of the following description in conjunction with the accompanying figures. Various embodiments can include and/or exclude different aspects, features and/or advantages where applicable. In addition, various embodiments can combine one or more aspect or feature of other embodiments where applicable. The descriptions of aspects, features and/or advantages of particular embodiments should not be construed as limiting other embodiments or the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of embodiments of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a schematic diagram of data flow from an input to an output of the NOC router;

FIG. 2(A) is a circuit diagram of an initialization circuit for the input buffer controller;

FIG. 2(B) is a circuit diagram of an input buffer controller of the NOC router;

FIG. 3 is a schematic diagram of cascaded data latches for an input buffer in the NOC router;

FIG. 4 is a schematic of an input controller of the NOC router;

FIG. 5 is an address control circuit of the input controller of the NOC router;

FIG. 6 is a selection circuit of the input controller of the NOC circuit;

FIG. 7 is a schematic diagram of a crossbar switch array in the NOC router;

FIG. 8(A) is a crossbar switch using a transmission gate;

FIG. 8(B) is a crossbar switch using a pass transistor;

FIG. 9 is a circuit diagram of an output buffer control circuit of the NOC router;

FIG. 10 is a single stage output buffer of the NOC router, and

FIG. 11 is a synchronization circuit for the signal Mcnt1 between two adjacent NOC routers.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

While the present invention may be embodied in many different forms, a number of illustrative embodiments are described herein with the understanding that the present disclosure is to be considered as providing examples of the principles of the invention and such examples are not intended to limit the invention to preferred embodiments described herein and/or illustrated herein.

FIG. 1 shows a schematic diagram of data flow from an input of the NOC router 1 to the output of the NOC router 1, based on an adaptive wormhole routing algorithm. The NOC router 1 includes an input buffer 20, an input controller 40, an arbiter 60, a crossbar switch 80 and an output buffer 100. In the multi-port router 1, each input port has a separate input buffer and a separate input controller and each output port has separate output buffer. NOC router 1 uses both input and output buffers.

Input buffer 20 is used to temporarily store incoming data to NOC router 1 to prevent any interruption in data transmission due to congestion at the output port. Conversely, output buffer 100 provides extra storage and helps restore the full swing of data from crossbar 80 and provides signal boost to the output channel.

The input controller 40 selects the appropriate output port based on the destination address of the data. Once the appropriate output port is determined by the input controller 40, arbiter 60 assigns the data to a particular output port. The corresponding crossbar 80 switches are then enabled for data transmission to the next router/destination.

FIG. 2(A) shows a design of the input buffer controller 40. The control signal ‘Mct1,’ generated by the source (processing element) or propagated from a previous output port, is responsible for data propagation through the router. The ‘RST’ signal is generated to reset all latches before a new communication is started. The ‘RESET’ pulse is only used during power-up to initialize all latch outputs to zero before the network operation. When ‘Mct1’ goes high, a new communication starts and data starts flowing through the cascaded latches asynchronously, as shown in FIG. 3.

A pulse train is generated at the source which propagates through the cascaded latches shown in FIG. 2(B) and generates control signals ‘Control1,’ ‘Control2,’ and ‘Control3,’ which act as clocks for the data latches 22 a, 22 b and 22 c, shown in FIG. 3. The signal ‘Cont1’ controls the data flow to the output port based on the status of the output buffer 100. When ‘Cont1’ is high, the D-latch (e.g. 22 c) is enabled if the data at the latch input is not equal to its output. The latch then generates a control pulse, e.g. ‘Control3’. This control pulse then propagates the data in the data latch (FIG. 3). Subsequently, data from previous latches also propagate through the input buffer.

The number of cascaded latches can be varied according to the network design, and the maximum number is chosen so that the data propagation delay is less than the combined delay of the input controller 40 and the arbiter 60. Thus, if the delay from the input controller 40 is x1 and the delay from the arbiter 60 is x2, and the delay from the cascaded data latches is x3, then x3 is <(x1+x2).

Having the delay from the data latches lower than the delay of the input controller and arbiter ensures that the input buffer delay does not affect the router latency, while keeping the design simple, resulting in less area and lower power consumption compared to a FIFO (first-in-first-out) queue design.

FIG. 4 shows the schematic block diagram of the input controller 40 in the asynchronous NOC router 1. It includes address control logic 41, address bit selector 42, level comparator 43, row comparator 44, column comparator 45, and a turn evaluator 46.

The present embodiment uses an adaptive shortest path algorithm in order to route the packets, discussed in detail below. The level comparator 43 determines if the packets need to go to an adjacent level, or stay on the same level. The row comparator 44 determines if the packets need to go to an adjacent row, or stay in the same row. The column comparator 45 determines if the packets need to go to an adjacent column, or stay in the same column.

The turn evaluator 46 then determines the appropriate turn the packets should take, based on the level, row and column comparators.

The address control circuit is shown in FIG. 5, which generates a control signal to latch address bits (shown in FIG. 6) from the first set of data (flits) of a packet when ‘RST’ (generated as shown in FIG. 2(A)) goes to high. The latched address bits are then compared with the coordinate of the local router and appropriate output ports are selected adaptively. The comparator circuits 43, 44 and 45 are logic based, unlike conventional look-up table based designs. Further, an ‘odd-even’ turn control circuit can be used to prevent any deadlock situation in the network.

One advantage of the input controller design in the present embodiment is that it uses shortest path adaptive routing, which does not need any congestion information from neighboring routers. Thus, the route that a packet will take will be a shortest possible route.

Based on the allowed turn evaluation, the input controller 40 then sends the output port requests to the arbiter 60. The arbiter 60 then grants one of the available output ports based on the request, or if none of the requested ports is available, (i.e., presently used by other input ports) then the requests are stored in a FIFO. Once one of the requested output ports is available, a control signal is generated for corresponding crossbar switches to establish a channel between the input and output ports.

FIG. 7 shows a schematic of the proposed crossbar switch array which uses transmission or pass gates (FIG. 8). Unlike tri-gate or multiplexer based crossbar arrays conventionally used in a NOC router, the present embodiment, using transmission gates or pass transistors, is designed to be fast, compact (low area) and consume less power than a conventional router.

FIG. 9 shows the control circuit of an output port of the NOC router 1. The signal ‘Mct1_nR’ controls if the following router's input port is ready for data communication. Based on the crossbar control signal, ‘Xbar_ct1’ and ‘Mct1_nR,’ the reset signal ‘RST’ is generated to initialize the communication. The ‘Cont1’ signal provides the present data status in the input buffer of the following router and controls the data flow in the channel in an asynchronous fashion. Once the input to the output channel is established by the crossbar link, the pulse train from the input buffer 20 controls the data flow to the output of the NOC router 1 and generates the control signal ‘Control’ for data flowing through the output latch 102 shown in FIG. 10. The output buffer 100 restores the full swing of data from crossbar 80 and provides a signal boost to the output channel, in addition to providing storage for the data under congestion.

FIG. 10 shows the single stage output buffer of the NOC router 1. Data latches provide the single stage buffer.

FIG. 11 shows the synchronization circuit of the control signal ‘Mcnt1’ between two subsequent router ports. This signal controls the overall data communication asynchronously between a source or an output port of a router and the flowing input port of an adjacent router.

While illustrative embodiments of the invention are set forth and described herein, the present invention is not limited to the various preferred embodiments described herein, but includes any and all embodiments having equivalent elements, modifications, omissions, combinations (e.g., of aspects across various embodiments), adaptations and/or alterations as would be appreciated by those in the art based on the present disclosure. The limitations in the claims (e.g., including that to be later added) are to be interpreted broadly based on the language employed in the claims and not limited to examples described in the present specification or during the prosecution of the application, which examples are to be construed as non-exclusive. For example, in the present disclosure, the term “preferably” is nonexclusive and means “preferably, but not limited to.” In this disclosure and during the prosecution of this application, means-plus-function or step-plus-function limitations will only be employed where for a specific claim limitation all of the following conditions are present in that limitation: a) “means for” or “step for” is expressly recited; b) a corresponding function is expressly recited; and c) structure, material or acts that support that structure are not recited. In this disclosure and during the prosecution of this application, the terminology “present invention” or “invention” may be used as a reference to one or more aspect within the present disclosure. The language present invention or invention should not be improperly interpreted as an identification of criticality, should not be improperly interpreted as applying across all aspects or embodiments (i.e., it should be understood that the present invention has a number of aspects and embodiments), and should not be improperly interpreted as limiting the scope of the application or claims. In this disclosure and during the prosecution of this application, the terminology “embodiment” can be used to describe any aspect, feature, process or step, any combination thereof, and/or any portion thereof, etc. In some examples, various embodiments may include overlapping features. In this disclosure, the following abbreviated terminology may be employed: “e.g.” which means “for example.”

Claims (19)

1. A network-on-chip router comprising:
an input buffer,
an input controller connected to said input buffer,
an arbiter connected to said input controller,
a crossbar connected to said arbiter and said input buffer, and
an output buffer connected to said crossbar,
wherein the propagation delay of data through the input buffer is lower than a combined propagation delay of data through the input controller and the arbiter.
2. The network-on-chip router according to claim 1, wherein said input buffer comprises:
a first data latch and a second data latch, arranged in series so that an output of the first data latch is an input of the second data latch.
3. The Network-on-chip router according to claim 2, wherein said input buffer further comprises:
a plurality of data latches arranged in a cascaded design.
4. The network-on-chip router according to claim 1, wherein said router is asynchronous.
5. The network-on-chip router according to claim 1, wherein said crossbar uses transmission gates.
6. The network-on-chip router according to claim 1, wherein said crossbar uses pass transistors.
7. The network-on-chip router according to claim 1, wherein said output buffer has a single stage.
8. The network-on-chip router according to claim 7, wherein said single stage output buffer uses a data latch.
9. The Network-on-chip router according to claim 1, wherein the input controller comprises:
a level comparator,
a row comparator, and
a column comparator.
10. The network-on-chip router according to claim 9, where the input controller further comprises:
a turn evaluator which is connected to the level comparator, row comparator and column comparator.
11. The network-on-chip router according to claim 8, wherein the output buffer further comprises:
a control circuit for each data latch,
wherein the control circuit is logic based.
12. The network-on-chip router according to claim 1, wherein:
said router is an adaptive router.
13. The network-on-chip router of claim 1,
wherein said router uses a shortest path routing algorithm.
14. A method of routing data on an integrated circuit using a network-on-chip router, comprising:
receiving data into a cascaded input buffer,
propagating the data through the cascaded input buffer and into an input controller and then propagating the data into an arbiter,
wherein the propagation delay through the cascaded input buffer is less than a combined propagation delay through the input controller and the arbiter, and
outputting the data from the network-on-chip router to another node.
15. The method of routing data according to claim 14, further comprising:
propagating the data from the input buffer to a crossbar.
16. The method of routing data according to claim 14, further comprising:
propagating the data from a crossbar to an output buffer.
17. The method of routing data according to claim 14, wherein the router uses a shortest path adaptive algorithm to route the data to a next node.
18. The method of routing data according to claim 14, wherein the input controller only uses logic based circuits.
19. The method of routing data according to claim 14, wherein the router only uses logic based circuits.
US12/751,811 2010-03-31 2010-03-31 Router design for 3D network-on-chip Active 2031-04-04 US8391281B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/751,811 US8391281B2 (en) 2010-03-31 2010-03-31 Router design for 3D network-on-chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/751,811 US8391281B2 (en) 2010-03-31 2010-03-31 Router design for 3D network-on-chip

Publications (2)

Publication Number Publication Date
US20110243147A1 US20110243147A1 (en) 2011-10-06
US8391281B2 true US8391281B2 (en) 2013-03-05

Family

ID=44709628

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/751,811 Active 2031-04-04 US8391281B2 (en) 2010-03-31 2010-03-31 Router design for 3D network-on-chip

Country Status (1)

Country Link
US (1) US8391281B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104243330A (en) * 2014-10-10 2014-12-24 南京大学 Low-density vertical interconnection oriented three-dimensional on-chip network router
CN104270279A (en) * 2014-10-28 2015-01-07 电子科技大学 On-line error detection circuit for fault of NoC (Network-on-Chip) illegal path
US20150049758A1 (en) * 2013-08-13 2015-02-19 Utah State University Hot carrier injection tolerant network on chip router architecture
CN105871742A (en) * 2016-03-24 2016-08-17 合肥工业大学 Adaptive router in NoC (network-on-chip) on basis of virtual output queue mechanism
US20170118139A1 (en) * 2015-10-26 2017-04-27 HGST Netherlands B.V. Fabric interconnection for memory banks based on network-on-chip methodology
US10103913B2 (en) * 2015-03-25 2018-10-16 Washington State University Systems and methods for network routing in small-world network-on-chip devices
US10193827B2 (en) 2013-08-13 2019-01-29 Dean Michael Ancajas Hot carrier injection tolerant network on chip router architecture
US10243881B2 (en) 2015-10-27 2019-03-26 Western Digital Technologies, Inc. Multilayer 3D memory based on network-on-chip interconnection

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013105931A1 (en) * 2012-01-10 2013-07-18 Intel Corporation Router parking in power-efficient interconnect architectures
CN102546417B (en) * 2012-01-14 2014-07-23 西安电子科技大学 Scheduling method of network-on-chip router based on network information
CN102821046B (en) * 2012-08-03 2015-05-06 北京理工大学 Output buffer system of on-chip network router
US9781043B2 (en) * 2013-07-15 2017-10-03 Netspeed Systems Identification of internal dependencies within system components for evaluating potential protocol level deadlocks
CN103581031A (en) * 2013-10-15 2014-02-12 复旦大学 Configurable on-chip router model used for heterogeneous multi-core on-chip network modeling
US9699079B2 (en) 2013-12-30 2017-07-04 Netspeed Systems Streaming bridge design with host interfaces and network on chip (NoC) layers
US9419912B2 (en) * 2014-02-11 2016-08-16 International Business Machines Corporation Selective underflow protection in a network switch
US9928204B2 (en) * 2015-02-12 2018-03-27 Netspeed Systems, Inc. Transaction expansion for NoC simulation and NoC design
US10348563B2 (en) 2015-02-18 2019-07-09 Netspeed Systems, Inc. System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology
US10116557B2 (en) * 2015-05-22 2018-10-30 Gray Research LLC Directional two-dimensional router and interconnection network for field programmable gate arrays, and other circuits and applications of the router and network
WO2016191304A1 (en) * 2015-05-22 2016-12-01 Gray Research LLC Directional two-dimensional router and interconnection network for field programmable gate arrays, and other circuits, and applications of the router and network
US10218580B2 (en) 2015-06-18 2019-02-26 Netspeed Systems Generating physically aware network-on-chip design from a physical system-on-chip specification
CN106209518B (en) * 2016-08-08 2019-01-11 合肥工业大学 One kind being based on the dynamic steering routing algorithm of " packet-circuit " switching technology

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080205432A1 (en) * 2005-04-07 2008-08-28 Koninklijke Philips Electronics, N.V. Network-On-Chip Environment and Method For Reduction of Latency
US20080294803A1 (en) * 2007-05-24 2008-11-27 Stmicroelectronics S.R.L. Method and system for full-duplex mesochronous communications and corresponding computer program product
US7518408B2 (en) * 2006-09-13 2009-04-14 Stmicroelectronics Sa Synchronizing modules in an integrated circuit
US20090147783A1 (en) * 2007-11-13 2009-06-11 Stmicroelectronics (Grenoble) Sas Buffering architecture for packet injection and extraction in on-chip networks
US20090292907A1 (en) * 2008-05-22 2009-11-26 Stephen Joseph Schwinn Dynamic Merging of Pipeline Stages in an Execution Pipeline to Reduce Power Consumption
US20100115483A1 (en) * 2008-10-30 2010-05-06 M2000 Sa. Crossbar structure with mechanism for generating constant outputs
US7739460B1 (en) * 2004-08-30 2010-06-15 Integrated Device Technology, Inc. Integrated circuit memory systems having write-back buffers therein that support read-write-modify (RWM) operations within high capacity memory devices
US20100211720A1 (en) * 2009-02-13 2010-08-19 The Regents Of The University Of Michigan Crossbar circuitry and method of operation of such crossbar circuitry
US7826460B2 (en) * 2006-10-10 2010-11-02 Samsung Electronics Co., Ltd Network-on-chip apparatus, and method for controlling dynamic frequency for the same
US20110064087A1 (en) * 2009-09-14 2011-03-17 Lan Ying-Cherng Method for Dynamical Adjusting Channel Direction and Network-on-Chip Architecture thereof
US7957381B2 (en) * 2005-03-08 2011-06-07 Commissariat A L'energie Atomique Globally asynchronous communication architecture for system on chip
US8040799B2 (en) * 2008-05-15 2011-10-18 International Business Machines Corporation Network on chip with minimum guaranteed bandwidth for virtual communications channels

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7739460B1 (en) * 2004-08-30 2010-06-15 Integrated Device Technology, Inc. Integrated circuit memory systems having write-back buffers therein that support read-write-modify (RWM) operations within high capacity memory devices
US7957381B2 (en) * 2005-03-08 2011-06-07 Commissariat A L'energie Atomique Globally asynchronous communication architecture for system on chip
US20080205432A1 (en) * 2005-04-07 2008-08-28 Koninklijke Philips Electronics, N.V. Network-On-Chip Environment and Method For Reduction of Latency
US7518408B2 (en) * 2006-09-13 2009-04-14 Stmicroelectronics Sa Synchronizing modules in an integrated circuit
US7826460B2 (en) * 2006-10-10 2010-11-02 Samsung Electronics Co., Ltd Network-on-chip apparatus, and method for controlling dynamic frequency for the same
US20080294803A1 (en) * 2007-05-24 2008-11-27 Stmicroelectronics S.R.L. Method and system for full-duplex mesochronous communications and corresponding computer program product
US7792030B2 (en) * 2007-05-24 2010-09-07 Stmicroelectronics S.R.L. Method and system for full-duplex mesochronous communications and corresponding computer program product
US20090147783A1 (en) * 2007-11-13 2009-06-11 Stmicroelectronics (Grenoble) Sas Buffering architecture for packet injection and extraction in on-chip networks
US8040799B2 (en) * 2008-05-15 2011-10-18 International Business Machines Corporation Network on chip with minimum guaranteed bandwidth for virtual communications channels
US8291201B2 (en) * 2008-05-22 2012-10-16 International Business Machines Corporation Dynamic merging of pipeline stages in an execution pipeline to reduce power consumption
US20090292907A1 (en) * 2008-05-22 2009-11-26 Stephen Joseph Schwinn Dynamic Merging of Pipeline Stages in an Execution Pipeline to Reduce Power Consumption
US20100115483A1 (en) * 2008-10-30 2010-05-06 M2000 Sa. Crossbar structure with mechanism for generating constant outputs
US20100211720A1 (en) * 2009-02-13 2010-08-19 The Regents Of The University Of Michigan Crossbar circuitry and method of operation of such crossbar circuitry
US20110064087A1 (en) * 2009-09-14 2011-03-17 Lan Ying-Cherng Method for Dynamical Adjusting Channel Direction and Network-on-Chip Architecture thereof

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
Edith Beigne et al. "An Asynchronous Power Aware and Adaptive NOC Based Circuit" IEEE Journal of Solid-State Circuits, Apr. 2009, pp. 1167-1177, vol. 44, No. 4.
Ge-Ming Chiu "The Odd-Even Turn Model for Adaptive Routing," IEEE Transactions on Parallel and Distributed Systems, Jul. 2000, pp. 729-738, vol. 11, No. 7.
Jingcao Hu et al. "DyAD-Smart Routing for Networks-on-Chip" Proceeding of Design Automation Conference (DAC), 2004, pp. 260-263.
Jingcao Hu et al. "DyAD—Smart Routing for Networks-on-Chip" Proceeding of Design Automation Conference (DAC), 2004, pp. 260-263.
Vassos Soteriou et al. "A High-Throughput Distributed Shared-Buffer NoC Router" IEEE Computer Architecture Letters, 2009, pp. 21-24, vol. 8, No. 1.

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150049758A1 (en) * 2013-08-13 2015-02-19 Utah State University Hot carrier injection tolerant network on chip router architecture
US10193827B2 (en) 2013-08-13 2019-01-29 Dean Michael Ancajas Hot carrier injection tolerant network on chip router architecture
CN104243330A (en) * 2014-10-10 2014-12-24 南京大学 Low-density vertical interconnection oriented three-dimensional on-chip network router
CN104270279A (en) * 2014-10-28 2015-01-07 电子科技大学 On-line error detection circuit for fault of NoC (Network-on-Chip) illegal path
CN104270279B (en) * 2014-10-28 2017-07-18 电子科技大学 A network-on-chip error detecting illegal path circuit fault line
US10103913B2 (en) * 2015-03-25 2018-10-16 Washington State University Systems and methods for network routing in small-world network-on-chip devices
US20170118139A1 (en) * 2015-10-26 2017-04-27 HGST Netherlands B.V. Fabric interconnection for memory banks based on network-on-chip methodology
US10243881B2 (en) 2015-10-27 2019-03-26 Western Digital Technologies, Inc. Multilayer 3D memory based on network-on-chip interconnection
CN105871742B (en) * 2016-03-24 2018-12-21 合肥工业大学 Adaptive router based on virtual output queue mechanism in a kind of network-on-chip
CN105871742A (en) * 2016-03-24 2016-08-17 合肥工业大学 Adaptive router in NoC (network-on-chip) on basis of virtual output queue mechanism

Also Published As

Publication number Publication date
US20110243147A1 (en) 2011-10-06

Similar Documents

Publication Publication Date Title
Scott et al. The blackwidow high-radix clos network
Michelogiannakis et al. Elastic buffer flow control for on-chip networks
Kim et al. Flattened butterfly topology for on-chip networks
US7830905B2 (en) Speculative forwarding in a high-radix router
Michelogiannakis et al. Evaluating bufferless flow control for on-chip networks
Zeferino et al. RASoC: A router soft-core for networks-on-chip
JP3816530B2 (en) Low latency, high clock frequency, Purejio asynchronous packet-based crossbar switching chip system and method
US7039058B2 (en) Switched interconnection network with increased bandwidth and port count
Abad et al. Rotary router: an efficient architecture for CMP interconnection networks
US8285900B2 (en) Method and apparatus for congestion-aware routing in a computer interconnection network
Lee et al. Low-power network-on-chip for high-performance SoC design
Wielage et al. Networks on silicon: blessing or nightmare?
US7046633B2 (en) Router implemented with a gamma graph interconnection network
JP4520742B2 (en) Asynchronous and techniques to facilitate the conversion between the synchronization area
US6308220B1 (en) Circulating parallel-search engine with random inputs for network routing table stored in a wide embedded DRAM
US20080211538A1 (en) Flexible wrapper architecture for tiled networks on a chip
Flich et al. Logic-based distributed routing for NoCs
US8352774B2 (en) Inter-clock domain data transfer FIFO circuit
EP1670199B1 (en) Design of channel alignment, error handling, and clock routing using hard-wired blocks for data transmission within programmable logic integrated circuits
Agarwal et al. Survey of network on chip (noc) architectures & contributions
US8316171B2 (en) Network on chip (NoC) with QoS features
US20020049901A1 (en) System and method for implementing source based and egress based virtual networks in an interconnection network
Gratz et al. Implementation and evaluation of on-chip network architectures
US9111151B2 (en) Network on chip processor with multiple cores and routing method thereof
US7467358B2 (en) Asynchronous switch based on butterfly fat-tree for network on chip application

Legal Events

Date Code Title Description
AS Assignment

Owner name: TOSHIBA AMERICA RESEARCH, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PAUL, BIPUL C.;REEL/FRAME:024514/0062

Effective date: 20100422

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4