JP2017120880A - Multi-layer ceramic electronic component and method of producing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of producing a multi-layer ceramic electronic component, which is capable of providing a side margin in a subsequent step while preventing a short circuit between internal electrodes.SOLUTION: In a method of producing a multi-layer ceramic electronic component, a multi-layer sheet including a plurality of laminated ceramic sheets and a plurality of internal electrodes disposed between the plurality of ceramic sheets is prepared. By cutting the multi-layer sheet, a multi-layer chip 116 having side surfaces P, Q from which the plurality of internal electrodes are exposed is produced. A surface layer of the side surface of the multi-layer chip is removed by a surface layer removing apparatus 300, and a side margin is provided to the side surface of the multi-layer chip, the surface layer of the multi-layer chip having been removed. With this configuration, the surface layer of the side surface of the multi-layer chip to which the side margin is provided is previously removed. This can prevent a short circuit between the internal electrodes in the side surface of the multi-layer chip due to drag of the internal electrodes, adhesion of foreign substances and the like in cutting the multi-layer sheet.SELECTED DRAWING: Figure 10

Description

  The present invention relates to a multilayer ceramic electronic component to which a side margin portion is retrofitted and a method for manufacturing the same.

  In recent years, with the miniaturization and high performance of electronic devices, there is an increasing demand for miniaturization and large capacity for multilayer ceramic capacitors used in electronic devices. In order to meet this demand, it is effective to enlarge the internal electrodes of the multilayer ceramic capacitor. In order to enlarge the internal electrode, it is necessary to thin the side margin portion for ensuring the insulation around the internal electrode.

  On the other hand, in a general method for manufacturing a multilayer ceramic capacitor, it is difficult to form a side margin portion having a uniform thickness due to the accuracy of each step (for example, patterning of internal electrodes, cutting of a multilayer sheet, etc.). Therefore, in such a method for manufacturing a multilayer ceramic capacitor, it becomes more difficult to ensure the insulation around the internal electrode as the side margin portion is made thinner.

  Patent Document 1 discloses a technique for retrofitting a side margin portion. That is, in this technique, by cutting the laminated sheet, a laminated chip with the internal electrode exposed on the side surface is produced, and a side margin portion is provided on the side surface of the laminated chip. As a result, a side margin portion having a uniform thickness can be formed, so that insulation around the internal electrode can be ensured even when the side margin portion is thinned.

JP 2012-209539 A

  A cutting method using a push blade or a rotary blade is widely used for cutting the laminated sheet, and the laminated sheet is cut into each laminated chip by various blades (blades). At this time, the blade that is cutting the laminated sheet may drag the internal electrode, and the internal electrode may be stretched along the cut surface. As a result, when adjacent internal electrodes on the side surface of the multilayer chip are short-circuited, a multilayer ceramic capacitor having the intended performance cannot be obtained.

  In view of the circumstances as described above, an object of the present invention is to provide a multilayer ceramic electronic component capable of retrofitting a side margin portion while preventing a short circuit of an internal electrode, and a manufacturing method thereof.

In order to achieve the above object, in a method of manufacturing a multilayer ceramic electronic component according to an aspect of the present invention, a plurality of laminated ceramic sheets, and a plurality of internal electrodes disposed between the plurality of ceramic sheets, A laminated sheet is prepared.
By cutting the laminated sheet, a laminated chip having a side surface from which the plurality of internal electrodes are exposed is produced.
The surface layer on the side surface of the multilayer chip is removed.
Side margin portions are provided on the side surfaces of the laminated chip from which the surface layer has been removed.
In this configuration, the surface layer on the side surface of the laminated chip provided with the side margin portion is removed in advance. As a result, it is possible to prevent a short circuit between the internal electrodes on the side surface of the multilayer chip due to dragging of the internal electrodes or adhesion of foreign matters when the laminated sheet is cut.

The laminated sheet may be cut by a press cutting blade or a rotary blade.
In this configuration, even when the laminated sheet is cut by a push cutting blade or a rotary blade that is relatively easy to drag the internal electrodes, short-circuiting between the internal electrodes on the side surface of the laminated chip can be prevented.

The surface layer may be removed by grinding the side surface of the multilayer chip.
The surface layer may be removed by blasting the side surface of the multilayer chip.
According to these configurations, a short circuit between the internal electrodes on the side surface of the multilayer chip can be effectively prevented.

The surface layer may be removed by irradiating the side surface of the multilayer chip with a laser.
You may irradiate the said laser to the several irradiation area | region which overlaps on the said side surface of the said laminated chip. As a result, even when the laser spot diameter is small, the entire region on the side surface of the chip can be irradiated with no gap.
The plurality of irradiation areas may be rectangular. Thereby, since the overlap amount of the irradiation region can be reduced, it becomes possible to efficiently irradiate the laser to the entire region on the side surface of the chip.
The laser may have a top hat type power distribution. Thereby, the output distribution of the laser becomes uniform in the entire irradiation region. Therefore, in this configuration, the positions and intervals of the irradiation regions can be determined without considering the laser output distribution.

A multilayer ceramic electronic component according to another aspect of the present invention includes a multilayer chip and a side margin portion.
The multilayer chip has a plurality of ceramic layers stacked in a first direction, a plurality of internal electrodes disposed between the plurality of ceramic layers, and a second direction orthogonal to the first direction, And a side surface adjacent to the end of the internal electrode and having a laser overlap mark formed thereon.
The side margin portion covers the side surface of the multilayer chip.

In the overlap mark, pores may be formed at the end portions of the plurality of internal electrodes.
The overlap marks may be arranged at a predetermined interval.
The overlap mark may form a predetermined pattern.

  In these configurations, since the surface layer is removed by laser irradiation without gaps on the side surfaces of the multilayer chip, a short circuit between the internal electrodes on the side surfaces of the multilayer chip can be effectively prevented.

  A multilayer ceramic electronic component capable of retrofitting a side margin while preventing a short circuit of an internal electrode and a manufacturing method thereof can be provided.

1 is a perspective view of a multilayer ceramic capacitor according to a first embodiment of the present invention. It is sectional drawing along the AA 'line of the said multilayer ceramic capacitor. It is sectional drawing along the BB 'line of the said multilayer ceramic capacitor. It is a flowchart which shows the manufacturing method of the said multilayer ceramic capacitor. It is a top view of the lamination sheet prepared by step S01 of the said manufacturing method. It is a perspective view of the lamination sheet which shows step S02 of the said manufacturing method. It is a top view of the lamination sheet which shows step S03 of the said manufacturing method. It is sectional drawing of the lamination sheet which shows step S03 of the said manufacturing method. It is sectional drawing which illustrates the side surface of the laminated chip after step S03 of the said manufacturing method. It is sectional drawing of the laminated chip which shows step S04 of the said manufacturing method. It is a perspective view of the surface layer removal apparatus used by step S04 of the said manufacturing method. It is a perspective view of the surface layer removal apparatus used by step S04 of the said manufacturing method. It is sectional drawing of the laminated chip which shows step S05 of the said manufacturing method. It is sectional drawing of the laminated chip which shows step S06 of the said manufacturing method. It is a perspective view of the unfired element body after Step S07 of the manufacturing method. It is a perspective view of the modification of the said surface layer removal apparatus. It is a side view of the multilayer chip which shows the surface layer removal method which concerns on the 2nd Embodiment of this invention. It is a figure which shows the irradiation region of the laser in the said surface layer removal method. It is a side view of the lamination | stacking chip | tip after implementing the said surface layer removal method. It is a fragmentary sectional view of the element of a multilayer ceramic capacitor manufactured by carrying out the above-mentioned surface layer removal method.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the drawing, an X axis, a Y axis, and a Z axis that are orthogonal to each other are shown as appropriate. The X axis, Y axis, and Z axis are common in all drawings.

<First Embodiment>
[Configuration of Multilayer Ceramic Capacitor 10]
1-3 is a figure which shows the multilayer ceramic capacitor 10 which concerns on the 1st Embodiment of this invention. FIG. 1 is a perspective view of a multilayer ceramic capacitor 10. 2 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along the line AA ′ of FIG. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along the line BB ′.

  The multilayer ceramic capacitor 10 includes an element body 11, a first external electrode 14, and a second external electrode 15. The external electrodes 14 and 15 are spaced apart from each other and face each other in the X-axis direction with the element body 11 interposed therebetween.

The element body 11 has two end surfaces facing the X-axis direction, two side surfaces facing the Y-axis direction, and two main surfaces facing the Z-axis direction. The ridges connecting the surfaces of the element body 11 are chamfered. In the element body 11, for example, the dimension in the X-axis direction can be set to 1.0 mm, and the dimension in the Y-axis and Z-axis directions can be set to 0.5 mm.
The shape of the element body 11 is not limited to such a shape. For example, each surface of the element body 11 may be a curved surface, and the element body 11 may have a rounded shape as a whole.

  The external electrodes 14 and 15 cover both end surfaces of the element body 11 in the X-axis direction, and extend to both side surfaces in the Y-axis direction and both main surfaces in the Z-axis direction that are connected to both end surfaces in the X-axis direction. Thereby, in both the external electrodes 14 and 15, the shape of the cross section parallel to the XZ plane and the cross section parallel to the XY axis is U-shaped.

Each of the external electrodes 14 and 15 is formed of a good conductor and functions as a terminal of the multilayer ceramic capacitor 10. As a good conductor for forming the external electrodes 14 and 15, for example, a metal mainly composed of nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), etc. Or alloys can be used.
The external electrodes 14 and 15 may have a single layer structure or a multilayer structure.

The external electrodes 14 and 15 having a multilayer structure may be configured, for example, as a two-layer structure of a base film and a surface film or a three-layer structure of a base film, an intermediate film, and a surface film.
The base film can be, for example, a baking film of a metal or alloy whose main component is nickel, copper, palladium, platinum, silver, gold or the like.
The intermediate film can be, for example, a plating film of a metal or alloy mainly composed of platinum, palladium, gold, copper, nickel, or the like.
The surface film can be, for example, a plating film of a metal or alloy containing copper, tin, palladium, gold, zinc, or the like as a main component.

The element body 11 includes a laminated chip 16 and a side margin portion 17.
The side margin portion 17 has a flat plate shape extending along the XZ plane and covers both side surfaces P and Q of the multilayer chip 16 in the Y-axis direction.
The multilayer chip 16 includes a capacitance forming portion 18 and a cover portion 19. The cover portion 19 has a flat plate shape extending along the XY plane, and covers both main surfaces of the capacitance forming portion 18 in the Z-axis direction.
The side margin portion 17 and the cover portion 19 mainly have a function of protecting the capacitance forming portion 18 and ensuring insulation around the capacitance forming portion 18.

  The capacitance forming unit 18 includes a plurality of first internal electrodes 12 and a plurality of second internal electrodes 13. Each of the internal electrodes 12 and 13 has a sheet shape extending along the XY plane, and is alternately arranged in the Z-axis direction. The first internal electrode 12 is connected to the first external electrode 14 and is separated from the second external electrode 15. On the contrary, the second internal electrode 13 is connected to the second external electrode 15 and is separated from the first external electrode 14.

  Each of the internal electrodes 12 and 13 is formed of a good conductor and functions as an internal electrode of the multilayer ceramic capacitor 10. As a good conductor for forming the internal electrodes 12 and 13, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or a metal containing these alloys Material is used.

The capacitance forming unit 18 is formed of dielectric ceramics. In the multilayer ceramic capacitor 10, a dielectric ceramic having a high dielectric constant is used as a material for forming the capacitance forming portion 18 in order to increase the capacitance of each dielectric ceramic layer between the internal electrodes 12 and 13. Examples of the dielectric ceramic having a high dielectric constant include a perovskite structure material containing barium (Ba) and titanium (Ti) typified by barium titanate (BaTiO ₃ ).

  The side margin part 17 and the cover part 19 are also formed of dielectric ceramics. The material for forming the side margin portion 17 and the cover portion 19 may be insulating ceramics. However, by using the same material as that for the capacitance forming portion 18, the manufacturing efficiency is improved and the internal stress in the element body 11 is reduced. It is suppressed.

  With the above configuration, in the multilayer ceramic capacitor 10, when a voltage is applied between the first external electrode 14 and the second external electrode 15, a plurality of pieces between the first internal electrode 12 and the second internal electrode 13 are provided. A voltage is applied to the dielectric ceramic layer. As a result, in the multilayer ceramic capacitor 10, charges corresponding to the voltage between the first external electrode 14 and the second external electrode 15 are stored.

  The configuration of the multilayer ceramic capacitor 10 is not limited to a specific configuration, and a known configuration can be appropriately adopted according to the size and performance required for the multilayer ceramic capacitor 10. For example, the number of internal electrodes 12 and 13 in the capacitance forming unit 18 can be determined as appropriate.

[Method of Manufacturing Multilayer Ceramic Capacitor 10]
FIG. 4 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 10. 5 to 15 are diagrams illustrating a manufacturing process of the multilayer ceramic capacitor 10. Hereinafter, a method for manufacturing the multilayer ceramic capacitor 10 will be described along FIG. 4 with reference to FIGS.

(Step S01: Preparation of ceramic sheet)
In step S01, a first ceramic sheet 101 and a second ceramic sheet 102 for forming the capacitance forming portion 18 and a third ceramic sheet 103 for forming the cover portion 19 are prepared.

  FIG. 5 is a plan view of the ceramic sheets 101, 102, 103. 5A shows the ceramic sheet 101, FIG. 5B shows the ceramic sheet 102, and FIG. 5C shows the ceramic sheet 103. The ceramic sheets 101, 102, 103 are configured as unfired dielectric green sheets, and are formed into a sheet shape using, for example, a roll coater or a doctor blade.

  In the step S01, the ceramic sheets 101, 102, 103 are not cut for each multilayer ceramic capacitor 10. FIG. 5 shows cutting lines Lx and Ly when cutting each multilayer ceramic capacitor 10. The cutting line Lx is parallel to the X axis, and the cutting line Ly is parallel to the Y axis.

  As shown in FIG. 5, an unfired first internal electrode 112 corresponding to the first internal electrode 12 is formed on the first ceramic sheet 101, and an unfired first internal electrode 112 corresponding to the second internal electrode 13 is formed on the second ceramic sheet 102. A fired second internal electrode 113 is formed. Note that no internal electrode is formed on the third ceramic sheet 103 corresponding to the cover portion 19.

  The internal electrodes 112 and 113 can be formed using any conductive paste. For example, a screen printing method or a gravure printing method can be used to form the internal electrodes 112 and 113 using a conductive paste.

  The internal electrodes 112 and 113 are disposed over two regions adjacent to each other in the X-axis direction that are partitioned by the cutting line Ly, and extend in a band shape in the Y-axis direction. The first internal electrode 112 and the second internal electrode 113 are shifted in the X-axis direction by one row of regions partitioned by the cutting line Ly. That is, the cutting line Ly passing through the center of the first internal electrode 112 passes through the region between the second internal electrodes 113, and the cutting line Ly passing through the center of the second internal electrode 113 passes through the region between the first internal electrodes 112. Passing through.

(Step S02: Lamination)
In step S02, the laminated sheet 104 is produced by laminating the ceramic sheets 101, 102, 103 prepared in step S01.

  FIG. 6 is a perspective view of the laminated sheet 104 obtained in step S02. In FIG. 6, for convenience of explanation, the ceramic sheets 101, 102, and 103 are shown in an exploded manner. However, in the actual laminated sheet 104, the ceramic sheets 101, 102, and 103 are integrated by being crimped by hydrostatic pressure or uniaxial pressure. Thereby, the high-density laminated sheet 104 is obtained.

In the laminated sheet 104, the first ceramic sheets 101 and the second ceramic sheets 102 corresponding to the capacitance forming unit 18 are alternately laminated in the Z-axis direction.
In the laminated sheet 104, the third ceramic sheets 103 corresponding to the cover portions 19 are laminated on the uppermost and lowermost surfaces in the Z-axis direction of the ceramic sheets 101 and 102 that are alternately laminated. In the example shown in FIG. 7, three third ceramic sheets 103 are laminated, but the number of third ceramic sheets 103 can be changed as appropriate.

(Step S03: Cutting)
In step S03, an unfired laminated chip 116 is produced by cutting the laminated sheet 104 obtained in step S02. In step S02, the laminated sheet 104 is cut by pressing.

  FIG. 7 is a plan view of the laminated sheet 104 after step S03. The laminated sheet 104 is cut along the cutting lines Lx and Ly while being attached to the tape T1 as a holding member. Thereby, the lamination sheet 104 is separated into pieces and the lamination chip 116 is obtained.

  FIG. 8 is a cross-sectional view of the laminated sheet 104 showing the process of step S03. In step S03, a cutting device provided with the press cutting blade 200 is used.

First, as shown in FIG. 8A, the press cutting blade 200 directed downward in the Z-axis direction is disposed above the laminated sheet 104 in the Z-axis direction.
Next, as shown in FIG. 8 (B), the push blade 200 is moved downward in the Z-axis direction until the push blade 200 reaches the tape T1, and the laminated sheet 104 is cut. At this time, the pressing blade 200 is not passed through the tape T1 so that the tape T1 is not cut.
Then, as shown in FIG. 8C, the push cutting blade 200 is moved upward in the Z-axis direction, and the push cutting blade 200 is pulled out from the laminated sheet 104.

Thereby, the laminated sheet 104 is separated into a plurality of laminated chips 116. At this time, the tape T1 connects the laminated chips 116 without being cut. Thereby, it becomes possible to handle a plurality of laminated chips 116 at a time in the subsequent steps, and the manufacturing efficiency is improved.
The cut surfaces of the laminated sheet 104 formed in step S03 become the Y-axis direction side faces P and Q and the X-axis direction end face of the laminated chip 116.

  FIG. 9 is an enlarged cross-sectional view illustrating the side surfaces P and Q of the multilayer chip 116 immediately after step S03. That is, the side surfaces P and Q of the laminated chip 116 immediately after cutting may be in a state illustrated in FIGS.

  On the side surfaces P and Q shown in FIG. 9 (A), scratches H are formed by, for example, foreign matter being caught by the push blade 200 in step S03. In the process in which the scratch H is formed in step S03, when the push blade 200 drags the internal electrodes 112 and 113, the internal electrodes 112 and 113 are stretched along the scratch H, thereby forming the extended portion R1. . When the extended portion R1 reaches from one of the internal electrodes 112 and 113 to the other, the internal electrodes 112 and 113 are connected to each other via the extended portion R1, thereby causing a short circuit.

  The scratches H as shown in FIG. 9A are not formed on the side surfaces P and Q shown in FIG. However, also in this case, when the pressing blade 200 drags the internal electrodes 112 and 113 in step S03, the internal electrodes 112 and 113 are extended along the side surfaces P and Q, so that the extended portion R2 is formed. . When the extended portion R2 reaches from one of the internal electrodes 112 and 113 to the other, the internal electrodes 112 and 113 are connected to each other via the extended portion R2, thereby causing a short circuit.

  A foreign substance R3 is attached to the side surfaces P and Q shown in FIG. As the foreign material R3, a conductive material generated from the internal electrodes 112, 113, the push cutting blade 200, and the like in step S03 is assumed. If such foreign matter R3 adheres to both of the internal electrodes 112 and 113, the internal electrodes 112 and 113 are connected to each other via the foreign matter R3, thereby causing a short circuit.

  Thus, in the laminated chip 116 immediately after step S03, the first internal electrode 112 and the second internal electrode 113 may be short-circuited on the side surfaces P and Q. If the first internal electrode 112 and the second internal electrode 113 are short-circuited, the multilayer ceramic capacitor 10 having the intended performance cannot be obtained.

  In particular, when the distance between the internal electrodes 112 and 113 is narrow, that is, when the dielectric ceramic layer between the internal electrodes 112 and 113 is thin, a short circuit between the internal electrodes 112 and 113 on the side surfaces P and Q tends to occur. Specifically, when the dielectric ceramic layer between the internal electrodes 112 and 113 is thinner than the internal electrodes 112 and 113, or when the dielectric ceramic layer is 1 μm or less, the internal electrodes 112 and 113 on the side surfaces P and Q Short circuit is particularly likely to occur.

  For cutting the laminated sheet 104, a technique using a blade different from the push cutting may be used, for example, a rotary blade (for example, a dicing blade) may be used. Furthermore, for cutting the laminated sheet 104, a technique that does not use a blade may be used. For example, laser cutting or water jet cutting may be used.

In any case, in step S03, a short circuit may occur between the first internal electrode 112 and the second internal electrode 113 on the side surfaces P and Q of the multilayer chip 116.
In the present embodiment, steps S04 and S06 (surface layer removal) are performed in order to eliminate the short circuit between the first internal electrode 112 and the second internal electrode 113 on the side surfaces P and Q of the multilayer chip 116.

(Step S04: Surface layer removal 1)
In step S04, the surface layer on the side surface P of the multilayer chip 116 obtained in step S03 is removed.

  The spread parts R1 and R2 and the foreign matter R3 shown in FIG. 9 are included in the surface layer of the side surface P immediately after step S03. For this reason, by removing the surface layer of the side surface P in step S04, the extended portions R1, R2 and the foreign matter R3 are also removed. Thereby, the short circuit between the first internal electrode 112 and the second internal electrode 113 on the side surface P is eliminated.

  The surface layer of the side surface P removed in step S04 can be, for example, a region having a depth of about 50 μm in the Y-axis direction from the side surface P of the multilayer chip 116 obtained in step S03. Note that the depth in the Y-axis direction of the side surface P to be removed in step S04 can be determined as appropriate so that the extended portions R1, R2 and the foreign matter R3 can be appropriately removed.

  FIG. 10 is a cross-sectional view of the multilayer chip 116 showing step S04. In step S04, the laminated chip 116 is pasted from the tape T1 to the tape T2, and the side surface Q is held by the tape T2. And the surface layer removal apparatus 300 for removing the surface layer of the side surface P is arrange | positioned so that the side surface P may be opposed.

  In the present embodiment, a grinder 300a shown in FIG. In the example shown in FIG. 11, a plurality of laminated chips 116 are arranged on the tape T2, and step S04 is performed on the plurality of laminated chips 116 at once. Thereby, the manufacturing efficiency of the multilayer ceramic capacitor 10 is improved.

  The grinder 300a includes a cylindrical body having a central axis parallel to the Z axis. In this cylindrical body, the outer peripheral surface is configured as a grinding surface. The grinder 300a rotates the cylindrical body around the central axis, brings the outer peripheral surface of the cylindrical body into contact with the side surface P of the multilayer chip 116, and grinds the side surface P of the multilayer chip 116, whereby the side surface P of the multilayer chip 116 is obtained. The surface layer of can be removed.

  By appropriately moving the tape T2 in the X-axis direction or the Z-axis direction, the surface layer on the side surface P can be removed from all the laminated chips 116 arranged on the tape T2. Note that the cylindrical body of the grinder 300a may be moved in the X-axis direction or the Z-axis direction without moving the tape T2.

As the surface layer removing apparatus 300, a grinder 300b shown in FIG. 12 can be used instead of the grinder 300a shown in FIG.
The grinder 300b includes a disc body having a central axis parallel to the Y axis. In this disk body, a flat surface is configured as a grinding surface. The grinder 300b rotates the disc body around the central axis, brings the flat surface of the disc body into contact with the side surface P of the laminated chip 116, and grinds the side surface P of the laminated chip 116, thereby causing the side surface P of the laminated chip 116 to be ground. The surface layer of can be removed.

  Thereafter, if necessary, the laminated chip 116 is washed to remove grinding dust or the like adhering to the side surface P or the like.

(Step S05: Side margin portion formation 1)
In step S05, an unfired side margin portion 117 is formed on the side surface P of the multilayer chip 116 obtained in step S04.

  In step S05, a side margin sheet 117s for forming the side margin portion 117 is prepared. The side margin sheet 117s is configured as an unfired dielectric green sheet, similarly to the ceramic sheets 101, 102, and 103 prepared in step S01. The side margin sheet 117s is formed into a sheet shape using, for example, a roll coater or a doctor blade.

FIG. 13 is a cross-sectional view of the laminated chip 116 showing the process of step S05.
First, as shown in FIG. 13A, the side margin sheet 117 s is disposed on the flat elastic body 400. The multilayer chip 116 is disposed with the side surface P facing the side margin sheet 117s.
Then, the side surface P of the multilayer chip 116 is pressed against the side margin sheet 117s. As a result, the side margin sheet 117 s is punched out by the side surface P of the multilayer chip 116.

  Thereafter, when the multilayer chip 116 is pulled up from the side margin sheet 117s, only the side margin portion 117 punched out from the side margin sheet 117s and attached to the side surface P is removed from the elastic body 400 as shown in FIG. It leaves and remains on the laminated chip 116 side. Thereby, the laminated chip 116 in which the side margin portion 117 is formed on the side surface P is obtained.

The side margin portion 117 on the side surface P of the multilayer chip 116 may be formed by a method other than the above punching.
For example, a side margin sheet 117s cut in advance may be attached to the side surface P of the laminated chip 116.
Further, the side margin portion 117 may be formed by applying a ceramic paste to the side surface P of the multilayer chip 116 without using the side margin sheet 117s. As a method for applying the ceramic paste, for example, a dipping method can be used.

(Step S06: Surface layer removal 2)
In step S06, the surface layer on the side surface Q of the multilayer chip 116 obtained in step S05 is removed.

  The removal of the surface layer on the side surface Q in step S06 can be performed in the same manner as the removal of the surface layer on the side surface P in step S04. By the step S06, the extended portions R1, R2 and the foreign matter R3 included in the surface layer of the side surface Q are also removed, so that the short circuit between the first internal electrode 112 and the second internal electrode 113 on the side surface Q is eliminated.

FIG. 14 is a cross-sectional view of the multilayer chip 116 showing step S06. In step S06, the laminated chip 116 is pasted from the tape T2 to the tape T3, and the side margin portion 117 provided on the side surface P is held by the tape T3.
Thereby, the direction of the side surfaces P and Q of the laminated chip 116 is opposite to that in step S04. For this reason, in step S06, the surface layer can be removed from side Q opposite to side P in the same manner as in step S04.
In step S06, the same surface layer removing apparatus 300 as in step S04 can be used.

(Step S07: Side margin portion formation 2)
In step S07, an unfired side margin portion 117 is formed on the side surface Q of the multilayer chip 116 obtained in step S06. The formation of the side margin portion 117 on the side surface Q in step S07 can be performed in the same manner as the formation of the side margin portion 117 on the side surface P in step S05.

Thus, the unfired element body 111 shown in FIG. 15 is obtained.
The shape of the element body 111 can be determined according to the shape of the element body 11 after firing. For example, in order to obtain the element body 11 of 1.0 mm × 0.5 mm × 0.5 mm, the element body 111 of 1.2 mm × 0.6 mm × 0.6 mm can be produced.

(Step S08: Firing)
In step S08, the unfired element body 111 obtained in step S07 is fired to produce the element body 11 of the multilayer ceramic capacitor 10 shown in FIGS. Firing can be performed, for example, in a reducing atmosphere or in a low oxygen partial pressure atmosphere.

(Step S09: External electrode formation)
In step S09, the multilayer electrodes 10 shown in FIGS. 1-3 are produced by forming the external electrodes 14 and 15 in the element body 11 obtained in step S08.

  In step S09, first, an unfired electrode material is applied so as to cover one X-axis direction end face of the element body 11, and an unfired electrode material is applied so as to cover the other X-axis direction end face of the element body 11. To do. The unfired electrode material applied to the element body 11 is baked, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere to form a base film on the element body 11. Then, the intermediate film and the surface film are formed on the base film baked on the element body 11 by a plating process such as electrolytic plating, and the external electrodes 14 and 15 are completed.

  Note that part of the processing in step S09 may be performed before step S08. For example, before step S08, an unfired electrode material is applied to both end surfaces in the X-axis direction of the unfired element body 111. In step S08, the unfired element body 111 is fired and at the same time, The underlying layer of the external electrodes 14 and 15 may be formed by baking.

[Modification of Surface Removal Device 300]
The surface layer removing apparatus 300 used in steps S04 and S06 is not limited to the grinders 300a and 300b shown in FIGS. 11 and 12 as long as the surface layers on the side surfaces P and Q of the laminated chip 116 can be removed.

  FIG. 16 is a view showing a modification of the surface layer removal apparatus 300.

  As shown in FIG. 16A, a laser irradiation apparatus 300c can be used as the surface layer removal apparatus 300. The laser irradiation apparatus 300c removes the surface layers of the side surfaces P and Q by irradiating the side surfaces P and Q of the multilayer chip 116 with laser.

  The laser irradiation apparatus 300c is not limited to a specific configuration, but is preferably a pulse laser apparatus with a short pulse width. Thereby, for example, it is possible to suppress the generation of foreign matter accompanying the temperature rise of the side surfaces P and Q of the multilayer chip 116. Examples of the pulse laser device having a short pulse width include a picosecond laser device having a pulse width in the picosecond region and a femtosecond laser device having a pulse width in the femtosecond region.

Note that conditions such as the type of laser irradiated by the laser irradiation apparatus 300c, the spot diameter, the intensity, the irradiation time, and the number of irradiations can be determined as appropriate.
Examples of the type of laser include a YAG laser and a fiber laser.
In addition, when the laser spot diameter is small, the laser irradiation apparatus 300c can be scanned in the X-axis and Z-axis directions to irradiate the entire region of the side surfaces P and Q of all the laminated chips 116. It is. Note that the tape T2 may be moved in the X-axis direction or the Z-axis direction without moving the laser irradiation apparatus 300c.

  Further, in order to remove the surface layers of the side surfaces P and Q of the multilayer chip 116, high energy rays other than laser can be used. For example, when an electron beam is used as the high energy beam, a high energy beam irradiation device including an electron gun can be used as the surface layer removing device 300.

  Further, as shown in FIG. 16B, a blast processing apparatus 300d can be used as the surface layer removing apparatus 300. The blast treatment apparatus 300d removes the surface layers of the side surfaces P and Q by spraying a granular abrasive on the side surfaces P and Q of the laminated chip 116. The size of the abrasive grains can be determined as appropriate, and can be, for example, 3 μm or less.

  The blasting process by the blasting apparatus 300d may be wet blasting or drive blasting (sand blasting, dry ice blasting, etc.). Abrasive grains used in wet blasting and sand blasting can be appropriately selected. For example, ceramic (alumina or the like), metal, glass, or plastic can be used. The conditions for the blasting process by the blasting apparatus 300d can be determined as appropriate.

In addition to these, the surface layer removing apparatus 300 may be configured to be able to remove the surface layers of the side surfaces P and Q of the multilayer chip 116 by a method other than the above, such as etching.
Further, in steps S04 and S06, the surface layer removing apparatus 300 is not necessarily used, and part or all of the processing by the surface layer removing apparatus 300 may be performed manually or using another apparatus. You may go. For example, a planar polishing plate may be used instead of the grinders 300a and 300b.

<Second Embodiment>
The surface layer removal method according to the second embodiment of the present invention is applicable to step S04 (surface layer removal 1) and step S06 (surface layer removal 2) in FIG. 4, and a laser irradiation apparatus is used as the surface layer removal apparatus 300.

  The laser irradiation apparatus used in this embodiment has a smaller laser spot diameter than the laser irradiation apparatus 300c shown in FIG. By reducing the spot diameter of the laser, a laser having a high energy density can be irradiated. Thereby, the laser irradiation time can be shortened, so that the surface layer can be efficiently removed.

  FIG. 17 is a diagram illustrating the side surfaces P and Q of the multilayer chip 116 before the surface layer is removed. In FIG. 17, an example of an irradiation region I that is a region irradiated with a laser for removing the surface layer is indicated by a broken line. The shape of the irradiation region I depends on the spot shape of the laser. In the example shown in FIG. 17, two irradiation regions I arranged in the X-axis direction are arranged in two rows in the Z-axis direction.

  Irradiation regions I adjacent in the X-axis and Z-axis directions overlap each other. Thereby, the irradiation area | region I is arrange | positioned on the side surfaces P and Q of the laminated chip 116 without a gap. For this reason, by irradiating all the irradiation regions I with the laser, it is possible to remove the surface layer of the entire regions of the side surfaces P and Q of the multilayer chip 116.

  As the laser irradiation device, for example, a pulse laser device capable of moving the laser spot by controlling the angle of a mirror that reflects the laser can be used. In such a laser irradiation apparatus, it is possible to irradiate all the irradiation regions I by moving the laser spot to a different irradiation region I for each laser irradiation.

  The spot shape of the laser is rectangular, that is, each irradiation region I is preferably rectangular. As a result, even if the overlap amount of the irradiation region I is reduced, it becomes difficult to form a gap between the irradiation regions I, so that the entire region on the side surface of the chip can be irradiated efficiently. Become. The four corners of each irradiation region I may be rounded.

  The laser output distribution is preferably a top hat type. As a result, the laser output distribution is uniform in the entire irradiation region I. Therefore, the position and interval of the irradiation region I on the side surfaces P and Q of the multilayer chip 116 can be determined without considering the laser output distribution.

  FIG. 18 is a diagram showing only the irradiation region I in FIG. As described above, since the adjacent irradiation regions I overlap each other in the X-axis and Z-axis directions, the region A1 irradiated with the laser once by the series of laser irradiations and the laser irradiation twice. A region A2 to be applied and a region A3 to which the laser is irradiated three times are formed.

  FIG. 19 is a diagram illustrating the side surfaces P and Q of the multilayer chip 116 after the laser is irradiated to all the irradiation regions I. On the side surfaces P and Q of the multilayer chip 116, the irradiation region I overlaps, and overlap marks Tr formed by laser irradiation appear in the regions A2 and A3 where the laser is irradiated a plurality of times.

  In the regions A2 and A3 on the side surfaces P and Q of the multilayer chip 116, surface layer removal by laser irradiation is performed a plurality of times. For this reason, in the regions A2 and A3, the surface layer removal proceeds more than the region A1 in which the surface layer removal by laser irradiation is performed only once. As a result, overlap marks Tr appear on the side surfaces P and Q of the multilayer chip 116.

  Therefore, if the overlap trace Tr is formed at the X-axis and Z-axis direction ends of the irradiation region I, it can be seen that the laser is irradiated without a gap. On the contrary, if the overlap trace Tr is not formed at the X-axis and Z-axis direction ends of the irradiation region I, there is a high possibility that a gap is formed between the adjacent irradiation regions I.

  In this way, by checking the overlap trace Tr on the side surfaces P and Q of the multilayer chip 116 by visual observation or an image, it is determined whether or not the laser is irradiated to the entire area of the side surfaces P and Q of the multilayer chip 116 without a gap. It can be easily distinguished. Therefore, it is possible to eliminate the laminated chip 116 having a region where the side surfaces P and Q are not irradiated with the laser.

  In the present embodiment, since the shape of the irradiation region I (that is, the laser spot shape) is rectangular, an overlap mark Tr having a pattern as shown in FIG. 19 is formed, for example. Specifically, an overlap trace Tr extending over the entire region in the X-axis direction and an overlap trace Tr extending in the Z-axis direction arranged at equal intervals in the X-axis direction are formed.

  FIG. 20 is a partial cross-sectional view of the element body 11 of the multilayer ceramic capacitor 10 manufactured by performing the surface layer removing method according to the present embodiment. FIG. 20 shows a cross section of the element body 11 corresponding to the position of the CC ′ line of FIG. FIG. 20 partially shows the vicinity of the interface between the laminated chip 16 and the side margin portion 17 in the element body 11.

  In the region where the overlap mark Tr shown in FIG. 19 is formed, pores Pr2 and Pr3 are formed at the ends of the internal electrodes 12 and 13 by removing the internal electrodes 112 and 113 by laser irradiation. On the other hand, in the region where the overlap trace Tr is not formed, pores are hardly formed at the end portions of the internal electrodes 12 and 13.

  That is, the presence of the overlap trace Tr in the element body 11 after forming the side margin portion 17 can be confirmed by the presence of the pores Pr2 and Pr3 in the cross section of the element body 11. By specifying the positions where the pores Pr2 and Pr3 exist in a plurality of cross sections of the element body 11, it is possible to determine the position and shape of the overlap mark Tr.

  In the element body 11 in which the pores Pr2 and Pr3 exist, in the binder removal process before firing, vaporized binder components and solvent components are easily released to the outside through the pores Pr2 and Pr3. For this reason, in the element | base_body 11 which concerns on this embodiment, the effect which suppresses the performance fall by the binder component and the residual of a solvent component is acquired.

  Note that the dimensions of the pores Pr2 and Pr3 in the Y-axis direction increase as the number of laser irradiations increases. Therefore, as shown in FIG. 20, in the pore Pr3 corresponding to the region A3 irradiated with the laser three times, the dimension in the Y-axis direction becomes larger than the pore Pr2 corresponding to the region A2 irradiated with the laser twice. .

  The configuration of the present embodiment can be changed as appropriate. For example, the shape of the irradiation region I (that is, the laser spot shape) does not have to be a rectangle, and may be, for example, a circle, an ellipse, or a polygon. Further, the laser output distribution in the irradiation region I is not limited to the top hat type, and may be, for example, a Gaussian type.

<Other embodiments>
As mentioned above, although embodiment of this invention was described, this invention is not limited only to the above-mentioned embodiment, Of course, a various change can be added.

For example, the steps shown in FIG. 4 may be switched in order as necessary.
As an example, after the unfired laminated chip 116 singulated in step S03 is fired to form the laminated chip 16, the side margin portion 117 may be provided on the laminated chip 16. In this case, steps S04 to S08 can be performed on the laminated chip 16 after firing.

  In the first and second embodiments, the surface layer on the side surface P of the multilayer chip 116 is removed in step S04, and the surface layer on the side surface Q of the multilayer chip 116 is removed in step S06. , Q may be removed simultaneously. In this case, for example, it is possible to irradiate the side surfaces P and Q of the multilayer chip 116 simultaneously with the both main surfaces of the multilayer chip 116 held in the Z-axis direction.

  In the first and second embodiments, the multilayer ceramic capacitor has been described as an example of the multilayer ceramic electronic component. However, the present invention generally relates to multilayer ceramic electronic components in which internal electrodes that are paired with each other are alternately arranged. It is applicable to. Examples of such a multilayer ceramic electronic component include a piezoelectric element.

DESCRIPTION OF SYMBOLS 10 ... Multilayer ceramic capacitor 11 ... Element body 12, 13 ... Internal electrode 14, 15 ... External electrode 16 ... Multilayer chip 17 ... Side margin part 18 ... Capacitance formation part 19 ... Cover part 104 ... Multilayer sheet 111 ... Unbaked element body 112, 113 ... Unfired internal electrode 116 ... Unfired laminated chip 117 ... Unfired side margin portion 200 ... Press cutting blade 300 ... Surface layer removing device P, Q ... Side surfaces T1-T3 ... Tape

Claims (12)

Preparing a laminated sheet having a plurality of laminated ceramic sheets, and a plurality of internal electrodes arranged between the plurality of ceramic sheets;
By cutting the laminated sheet, to produce a laminated chip having a side surface where the plurality of internal electrodes are exposed,
Removing the surface layer of the side surface of the laminated chip;
A method of manufacturing a multilayer ceramic electronic component, wherein a side margin is provided on the side surface of the multilayer chip from which the surface layer has been removed. It is a manufacturing method of the multilayer ceramic electronic component according to claim 1,
A method for producing a laminated ceramic electronic component, comprising cutting the laminated sheet with a press cutting blade or a rotary blade. It is a manufacturing method of the multilayer ceramic electronic component according to claim 1 or 2,
A method for producing a multilayer ceramic electronic component, wherein the surface layer is removed by grinding the side surface of the multilayer chip. It is a manufacturing method of the multilayer ceramic electronic component according to claim 1 or 2,
A method for manufacturing a multilayer ceramic electronic component, wherein the surface layer is removed by blasting the side surface of the multilayer chip. It is a manufacturing method of the multilayer ceramic electronic component according to claim 1 or 2,
A method for manufacturing a multilayer ceramic electronic component, wherein the surface layer is removed by irradiating the side surface of the multilayer chip with a laser. It is a manufacturing method of the multilayer ceramic electronic component according to claim 5,
A method for manufacturing a multilayer ceramic electronic component, comprising: irradiating a plurality of irradiation regions overlapping on the side surface of the multilayer chip with the laser. It is a manufacturing method of the multilayer ceramic electronic component according to claim 6,
The plurality of irradiation areas are rectangular.
Manufacturing method of multilayer ceramic electronic component. A method for producing a multilayer ceramic electronic component according to claim 6 or 7,
The laser has a top-hat type output distribution. A plurality of ceramic layers stacked in a first direction, a plurality of internal electrodes disposed between the plurality of ceramic layers, and a second direction orthogonal to the first direction, the ends of the plurality of internal electrodes A laminated chip having a side surface adjacent to the portion and formed with a laser overlap trace;
A side margin that covers the side surface of the multilayer chip;
A multilayer ceramic electronic component comprising: The multilayer ceramic electronic component according to claim 9,
In the overlap mark, a pore is formed at the end of the plurality of internal electrodes. Multilayer ceramic electronic component. The multilayer ceramic electronic component according to claim 9 or 10,
The overlap marks are arranged at a predetermined interval. The multilayer ceramic electronic component. The multilayer ceramic electronic component according to any one of claims 9 to 11,
The overlap trace forms a predetermined pattern. Multilayer ceramic electronic component.

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