JP2017059815A - Laminate electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminate electronic component having excellent insulation resistance.SOLUTION: In a laminate electronic component (laminate ceramic capacitance) 2 having an element main body 3 in which internal electrode layers 12 and internal dielectric layers 10 which are substantially parallel to a plane containing a first axis and a second axis are alternately laminated along a direction of a third axis, an insulating layer is provided on each of a pair of side faces facing each other in the direction of the first axis of the element main body 3, and external electrodes 6, 8 which are electrically connected to the internal electrode layers 12 are respectively provided on a pair of end faces facing each other in the direction of the second axis of the element main body. The end portion of the internal electrode layer 12 in the first axial direction is drawn inwards along the direction of the first axis from the end portion in the first axial direction of the internal dielectric layer by a predetermined drawing distance, and the drawing distance is dispersed within a predetermined range in each layer of the internal electrode layers 12.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a laminated electronic component.

  In recent years, there is a high demand for miniaturization of electronic components due to the increase in the density of electronic circuits used in digital electronic devices such as mobile phones, and miniaturization and increase in capacity of laminated electronic components constituting the circuits are rapidly progressing. It is out.

  Patent Document 1 proposes a multilayer ceramic capacitor having a structure in which a side gap is eliminated in order to increase the use efficiency of an electrode material and increase the capacitance and accuracy. However, since the internal electrode is exposed on the side surface of the ceramic sintered body, there is a problem that the withstand voltage is low.

  Further, when the dielectric layer is thinned, the electric field tends to concentrate at the end portion of the internal electrode layer, and the insulation resistance tends to decrease.

  Moreover, as shown in Patent Document 2, a multilayer ceramic electronic component having a side gap is also known. However, in the prior art of multilayer ceramic electronic components having side gaps, in order to increase the withstand voltage, it is necessary to make the conductor layer enter from the side of the ceramic sintered body to the inside, and to make the amount of penetration uniform. Yes. However, as the thickness of the ceramic layer is reduced, the mechanical strength of the ceramic layer without the conductor layer is reduced, and structural defects (cracks or delamination) are likely to occur in the insulating layer forming process. It has been found by the present inventors that there is a problem that it is difficult to suppress a decrease in resistance.

Japanese Patent Publication No. 2-30570 JP-A-11-340081

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multilayer electronic component having a good insulation resistance.

  In order to achieve the above object, the multilayer electronic component of the present invention is as follows.

[1] A multilayer electronic component including an element body in which internal electrode layers and dielectric layers substantially parallel to a plane including the first axis and the second axis are alternately stacked along the direction of the third axis. And
An insulating layer is provided on each of a pair of end faces (side surfaces) facing each other in the direction of the first axis of the element body,
An external electrode electrically connected to the internal electrode layer is provided on each of a pair of end faces facing each other in the direction of the second axis of the element body,
The end in the first axial direction of the internal electrode layer is drawn in at a predetermined drawing distance from the end in the first axial direction of the dielectric layer to the inside along the direction of the first axis.
The multilayer electronic component, wherein the pull-in distance is dispersed in a predetermined range in each of the internal electrode layers.

  According to the present invention, the internal electrode layer pull-in distances are dispersed within a predetermined range in each of the internal electrode layers, so that the internal electrode layers of different layers are arranged at both ends in the first axial direction of the internal electrode layer. Can be effectively prevented, and the distance between the internal electrode layers of different layers can be made sufficient. For this reason, even if the dielectric layer is thinned, a laminated electronic component having a good insulation resistance can be provided.

  The following aspect is illustrated as a specific aspect of said [1].

[2] The multilayer electronic component according to [1], wherein a CV value indicating a degree of dispersion of the pull-in distance is 0.05 to 1.0.

[3] The thickness of the dielectric layer between the kth internal electrode layer and the (k + 1) th internal electrode layer is td _k ,
The pull-in distance of the _kth internal electrode layer is d _k ,
The pull-in distance of the internal electrode layer of the (k + 1) th layer is d _{k + 1} ,
When Q value = td _k ² / (td _k ² + | d _{k + 1} −d _k | ² ),
The multilayer electronic component according to [1] or [2], wherein the Q value is 0.004 to 0.300.

[4] The multilayer electronic component according to any one of [1] to [3], wherein the insulating layer includes Si and Ba.

[5] The multilayer electronic component according to any one of [1] to [4], wherein a nonconductor portion exists between the end portion in the first axial direction of the internal electrode layer and the insulating layer.

[6] The multilayer electronic component according to [5], wherein the non-conductor portion includes an oxide of an element constituting the internal electrode layer.

[7] Green lamination by laminating a green sheet in which the internal electrode pattern layer that is continuous in the direction of the first axis and substantially parallel to the plane including the first axis and the second axis is formed in the direction of the third axis Obtaining a body;
Cutting the green laminate to obtain a green chip by obtaining a cut surface parallel to a plane including the second axis and the third axis; and
Firing the green chip to obtain an element body in which internal electrode layers and dielectric layers are alternately stacked; and
Applying an insulating layer paste to the end face of the element body in the first axial direction and baking it to obtain a ceramic sintered body on which an insulating layer is formed; and
By baking a paste for external electrodes on the end surface in the second axial direction of the ceramic sintered body to obtain a laminated electronic component on which external electrodes are formed, and
The end in the first axial direction of the internal electrode layer is drawn in at a predetermined drawing distance from the end in the first axial direction of the dielectric layer to the inside along the direction of the first axis.
A method of manufacturing a laminated electronic component in which the pull-in distance is dispersed in a predetermined range in each of the internal electrode layers.

FIG. 1 is a schematic cross-sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG. FIG. 3A is an enlarged view of a main part of FIG. 3B is an enlarged view of a main part of FIG. 3C is an enlarged view of a main part of FIG. FIG. 4 is a schematic cross-sectional view showing a green sheet laminating step in the manufacturing process of the monolithic ceramic capacitor shown in FIG. 5A (a) is a plan view showing a part of the nth internal electrode pattern layer along the line VV shown in FIG. 4, and FIG. 5A (b) is an (n + 1) th internal electrode pattern layer. It is a top view which shows a part of. FIG. 5B is a plan view showing a part of the internal electrode pattern layer along the line VV shown in FIG. FIG. 6A is a schematic cross-sectional view parallel to the XZ axis plane of the laminated body after the green sheets shown in FIG. 4 are laminated. 6B is a schematic cross-sectional view parallel to the YZ axis plane of the laminated body after the green sheets shown in FIG. 4 are laminated. FIG. 7 is a schematic diagram for explaining a method for measuring the deflection strength of this embodiment.

  Based on this embodiment, it demonstrates in detail, referring drawings, but this invention is not limited only to embodiment described below.

  The constituent elements described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the constituent elements described below can be appropriately combined.

  Hereinafter, the present invention will be described based on embodiments shown in the drawings.

Overall Configuration of Multilayer Ceramic Capacitor The overall configuration of a multilayer ceramic capacitor will be described as an embodiment of the multilayer electronic component according to this embodiment.

  As shown in FIG. 1, the multilayer ceramic capacitor 2 according to this embodiment includes a ceramic sintered body 4, a first external electrode 6, and a second external electrode 8. Further, as shown in FIG. 2, the ceramic sintered body 4 has an element body 3 and an insulating layer 16.

  The element body 3 has an inner dielectric layer 10 and an internal electrode layer 12 substantially parallel to a plane including the X axis and the Y axis, and the internal electrode layer 12 is in the Z axis between the inner dielectric layers 10. They are stacked alternately along the direction. Here, “substantially parallel” means that most of the portions are parallel but may have some portions that are not parallel. The internal electrode layer 12 and the inner dielectric layer 10 are somewhat This means that it may be uneven or inclined.

  A portion where the inner dielectric layer 10 and the internal electrode layer 12 are alternately laminated is an interior region 13.

  The element body 3 has an exterior region 11 on both end faces in the stacking direction Z (Z axis). The exterior region 11 is formed by laminating a plurality of outer dielectric layers thicker than the inner dielectric layer 10 constituting the interior region 13.

  In the following, “inner dielectric layer 10” and “outer dielectric layer” may be collectively referred to as “dielectric layer”.

The materials of the dielectric layers constituting the inner dielectric layer 10 and the exterior region 11 may be the same or different, and are not particularly limited. For example, a dielectric material having a perovskite structure such as ABO ₃ or an alkali niobate ceramic Is composed as a main component.

In ABO ₃ , A is, for example, at least one of Ca, Ba, Sr and the like, and B is at least one of Ti, Zr and the like. The molar ratio of A / B is not particularly limited, and is 0.980 to 1.020.

  In addition, examples of the accessory component include, but are not limited to, silicon dioxide, aluminum oxide, magnesium oxide, alkali metal compound, alkaline earth metal compound, manganese oxide, rare earth element oxide, and vanadium oxide. The content may be appropriately determined according to the composition and the like.

  Note that the firing temperature can be lowered by using silicon dioxide or aluminum oxide as a subsidiary component. In addition, the lifetime can be improved by using magnesium oxide, an alkali metal compound, an alkaline earth metal compound, manganese oxide, a rare earth element oxide, vanadium oxide, or the like as a subcomponent.

  The number of laminated inner dielectric layers 10 and outer dielectric layers may be determined as appropriate according to the application.

  One internal electrode layer 12 laminated alternately is electrically connected to the inside of the first external electrode 6 formed outside the first end in the Y-axis direction of the ceramic sintered body 4. It has a drawer 12A. The other internal electrode layer 12 that is alternately laminated is electrically connected to the inside of the second external electrode 8 formed outside the second end in the Y-axis direction of the ceramic sintered body 4. A leading portion 12B.

  The interior area 13 includes a capacity area 14 and lead areas 15A and 15B. The capacitance region 14 is a region where the internal electrode layer 12 is laminated with the inner dielectric layer 10 sandwiched along the lamination direction. The lead area 15 </ b> A is an area located between the lead portions 12 </ b> A of the internal electrode layer 12 connected to the external electrode 6. The lead area 15 </ b> B is an area located between the lead portions 12 </ b> B of the internal electrode layer 12 connected to the external electrode 8.

  The conductive material contained in the internal electrode layer 12 is not particularly limited, and metals such as Ni, Cu, Ag, Pd, Al, and Pt, or alloys thereof can be used. The Ni alloy is preferably an alloy of Ni and one or more elements selected from Mn, Cr, Co and Al, and the Ni content in the alloy is preferably 95% by weight or more. In addition, in Ni or Ni alloy, various trace components, such as P, may be contained about 0.1 wt% or less.

  The internal electrode layer 12 may be formed using a commercially available electrode paste, and the thickness of the internal electrode layer 12 may be appropriately determined according to the application.

  As shown in FIG. 2, insulating layers 16 that cover the end surfaces of the internal electrode layers 12 of the element body 3 are provided on both end surfaces of the ceramic sintered body 4 in the X-axis direction.

  Further, in this embodiment, the X-axis direction end portion of the internal electrode layer 12 sandwiched between the inner dielectric layers 10 adjacent in the stacking direction (Z-axis direction) is the X-axis direction end face of the element body 3, that is, the inner dielectric material. The layers 10 are pulled inward along the X-axis direction from the X-axis direction end portion with a predetermined pull-in distance, and the pull-in distances are dispersed in a predetermined range in each layer of the internal electrode layer 12.

  Here, the pull-in distance refers to the distance from the end of the inner dielectric layer 10 in the X-axis direction to the end of the internal electrode layer 12 in the X-axis direction. Further, even when a non-conductor portion 18 to be described later exists between the X-axis direction end portion of the internal electrode layer 12 and the insulating layer 16, the pull-in distance is from the X-axis direction end portion of the inner dielectric layer 10 to the internal electrode. This refers to the distance to the end of the layer 12 in the X-axis direction.

  Since the end portions of the inner dielectric layer 10 and the internal electrode layer 12 may be uneven, in this case, the outermost portions of the inner dielectric layer 10 and the internal electrode layer 12 are used as a reference. That is, the distance from the outermost portion in the X-axis direction of the inner dielectric layer 10 to the outermost portion in the X-axis direction of the internal electrode layer 12 at the end portion of one inner dielectric layer 10 in the X-axis direction. The pull-in distance.

  In the present embodiment, it is not necessary for all the internal electrode layers 12 to be drawn inward within a predetermined range, and a part of the internal electrode layers 12 may be exposed on the end surface in the X-axis direction of the element body 3. .

  For example, the degree of dispersion of the pull-in distance is represented by a CV value. The CV value is a ratio between standard deviation and average (standard deviation / average). The calculation method of the CV value of the degree of dispersion of the pull-in distance is as follows.

As shown in FIG. 3A, Δd _k = | d _k −d _{a where the} pulling distance in the kth layer is d _k μm and the average pulling distance of the element body 3 having the N internal electrode layers is d _a μm. | Then, the standard deviation of the pull-in distance is represented by (Δd ₁ ² + Δd ₂ ² +... Δd _k ² +... Δd _N ² ) ^1/2 . In summary, the CV value is expressed by the following formula (1).

  In this embodiment, the CV value is preferably 1.0 or less, more preferably 0.05 to 1.0. Thereby, a multilayer electronic component having a good insulation resistance can be obtained.

  The present inventors consider the factors for obtaining such effects as follows. The internal electrode layer 12 that has entered from the inside of the element body 3 is generally disconnected or insulated due to contact between the inner dielectric layers 10 as the inner dielectric layer 10 is made thinner. The internal electrode layer 12 is easily stretched or has a structural defect due to handling of the formation process of the layer 16 or the like. Thus, the end portion of the internal electrode layer 12 in the X-axis direction causes a decrease in insulation resistance.

  Here, “elongation of the internal electrode layer 12” is a phenomenon in which the internal electrode layer 12 extends when an extra external force is applied to the side surface of the element body 3 where the internal electrode layer 12 is exposed. Examples of the extra external force include an external force when the element bodies 3 collide with each other when handling a large amount of the element bodies 3, and an external force applied to the side surface of the element body 3 when the element bodies 3 are held with tweezers. Due to the extension of the internal electrode layer 12, adjacent internal electrode layers 12 are connected to each other, which may cause a short circuit.

  The present embodiment is characterized in that the pull-in distance of the internal electrode layer 12 is intentionally dispersed with respect to the end portion in the X-axis direction of the internal electrode layer 12 that causes the expansion of the internal electrode layer 12 or a structural defect. is there. The dispersion of the pull-in distance at the end in the X-axis direction of the internal electrode layer 12 suppresses the elongation and structural defects of the internal electrode layer 12, and thus it is considered that the reduction of the insulation resistance can be suppressed.

  Further, the dispersion of the drawing distance at the end of the internal electrode layer 12 in the X-axis direction also serves to prevent the electric field from concentrating on the end of the internal electrode layer 12 in the X-axis direction. In particular, even when the inner dielectric layer 10 is thinned to about 0.5 μm or less, for example, it is possible to suppress a decrease in insulation resistance and to suppress electric field concentration.

  Further, as in the present embodiment, the drawing distances at the end portions in the X-axis direction of the internal electrode layer 12 are dispersed, so that the internal electrode layers of different layers are arranged at both ends in the X-axis direction of the internal electrode layer 12. 12 can be prevented from coming into contact, and the distance between the internal electrode layers 12 of different layers can be made sufficient. For this reason, it is possible to suppress a decrease in insulation resistance when the inner dielectric layer 10 is thinned and to reduce a short-circuit defect rate.

  The pull-in of the end portion of the internal electrode layer 12 in the X-axis direction is formed by, for example, a difference in sintering shrinkage between the material forming the internal electrode layer 12 and the material forming the inner dielectric layer 10. Further, the pull-in distance of the end portion in the X-axis direction of the internal electrode layer 12 can also be adjusted by polishing the end surface in the X-axis direction of the element body 3 before forming the insulating layer 16 by barrel polishing or the like.

  The method for dispersing the pull-in distance of the internal electrode layer 12 is not particularly limited. For example, as described later, the internal electrode layer 12 is etched by changing the content of the common material for each internal electrode layer 12. The pull-in distance of the layer 12 can be dispersed.

  That is, in the internal electrode layer 12 having a high content of the common material, the internal electrode layer 12 is difficult to be removed by etching. However, in the internal electrode layer 12 having a low content of the common material, the internal electrode layer 12 is easily etched away. As described above, the internal electrode layer 12 is easily etched away by etching, so that the drawing distance of the internal electrode layer 12 can be dispersed in each layer of the internal electrode layer 12.

  Further, by changing the concentration of the etching solution and the etching time, the degree of dispersion of the pull-in distance at the end of the internal electrode layer 12 in the X-axis direction can be changed.

  In addition, by changing the etching rate of ion milling, it is possible to disperse the drawing distance at the end of the internal electrode layer 12 in the X-axis direction or change the degree of dispersion.

  Further, by forming a non-conductor portion 18 to be described later at the end of the internal electrode layer 12 in the X-axis direction, the drawing distance of the end of the internal electrode layer 12 in the X-axis direction can be dispersed or the degree of dispersion can be increased. Can be changed.

  In the present embodiment, as shown in FIG. 3B, it is preferable that a non-conductor portion 18 exists between the end portion in the X-axis direction of the internal electrode layer 12 and the insulating layer 16. Thereby, the drawing distance of the internal electrode layer 12 can be dispersed in each layer of the internal electrode layer 12, and the internal electrode layers 12 of different layers are in contact with each other at both ends in the X-axis direction of the internal electrode layer 12. And the distance between the internal electrode layers 12 of different layers can be made sufficient. For this reason, it is possible to reduce the short-circuit defect rate when the inner dielectric layer 10 is thinned.

  In the present embodiment, it is preferable that the non-conductor portion 18 exists between the end portions in the X-axis direction of all the internal electrode layers 12 and the insulating layer 16, but there may be a layer in which the non-conductor portion does not exist.

  The component constituting the non-conductor portion 18 is not particularly limited, and may be, for example, an oxide, nitride, alloy, or mixture of elements constituting the internal electrode layer 12, but constitutes the internal electrode layer 12. More preferably, an oxide of the element is included. Thereby, since the adhesiveness of the both ends of the internal electrode layer 12 and the insulating layer 16 improves, a withstand voltage becomes more favorable. For example, when the internal electrode layer 12 contains Ni, it is preferable that the nonconductor portion 18 contains NiO.

  The insulating layer 16 of the present embodiment covers both end portions in the X-axis direction of the end surface (main surface) in the Z-axis direction of the element body 3 and / or both end portions in the X-axis direction of the end surface in the Y-axis direction of the element body 3. It is preferable to integrally have the insulating layer extension 16a. Although not shown, both ends of the external electrodes 6 and 8 in the Z-axis direction cover both ends of the insulating layer extension 16a in the Y-axis direction.

  In the present embodiment, both ends in the X-axis direction of the external electrodes 6 and 8 shown in FIG. 1 do not cover both ends in the Y-axis direction of the insulating layer 16 shown in FIG. 2 from both sides in the X-axis direction. However, it may be configured to cover.

  The softening point of the insulating layer 16 is preferably 500 ° C to 1000 ° C. Thereby, the influence of the structural defect which can generate | occur | produce in the process before and behind can be reduced.

  The component which comprises the insulating layer 16 of this embodiment is not specifically limited, For example, although ceramic, aluminum, glass, titanium, resin etc. are mentioned, it is preferable that Si and Ba are included. By including Si and Ba in the insulating layer 16, the adhesive strength between the element body 3 and the insulating layer 16 is improved. As a result, even if the thickness of the inner dielectric layer 10 is reduced, the inner dielectric layer 10 can have resistance to external stress due to deflection. This is considered to be because a reaction phase is formed at the interface between the insulating layer 16 and the element body 3. Here, the reaction phase refers to a portion where at least one component of the insulating layer 16 has diffused into the inner dielectric layer 10.

  Regarding the recognition of the reaction phase, for example, the STEM-EDS analysis of the Si element is performed on the interface between the dielectric layer of the ceramic sintered body 4 and the insulating layer 16, the mapping data of the Si element is obtained, and the Si element exists. The location can be recognized as a reaction phase

  By covering the end face of the element body 3 in the X-axis direction with the insulating layer 16, not only the insulation is improved, but also the durability and moisture resistance against the external environmental load are increased. In addition, since the insulating layer 16 covers the end surface of the element body 3 after firing in the X-axis direction, the uniform insulating layer 16 having a small gap (side gap) width can be formed.

  The material of the external electrodes 6 and 8 is not particularly limited, but a known conductive material such as at least one of Ni, Pd, Ag, Au, Cu, Pt, Rh, Ru, Ir, or an alloy or conductive resin thereof. Can be used. The thickness of the external electrodes 6 and 8 may be determined as appropriate according to the application.

  In FIG. 1, the X axis, the Y axis, and the Z axis are perpendicular to each other, the Z axis is coincident with the stacking direction of the inner dielectric layer 10 and the internal electrode layer 12, and the Y axis is the extraction region 15A. , 15B (leading portions 12A, 12B) coincides with the direction in which they are formed.

  In the present embodiment, as shown in FIG. 2, the outer surface of the insulating layer 16 from the end surface in the X-axis direction of the element body 3 along the width direction (X-axis direction) of the ceramic sintered body 4 in the insulating layer 16. The section up to is the gap.

  In this embodiment, the width Wgap of the gap portion in the X-axis direction is along the width direction (X-axis direction) of the ceramic sintered body 4 from the end surface in the X-axis direction of the element body 3 in the X-axis direction of the insulating layer 16. However, the width Wgap does not have to be uniform along the Z-axis direction, and may slightly vary. The width Wgap is preferably 0.1 μm to 40 μm, and is extremely small as compared with the width W0 of the element body 3.

  In the present embodiment, the width Wgap can be made extremely small as compared with the conventional case, and the pull-in distance of the internal electrode layer 12 is sufficiently small. Therefore, in this embodiment, it is possible to obtain a multilayer capacitor having a large capacity while being small.

  Note that the width W0 of the element body 3 matches the width of the inner dielectric layer 10 along the X-axis direction.

  By making Wgap within the above range, cracks are less likely to occur, and even if the ceramic sintered body 4 is further miniaturized, there is little decrease in capacitance.

  In the present embodiment, as shown in FIG. 2, at both ends in the Z-axis direction of the insulating layer 16, the insulating layer extension portion 16a that covers the X-axis direction ends of both end surfaces in the Z-axis direction of the element body 3 is provided as the insulating layer. 16 may be integrally formed. The ratio of the respective widths W1 and W0 in the X-axis direction of the insulating layer extension 16a from both end surfaces in the X-axis direction of the element body 3 is preferably 1/30 ≦ W1 / W0 <1/2.

As shown in FIG. 3C, the thickness of the inner dielectric layer 10 between the k-th layer of the internal electrode layer 12 and the k + 1 th layer of the inner electrode layers 12 and td _k, retraction distance of the inner electrode layer 12 of the k-th layer Is d _k and the pull-in distance of the ( _{k + 1) th} internal electrode layer 12 is d _{k + 1} . In the present embodiment, the distance between the end in the X-axis direction of the kth internal electrode layer 12 and the end in the X-axis direction of the (k + 1) th internal electrode layer 12 is preferably an appropriate distance. As an equation for quantifying this point, the following equation (2) may be mentioned.
Q value = td _k ² / (td _k ² + | d _{k + 1} −d _k | ² ) (2)

  The Q value in Expression (2) is the square of “the thickness of the dielectric layer between the kth internal electrode layer and the (k + 1) th internal electrode layer” and “X-axis direction of the kth internal electrode layer” And the square of the distance in the X-axis direction of the (k + 1) th internal electrode layer ”. In the present embodiment, the Q value is preferably 0.004 to 0.300, and more preferably 0.015 to 0.300.

  When the Q value is 0.004 or more, the distance between the end portions of the internal electrode layer 12 is not too long with respect to the thickness of the inner dielectric layer 10 as compared with the case where the Q value is less than 0.004. The area is sufficient and the capacitance is good. When the Q value is 0.015 or more, the electrostatic capacity becomes better. Further, when the Q value is 0.300 or less, the distance between the end portions of the internal electrode layer 12 is not too short with respect to the thickness of the inner dielectric layer 10 as compared with the case where the Q value is larger than 0.300. In addition, the electric field is less likely to concentrate at the end portion in the X-axis direction of the internal electrode layer 12, and the breakdown voltage defect rate is improved.

  As in the present embodiment, in each layer of the internal electrode layer 12, the pull-in distances of the end portions in the X-axis direction of the internal electrode layer 12 are dispersed, and the Q value is included in the above range. It is possible to prevent the internal electrode layers 12 of different layers from coming into contact with each other at both ends in the X-axis direction of the layer 12 and to make the distance between the internal electrode layers 12 of the different layers sufficient. For this reason, it is possible to reduce the short-circuit defect rate when the inner dielectric layer 10 is thinned.

  In FIG. 3B, the non-conductor portion 18 is formed at the end in the X-axis direction of each internal electrode layer 12 within a predetermined width WU from the end in the X-axis direction of the internal electrode layer 12. As shown in FIG. 3B, the end portion of the non-conductor portion 18 may be uneven, but the widest portion in one non-conductor portion 18 is defined as the width WU.

  Further, the width WU of the non-conductor portion 18 may vary for each internal electrode layer 12.

  The non-conductor portion 18 of the present embodiment is obtained by subjecting the end portion of the internal electrode layer 12 to oxidation treatment, nitriding treatment, or alloying treatment by sputtering. Further, the width WU of the non-conductor portion 18 can be controlled by changing a holding time, a sputtering time, or the like when the end portion of the internal electrode layer 12 is oxidized or nitrided.

The widths Wgap on both sides in the X-axis direction of the ceramic sintered body 4 may be the same as or different from each other. Further, the widths W1 on both sides of the ceramic sintered body 4 in the X-axis direction may be the same or different from each other. Furthermore, the mean value d _a retraction distance of the device body 3 may also be the same or different from each other.

  It is preferable that the insulating layer 16 does not cover the both end surfaces in the Y-axis direction of the element body 3 shown in FIG. This is because external electrodes 6 and 8 need to be formed on both end surfaces in the Y-axis direction of the element body 3 and connected to the internal electrode layer 12. Further, the external electrodes 6 and 8 of the present embodiment may be configured to cover the insulating layer extension 16a.

  The thickness td of the inner dielectric layer 10 is not particularly limited, and is preferably 0.1 μm to 5.0 μm.

  The thickness te of the internal electrode layer 12 is not particularly limited, and is preferably 0.1 μm to 5.0 μm.

  The thickness to of the exterior region 11 is not particularly limited, and is preferably 0.1 to 5.0 μm.

Manufacturing Method of Multilayer Ceramic Capacitor Next, a manufacturing method of the multilayer ceramic capacitor 2 as one embodiment of the present invention will be specifically described. In the multilayer ceramic capacitor 2 according to the present embodiment, a green chip is produced by a normal printing method or sheet method using a paste, and this is fired, and then an insulating layer paste is applied and baked to form an insulating layer 16. The external electrodes 6 and 8 are manufactured by printing or transferring and baking.

  First, in order to manufacture the inner green sheet 10a that will constitute the inner dielectric layer 10 shown in FIG. 1 and the outer green sheet 11a that will constitute the outer dielectric layer after firing, the inner green sheet paste and Prepare the outer green sheet paste.

  The inner green sheet paste and the outer green sheet paste are usually composed of an organic solvent-based paste or an aqueous paste obtained by kneading ceramic powder and an organic vehicle.

  The raw material for the ceramic powder is appropriately selected from various compounds to be composite oxides and oxides, such as carbonates, nitrates, hydroxides, organometallic compounds, and the like, and can be used as a mixture. In this embodiment, the raw material of the ceramic powder is used as a powder having an average particle size of 0.45 μm or less, preferably about 0.1 to 0.3 μm. In order to make the inner green sheet extremely thin, it is desirable to use a powder finer than the thickness of the green sheet.

  An organic vehicle is obtained by dissolving a binder in an organic solvent. The binder used for the organic vehicle is not particularly limited, and may be appropriately selected from usual various binders such as ethyl cellulose and polyvinyl butyral. The organic solvent to be used is not particularly limited, and may be appropriately selected from various organic solvents such as alcohol, acetone and toluene.

  In addition, the green sheet paste may contain additives selected from various dispersants, plasticizers, dielectrics, subcomponent compounds, glass frit, insulators, and the like, if necessary.

  Examples of the plasticizer include phthalate esters such as dioctyl phthalate and benzylbutyl phthalate, adipic acid, phosphate esters, glycols, and the like.

  Next, in order to manufacture the internal electrode pattern layer 12a which will constitute the internal electrode layer 12 shown in FIG. 1 after firing, an internal electrode layer paste is prepared. The internal electrode layer paste is prepared by kneading the above-described conductive material made of various conductive metals or alloys and the above-described organic vehicle.

  When Ni is used as the conductive material, for example, Ni powder produced using a commercially available CVD method, wet chemical reduction method, or the like may be used.

  In the present embodiment, first, a conductive material made of the various conductive metals and alloys described above and the organic vehicle described above are kneaded to produce an internal electrode layer paste.

  Next, a common material is added to the internal electrode layer paste and kneaded to prepare an internal electrode layer paste for the nth layer.

  In addition to the above, a common material is added to the internal electrode layer paste and kneaded to prepare an internal electrode layer paste for the (n + 1) th layer.

  When controlling the dispersion of the pull-in distance at the end of the internal electrode layer 12 by the amount of the common material, the content of the common material in the internal electrode layer paste for the nth layer and the internal electrode layer for the (n + 1) th layer The content of the paste common material is different.

  The component of the common material is not particularly limited, and for example, the same component as the component constituting the main component of the dielectric layer can be used.

  Next, the inner green sheet 10a is formed on a carrier sheet (for example, a PET film) as a support by a doctor blade method or the like. The inner green sheet 10a is dried after being formed on the carrier sheet.

  Next, as shown in FIG. 4, the nth internal electrode pattern layer 12a is formed on the surface of the inner green sheet 10a using the nth internal electrode layer paste. Further, the inner green sheet 10a is formed in the same manner as described above, and the n + 1th internal electrode pattern layer is formed on the surface thereof using the n + 1th internal electrode layer paste.

  In this way, the inner green sheet 10a on which the nth internal electrode pattern layer is formed and the inner green sheet 10a on which the (n + 1) th internal electrode pattern layer is formed are alternately laminated, and the inner lamination shown in FIG. The body 13a is manufactured.

  And after manufacturing the inner laminated body 13a, the outer side green sheet paste is used, the outer side green sheet 11a is formed, and it presses in a lamination direction, and obtains a green laminated body.

  By doing in this way, after baking a green laminated body, the content of the common material contained in the n-th internal electrode layer 12 and the content of the common material contained in the n + 1-th internal electrode layer 12 are different. The main body 3 is obtained. That is, two types of internal electrode layers 12 having different contents of common materials are alternately stacked on the element body 3 with the inner dielectric layer 10 interposed therebetween. When the dispersion of the pull-in distance is controlled by a method other than the amount of the common material, the amount of the common material may be the same.

  In addition to the above, the green laminate may be manufactured by alternately stacking a predetermined number of inner green sheets 10a and internal electrode pattern layers 12a directly on the outer green sheet 11a, and pressing in the laminating direction. You may get

  Further, when the inner laminate 13a is manufactured, as shown in FIG. 5A (a), in the n-th layer, a gap 32 of the inner electrode pattern layer 12a is formed in the Y-axis direction, and the flat is continuous in the X-axis direction. The internal electrode pattern layer 12a is formed.

  Next, as shown in FIG. 5A (b), also in the (n + 1) th layer, the gap 32 of the internal electrode pattern layer 12a is formed in the Y-axis direction, and the continuous flat internal electrode pattern layer 12a is formed in the X-axis direction. To do. At this time, the gap 32 between the n-th layer and the (n + 1) th internal electrode pattern layer 12a is formed so as not to overlap in the Z-axis direction, which is the stacking direction.

  In this way, a plurality of inner green sheets 10a having the internal electrode pattern layer 12a are stacked to manufacture the internal stacked body 13a, and the green stacked body is obtained by the above method.

  Next, the green laminated body is cut along the C1 cut surface and the C2 cut surface of FIGS. 5A (a), 5A (b), 6A, and 6B to obtain green chips. C1 is a cutting plane parallel to the YZ axis plane, and C2 is a cutting plane parallel to the ZX axis plane.

  As shown in FIG. 5A (a), the C2 cut surface adjacent to the C2 cut surface that cuts the internal electrode pattern layer 12a in the nth layer cuts the gap 32 of the internal electrode pattern layer 12a. Further, the C2 cut surface obtained by cutting the internal electrode pattern layer 12a in the nth layer cuts the gap 32 of the internal electrode pattern layer 12a in the n + 1th layer.

  By obtaining a green chip by such a cutting method, the n-th internal electrode pattern layer 12a of the green chip is exposed at one cut surface and not at the other cut surface in the C2 cut surface of the green chip. It becomes composition. Further, the n + 1-th internal electrode pattern layer 12a of the green chip is exposed at the cut surface of the C2 cut surface of the green chip where the internal electrode pattern layer 12a is exposed at the nth layer. First, the internal electrode pattern layer 12a is exposed at the cut surface of the nth layer where the internal electrode pattern layer 12a is not exposed.

  Further, the internal electrode pattern layer 12a is exposed in all layers on the C1 cut surface of the green chip.

  In addition, it does not specifically limit as a formation method of the internal electrode pattern layer 12a, You may form by thin film formation methods, such as vapor deposition and sputtering other than the printing method and the transfer method.

  Further, the step absorption layer 20 may be formed in the gap 32 of the internal electrode pattern layer 12a. By forming the step absorption layer 20, there is no step due to the internal electrode pattern layer 12a on the surface of the green sheet 10a, which contributes to preventing deformation of the finally obtained ceramic sintered body 4.

  The step absorption layer 20 is formed by a printing method or the like, for example, similarly to the internal electrode pattern layer 12a. The step absorption layer 20 includes a ceramic powder and an organic vehicle similar to the green sheet 10a. However, unlike the green sheet 10a, the step absorption layer 20 is formed by printing and is adjusted so that printing is easy. Examples of the printing method include screen printing and gravure printing.

  The green chip is solidified by removing the plasticizer by solidification drying. The green chip after solidification drying is put into a barrel container together with a medium and a polishing liquid, and barrel-polished by a horizontal centrifugal barrel machine or the like. The green chip after barrel polishing is washed with water and dried. The element body 3 is obtained by performing a binder removal process, a baking process, and an annealing process performed as necessary on the dried green chip.

  The binder removal step may be performed under known conditions. For example, the holding temperature may be 200 ° C. to 400 ° C.

  In the present embodiment, the firing process and the annealing process are performed in a reducing atmosphere. Other firing conditions or annealing conditions may be known conditions. For example, the firing holding temperature is 1000 ° C. to 1300 ° C., and the annealing holding temperature is 500 ° C. to 1000 ° C.

  The binder removal step, the firing step, and the annealing step may be performed continuously or independently.

  After annealing, the end of the internal electrode layer in the X-axis direction is insulated. Examples of the insulating treatment method include wet etching, oxidation treatment, ion milling, nitriding treatment, and alloying.

For example, the end portion in the X-axis direction of the internal electrode layer 12 containing Ni is obtained by performing wet etching with FeCl _{3 on} the end surface in the X-axis direction of the element body 3 and performing an oxidation treatment in an atmosphere. Thus, the end of the internal electrode layer 12 in the X-axis direction can be insulated.

As described above, in the element body 3 of the present embodiment, the content of the common material contained in the nth internal electrode layer 12 is different from the content of the common material contained in the n + 1th internal electrode layer 12. Therefore, by performing wet etching with FeCl ₃ , the internal electrode layer 12 with a large amount of co-material is less likely to be scraped, and the internal electrode layer 12 with less co-material tends to be more easily scraped. The pull-in distance of the internal electrode layer 12 is dispersed.

The conditions for wet etching and oxidation treatment are not particularly limited, but it is preferable to perform the conditions under the following conditions.
<Wet etching>
FeCl ₃ etching solution: 10 to 30 parts by weight of FeCl ₃ is added to 100 parts by weight of the etching solution.
Etching time: 5 to 720 sec.
<Oxidation treatment>
Temperature increase (temperature decrease) rate: 10 ° C. to 5000 ° C./hour Holding temperature: 500 ° C. to 1000 ° C.
Atmosphere: in the air

  Next, an insulating layer paste is applied to both end faces in the X-axis direction of the element body 3 and baked to form the insulating layer 16, thereby obtaining the ceramic sintered body 4 shown in FIGS. 1 and 2. The insulating layer 16 not only enhances the insulation, but also improves the moisture resistance.

  In the case of applying the insulating layer paste, the paste is not limited to both ends of the element body 3 in the X axis direction, but both ends of the element body 3 in the Z axis direction and / or the Y axis. You may make it apply | coat also to the both ends of the X-axis direction of the both end surfaces of a direction.

  When the insulating layer 16 is made of glass, this insulating layer paste is obtained, for example, by kneading a glass raw material, a binder mainly composed of ethyl cellulose, terpineol and acetone, which are dispersion media, with a mixer.

  In the case where the insulating layer 16 is made of resin, the insulating layer paste is not used, and the X-axis end of the element body 3 and the both end faces of the element body 3 in the Z-axis direction are used as the resin. And / or applied to both ends in the X-axis direction of both end surfaces in the Y-axis direction.

  The method for applying the insulating layer paste to the element body 3 is not particularly limited, and examples thereof include dip, printing, application, vapor deposition, and sputtering.

  The element body 3 is coated with an insulating layer paste, dried, treated to remove the binder, and baked to obtain a ceramic sintered body 4.

  The glass component liquefied at the time of baking easily enters the gap from the end of the inner dielectric layer 10 to the end of the internal electrode layer 12 by capillary action. Accordingly, the insulating layer 16 surely fills the voids, and not only enhances the insulation, but also improves the moisture resistance.

  When the insulating layer 16 is a resin, the resin is applied to a predetermined portion of the element body 3 and then only dried.

  The end surfaces of the ceramic sintered body 43 obtained as described above are subjected to end surface polishing, for example, by barrel polishing or sand blasting, if necessary, on both end surfaces in the Y axis direction and / or both end surfaces in the Z axis direction.

  Next, the external electrode paste is applied and baked on both end surfaces in the Y-axis direction of the ceramic sintered body on which the insulating layer 16 is baked to form the external electrodes 6 and 8. The external electrode paste may be prepared in the same manner as the internal electrode layer paste described above.

  When the end portion of the internal electrode layer 12 is oxidized, the internal portions exposed to both end surfaces in the Y-axis direction of the ceramic sintered body 4 in which the external electrodes 6 and 8 are formed. The end portion of the electrode layer 12 may also be oxidized. Therefore, when the oxidation treatment is performed, it is preferable to reduce both ends of the ceramic sintered body 4 in the Y-axis direction before applying the external electrode paste or when baking the external electrode paste.

  The external electrodes 6 and 8 may be formed prior to the formation of the insulating layer 16, may be performed after the formation of the insulating layer 16, or may be performed simultaneously with the formation of the insulating layer 16. After the layer 16 is formed.

  Also, the method of forming the external electrodes 6 and 8 is not particularly limited, and an appropriate method such as application / baking of an external electrode paste, plating, vapor deposition, or sputtering can be used.

  Then, if necessary, a coating layer is formed on the surfaces of the external electrodes 6 and 8 by plating or the like.

  The multilayer ceramic capacitor 2 of the present embodiment manufactured as described above is mounted on a printed circuit board by soldering or the like, and used for various electronic devices.

  Conventionally, since a part of the dielectric layer was used as a gap portion, a blank space on the surface of the green sheet where the internal electrode pattern layer is not formed at predetermined intervals along the X-axis direction in the portion that becomes the gap portion after firing. A pattern was formed.

  On the other hand, in the present embodiment, the internal electrode pattern layer is formed continuously along the X-axis direction, and the gap portion is obtained by forming an insulating layer on the element body. For this reason, a blank pattern for forming the gap portion is not formed. Therefore, unlike the conventional method, a flat internal electrode pattern layer film is formed on the green sheet. For this reason, the acquisition number of green chips per area of the green sheet can be increased as compared with the conventional case.

  Further, in the present embodiment, unlike the conventional case, it is not necessary to care about the blank pattern when cutting the green laminated body, so that the cutting yield is improved as compared with the conventional case.

  Furthermore, conventionally, when green sheets are stacked, the margin pattern portion is thinner than the portion where the internal electrode pattern layer is formed, and the cutting surface of the green chip is curved when cut. was there. Further, conventionally, since the bulge is formed near the blank pattern portion of the internal electrode pattern layer, the internal electrode layer has irregularities, and there is a possibility that the internal electrode or the green sheet is deformed by laminating them. On the other hand, in the present embodiment, no blank pattern is formed, and the rising of the internal electrode pattern layer is not formed.

  Further, in the present embodiment, the internal electrode pattern layer is a flat film, the internal electrode pattern layer does not swell, and the internal electrode pattern layer does not bleed or blur near the gap portion. Capacity can be improved. This effect is more remarkable as the element body is smaller.

  As mentioned above, although embodiment of this invention has been described, this invention is not limited to the embodiment mentioned above at all, and can be variously modified within the range which does not deviate from the summary of this invention.

  For example, in each of the internal electrode layers 12, as a method of dispersing the pull-in distance at the end of the internal electrode layer 12 in the X-axis direction or changing the degree of dispersion, a predetermined internal electrode pattern layer is used in the above. Although a method of performing wet etching has been shown, it is not limited to the above method.

  In addition to the above method, by forming the non-conductor portion 18 at the end portion of the internal electrode layer 12 in the X-axis direction, the end portions of the internal electrode layer 12 in the X-axis direction can be formed in each layer of the internal electrode layer 12. The pull-in distance can be dispersed and the degree of dispersion can be changed.

  Specifically, the non-conductor portion 18 can be formed by oxidizing, nitriding, or alloying the end portion of the internal electrode layer 12 in the X-axis direction.

  In this case, the element body 3 used may be an element body 3 in which two types of internal electrode layers 12 having different contents of the above-mentioned common materials are alternately stacked with the inner dielectric layer 10 interposed therebetween, The element body 3 in which internal electrode layers 12 having the same content of the common material are alternately stacked with the inner dielectric layer 10 interposed therebetween may be used, or the internal electrode layer 12 may not include the common material. .

  Further, the method for oxidizing the end portion of the internal electrode layer 12 in the X-axis direction is not particularly limited, and may be oxidized under the above-described oxidation treatment conditions, or may be applied to the end portion of the element body 3 in the X-axis direction. The oxidation may be performed by applying a gas laser and raising the temperature with a laser, or nickel oxide may be applied to the end of the internal electrode layer 12 in the X-axis direction by sputtering or the like.

  The internal electrode pattern layer 12a is a pattern having gaps 32 in the lattice-like internal electrode pattern layer 12a as shown in FIG. 5B in addition to the patterns shown in FIGS. 5A (a) and 5A (b). May be.

  The multilayer electronic component of the present invention is not limited to multilayer ceramic capacitors, and can be applied to other multilayer electronic components. Other laminated electronic components are all electronic components in which dielectric layers are laminated via internal electrodes. For example, bandpass filters, chip inductors, laminated three-terminal filters, piezoelectric elements, chip thermistors, chip varistors, chips Examples include resistors and other surface mount (SMD) chip type electronic components.

  Hereinafter, although this invention is demonstrated based on a more detailed Example, this invention is not limited to these Examples.

Example 1
As described below, capacitor samples of Sample No. 1 to Sample No. 10 were produced, and CV values indicating the degree of dispersion of the pull-in distance of the internal electrode layers were measured and the insulation resistance defect rate was evaluated.

First, 100 parts by weight of BaTiO ₃ based ceramic powder, 10 parts by weight of polyvinyl butyral resin, 5 parts by weight of dioctyl phthalate (DOP) as a plasticizer, and 100 parts by weight of alcohol as a solvent are mixed by a ball mill. Thus, a paste for the inner green sheet was obtained.

  In addition to the above, 44.6 parts by weight of Ni particles, 52 parts by weight of terpineol, 3 parts by weight of ethyl cellulose, and 0.4 parts by weight of benzotriazole are kneaded with three rolls to form a slurry. Thus, an internal electrode layer paste was prepared.

Further, 15.0 parts by weight of BaTiO ₃ as a co-material was added to 100 parts by weight of the internal electrode layer paste, and an internal electrode layer paste for the nth layer kneaded by three rolls was prepared.

Further, 30.0 parts by weight of BaTiO ₃ as a co-material was added to 100 parts by weight of the internal electrode layer paste, and an internal electrode layer paste for the (n + 1) th layer kneaded by three rolls was produced.

  In this manner, two types of internal electrode layer pastes were prepared: an internal electrode layer paste for the nth layer and an internal electrode layer paste for the (n + 1) th layer.

  Using the inner green sheet paste prepared above, an inner green sheet was formed on a PET film so that the thickness after drying was 7 μm. Next, the n-th internal electrode pattern layer 12a is formed in a predetermined pattern using the internal electrode layer paste for the n-th layer thereon, and then the sheet is peeled off from the PET film, The inner green sheet 10a having the electrode pattern layer 12a was obtained.

  Moreover, the inner side green sheet 10a was formed on the PET film so that the thickness after drying might be set to 7 micrometers using the paste for inner side green sheets produced above. Next, an n + 1-th internal electrode pattern layer 12a is formed in a predetermined pattern using an n + 1-th internal electrode layer paste thereon, then the sheet is peeled off from the PET film, and the n + 1-th layer internal electrode layer 12a is formed. The inner green sheet 10a having the electrode pattern layer 12a was obtained.

  In this way, two types of inner green sheets having the internal electrode pattern layers 12a having different contents of the common material were alternately laminated to produce an internal laminate 13a shown in FIG.

  Next, using the outer green sheet paste on the upper and lower sides of the inner laminate 13a, an appropriate number of outer green sheets 11a were formed and pressure-bonded in the laminating direction to obtain a green laminate. The outer green sheet paste was obtained in the same manner as the inner green sheet paste.

  Next, as shown in FIGS. 5A (a), 5A (b), 6A, and 6B, the green laminate was cut along the C1 cut surface and the C2 cut surface to obtain green chips.

  Next, the obtained green chip was subjected to binder removal processing, firing and annealing under the following conditions to obtain an element body 3.

  The binder removal treatment conditions were a temperature rising rate of 60 ° C./hour, a holding temperature: 260 ° C., a holding time: 8 hours, and an atmosphere: in the air.

The firing conditions were a temperature rising rate of 200 ° C./hour, a holding temperature of 1000 ° C. to 1200 ° C., and a temperature holding time of 2 hours. The cooling rate was 200 ° C./hour. The atmosphere gas was a humidified N ₂ + H ₂ mixed gas.

The annealing conditions were temperature rising rate: 200 ° C./hour, holding temperature: 500 ° C. to 1000 ° C., temperature holding time: 2 hours, cooling rate: 200 ° C./hour, and atmospheric gas: humidified N ₂ gas.

  A wetter was used for humidifying the atmospheric gas during firing and annealing.

After annealing, an insulation process was performed on the X-axis end of the internal electrode layer. By performing wet etching with an etching solution having a FeCl ₃ concentration of 15% by weight, the X-axis end portion of the internal electrode layer was drawn inward and insulation was performed. The etching time was as shown in Table 1.

  Next, glass powder, a binder mainly composed of ethyl cellulose, and tarpione and acetone as dispersion media were kneaded with a mixer to prepare an insulating layer paste.

Insulating layer paste is applied by dipping on the entire X-axis end face of the element body 3, the X-axis end of the Y-axis end face, and the X-axis end of the Z-axis end face, and then dried. Then, the obtained chip was subjected to binder removal processing and baking using a belt conveyor furnace to form an insulating layer 16 on the element body 3 to obtain a ceramic sintered body 4. The drying, binder removal, and baking conditions of the insulating layer paste were as follows.
Drying temperature: 180 ° C
Binder removal Temperature rising rate: 1000 ° C / hour Holding temperature: 500 ° C
Temperature holding time: 0.25 hours Atmosphere: Baking in air Temperature rising rate: 700 ° C / hour Holding temperature: 700 ° C to 1000 ° C
Temperature holding time: 0.5 hour Atmosphere: humidified N ₂ gas

  The end surface in the Y-axis direction of the obtained ceramic sintered body 4 was polished by barrel treatment.

  Next, 100 parts by weight of a mixture of spherical Cu particles having an average particle diameter of 0.4 μm and flaky Cu powder, and 30 parts by weight of an organic vehicle (5 parts by weight of ethyl cellulose resin dissolved in 95 parts by weight of butyl carbitol) And 6 parts by weight of butyl carbitol were kneaded to obtain a paste for an external electrode.

The obtained paste for external electrodes was transferred to the end surface in the Y-axis direction of the ceramic sintered body 4 and fired at 850 ° C. for 10 minutes in an N ₂ atmosphere to form external electrodes, whereby a multilayer ceramic capacitor 2 was obtained.

  The size of the capacitor sample (multilayer ceramic capacitor 2) manufactured as described above was 3.2 mm × 2.5 mm × 1.5 mm, and the inner dielectric layer 10 was 10 layers. The thickness of the inner dielectric layer 10 is 5.0 μm, the thickness of the internal electrode layer 12 is about 1.2 μm, and the width Wgap in the X-axis direction of the gap portion formed by the insulating layer 16 is about 20. It was 0 μm.

  The obtained capacitor sample or the like was measured or evaluated by the following method.

<CV value>
Resin filling is performed so that the capacitor sample stands with the end surface in the Y-axis direction facing down, the other end surface is polished along the Y-axis direction of the multilayer ceramic capacitor 2, and the length of the element body 3 in the Y-axis direction is A polished cross-section of 1 / 2L0 was obtained. Next, ion milling was performed on the polished cross section to remove sagging due to polishing. In this way, a cross section for observation was obtained.

Next, the pull-in distance of the end portion in the X-axis direction of the internal electrode layer 12 shown in FIG. 3A was measured at 20 points per cross section of one sample. This operation was performed on 10 capacitor samples. And an average value d _a retraction distance of the measured 200 points was determined CV value by the equation (1). In addition, it did not count about the location where the internal electrode layer 12 is missing.

  For the measurement of the pull-in distance, a digital microscope (VHX microscope manufactured by Keyence Corporation) was used, and observation and measurement were performed with a 5000 × lens. When observing with a digital scope, a clear difference appears between the insulating layer 16 with low brightness and Ni with high brightness by observing in the internal light mode. Therefore, the internal electrode including the insulating layer 16 and Ni is used. The boundary of the layer 12 can be determined. The results are shown in Table 1.

<Insulation resistance defect rate>
With respect to the capacitor samples, the insulation resistance of 100 capacitor samples was measured with a digital resistance meter (R8340 manufactured by ADVANTEST) at room temperature under the conditions of a measurement voltage of 4 V and a measurement time of 30 seconds. The average specific resistance value was calculated from the electrode area of the capacitor sample and the thickness of the inner dielectric layer 10. The results are shown in Table 1. It is preferable that the specific resistance is high, and it is determined that the specific resistance value is less than 1.0 × 10 ⁹ Ωcm for all the measured samples if it is 25% or less, and if it is 15% or less, it is even better. It was judged. In Table 1, it has described with (circle), (triangle | delta), and x in order from the one where an insulation resistance defect rate is favorable.

  From sample number 1 to sample number 10, when the CV value is 1.0 or less, the CV value is 1.198 (sample number 9) and the CV value is 2.241 (sample number 10). It was confirmed that the insulation resistance defect rate was good. Furthermore, when the CV value was 0.05 or more and 1.0 or less, it was confirmed that the insulation resistance defect rate was even better than when the CV value was 0.023 (Sample No. 1).

  In the case of sample number 1, the CV value is relatively low, that is, the pull-in distance is not dispersed. Therefore, when the inner dielectric layer is thinned, the electric field tends to concentrate on the end of the internal electrode layer in the X-axis direction. Therefore, it is considered that the insulation resistance defect rate is higher than that in the case of sample numbers 2 to 8.

  In the case of sample number 9 and sample number 10, since the CV value is too high, that is, the dispersion of the pull-in distance is too large, structural defects are likely to occur, and as a result, the insulation resistance failure rate is the case of sample numbers 1 to 8. It seems that it was higher than that.

Example 2
Except that the FeCl ₃ concentration of the etching solution and the etching time were changed as shown in Table 2, capacitor samples of Sample No. 11 to Sample No. 24 were prepared in the same manner as in Example 1, and the Q value was measured and insulated. The resistance failure rate, the capacitance ratio (C / C40), and the dielectric breakdown voltage failure rate were evaluated. The results are shown in Table 2. For sample number 13, the CV value was also measured. The results are shown in Table 3.

  The insulation resistance defect rate of sample numbers 11 to 24 and the CV value of sample number 13 were measured in the same manner as in Example 1. The measurement method of the Q value and the evaluation method of the capacitance ratio and the breakdown voltage failure rate are as follows.

<Q value>
A capacitor sample was prepared, and a cross section for observation was obtained in the same manner as in the case of the CV value.
Next, at 20 points per cross section of one sample, the pull-in distance of the end portion in the X-axis direction of the internal electrode layer 12 shown in FIG. 3C is measured, and the inner dielectric layer 10 between the measured internal electrode layers 12 is measured. The thickness td _k was measured. This operation was performed on 10 capacitor samples. The average of | d _{k + 1} −d _k | is _obtained based on the measured pull-in distances at 200 locations, the average td _a of the thickness td _k of the inner dielectric layer 10 is obtained, and the Q value is calculated by the above equation (2). Asked. In addition, it did not count about the location where the internal electrode layer 12 is missing.

  For the measurement of the pull-in distance and the thickness of the inner dielectric layer 10, a digital microscope (VHX microscope manufactured by Keyence Corporation) was used, and observation and measurement were performed in the same manner as in the case of the CV value. The results are shown in Table 2.

<Capacitance ratio (C / C40)>
The electrostatic capacity of 100 capacitor samples was measured with a digital LCR meter at 25 ° C. under the conditions of 1 kHz and 5.0 Vrms, and the average value (C) was obtained. Further, under the same conditions, the capacitance of 100 conventional products having the same chip size as in this example and having a gap width Wgap (side gap) of 40 μm was measured, and the average value (C40) was obtained. The capacitance ratio (C / C40) was determined. The results are shown in Table 2. The case where the capacitance ratio (C / C40) was 1.2 or more was judged to be particularly good, the case where 1.0 to 1.1 was good, and the case where it was less than 1.0 was judged as bad. In Table 2, “O”, “Δ”, and “X” are shown in order from the one with the better capacitance ratio (C / C40).

<Dielectric breakdown voltage failure rate>
Using a breakdown voltage measuring device, the capacitor sample was boosted at 10 V / sec, the voltage was continuously applied, the voltage at which a current of 10 mA flowed was defined as the breakdown voltage, and the value divided by the thickness of the inner dielectric layer 10 The breakdown voltage value was used. A capacitor sample having a dielectric breakdown at 40 V / μm or less was regarded as defective, and the defect rate in 100 capacitor samples was determined. The results are shown in Table 2. The case where the breakdown voltage failure rate was 20% or less was judged good, the case where it was 15% or less was further good, and the case where it was 3% or less was judged very good. In Table 2, ◎, ○, Δ, and X are listed in order from the one with the better breakdown voltage failure rate.

  From sample number 11 to sample number 24, when the Q value is 0.004 or more and 0.300 or less (sample numbers 13, 14, 16, 17, 18, 21, 22, 23), the Q value is less than 0.004. It was confirmed that the capacitance ratio (C / C40) was better than in the case of (Sample Nos. 19 and 24).

  Further, from the sample numbers 11 to 24, when the Q value is 0.004 or more and 0.300 or less (sample numbers 13, 14, 16, 17, 18, 21, 22, 23), the Q value is 0.00. It was confirmed that the dielectric breakdown voltage defect rate was better than in the case of exceeding 300 (sample numbers 11, 12, 15 and 20).

  When the Q value is less than 0.004 (sample numbers 19 and 24), it means that the dispersion of the pull-in distance of the adjacent internal electrode layers is too large, thereby comparing with a sample having a Q value of 0.004 or more. Thus, it is considered that the capacitance is defective.

  When the Q value is more than 0.300 (sample numbers 11, 12, 15 and 20), it means that the dispersion of the pull-in distances of the adjacent internal electrode layers is too small, so that the Q is 0.300 or less. It is thought that the breakdown voltage failure rate is worse than that.

Example 3
The composition and softening point of the glass contained in the insulating layer 16 are shown in Table 4, except that the holding temperature during baking of the insulating layer paste is 700 ° C., and the thickness of the inner dielectric layer is 1.6 μm. Capacitor samples of sample number 25 to sample number 29 were prepared in the same manner as in Example 1 to measure the Q value, insulation resistance failure rate, capacitance ratio (C / C40), dielectric breakdown voltage failure rate, and deflection strength. Evaluated. The results are shown in Table 5.

Incidentally, _BaO in the glass of sample No. 25 to sample No. 29 in Table 4, the composition of _{SiO 2, Na 2 O, Bi} 2 O 3 is the sum is not in 100% by weight, which is a glass powder This is because it contains minute components other than BaO, SiO ₂ , Na ₂ O, and Bi ₂ O ₃ .

  In addition, the measurement of the Q value and the evaluation of the insulation resistance failure rate, the capacitance ratio (C / C40) and the dielectric breakdown voltage failure rate of sample numbers 25 to 29 were performed in the same manner as in Example 1 or Example 2. It was. The evaluation method of deflection strength is as follows.

<Deflection strength>
The capacitor sample 102 was mounted on the glass epoxy substrate 104 (FIG. 7), and a predetermined load was applied for 5 seconds from the direction of the arrow P1 by the push rod 106 so that the deflection amount was 1.0 mm. Then, the ratio of the defective deflection product of 100 capacitor samples was determined as a defective defective product whose capacitance changed by ± 10% or more compared to the initial capacitance. In this embodiment, less than 15% is judged as good and is marked with ◯. Moreover, x is attached when it is 15% or more. The internal structure of the capacitor sample 102 according to this example is the same as that of the multilayer ceramic capacitor 2 shown in FIGS.

From sample number 25 to sample number 29, when both BaO and SiO ₂ are included as glass components (sample number 28 and sample number 29), when either one of BaO and SiO ₂ is included (sample number 25) It was confirmed that the deflection strength was better than that of Sample No. 27).

  When the insulating layer contains both Si and Ba (sample number 28 and sample number 29), since the insulating layer has the same composition as the dielectric layer, a reaction phase is easily formed between the insulating layer and the dielectric layer. In addition, the adhesion between the insulating layer and the element body is increased. As a result, even if the thickness of the inner dielectric layer was reduced to 1.6 μm, it was possible to have resistance against external stress due to deflection and to obtain good results with respect to the deflection strength. .

Example 4
Except that the thickness td _a of the inner dielectric layer 10 was changed as described in Table 6, to prepare a sample No. 30 Sample No. 32 in the same manner as in Example 1, confirmation of the presence or absence of the non-conductor portion 18, measurements and insulation resistance defect rate td _a, were evaluated breakdown voltage defect rate and short-circuit defect rate. The results are shown in Table 6. In the column “Presence / absence of non-conductor portion”, the case where there is a non-conductor portion is indicated as “◯”, and the case where there is no non-conductor portion is indicated as “X”.

Further, the thickness td _a of the inner dielectric layer 10 is changed as described in Table 6, after the element body 3 is wet-etched, except where oxidizing treatment under the following conditions, the sample number in the same manner as in Example 1 Sample No. 33 to sample No. 35 were confirmed, the presence / absence of the non-conductor portion 18 was confirmed, the average width (WU _a ) and td _a of the non-conductor portion 18 were measured, and the insulation resistance failure rate, breakdown voltage failure rate, and short failure The rate was evaluated. The results are shown in Table 6.

The evaluation of the measurement as well as the insulation resistance defect rate and breakdown voltage failure rate of td _k of sample No. 30 to sample No. 35 was carried out in the same manner as in Example 1 and Example 2. The method for confirming the presence / absence of the non-conductor portion 18, the method for measuring the width (WU) of the non-conductor portion 18 and the method for evaluating the short-circuit defect rate are as described below.

<Oxidation treatment conditions>
Temperature rising rate: 250 ° C / hour Holding temperature: 600 ° C
Temperature holding time: 12 hours Atmosphere: in air

<Non-conductor width (WU)>
A capacitor sample was prepared, and a cross section for observation was obtained in the same manner as in the case of the CV value.
Next, the width WU of the non-conductor portion 18 shown in FIG. 3B was measured at 20 points per cross section of one sample. As shown in FIG. 3B, the widest portion of one non-conductor portion 18 is defined as the width WU. This operation was performed on 10 capacitor samples. The average value (width WU _a ) of the width WU was determined based on the measured width WU at 200 locations. In addition, it did not count about the location where the internal electrode layer 12 is missing.

  For measurement of the width WU, a digital microscope (VHX microscope manufactured by Keyence Corporation) was used, and observation and measurement were performed with a 5000 × lens. When observing with a digital scope, a clear difference appears between NiO with low brightness and Ni with high brightness by observing in the internal light mode. Therefore, the width of the non-conductor portion 18 made of NiO WU can be measured. The results are shown in Table 6.

<Short defective rate>
The resistance value of each capacitor sample was measured using an insulation resistance meter (E2377A manufactured by HEWLETT PACKARD), and a sample having a resistance value of 100 kΩ or less was determined as a short-circuit defective sample. The above measurement was performed on 100 capacitor samples, and the ratio of the samples that caused the short failure to the total measurement samples was defined as the short failure rate. The results are shown in Table 6. In this example, 15% or less was judged good. Further, in Table 6, the case where the short-circuit defect rate is 15% or less is described as ◯, and the case where it is over 15% is described as ×.

  From Sample No. 30 to Sample No. 35, when the non-conductor portion is provided (Sample No. 33 to Sample No. 35), the inner dielectric layer is formed as compared with the case where there is no non-conductor portion (Sample No. 30 to Sample No. 32). It was confirmed that the short-circuit defect rate was good even when the layer was thinned.

  A major cause of shorting is handling when applying an insulator. The thinner the inner dielectric layer, the higher the short-circuit defect rate (sample number 30 to sample number 32). (Sample No. 33 to Sample No. 35), it was confirmed that the short-circuit defect rate drastically decreased.

Example 5
Example 1 except that the thickness td _a of the inner dielectric layer 10 was changed as shown in Table 7 and the end portion of the internal electrode layer 12 was processed under the following conditions after the element body 3 was wet etched. Similarly, sample numbers 36 to 38 were prepared, and the average widths WU _a and td _a of the non-conductor portion 18 were measured, and the insulation resistance failure rate and the dielectric breakdown voltage failure rate were evaluated. The results are shown in Table 7. The evaluation of the measurement as well as the insulation resistance defect rate and breakdown voltage failure rate of td _a sample No. 36 to sample No. 38 was carried out in the same manner as in Example 1 and Example 2.

<Treatment of edge of internal electrode layer of sample number 36>
Oxidation condition at end of internal electrode layer 12: box furnace Temperature rising rate: 250 ° C./hour Holding temperature: 600 ° C.
Temperature holding time: 12 hours Atmosphere: in air

<Treatment of edge of internal electrode layer of sample number 37>
Nitriding conditions at the end of the internal electrode layer 12: Nitriding furnace Temperature rising rate: 250 ° C./hour Holding temperature: 600 ° C.
Temperature holding time: 12 hours Atmosphere: in NH ₃

<Treatment of edge of internal electrode layer of sample number 38>
The alloy condition at the end of the internal electrode layer 12 was sputtering. Specifically, sputtering was performed on the end face of the element body 3 in the X-axis direction using Cr as a target. The conditions were as follows.
Current value: 40 mA
Sputtering time: 60 s × 3 times Thereafter, a Ni—Cr non-conductive coating was formed by performing the same heat treatment as that for the end of the internal electrode layer 12 of sample number 36.

  From sample number 36 to sample number 38, when the non-conductor portion is an oxide (sample number 36), when the non-conductor portion is nitride (sample number 37), or when the non-conductor portion is Ni-Cr alloy (Sample No. 38) was confirmed to have good insulation resistance failure rate and dielectric breakdown voltage failure rate even when the inner dielectric layer was thinned. In Sample No. 36 to Sample No. 38, it is considered that the presence of the non-conductor portion strengthens the adhesiveness between the insulating layer and the element main body, and the breakdown voltage is less likely to occur.

  Further, when the non-conductor portion is an oxide (sample number 36), when the non-conductor portion is a nitride (sample number 37) or when the non-conductor portion is a Ni—Cr alloy (sample number 38). In comparison, it was confirmed that the breakdown voltage failure rate was good.

  As described above, the multilayer electronic component according to the present invention is useful as an electronic component used in a notebook computer or a smartphone that is often used in a small size and a high capacity.

2, 102 ... Multilayer ceramic capacitor 3 ... Element body 4 ... Ceramic sintered body 6 ... First external electrode 8 ... Second external electrode 10 ... Inner dielectric layer 10a ... Inner green sheet 11 ... Exterior region 11a ... Outer green sheet 12 ... Internal electrode layers 12A and 12B ... Leading part 12a ... Internal electrode pattern layer 13 ... Interior region 13a ... Internal laminated body 14 ... Capacitance region 15A, 15B ... Leading region 16 ... Insulating layer 16a ... Insulating layer extension 18 ... Non-conductor part 20 ... Step absorbing layer 32 ... Internal electrode pattern layer gap 104 ... Substrate 106 ... Push rod

Claims (6)

A laminated electronic component comprising an element body in which internal electrode layers and dielectric layers substantially parallel to a plane including the first axis and the second axis are alternately laminated along the direction of the third axis,
An insulating layer is provided on each of a pair of side surfaces facing each other in the direction of the first axis of the element body,
An external electrode electrically connected to the internal electrode layer is provided on each of a pair of end faces facing each other in the direction of the second axis of the element body,
The end in the first axial direction of the internal electrode layer is drawn in at a predetermined drawing distance from the end in the first axial direction of the dielectric layer to the inside along the direction of the first axis.
The multilayer electronic component, wherein the pull-in distance is dispersed in a predetermined range in each of the internal electrode layers.   The multilayer electronic component according to claim 1, wherein a CV value indicating a degree of dispersion of the pull-in distance is 0.05 to 1.0. The thickness of the dielectric layer between the k-th layer of the inner electrode layer and the k + 1 th layer of the inner electrode layer and td _k,
The pull-in distance of the _kth internal electrode layer is d _k ,
The pull-in distance of the internal electrode layer of the (k + 1) th layer is d _{k + 1} ,
When Q value = td _k ² / (td _k ² + | d _{k + 1} −d _k | ² ),
The multilayer electronic component according to claim 1, wherein the Q value is 0.004 to 0.300.   The laminated electronic component according to claim 1, wherein the insulating layer contains Si and Ba.   5. The multilayer electronic component according to claim 1, wherein a nonconductor portion exists between an end portion of the internal electrode layer in the first axial direction and the insulating layer.   The multilayer electronic component according to claim 5, wherein the non-conductor portion includes an oxide of an element constituting the internal electrode layer.

Images