JP2017060272A - Control device of three level invertor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control device of a three level invertors, which can suppress neutral point potentials from being destabilized regardless of the amplitude of input and output of active power and reactive power.SOLUTION: By using a result determined by multiplying a phase ωt held inside an inverter by minus 2, an inverter output current detected value Iis dq-converted. This converts a reversed-phase secondary harmonic component included in the inverter output current detected value Iinto a direct current. The inverter output current detected value Iconverted into the direct current is compared with secondary harmonic command values ID* and IQ*, and then respective deviations thereof are determined. The respective deviations are processed by third and fourth amplifiers 13 and 14, so that a deviation of the reversed-phase secondary harmonic current can be reduced to zero. A resultant voltage command value is converted into a command value on a fixed coordinate by a second dq-inverter 10, which is added to a voltage command value obtained by a first dq-inverter 2.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a three-level inverter that performs current control such as grid connection and motor drive, and more particularly to neutral point potential balance control.

  FIG. 1A is a configuration diagram illustrating a three-level inverter that outputs a three-level phase voltage to the UVW terminal. Each phase voltage is generated by ON / OFF operation of a switching element in the inverter. Further, the ON / OFF operation of the switching element is determined by a gate command described later.

  As a type of the three-level inverter, there is an NPC type shown in FIG. 1B in addition to the T type shown in FIG. In either configuration, the first and second DC capacitors C1 and C2 are connected in series between the DC terminals, and the DC voltage between the DC terminals is divided by half, and this voltage dividing point is set as a neutral point.

FIG. 1C is a configuration example in which a three-level inverter is connected to the system power supply 60. A filter circuit composed of reactors L1, L2 and capacitor C is connected to the inverter output, and the output of the filter path is connected to the system. The filter circuit may be other than the LCL configuration. Although omitted in FIG. 1C, various other loads and power conversion devices are connected to the system power supply 60. The inverter INV converts AC power supplied from the system power supply 60 into _DC and stores it in the voltage source V _DC on the DC side in FIG. Alternatively, the DC power of the voltage source V _DC is converted into AC and supplied to the system power supply 60.

  In addition, the reactive power is exchanged with the system power supply 60, the reactive power output by other loads connected to the system power supply 60 is canceled, the fluctuation of the system voltage amplitude is suppressed, the reactive power compensation is performed, There are applications in which different loads and power conversion devices are connected to the DC side of the device, driving DC loads, and frequency conversion of power using the connected power conversion devices.

FIG.1 (d) is a figure of the control apparatus of a grid connection inverter. The PLL receives the system voltage detection value Vs and outputs a phase signal ωt synchronized therewith. The phase signal ωt is input to a first dq converter 1 and a first dq inverse converter 2 which will be described later. The first low-pass filter LPF1 removes noise, switching ripple, and the like from the inverter output current detection value Iinv. The first dq converter 1 converts the output signal of the first low-pass filter LPF1 into a value on a rotational coordinate synchronized with the system voltage detection value V _S.

  The first and second subtracters 3 and 4 calculate the deviation between the d-axis and q-axis output current command values ID * and IQ * on the dq coordinate and the actual output current detection signal (output of the dq converter 1). Calculate. The first and second amplifiers PI1 and PI2 amplify the outputs of the first and second subtracters 3 and 4 by an operation such as proportional integration to calculate a voltage command value.

The first dq inverse converter 2 converts the voltage command value (outputs of the first and second amplifiers PI1 and PI2) from a value on the rotating coordinate synchronized with the system voltage detection value V _S to a value on the fixed coordinate. The PWM controller 5 compares the voltage command value on the fixed coordinates with the carrier triangular wave, and outputs a gate command Gate for the switching element. The gate command Gate, which is the output of the PWM control unit 5, is input to the inverter and performs switching according to the signal.

  The three-level inverter performs neutral point potential control according to Patent Document 1, Patent Document 2, Patent Document 3, and the like. The components for that purpose are shown below.

  The fifth subtracter 6 subtracts the voltage detection value VN1 of the second DC capacitor from the voltage detection value VP1 of the first DC capacitor to obtain a deviation of the neutral point potential. The second low-pass filter LPF2 removes noise and switching ripples from the output of the fifth subtracter 6, ripples having a frequency component that is three times the fundamental wave that is generated when reactive power is output from the inverter, and the like.

  The neutral point potential controller 7 receives the output signal of the second low-pass filter LPF2 and outputs an appropriate voltage command value that reduces the deviation of the neutral point potential. In the first adder 8, the output signal of the neutral point potential control unit 7 and the voltage command value on the fixed coordinates (the output of the first dq inverse converter 2) are added and input to the PWM control unit 5. .

  FIG. 13 shows an example of the configuration of the neutral point potential control unit 7 described in Patent Document 3. Reference numeral 2 in FIG. 13 corresponds to the neutral point potential control unit 7 in FIG. Depending on the type of the neutral point potential controller 7, the “input 2” signal and the “input 3” signal in FIG. 1D may be unnecessary.

 With the above block, the inverter can output a current substantially equal to the d-axis and q-axis output current command values ID * and IQ *. In particular, for the fundamental wave component (DC component on the dq coordinate), the inverter output current theoretically matches the command value. However, the harmonic current and other components that are alternating current components on the dq coordinate are not completely matched, and a deviation occurs.

Japanese Patent Application Laid-Open No. 07-79574 JP 09-233840 A JP2013-240262A JP 2013-255317 A

“Stabilization of neutral point potential by harmonic power flow of 3-level PWM inverter system SVG”

  In the inverter of FIG. 1, the neutral point potential NP of the inverter is unbalanced during operation due to the individual difference of the switching elements, the difference in capacitance between the first DC capacitor C1 and the second DC capacitor C2, the difference in leakage current, etc. An imbalance between the voltage detection value VP1 of the DC capacitor and the voltage detection value VN1 of the second DC capacitor may occur, and the following problems (1) and (2) occur.

  (1) Capacitors and switching elements in the inverter are damaged by overvoltage application.

  (2) Distortion of the inverter output voltage is increased, which causes adverse effects such as harmonic current outflow to the system.

  As a neutral point potential control method, it is known that a DC offset should be added to the zero phase of the output voltage when the inverter inputs and outputs active power. However, in this method, when the input / output amount of the active power of the inverter is small, the effect of neutral point potential control is reduced. If there is reactive power input / output, as described in Patent Literature 1 and Patent Literature 4, the sixth harmonic may be added to the zero phase of the output voltage.

Patent Document 1 is a method of controlling a neutral point potential by superimposing a 6th harmonic on a voltage command value. In this method, the DC component A ₀ ′ of the current i _NP flowing through the neutral point is expressed by [Expression 6]. Further, as shown in paragraph [0036], it is shown that the maximum effect can be obtained when the power factor is zero (only reactive power is input and output).

However, since the magnitude of A ₀ ′ is proportional to the effective current value output from the inverter, there is a problem that the neutral point potential control effect is reduced when the input / output amount of reactive power of the inverter is reduced. For example, in a state where the inverter is connected to the system and is on standby with zero current output, the inverter outputs only reactive power flowing through the filter. Since the% impedance of the filter is generally about 4% on the basis of the inverter capacity, the current i _NP flowing through the neutral point is reduced to about 4% compared to the state where the rated current is output. Therefore, the neutral point voltage suppression effect is greatly reduced. Furthermore, if the inverter has a delayed reactive power output command of about 4% with respect to the inverter capacity reference, the inverter responds by reducing the reactive power of the advanced component supplied to the filter. There is a risk that it will drop along with it, and in some cases it will become uncontrollable.

  In Patent Document 4, a DC offset is added to the zero phase of the output voltage when the input / output amount of the active power of the inverter is large, and a sixth harmonic offset is added to the zero phase of the output voltage when the input / output amount of the reactive power is large. In addition, the neutral point potential is controlled. However, this method also makes the neutral point potential uncontrollable when the input / output amounts of both electric powers are small.

  In order to solve this, Patent Document 2 proposes that the inverter inputs and outputs some reactive power and active power and controls the neutral point potential in claims 2 and 3. However, the reactive power input / output affects the amplitude of the system voltage. The input / output of active power affects the frequency of the system power supply, and it is necessary to install a separate storage element in the inverter, which causes an increase in cost when applied to applications that do not originally require a storage element, such as a reactive power compensator. It becomes.

  Patent Document 3 assumes that, in claim 6 and Embodiment 4, when the output current of the grid-connected inverter is small, the inverter receives a small amount of active power from the system power supply to compensate for no-load loss. The neutral point potential is controlled by superimposing a DC offset on the output voltage command value. However, since the sign of the offset must be changed depending on the direction in which the active power flows, this method is reversed if, for example, an unintended small amount of regeneration occurs on the DC side of the inverter and a small amount of active power must be output. In addition, the neutral point potential may become unstable.

  Non-Patent Document 1 proposes a method of controlling a neutral point potential by outputting a second harmonic current. However, harmonic currents are affected by overheating and dielectric breakdown of power factor correction capacitors, transformer burnout, motor beats, and circuit breaker malfunctions. Is provided. In Non-Patent Document 1, no second harmonic current flows in the steady state. However, in the transient state, as shown in Non-Patent Document 1, the second harmonic current becomes larger as the distortion of the current waveform becomes clear. Is superimposed. Therefore, there is a problem that distortion of the output current waveform in the transient state becomes large. Further, this Non-Patent Document 1 does not explain whether the secondary harmonic current to be superimposed is normal phase or reverse phase.

There is also a method of controlling the neutral point potential using a second harmonic current. However, since this method is assumed to be applied to a configuration in which current control is not applied and a plurality of units are connected in parallel, it cannot be applied to an inverter that performs current control such as grid connection or motor drive.

  As described above, in the control device of the three-level inverter, it becomes a problem to suppress the instability of the neutral point potential regardless of the input / output levels of the active power and the reactive power.

  The present invention has been devised in view of the above-described conventional problems, and one aspect thereof is connected in series between DC terminals, divides a DC voltage between DC terminals, and this voltage dividing point is defined as a neutral point. Control of a three-level inverter for grid connection or motor drive, comprising: first and second DC capacitors that perform switching, and a plurality of switching elements that convert DC voltage to AC voltage or AC voltage to DC voltage A first low-pass filter that removes noise and switching ripple of an inverter output current detection value, and dq-converts an output of the first low-pass filter based on a system voltage phase or a motor rotation angle phase, a first dq converter for converting to a q-axis inverter output current detection value, a first dq converter for calculating a deviation between the d-axis and q-axis output current command values and the d-axis and q-axis inverter output current detection values; , The second subtracter, the first and second amplifiers that amplify the deviation calculated by the first and second subtractors, and the output of the first and second amplifiers to the system voltage phase or the motor rotation angle phase A first dq inverse converter for inversely converting dq based on the first multiplier, a first multiplier for multiplying a system voltage phase or a motor rotation angle phase by -2, and an inverter output current detection value based on an output of the first multiplier based on dq The second dq converter that converts and outputs the second harmonic detection value of the d axis and q axis, the second harmonic command value of the d axis and q axis, and the second harmonic detection value of the d axis and q axis The third and fourth subtractors for calculating the deviation between the second and the fourth harmonic command values for the d-axis and the q-axis and the second harmonic detection value for the d-axis and the q-axis are amplified. , A fourth amplifier, a second dq inverse transformer that inversely transforms the output of the third and fourth amplifiers based on the output of the first multiplier, and a first dq A neutral point potential control unit that outputs a value that reduces the deviation of the neutral point potential according to the deviation of the neutral point potential that is the deviation between the voltage detection value of the current capacitor and the voltage detection value of the second DC capacitor; A PWM control unit that generates a gate command based on a value obtained by adding the output of the 1dq inverse converter, the output of the second dq inverse converter, and the output of the neutral point potential control unit. And

  Moreover, as another aspect, it connects in series between DC terminals, divides the DC voltage between DC terminals, the 1st, 2nd DC capacitor which makes this voltage dividing point a neutral point, and DC voltage is made into AC voltage, Alternatively, a control device for a three-level inverter for grid connection or motor drive that includes a plurality of switching elements that convert AC voltage into DC voltage, and eliminates noise and switching ripple of the inverter output current detection value And a first dq converter that converts the output of the first low-pass filter based on the phase of the system voltage or the rotation angle phase of the motor into a d-axis and q-axis inverter output current detection value And a second multiplier for multiplying the phase of the system voltage or the rotation angle phase of the motor by -3, and a voltage detection value of the first and second DC capacitors based on the output of the second multiplier The d-axis second harmonic command value and the fixed q-axis second harmonic command value corresponding to the deviation, or the fixed d-axis second harmonic command value and the first and second DC capacitors A third dq inverse converter for inversely converting a q-axis second harmonic command value corresponding to a deviation of the detected voltage value by dq, an output of the third dq inverse converter, an output current command value for the d-axis and the q-axis, , And the first and second subtracters for calculating the deviations between the outputs of the second and third adders and the d-axis and q-axis inverter output current detection values, respectively. The first and second amplifiers for amplifying the deviations calculated by the first and second subtractors, and the output of the first and second amplifiers based on the phase of the system voltage or the rotation angle phase of the motor. A first dq inverse converter that performs reverse conversion, a voltage detection value of the first DC capacitor, and a voltage detection value of the second DC capacitor; A neutral point potential control unit that outputs a value that reduces the deviation of the neutral point potential according to the deviation of the neutral point potential that is a deviation, an output of the first dq inverse converter, and an output of the neutral point potential control unit And a PWM control unit that generates a gate command based on a value obtained by adding the two.

  Further, as one aspect thereof, the d-axis second-order harmonic command value or the q-axis second-order harmonic command value is changed according to the deviation of the voltage detection values of the first and second capacitors. It is characterized by that.

  As another aspect, the first and second capacitors are connected in series between the DC terminals, divide the DC voltage between the DC terminals, and the voltage dividing point is a neutral point, and the DC voltage is an AC voltage, or A three-level inverter control device for system interconnection or motor drive, comprising a plurality of switching elements for converting AC voltage to DC voltage, and removing noise and switching ripple of the inverter output current detection value A first low-pass filter, and a first dq converter that performs dq conversion on the output of the first low-pass filter based on the phase of the system voltage or the rotation angle phase of the motor, and converts it into d-axis and q-axis inverter output current detection values The first and second subtractors for calculating the deviation between the d-axis and q-axis output current command values and the d-axis and q-axis inverter output current detection values, respectively, and the first and second subtractors. First and second amplifiers that amplify the deviation, a first dq inverse converter that inversely transforms the outputs of the first and second amplifiers based on the phase of the system voltage or the rotation angle phase of the motor, and the system voltage The first multiplier for multiplying the phase of the motor or the rotation angle phase of the motor by -2 and the inverter output current detection value are dq converted based on the output of the first multiplier, and the second harmonic of the d-axis and q-axis A second dq converter for outputting a detection value; third and fourth subtractors for calculating a deviation between a second harmonic command value for the d-axis and the q-axis and a second harmonic detection value for the d-axis and the q-axis; , The third and fourth amplifiers for amplifying the deviation between the d-axis and q-axis second harmonic command values and the d-axis and q-axis second harmonic detection values, and the outputs of the third and fourth amplifiers A second dq inverse converter that inversely transforms dq based on the output of the first multiplier, and quadruples the phase of the system voltage or the rotation angle phase of the motor A second multiplier, a third dq converter that dq-converts the inverter output current detection value based on the output of the second multiplier, and outputs a fourth harmonic detection value of the d-axis and the q-axis, and a d-axis , Q-axis fourth harmonic command value and d-axis, q-axis fourth harmonic detection value, the fifth and sixth subtractors for calculating the deviation, and the outputs of the fifth and sixth subtractors are amplified. The sixth and seventh amplifiers, the fourth dq inverse converter that inversely converts the outputs of the sixth and seventh amplifiers based on the output of the multiplier, the voltage detection value of the first DC capacitor, and the second DC capacitor A neutral point potential control unit that outputs a value that reduces the deviation of the neutral point potential according to the deviation of the neutral point potential that is the deviation of the voltage detection value; the output of the first dq inverse converter; and the neutral point potential A gate command is generated based on a value obtained by adding the output of the control unit, the output of the second dq inverse converter, and the output of the fourth dq inverse converter. And a PWM control unit.

  Moreover, as another aspect, it connects in series between DC terminals, divides the DC voltage between DC terminals, the 1st, 2nd DC capacitor which makes this voltage dividing point a neutral point, and DC voltage is made into AC voltage, Alternatively, a control device for a three-level inverter for grid connection or motor drive that includes a plurality of switching elements that convert AC voltage into DC voltage, and eliminates noise and switching ripple of the inverter output current detection value And a first dq converter that converts the output of the first low-pass filter based on the phase of the system voltage or the rotation angle phase of the motor into a d-axis and q-axis inverter output current detection value A third multiplier for multiplying the phase of the system voltage or the rotation angle phase of the motor by -3, and a voltage detection value of the first and second DC capacitors based on the output of the third multiplier The d-axis second harmonic command value and the fixed q-axis second harmonic command value corresponding to the deviation, or the fixed d-axis second harmonic command value and the first and second DC capacitors A third dq inverse converter that inversely converts a q-axis second-order harmonic command value according to a deviation of the voltage detection value by dq, a fourth multiplier that triples the phase of the system voltage or the rotation angle phase of the motor, Based on the output of the fourth multiplier, the d-axis fourth harmonic command value and the fixed q-axis fourth harmonic command value according to the deviation of the voltage detection value of the first and second DC capacitors, or A fifth dq inverse converter that inversely transforms a q-axis fourth-order harmonic command value corresponding to a deviation between a fixed fourth-order harmonic command value of the d-axis and a voltage detection value of the first and second DC capacitors; , The d-axis and q-axis output current command values, the output of the third dq inverse converter, and the output of the fifth dq inverse converter, first and second subtractors for calculating deviations from the d-axis and q-axis inverter output current detection values, and first and second amplifiers for amplifying the deviations calculated by the first and second subtractors; A first dq inverse converter that inversely transforms the outputs of the first and second amplifiers based on the phase of the system voltage or the rotation angle phase of the motor, a voltage detection value of the first DC capacitor, and a voltage of the second DC capacitor A neutral point potential control unit that outputs a value that reduces the deviation of the neutral point potential according to the deviation of the neutral point potential that is a deviation of the detected value, the output of the first dq inverse converter, and the neutral point potential control And a PWM control unit that generates a gate command based on a value obtained by adding the outputs of the units.

  Further, as one aspect thereof, the d-axis second harmonic command value or the q-axis second harmonic command value, and the d-axis fourth harmonic command value or the q-axis fourth harmonic command value are: The first and second DC capacitors are changed according to the deviation of the detected voltage value.

  Further, as one aspect thereof, the output terminal of the inverter is connected to the system power supply via a filter circuit, and the dq converter and the dq inverse converter perform dq conversion and dq inverse conversion based on the phase of the system voltage. It is characterized by that.

  Further, as one aspect thereof, the output terminal of the inverter is connected to a motor, and the dq converter and the dq inverse converter perform dq conversion and dq inverse conversion based on the rotation angle phase of the motor. .

  Further, as one aspect thereof, a sixth multiplier that multiplies the system voltage phase or the rotation angle phase of the motor by -2 and an inverter output current detection value is dq-converted based on the output of the sixth multiplier, and d-axis, q A fifth dq converter that outputs an inverter output current detection value of the shaft, third and fourth low-pass filters that remove pulsation from the output of the fifth dq converter, and an eighth that multiplies the output of the third low-pass filter by a coefficient Qam. A multiplier, a ninth multiplier that multiplies the output of the third low-pass filter by a coefficient Qbm, a tenth multiplier that multiplies the output of the fourth low-pass filter by a coefficient Qam, and a coefficient Qbm at the output of the fourth low-pass filter. An eleventh multiplier for multiplying, an eighth adder for adding the output of the eighth multiplier and the inverted value of the output of the eleventh multiplier, the output of the ninth multiplier and the output of the tenth multiplier; 9th adder to add The seventh and eighth subtractors for outputting the deviation between the outputs of the eighth and ninth adders and the outputs of the fifth and sixth low-pass filters that receive the second harmonic command value as an estimated value of disturbance. The ninth and tenth subtractors for calculating the second harmonic command value by taking the deviation between the disturbance command value for suppressing the disturbance and the estimated value of the disturbance, and the second harmonic command value are input. , The fifth and sixth low-pass filters output to the eighth subtractor, the seventh multiplier for multiplying the system voltage phase or the motor rotation angle phase by -3, and the output of the seventh multiplier, A fifth dq inverse converter that inversely transforms the output of the tenth subtractor and an output of the fifth dq inverse converter are added to the output current command values of the d-axis and q-axis, and the output current command value of the d-axis and q-axis The sixth and seventh adders for correcting the above are provided.

  According to the present invention, in a control device for a three-level inverter, it is possible to suppress instability of a neutral point potential regardless of the magnitude of input / output of active power and reactive power.

The figure which shows an inverter and an inverter control apparatus. The figure which shows the inverter control apparatus of Embodiment 1. FIG. The figure which shows the proportional gain of the existing current control in a Bode diagram, and the gain relationship of an integral amplifier. The figure which shows the case where an output current command value is made equal in Embodiment 1. FIG. The figure which shows the inverter control apparatus of Embodiment 2. FIG. The figure which shows the inverter control apparatus of Embodiment 3. The figure which shows the inverter control apparatus of Embodiment 4. The figure which shows the other example of the inverter control apparatus of Embodiment 2. FIG. The figure which shows the other example of the inverter control apparatus of Embodiment 3. FIG. 4 is a calculation block diagram of a fourth harmonic command value. The figure which shows the inverter electric current command value calculating part of Embodiment 5. FIG. The figure which applied Embodiment 1 to the inverter control apparatus for motor drive. The figure which shows the conventional inverter control apparatus.

[Embodiment 1]
FIG. 2 shows an inverter control device per inverter according to the first embodiment. The inverter control apparatus according to the first embodiment is obtained by adding the following configuration to FIG.

The first multiplier 17 multiplies the phase signal ωt of the system voltage by −2. The second dq converter 9 is based on the multiplied phase −2ωt, and the secondary output of the d-axis and q-axis on the rotation coordinate in which the inverter output current detection value I _INV is synchronized with the negative second-order harmonic of the system voltage detection value Vs. Convert to harmonic detection value.

The third and fourth subtractors 11 and 12 calculate the deviation between the secondary harmonic command values ID _{N2 *} and IQ _{N2 *} and the actual detected secondary harmonics of the d and q axes. The d-axis second-order harmonic command value ID _{N2 *} is fixed at 0. The q-axis second-order harmonic command value IQ _{N2 *} is also normally 0.

  The third and fourth amplifiers 13 and 14 amplify the outputs of the third and fourth subtractors 11 and 12 by an operation such as integration, and calculate the voltage command value of the antiphase second harmonic component. The second dq inverse converter 10 converts the voltage command value of the antiphase second harmonic component into a value on a fixed coordinate. The output of the second dq inverse converter 10 is added to the output of the first dq inverse converter 2 and the output of the neutral point potential control unit 7 in the first adder 8 and is input to the PWM control unit 5.

Examine the relationship between the 3-level inverter and the second harmonic. First, voltage distortion when the neutral point potential is unbalanced will be described. The inverter output U-phase voltage V _U in an ideal state without imbalance is expressed by the following equation (1).

V ₀ is the rated output voltage of the inverter (approximately equal to the rating of the system voltage detection value Vs), and ω is the rated angular frequency (usually 50 Hz × 2π or 60 Hz × 2π). The degree of unbalance of the neutral point potential is k (−1 ≦ k ≦ 1), and the voltage detection value VP1 of the first DC capacitor and the voltage detection value VN1 of the second DC capacitor are expressed as the following equation (2).

This imbalance causes a difference between the positive side amplitude and the negative side amplitude in the output phase voltage. The inverter output U-phase voltage V _U ′ distorted by this difference is expressed by the following equation (3).

For the distorted inverter output U-phase voltage V _U ′, Fourier series expansion is performed to check the distortion of each order. The coefficients a _n, a following equation (4).

Incidentally, n of coefficients a _n and (4) is a harmonic order. When n is an even number, the coefficient an is _expressed by the following equation (5).

  When n is an odd number, the following equation (6) is obtained.

The coefficient b _n is expressed by the following equation (7).

  The above is expanded to three phases. The inverter output phase voltage of each phase when there is no unbalance is expressed by the following equation (8).

  Secondary voltage distortions V2u, V2v, and V2w of each phase generated by unbalance of neutral point potential are expressed by the following equation (9).

  The secondary voltage distortions V2u, V2v, and V2w are out of phase because the relationship between the phase advance and delay of the V phase and the W phase with respect to the U phase is opposite to that of the fundamental wave. When the same study is performed on the fourth-order voltage distortions V4u, V4v, and V4w, the relationship between the phase advance and delay is the same as that of the fundamental wave as shown in the following equation (10), and the phase is positive.

  From the above formulas, the following (1) to (3) are understood.

  (1) When the neutral point potential is unbalanced, even-order voltage distortion occurs in the inverter output voltage. As a result, an unintended even-order harmonic current is output.

(2) The voltage distortion of the nth harmonic of the inverter output voltage is inversely proportional to (n ² −1), and the voltage distortion of the second harmonic is the largest. (3) The second harmonic caused by the neutral point potential imbalance. The voltage distortion of the wave is opposite phase, and the voltage distortion of the fourth harmonic is positive phase.

  Next, the influence of the current on the neutral point potential when distortion is superimposed on the inverter output current will be described. When the output voltage command value of the inverter is set to v, the ratio of the middle arm ON period to one switching cycle can be expressed by the following equation (11).

_Assuming that the inverter output current at this time is i _INV , the current flowing out from the neutral point potential (hereinafter referred to as neutral point potential flowing out current) i _NP is expressed by the following equation (12).

Here, v and i _INV are set as in equation (13).

The average value I _NP of one period of the fundamental wave of the neutral point potential outflow current i _NP is expressed by the following equation (14).

  When n is an even number, the following equation (15) is obtained.

  When n is an odd number, the following equation (16) is obtained.

When a quantitative evaluation is performed, the average value I _NP2 of one period of the fundamental wave of the neutral point potential outflow current I _{NP at} the current of the second harmonic, n = 2, and the amplitude of I ₂ is the current phase θ = 180 deg. It becomes the maximum and becomes the following expression (17).

On the other hand, in the current phase θ = 90 deg or 270 deg, the average value I _NP2 = 0. The larger the average value I _NP2 , the more the neutral point potential is affected. When n = 2, expansion to three phases is performed. When the inverter output current is only the second-order harmonic of the opposite phase, it is expressed by the following equation (18).

Under this condition, when the sum of the average values of one period of the fundamental wave of the neutral point potential outflow current I _NP is obtained, the following equation (19) is obtained.

  On the other hand, when the inverter output current is only a positive second-order harmonic, the following equation (20) is obtained.

The total of the neutral point potential outflow current I _NP is given by equation (21) and does not affect the neutral point potential.

As can be understood from the above equations, the following (1) to (4) can be understood.
(1) Even if odd harmonics including the fundamental wave are superimposed on the inverter output current, the neutral point potential is not affected.
(2) Even-order harmonics have the greatest effect on the neutral point potential when θ = 0 deg or 180 deg, and do not affect the neutral point potential when θ = 90 deg or 270 deg.
(3) The neutral point potential outflow current I _NP of the even-order harmonic is inversely proportional to (n ² −1), and the current distortion of the second-order harmonic is the largest (n: harmonic order)
(4) The current distortion of the second harmonic that affects the neutral point potential is negative, and the positive phase does not affect it.

  In the following, although the inverter output current has only the fundamental wave component, the influence on the neutral point potential when distortion is superimposed on the output voltage will be described.

v and average value i _INV are set as shown in equation (22), and neutral point potential outflow current I _NP is obtained.

As before, the average value I _NPV of one period of the fundamental wave of the neutral point potential outflow current I _NP is obtained.

However, since it is difficult to divide the section as it is, the neutral point current outflow current I _NP is approximated by the following equation (24).

Using this approximation, the average value I _NPV of one period of the fundamental wave of the neutral point potential outflow current I _NP is calculated as the following equation (25).

  When n is an odd number, the following equation (26) is obtained.

  When n is an even number, the following equation (27) is obtained.

  This equation corresponds to Equation (6) in Patent Document 1. Although the equations are different, this is because the characters used are different, and further, the current is examined by the effective value in Patent Document 1 and here the amplitude. Further, in Patent Document 1, there is a difference in which sin is used as a reference, and here, cos is used as a reference.

  In Patent Document 1, the neutral potential is controlled by superimposing a sixth harmonic on the voltage command value. Substituting n = 6 into this equation, the control effect is evaluated quantitatively. Assuming that the amplitude of the superimposed sixth harmonic is 10% of the carrier triangular wave, a = 0.1, and the current phase θ is θ = 90 deg at which the maximum effect can be obtained as in paragraph [0036] of Patent Document 1, (28).

  The phase of the voltage distortion to be superimposed is φ = 90 deg = π / 2, and the neutral point potential outflow current becomes maximum, and the following equation (29) is obtained.

In Equation (6) of Patent Document 1, when k = 0.1, λ = V, IM = I / √2, φ = 90 deg, α = −90 deg are substituted so as to satisfy the same condition, A ₀ ′ is an average. It is equal to the value I _NPV . Here, a comparison is made with the one-cycle average value I _NP2 of the neutral point potential outflow current due to the second harmonic current distortion obtained earlier. When I _NP2 and I _NPV6 are connected with an equal sign, the following equation (30) is obtained.

The second harmonic current amplitude I _{2 in} which both are equal is expressed by the following equation (31).

That is, 20 * I ₂ ≈I.

  From the above formulas, the following (1) to (3) are understood.

(1) From the above equation (31), I ₂ ≈0.0514I, it can be seen that the second harmonic current superimposed on the inverter output current has a great influence on the neutral point potential.

(2) For example, when the second harmonic current (amplitude I ₂ ) flows by 1%, about 20 to cancel the influence on the neutral point potential by the combination of the reactive current and the conventional neutral point potential control. % Reactive current (amplitude I) is required.

(3) On the contrary, when neutral point potential control by second harmonic current (amplitude I ₂ ) is applied to an inverter that controls neutral point potential using 20% reactive current (amplitude I). The required second harmonic current amplitude I ₂ need only be 1%.

  The operation of the first embodiment will be described. In the first embodiment, a function is added to the inverter control device so as to remove the negative-phase second-order harmonic current that has a large influence on the neutral point potential based on the examination results so far.

First, the phase ωt held in the inverter is multiplied by −2, and the result is used to dq-convert the inverter output current detection value I _INV . Thereby, the negative phase second harmonic component contained in the inverter output current detection value I _INV can be converted into direct current (d-axis component and q-axis component). Next, the inverter output current detection value converted into the direct current (d-axis component and q-axis component) is compared with the second harmonic command value ID _N2 * (= 0) and IQ _N2 *, and each deviation is obtained. By processing each deviation by the third and fourth amplifiers (I _{N2 in} FIG. 2), the deviation of the negative second-order harmonic current can be made zero. The obtained voltage command value is converted into a command value on a fixed coordinate by the second dq inverse converter 10 and added to the voltage command value obtained by the first dq inverse converter.

  A method for designing the gains of the third and fourth amplifiers 13 and 14 will be described. When applying this Embodiment 1 with respect to the existing apparatus, it is calculated | required to suppress only a reverse phase 2nd order harmonic, without affecting other harmonics. For this purpose, the integral gain for a frequency of 25 Hz or less on the rotational coordinate may be made equal to the proportional gain of the existing current control.

  Since the integral amplifier has a characteristic that the gain decreases as the frequency increases, the gain for 50 Hz corresponding to the negative phase first harmonic and the negative phase third harmonic is ½ of the proportional gain of the existing current control. The effect is almost as follows.

FIG. 3 is a Bode diagram showing the relationship between the proportional gain (dotted line) of the existing current control and the gains (solid line) of the third and fourth amplifiers 13 and 14. By designing the gain I _N2 to gain in 25Hz on a rotating coordinate are equal, the third 50Hz on rotating coordinates, the gain I _N2 of the fourth amplifier 13 and 14 1/2 of the existing current control proportional gain The existing current control proportional amplifier will operate more favorably. At a frequency of 100 Hz or higher, the gain I _N2 of the third and fourth amplifiers 13 and 14 is further reduced.

In the first embodiment (FIG. 2), there are two current command values for each of the d-axis and q-axis (ID *, IQ *, ID _N2 *, IQ _N2 *), and the values are different. May cause interference. However, by applying the gain design method described above, the superiority to each harmonic is determined as follows, and interference can be avoided.

  (Basic wave): The integral gain of the existing current control block is infinite, the integral gain of the additional block is 1/6 or less of the proportional gain of the existing current control block, and the control performed by the existing current control block has priority.

  (Negative phase second harmonic): The proportional gain of the existing current control block is finite. On the other hand, since the integral gain of the additional block becomes infinite, priority is given to the control performed by the additional block.

  (Negative phase primary, third harmonic): The integral gain of the additional block is ½ or less of the proportional gain of the existing current control block, and priority is given to the control performed by the existing current control block.

  (Other harmonics): In the existing current control block, at least the proportional gain set by the proportional amplifier is used, and the integral gain of the additional block is less than 1/4 of the proportional gain of the existing current control block. Priority is given to the control to be performed. Therefore, in the first embodiment, one dq converter can be omitted as compared with the case where the output current command values are equal as shown in FIG. 4, and the calculation load can be reduced.

  As shown in FIG. 2, the first embodiment is used in combination with neutral point potential control such as Patent Document 1, Patent Document 3, and Patent Document 4. If this embodiment 1 is not used in combination with neutral point potential control, instability of the neutral point potential due to the reverse phase second harmonic can be suppressed, but there is no neutral point potential control effect. It is.

  In the first embodiment, the system voltage detection value Vs is expressed by the following equation (31) with cos as a reference.

  Also, the definition of dq conversion is that the d-axis is positive and the q-axis is positive when dq conversion is performed under the condition that the inverter output current has the same phase with respect to the system voltage detection value Vs and is expressed by the following equation (32). Assumes zero.

Under this condition, only the d-axis current affects the neutral point potential, and not the q-axis current. Therefore, the d-axis second harmonic command value ID _N2 * must always be zero, but the q-axis second harmonic command value IQ _N2 * may not be zero. The second harmonic command value IQ _N2 * can be changed in accordance with the purpose.

  Since the first embodiment is applied to the current control inverter, interference with the existing current control block can be avoided as described above without extracting only the antiphase second harmonic by the filter. As a result, the extraction filter is not required and the response speed is improved, so that the effect of improving the stability of the neutral point potential is enhanced.

  As described above, according to the first embodiment, it is possible to suppress the output of the negative second-order harmonic current that greatly affects the neutral point potential of the three-level inverter. Thereby, the neutral point potential instability in the prior art can be suppressed regardless of the amount of input / output of the active power of the inverter. Furthermore, the influence on the system voltage can be reduced. Further, since no second-order second-order harmonic current is output as compared with the second and third embodiments described later, the distortion of the output current can be reduced.

[Embodiment 2]
FIG. 5 shows an inverter control apparatus according to the second embodiment. The inverter control device according to the second embodiment is obtained by adding the following configuration to FIG.

The fifth amplifier 39 amplifies the neutral point potential deviation signal output from the second low-pass filter LPF2 by calculation such as proportionality. The first limiter 40 limits the output of the fifth amplifier 39 so as not to exceed the set value. The set value of the first limiter 40 is ± 0.3% to ± 1%. The output of the first limiter 40 is the d-axis second harmonic command value ID _N2 *.

The second multiplier 41 multiplies the phase signal ωt by −3. The third dq inverse converter 42 includes a d-axis second harmonic command value ID _N2 *, a q-axis second harmonic command value IQ _N2 * (usually zero as in the first embodiment), − And converted to a value on the fundamental wave rotation coordinates.

  The fourth and fifth adders 43 and 44 add the output of the third dq inverse converter 42 and the d-axis and q-axis output current command values ID * and IQ *.

The operation of the second embodiment will be described. In the second embodiment, the d-axis second-order harmonic command value ID _N2 * is changed in accordance with the neutral point potential deviation, and is superimposed on the existing d-axis and q-axis output current command values ID * and IQ *. It is a method to do.

  First, the neutral point potential deviation is obtained from the difference between the DC voltage detection values VP1 and VN1. The second low-pass filter LPF2 is applied to the deviation to remove noise and unnecessary pulsation. A gain G is applied to the deviation signal from which the pulsation has been removed by the fifth amplifier 39 to convert it into a command value for the reverse phase second harmonic current.

Next, the first limiter 40 is applied to the command value so that the output current is not distorted more than necessary. The output of the first limiter 40 is the d-axis second harmonic command value ID _N2 *. The obtained d-axis second harmonic command value ID _N2 * is converted into a value on the fundamental wave rotation coordinate by performing dq inverse transformation together with a separately prepared q-axis second harmonic command value IQ _N2 *. , D-axis and q-axis output current command values ID * and IQ *. Although the q-axis second-order harmonic command value IQ _N2 * may be zero, it may be changed according to the purpose of the apparatus as in the first embodiment.

In the second embodiment, since the function of controlling the neutral point potential using the d-axis second-order harmonic command value ID _N2 * obtained based on the deviation of the neutral point potential is mounted, a sufficient neutral point potential is provided. The stabilization effect can be obtained. Further, the calculation load can be reduced by reducing one dq converter as compared with the first embodiment and the third embodiment described later.

  Similarly to the first embodiment, the second embodiment is also used in combination with neutral point potential control such as Patent Document 1, Patent Document 3, and Patent Document 4.

  This is due to the following reason.

  (1) When neutral point potential control is not used together, disturbance to the neutral point potential increases as the inverter output current increases. If the second harmonic current is increased for coping, the distortion of the inverter output current increases.

  (2) When the inverter output current increases, a sufficient effect can be obtained even with conventional neutral point potential control.

  In Non-Patent Document 1, as shown in FIG. 5 of Non-Patent Document 1, the output current in the transient state was greatly distorted. However, in the second embodiment, as in the first embodiment, since the anti-phase second harmonic current used for control is suppressed to a very small amount (about 5% of the reactive current amplitude of the method of Patent Document 1), even in a transient state. The output current can control the neutral point potential with almost no distortion.

  As described above, according to the second embodiment, the same operational effects as those of the first embodiment can be obtained. Further, even at no load or light load, the neutral point potential can be controlled by outputting a very small amount of the second harmonic current. Even a two-level inverter may output a second harmonic current of about 1%, and the distortion of the output current can be made smaller than that.

  Further, since the second harmonic is superimposed on the output current command value in a feedforward manner in accordance with the deviation of the neutral point potential, the response is quicker than that of the third embodiment to be described later, and the neutral point potential deviation is easily suppressed. There are advantages.

  Compared to the first embodiment, the number of dq converters and integrators is reduced, and the calculation load is reduced.

  Furthermore, since the second embodiment has an effect of controlling the neutral point potential, it is possible to reduce the sixth harmonic to the voltage command value to be superimposed by the conventional neutral point potential control used together. As a result, there is a margin in the voltage command value, and the inverter DC voltage can be lowered if the same AC voltage is output. Therefore, the breakdown voltage required for the components can be reduced. Furthermore, the switching loss of the switching device inside the inverter can be reduced by lowering the inverter DC voltage.

[Embodiment 3]
FIG. 6 shows an inverter control unit according to the third embodiment. The inverter control apparatus according to the third embodiment is a combination of the first and second embodiments.

The dead band 16 receives a neutral point potential deviation signal output from the second low-pass filter LPF2, and outputs zero when the deviation is smaller than a predetermined set value. The fifth amplifier 39 amplifies the output of the dead band 16 by an operation such as proportionality. The limiter 40 limits the output of the fifth amplifier 39 so as not to exceed the set value. The limiter 40 becomes the d-axis second harmonic command value ID _N2 *.

The second harmonic command values ID _N2 * and IQ _N2 * obtained in the above block are calculated by calculating the deviation from the output of the second dq converter 9 by the subtractor 11 as in the first embodiment. 4 is output to the amplifiers 13 and 14.

The operation of the third embodiment will be described. In the third embodiment, a function for changing the d-axis second-order harmonic command value ID _N2 * in accordance with the neutral point potential deviation of the second embodiment is added to the configuration of the first embodiment. Unlike Embodiment 2, the deviation with respect to the anti-phase second harmonic becomes zero, and the output of the anti-phase second harmonic current can be made as designed.

In addition, a dead band 16 is added in the process of calculating the d-axis second-order harmonic command value ID _N2 *. As a result, in the normal state (the state where there is no large fluctuation in the neutral point potential, that is, the state where there is almost no fluctuation in the system voltage detection value Vs or the load), the negative phase second harmonic current is not output, and Only when the value fluctuates greatly, a small amount of second harmonic can be output to control the neutral point potential, and the frequency of output of the reverse phase second harmonic current can be reduced as compared with the first and second embodiments. Can do.

  As described above, according to the third embodiment, the neutral point potential can be controlled by outputting a very small amount of the second harmonic current even under no load or light load. Also, by using feedback control, the difference between the command value of the second harmonic current and the actual output current becomes zero, and the amplitude of the negative second harmonic used to control the neutral point potential is intended. The current distortion can be made smaller than in the second embodiment.

  Furthermore, by limiting the output of the second harmonic current only when a sudden disturbance occurs and the neutral point potential deviation becomes large, the output current distortion at the time of steady state should be made as small as that of the first embodiment. Can do.

  Further, the third embodiment can also obtain the reduction effect of the breakdown voltage required for the parts and the effect of reducing the switching loss as in the second embodiment.

[Embodiment 4]
FIG. 7 shows an inverter control apparatus according to the fourth embodiment. In the fourth embodiment, the following configuration is added to the inverter control device.

The second multiplier 18 multiplies the phase signal ωt by four. The fourth dq converter 19 is based on the multiplied phase 4ωt, and the inverter output current detection value I _INV is synchronized with the positive fourth-order harmonic of the system voltage detection value Vs. Convert to wave detection value. The fifth and sixth subtracters 20 and 21 calculate a deviation between the fourth harmonic command values ID _P4 * and IQ _P4 * and the fourth harmonic detection values of the d-axis and the q-axis. The d-axis fourth harmonic command value ID _P4 * is fixed at 0. The q-axis fourth-order harmonic command value IQ _P4 * is also normally 0.

  The sixth and seventh amplifiers 22 and 23 amplify the outputs of the fifth and sixth subtracters 20 and 21 by calculation such as integration, and calculate the voltage command value of the positive-phase fourth-order harmonic component. The fourth dq inverse converter 24 converts the voltage command value of the normal phase fourth harmonic component into a value on a fixed coordinate.

  The output of the fourth dq inverse converter 24 is added by the adder 25 with the voltage command value of the antiphase second harmonic component (the output of the second dq inverse converter 10). The output of the adder 25, the output of the first dq inverse converter 2, and the output of the neutral point potential control unit 7 are added by the first adder 8 and input to the PWM control unit 5.

The fourth embodiment is a system in which the first embodiment is extended to the fourth harmonic. For the 4th harmonic current, the positive phase affects the neutral point potential, so the second multiplier 18 multiplies the phase ωt by 4 and the 4th dq converter 19 converts the positive phase 4th harmonic current to direct current. The fifth subtracter 20 and the sixth amplifier 22 control the d-axis component of the positive-phase fourth-order harmonic current to zero. Further, the sixth subtractor 21 and the seventh amplifier 23 control the q-axis component of the positive-phase fourth-order harmonic current to the fourth-order harmonic command value IQ _P4 *. (Normally IQ _P4 * = 0)
Thereby, the stability of the neutral point potential can be further improved. The gain I _P4 of the sixth and seventh amplifiers 22 and 23 can be designed in the same manner as the gain I _{N2 of the} first embodiment.

  The fourth embodiment can be extended to suppress a current that affects a neutral point potential of a higher order. However, the sixth harmonic that affects the neutral point potential is in-phase and can be omitted because it does not normally occur in a three-phase three-wire inverter. Further, from the examination results so far, even if the amplitudes of the harmonic currents are equal, the influence on the neutral point potential decreases as the order increases, and becomes 1/5 in the 4th order and 1/21 in the 8th order.

Therefore, only the second and fourth orders of the harmonic current to be controlled are sufficient. As shown in FIGS. 8 and 9, the second and third embodiments can also correspond to the fourth-order harmonic as in the fourth embodiment. However, it should be noted that the sign of the average value I _NP of one period of the fundamental wave of the neutral point potential outflow current changes depending on the order. As shown in FIG. 10, the gain for _{obtaining the} d-axis fourth-order harmonic command value ID _P4 * from the neutral point potential deviation must be negative.

  FIG. 8 shows an example of the second embodiment corresponding to the fourth harmonic, and FIG. 9 shows an example of the third embodiment corresponding to the fourth harmonic.

  As described above, according to the fourth embodiment, in addition to the first embodiment, neutral point potential instability caused by an unintended output of the fourth harmonic current can be suppressed.

[Embodiment 5]
FIG. 11 shows a current command value calculation block per inverter of the fifth embodiment. The current command value calculation block of the fifth embodiment calculates the d-axis and q-axis output current command values ID * and IQ * of FIG. 1D, and has the following configuration.

The sixth multiplier 30 multiplies the phase signal ωt by −2. The fifth dq converter 31 converts the inverter output current detection value I _INV into a value on the rotational coordinate synchronized with the negative second-order harmonic of the system voltage detection value Vs based on the multiplied phase −2ωt. The third and fourth low-pass filters LPF3 and LPF4 remove pulsations caused by the fundamental wave and other harmonics from the output signal of the fifth dq converter 31. The sixth multiplier 30, the fifth dq converter 31, the third and fourth low-pass filters LPF3 and LPF4 mainly constitute a periodic disturbance detection unit.

The periodic disturbance observer 32 receives the output signals of the third and fourth low pass filters LPF3 and LPF4, and outputs the second harmonic command values ID _N2 * and IQ _N2 * that are optimal for suppressing the negative second harmonic current. To do.

The seventh multiplier 33 multiplies the phase signal ωt by −3. The fifth dq inverse converter 34 inversely transforms the second harmonic command values ID _N2 * and IQ _N2 * into values on the fundamental rotation coordinates based on the phase −3ωt. The output of the fifth dq inverse converter 34 is added to the output current command values ID * and IQ * of the d-axis and q-axis in the sixth and seventh adders 51 and 52, and the new d-axis and q-axis output current command value is added. ID * ′ and IQ * ′, which replace the output current command values ID * and IQ * of the d-axis and q-axis in FIG.

  The periodic disturbance observer 32 is configured as follows.

The coefficients Qam and Qbm are the third and fourth low-pass by detecting the d-axis and q-axis second-order harmonic command values ID _N2 * and IQ _N2 * through the current control, and the inverter actually outputting the current. This represents an inverse model in which characteristics such as phase delay and amplitude change until the signal passes through the filters LPF3 and LPF4 and returns to the periodic disturbance observer 32 are shown.

  The eighth to eleventh multipliers 35a to 35d multiply the output signals of the third and fourth low-pass filters LPF3 and LPF4 by the coefficients Qam and Qbm, respectively. The eighth adder 36a adds a value obtained by inverting the output of the eighth multiplier 35a and the output of the eleventh multiplier 35d. The ninth adder 36b adds the output of the ninth multiplier 35b and the output of the tenth multiplier 35c.

The seventh subtractor 37a calculates the deviation between the output of the eighth adder 36a and the output of the fifth low-pass filter LPF5 that receives the second harmonic command value ID _N2 *. The eighth subtractor 37b calculates the deviation between the output of the ninth adder 36b and the output of the sixth low-pass filter LPF6 that receives the second harmonic command value IQ _N2 *. The outputs of the seventh and eighth subtracters 37a and 37b are disturbance estimation results superimposed in the actual system.

The ninth and tenth subtractors 38a and 38b calculate the deviation between the outputs of the seventh and eighth subtracters 37a and 37b and the disturbance command value (= 0). The outputs of the ninth and tenth subtracters 38a and 38b are output from the periodic disturbance observer 32 as the second harmonic command values ID _N2 * and IQ _N2 *. The second harmonic command values ID _N2 * and IQ _N2 * are separately passed through the fifth and sixth low-pass filters LPF5 and LPF6 in the periodic disturbance observer 32 and input to the seventh subtractor 37a and the eighth subtractor 37b. To do.

  The fifth embodiment is a method of suppressing the antiphase second harmonic current using the periodic disturbance observer of Patent Document 5. When the system configuration is complicated, a large number of resonance points are generated, and the control becomes unstable due to an increase in the phase delay. On the contrary, in the configuration of the first embodiment, there is a possibility that the antiphase second harmonic is increased.

  Therefore, by using the periodic disturbance observer 32 and appropriately setting the coefficients Qam and Qbm, the phase delay can be canceled and the control can be stabilized. The coefficients Qam and Qbm can be provided with an automatic adjustment function as in Embodiment 7 of Patent Document 5.

  The d-axis and q-axis output current command values ID * ′ and IQ * ′ in FIG. 11 are input as the d-axis and q-axis output current command values ID * and IQ * in FIGS. . As in the first embodiment, the fifth embodiment has only a function of suppressing the antiphase second harmonic current and preventing the neutral point potential from becoming unstable. In the case of adding a function of controlling the neutral point potential using the antiphase second harmonic current as in the second and third embodiments, it can be dealt with by changing the d-axis disturbance command value.

  As described above, according to the fifth embodiment, in addition to the first embodiment, the negative second-order harmonic current can be correctly controlled to zero even when connected to a complex system having a large number of resonance points. .

  Further, if an automatic adjustment function is added, even if the system characteristics fluctuate greatly, it is not necessary to stop the apparatus and reset the coefficient, so that the operation can be continued stably.

  The above first to fifth embodiments can be applied to a current control inverter. For example, the present invention can be applied not only to a grid-connected inverter but also to a motor driving inverter. However, if a harmonic current is passed through the motor, it will cause torque ripple. It is desirable to apply the first, fourth, and fifth embodiments if the torque ripple is not acceptable at all, and the second and third embodiments if the application is not problematic even if a slight torque ripple occurs.

  FIG. 12 shows an example in which the first embodiment is applied to an inverter for driving a PM motor. The phase ωt is changed from the PLL output result of the system voltage detection value Vs to the rotation angle phase θ that is the output result of the rotary encoder PP.

In general, since the d axis of the rotation coordinate is used as the magnetic flux axis in the motor drive inverter, the induced voltage of the motor is synchronized with the q axis, and the voltage axis is shifted by 90 degrees from the grid interconnection inverter. For this reason, in a general motor drive inverter, the q-axis second harmonic command value IQ _N2 * is fixed to zero. When the second or third embodiment is applied to an inverter for driving a motor, the command value of the anti-phase second harmonic current obtained by multiplying the deviation of the neutral point potential by the gain G is the second harmonic command value of the d axis. It is not the ID _N2 * but the q-axis second-order harmonic command value IQ _N2 *.

  The first to fifth embodiments are not limited to the three-level inverter having the configuration shown in FIGS. Embodiments 1 to 5 can be applied to any three-level inverter provided with a series connection circuit of DC capacitors C1 and C2 in the DC voltage section.

I _INV ... Inverter output current detection value Vs ... System voltage detection value ID *, IQ * ... d-axis and q-axis output current detection values ID _N2 *, IQ _N2 * ... d-axis and q-axis second harmonic command values ID _P4 *, IQ _P4 * ... d-axis and q-axis fourth harmonic command values

Claims (9)

First and second DC capacitors that are connected in series between the DC terminals, divide the DC voltage between the DC terminals, and have this voltage dividing point as a neutral point;
A control device for a three-level inverter for system interconnection or motor drive, comprising: a DC voltage as an AC voltage; or a plurality of switching elements that convert an AC voltage into a DC voltage.
A first low-pass filter for removing noise and switching ripple of the inverter output current detection value;
A first dq converter that performs dq conversion on the output of the first low-pass filter based on a system voltage phase or a motor rotation angle phase, and converts it into d-axis and q-axis inverter output current detection values;
first and second subtractors for calculating the deviation between the d-axis and q-axis output current command values and the d-axis and q-axis inverter output current detection values, respectively;
First and second amplifiers for amplifying the deviation calculated by the first and second subtractors;
A first dq inverse converter that inversely transforms the outputs of the first and second amplifiers based on a system voltage phase or a motor rotation angle phase;
A first multiplier for multiplying a system voltage phase or a motor rotation angle phase by -2,
A second dq converter that dq converts an inverter output current detection value based on an output of the first multiplier and outputs a second harmonic detection value of d-axis and q-axis;
third and fourth subtractors for calculating a deviation between the d-axis and q-axis second harmonic command values and the d-axis and q-axis second harmonic detection values;
third and fourth amplifiers for amplifying the deviation between the d-axis and q-axis second harmonic command values and the d-axis and q-axis second harmonic detection values;
A second dq inverse transformer that inversely transforms the output of the third and fourth amplifiers based on the output of the first multiplier;
A neutral point potential control unit that outputs a value that reduces the deviation of the neutral point potential according to the deviation of the neutral point potential that is the deviation between the voltage detection value of the first DC capacitor and the voltage detection value of the second DC capacitor; ,
A PWM control unit that generates a gate command based on a value obtained by adding the output of the first dq inverse converter, the output of the second dq inverse converter, and the output of the neutral point potential control unit;
A control device for a three-level inverter. First and second DC capacitors that are connected in series between the DC terminals, divide the DC voltage between the DC terminals, and have this voltage dividing point as a neutral point;
A control device for a three-level inverter for grid connection or motor drive, comprising a DC voltage as an AC voltage, or a plurality of switching elements for converting an AC voltage into a DC voltage,
A first low-pass filter for removing noise and switching ripple of the inverter output current detection value;
A first dq converter that performs dq conversion on the output of the first low-pass filter based on the phase of the system voltage or the rotation angle phase of the motor, and converts it into d-axis and q-axis inverter output current detection values;
A second multiplier that -3 times the phase of the system voltage or the rotation angle phase of the motor;
Based on the output of the second multiplier, the d-axis second harmonic command value and the fixed q-axis second harmonic command value according to the deviation of the voltage detection values of the first and second DC capacitors, Alternatively, a third dq inverse converter that inversely converts a q-axis second harmonic command value corresponding to a deviation between a fixed d-axis second-order harmonic command value and a voltage detection value of the first and second DC capacitors. When,
Second and third adders for respectively adding the output of the third dq inverse converter and the d-axis and q-axis output current command values;
First and second subtractors for calculating deviations between the outputs of the second and third adders and the d-axis and q-axis inverter output current detection values, respectively;
First and second amplifiers for amplifying the deviation calculated by the first and second subtractors;
A first dq inverse converter that inversely transforms the outputs of the first and second amplifiers based on the phase of the system voltage or the rotation angle phase of the motor;
A neutral point potential controller that outputs a value that reduces the deviation of the neutral point potential according to the deviation of the neutral point potential that is the deviation between the voltage detection value of the first DC capacitor and the voltage detection value of the second DC capacitor When,
A three-level inverter control device comprising: a PWM control unit that generates a gate command based on a value obtained by adding the output of the first dq inverse converter and the output of the neutral point potential control unit . The d-axis second harmonic command value or the q-axis second harmonic command value is:
2. The control device for a three-level inverter according to claim 1, wherein the control device is changed in accordance with a deviation of a voltage detection value of the first and second capacitors. First and second capacitors connected in series between the DC terminals, dividing the DC voltage between the DC terminals, and having this voltage dividing point as a neutral point;
A control device for a three-level inverter for grid connection or motor drive, comprising a DC voltage as an AC voltage, or a plurality of switching elements for converting an AC voltage into a DC voltage,
A first low-pass filter for removing noise and switching ripple of the inverter output current detection value;
A first dq converter that performs dq conversion on the output of the first low-pass filter based on the phase of the system voltage or the rotation angle phase of the motor, and converts it into d-axis and q-axis inverter output current detection values;
first and second subtractors for calculating the deviation between the d-axis and q-axis output current command values and the d-axis and q-axis inverter output current detection values, respectively;
First and second amplifiers for amplifying the deviation calculated by the first and second subtractors;
A first dq inverse converter that inversely transforms the outputs of the first and second amplifiers based on the phase of the system voltage or the rotation angle phase of the motor;
A first multiplier for multiplying the phase of the system voltage or the rotation angle phase of the motor by -2,
A second dq converter that dq converts an inverter output current detection value based on an output of the first multiplier and outputs a second harmonic detection value of d-axis and q-axis;
third and fourth subtractors for calculating a deviation between the d-axis and q-axis second harmonic command values and the d-axis q-axis second harmonic detection value;
third and fourth amplifiers for amplifying the deviation between the d-axis and q-axis second harmonic command values and the d-axis and q-axis second harmonic detection values;
A second dq inverse transformer that inversely transforms the output of the third and fourth amplifiers based on the output of the first multiplier;
A second multiplier for quadrupling the phase of the system voltage or the rotation angle phase of the motor;
A third dq converter that dq-converts an inverter output current detection value based on the output of the second multiplier and outputs a fourth-harmonic detection value of the d-axis and the q-axis;
fifth and sixth subtractors for calculating a deviation between the fourth harmonic command value of the d-axis and the q-axis and the fourth harmonic detection value of the d-axis and the q-axis;
Sixth and seventh amplifiers for amplifying the outputs of the fifth and sixth subtractors;
A fourth dq inverse transformer that inversely transforms the outputs of the sixth and seventh amplifiers based on the output of the multiplier;
A neutral point potential control unit that outputs a value that reduces the deviation of the neutral point potential according to the deviation of the neutral point potential that is the deviation between the voltage detection value of the first DC capacitor and the voltage detection value of the second DC capacitor; ,
PWM that generates a gate command based on the sum of the output of the first dq inverse converter, the output of the neutral point potential controller, the output of the second dq inverse converter, and the output of the fourth dq inverse converter And a control unit for the three-level inverter. First and second DC capacitors that are connected in series between the DC terminals, divide the DC voltage between the DC terminals, and have this voltage dividing point as a neutral point;
A control device for a three-level inverter for grid connection or motor drive, comprising a DC voltage as an AC voltage, or a plurality of switching elements for converting an AC voltage into a DC voltage,
A first low-pass filter for removing noise and switching ripple of the inverter output current detection value;
A first dq converter that performs dq conversion on the output of the first low-pass filter based on the phase of the system voltage or the rotation angle phase of the motor, and converts it into d-axis and q-axis inverter output current detection values;
A third multiplier for multiplying the phase of the system voltage or the rotation angle phase of the motor by -3,
Based on the output of the third multiplier, the d-axis second harmonic command value and the fixed q-axis second harmonic command value according to the deviation of the voltage detection values of the first and second DC capacitors, Alternatively, a third dq inverse converter that inversely converts a q-axis second harmonic command value corresponding to a deviation between a fixed d-axis second-order harmonic command value and a voltage detection value of the first and second DC capacitors. When,
A fourth multiplier that triples the phase of the system voltage or the rotation angle phase of the motor;
Based on the output of the fourth multiplier, the d-axis fourth harmonic command value and the fixed q-axis fourth harmonic command value according to the deviation of the voltage detection values of the first and second DC capacitors, Alternatively, a fifth dq inverse converter that inversely transforms a q-axis fourth-order harmonic command value corresponding to a deviation between a fixed d-axis fourth-order harmonic command value and a voltage detection value of the first and second DC capacitors. When,
A value obtained by adding the output current command value of the d-axis and q-axis, the output of the third dq inverse converter, and the output of the fifth dq inverse converter, and the inverter output current detection value of the d-axis and q-axis First and second subtractors for calculating deviations, respectively;
First and second amplifiers for amplifying the deviation calculated by the first and second subtractors;
A first dq reverse converter for performing dq reverse conversion on the output of the first and second amplifiers based on the phase of the system voltage or the rotation angle phase of the motor, the voltage detection value of the first DC capacitor, and the voltage detection value of the second DC capacitor A neutral point potential control unit that outputs a value that reduces the deviation of the neutral point potential according to the deviation of the neutral point potential that is a deviation of
A three-level inverter control device comprising: a PWM control unit that generates a gate command based on a value obtained by adding the output of the first dq inverse converter and the output of the neutral point potential control unit . The d-axis second harmonic command value or the q-axis second harmonic command value, and the d-axis fourth harmonic command value or the q-axis fourth harmonic command value are:
5. The control device for a three-level inverter according to claim 4, wherein the controller is changed in accordance with a deviation of a voltage detection value of the first and second DC capacitors. Connect the output terminal of the inverter to the system power supply through the filter circuit,
The three-level inverter control device according to claim 1, wherein the dq converter and the dq inverse converter perform dq conversion and dq inverse conversion based on a phase of a system voltage. Connect the inverter output terminal to the motor,
The three-level inverter control device according to claim 1, wherein the dq converter and the dq inverse converter perform dq conversion and dq inverse conversion based on a rotation angle phase of a motor. A sixth multiplier for multiplying the system voltage phase or the rotation angle phase of the motor by -2,
A fifth dq converter that dq-converts the inverter output current detection value based on the output of the sixth multiplier and outputs the d-axis and q-axis inverter output current detection values;
Third and fourth low-pass filters for removing pulsation from the output of the fifth dq converter;
An eighth multiplier for multiplying the output of the third low-pass filter by a coefficient Qam;
A ninth multiplier for multiplying the output of the third low-pass filter by a coefficient Qbm;
A tenth multiplier for multiplying the output of the fourth low-pass filter by a coefficient Qam;
An eleventh multiplier for multiplying the output of the fourth low-pass filter by a coefficient Qbm;
An eighth adder for adding an output of the eighth multiplier and a value obtained by inverting the output of the eleventh multiplier;
A ninth adder for adding the output of the ninth multiplier and the output of the tenth multiplier;
Seventh and eighth subtractors for outputting a deviation between the outputs of the eighth and ninth adders and the outputs of the fifth and sixth low-pass filters that receive the second harmonic command value as an estimated value of disturbance; ,
Ninth and tenth subtractors for calculating the second harmonic command value by taking the deviation between the disturbance command value for suppressing the disturbance and the estimated value of the disturbance;
Fifth and sixth low-pass filters that receive the second harmonic command value and output to the seventh and eighth subtractors;
A seventh multiplier for multiplying the system voltage phase or the rotation angle phase of the motor by -3,
A fifth dq inverse transformer for dq inversely transforming the outputs of the ninth and tenth subtracters based on the output of the seventh multiplier;
6th and 7th adders for adding the outputs of the fifth dq inverse converters to the d-axis and q-axis output current command values and correcting the d-axis and q-axis output current command values. The control device for a three-level inverter according to claim 1.

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