KR20200094945A - Synchronous reference frame pahse locked loop, method and system for dc offset compensation of single phase grid connected inverter - Google Patents

Abstract

Disclosed are a synchronous reference frame phase synchronous locked loop and a direct current (DC) offset compensation method and system for a single-phase grid-connected inverter using the same. According to an embodiment of the present invention, the synchronous reference frame phase synchronous locked loop, which is a synchronous reference frame phase locked loop (SRF-PLL) for DC offset compensation of a single-phase grid-connected inverter, comprises: a proportional integral (PI) phase controller which calculates a phase angle from a measured grid voltage; an offset detection unit which detects d-axis and q-axis voltages in a rest reference frame of a DC offset component included in the grid voltage and detects the magnitude of a DC offset based on the d-axis and q-axis voltages of the DC offset component; and an offset compensation unit which compensates for the DC offset from a pre-measured grid voltage based on the offset magnitude.

Description

Synchronous coordinate system phase-locked loop and DC offset compensation method and system of single-phase grid type inverter using the same {SYNCHRONOUS REFERENCE FRAME PAHSE LOCKED LOOP, METHOD AND SYSTEM FOR DC OFFSET COMPENSATION OF SINGLE PHASE GRID CONNECTED INVERTER}

An embodiment of the present invention relates to a DC offset compensation technology of a single-phase grid type inverter.

In the grid-connected inverter, research and development are being conducted on technologies for high power quality and reliability improvement as the need for energy saving and energy efficiency improvement is increased. In the case of a grid-connected inverter, the performance of the system may be degraded due to the amplitude and phase difference with the grid-side voltage. To prevent this, it is necessary to accurately measure and synchronize the phase and amplitude information from the grid voltage.

1 is a diagram schematically showing the configuration of a general single-phase grid-connected inverter system, and includes a power conversion circuit, a phase locked loop (PLL) for measuring a phase angle, a coordinate converter, a current controller, a voltage controller, and a PWM. . Here, the system voltage (Vs) used as the input signal of the phase locked loop (PLL) for measuring the phase angle is a voltage sensor (not shown), a matching circuit (not shown), and an A/D converter (not shown). It is measured through

When measuring the system voltage (Vs), a DC offset occurs in the measurement path due to the nonlinear characteristics of the components (voltage sensor, matching circuit, A/D converter, etc.). In addition, when the inverter is controlled using a synchronous coordinate system that converts an AC signal with a constant frequency into a DC signal, the DC offset appears as a harmonic component of the grid frequency on the synchronous coordinate system, and thus a specific ripple in the d-axis voltage of the synchronous coordinate system. The ingredients will be included. In this case, distortion occurs in the inverter output as well, resulting in deterioration of the overall system performance.

Korean Registered Patent Publication No. 10-1761033 (2017.07.24)

The disclosed embodiment is to provide a new technique capable of compensating for a DC offset included in the grid voltage.

The synchronous coordinate system phase-locked loop according to the disclosed embodiment is a SRF-PLL (Synchronous Reference Frame Phase Locked Loop) for DC offset compensation of a single-phase grid-connected inverter, and the measured grid voltage PI (Proportional Integral) phase controller for calculating a phase angle from; An offset detection unit that detects d-axis and q-axis voltages of the DC offset component of the DC offset component and detects the magnitude of the DC offset based on the d-axis and q-axis voltages of the DC offset component; And an offset compensating unit for compensating for a DC offset from a pre-measured system voltage based on the detected DC offset size.

The offset detection unit may include a high pass filter (HPF) for detecting a d-axis voltage of a DC offset component included in the system voltage; A first All Pass Filter (APF) configured to generate a stationary coordinate system q-axis voltage of the DC offset component by inputting the d-axis voltage of the HPF as an input; And an offset size calculator configured to detect the magnitude of the DC offset based on the d-axis and q-axis voltages of the DC offset component.

The HPF may detect the d-axis voltage of the stationary coordinate system of the DC offset component by receiving the output of the integrator of the PI phase controller as an input.

The output of the HPF can be expressed by the following equation.

(Mathematics)

: DC 오프셋 성분의 정지 좌표계 d축 전압

: DC offset component's d-axis voltage

: PI 위상 제어기의 적분기 출력 값

: PI phase controller's integrator output value

: HPF의 컷 오프(cut off)

: HPF cut off

s: Laplace variable

: PI 위상 제어기의 적분기의 비례 이득

: Proportional gain of PI phase controller's integrator

: DC 오프셋

: DC offset

: PI 위상 제어기에 의해 추종된 각 주파수

: Each frequency followed by PI phase controller

The q-axis voltage in the stationary coordinate system of the DC offset component by the first APF may be expressed by the following equation.

(Mathematics)

: DC 오프셋 성분의 정지 좌표계 q축 전압

: DC offset component q-axis voltage

t: time

The offset size calculator may detect the size of the DC offset by the following equation.

(Mathematics)

_: DC 오프셋의 크기

_: DC offset size

The offset compensation unit may include: an offset difference detector configured to detect a difference between an n (n is a natural number)-th detected DC offset size and an n+1-th or n-1-th detected DC offset size; An offset difference accumulator for accumulating the detected DC offset difference value; A switch unit configured to converge the output value of the offset difference accumulating unit to a preset value according to a switching control signal; And a subtraction unit for subtracting an output value of the offset difference accumulating unit from the system voltage.

The switch unit is configured to add the detected DC offset difference value by the offset difference accumulating unit according to a first switching control signal, and calculate the detected DC offset difference value by the offset difference accumulating unit according to a second switching control signal. It can be arranged to be removed.

The output of the subtraction unit is a stop coordinate system d-axis voltage of the system voltage for which DC offset is compensated, and the synchronous coordinate system phase loop is the stop coordinate system q of the system voltage compensated for the DC offset by receiving the output of the subtraction unit as an input. A second APF generating an axial voltage; And a coordinate conversion unit that coordinates the d-axis voltage and the q-axis voltage of the system voltage compensated for the DC offset to a synchronous coordinate system.

The DC offset compensation method of a single-phase grid-connected inverter according to an embodiment disclosed is for DC offset compensation of a single-phase grid-connected inverter using SRF-PLL (Synchronous Reference Frame Phase Locked Loop). A method comprising the steps of: detecting d-axis and q-axis voltages in a stationary coordinate system of a DC offset component included in a measured system voltage; Detecting the magnitude of the DC offset based on the d-axis and q-axis voltages of the DC offset component; And compensating for a DC offset from the previously measured grid voltage based on the detected DC offset magnitude.

The step of detecting the d-axis voltage in the stationary coordinate system of the DC offset component includes an output of an integrator of a proportional integral (PI) phase controller as an input of a high pass filter (HPF), and the output of the HPF is an input of the DC offset component. It can be done with the d-axis voltage of the stationary coordinate system.

The output of the HPF can be expressed by the following equation.

(Mathematics)

: DC 오프셋 성분의 정지 좌표계 d축 전압

: DC offset component's d-axis voltage

: PI 위상 제어기의 적분기 출력 값

: PI phase controller's integrator output value

: HPF의 컷 오프(cut off)

: HPF cut off

s: Laplace variable

: PI 위상 제어기의 적분기의 비례 이득

: Proportional gain of PI phase controller's integrator

: DC 오프셋

: DC offset

: PI 위상 제어기에 의해 추종된 각 주파수

: Each frequency followed by PI phase controller

The step of detecting the stationary coordinate system q-axis voltage of the DC offset component includes the output of the HPF as an input of a first APF (All Pass Filter), and the output of the first APF is the stationary coordinate system q-axis of the DC offset component. You can do it with voltage.

The q-axis voltage in the stationary coordinate system of the DC offset component by the first APF may be expressed by the following equation.

(Mathematics)

: DC 오프셋 성분의 정지 좌표계 q축 전압

: DC offset component q-axis voltage

t: time

In the detecting of the magnitude of the DC offset, the magnitude of the DC offset may be detected by the following equation.

(Mathematics)

_: DC 오프셋의 크기

_: DC offset size

Compensating the DC offset may include, by an offset difference detection unit, detecting a difference between an n (n is a natural number)-th detected DC offset size and an n+1-th or n-1 th detected DC offset size; Accumulating the detected DC offset difference value by an offset difference accumulator; At a switch unit, allowing an output value of the offset difference accumulating unit to converge to a preset value according to a switching control signal; And subtracting an output value of the offset difference accumulating unit from the system voltage by a subtracting unit.

The step of allowing the output value of the offset difference accumulator to converge to a preset value includes, in the switch unit, adding the detected DC offset difference value from the offset difference accumulator according to a first switching control signal, and a second switching The detected DC offset difference value may be subtracted from the offset difference accumulator according to a control signal.

The output of the subtraction unit is a stop coordinate system d-axis voltage of the system voltage for which DC offset is compensated, and the DC offset compensation method of the single-phase system type inverter includes the output of the subtraction unit as an input of the second APF and the DC offset is Generating a stationary coordinate system q-axis voltage of the compensated system voltage; And converting coordinates of the d-axis voltage and q-axis voltage of the system voltage compensated for the DC offset into a synchronous coordinate system.

According to the disclosed embodiment, by detecting and compensating for a DC offset included in the grid voltage in a single-phase grid inverter, it is possible to prevent the system performance from deteriorating due to the DC offset.

1 is a diagram schematically showing the configuration of a general single-phase grid-connected inverter system
2 is a diagram showing a measurement path of a system voltage using a voltage sensor
3 is a diagram showing the configuration of a synchronous coordinate system phase-locked loop (SRF PLL) according to an embodiment of the present invention
4 is a diagram showing a signal waveform of a typical SRF-PLL
5 is a diagram showing a signal waveform of an SRF-PLL according to an embodiment of the present invention
6 is a block diagram illustrating and describing a computing environment including a computing device suitable for use in example embodiments.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. The following detailed description is provided to aid in a comprehensive understanding of the methods, apparatus and/or systems described herein. However, this is only an example and the present invention is not limited thereto.

In describing the embodiments of the present invention, when it is determined that a detailed description of known technology related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In addition, terms to be described later are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of users or operators. Therefore, the definition should be made based on the contents throughout this specification. The terminology used in the detailed description is only for describing embodiments of the present invention and should not be limiting. Unless expressly used otherwise, a singular form includes a plural form. In this description, expressions such as “including” or “equipment” are intended to indicate certain characteristics, numbers, steps, actions, elements, parts or combinations thereof, and one or more other than described. It should not be interpreted to exclude the presence or possibility of other characteristics, numbers, steps, actions, elements, or parts or combinations thereof.

In the following description, terms such as “transmission”, “communication”, “transmission”, “reception”, and the like of a signal or information are not only those in which a signal or information is directly transmitted from one component to another. This includes passing through other components. In particular, "sending" or "transmitting" a signal or information to a component indicates the final destination of the signal or information and does not mean a direct destination. The same is true for "reception" of signals or information. Also, in this specification, when two or more pieces of data or information are “related” means that acquiring one piece of data (or information) can acquire at least part of the other piece of data (or information) based on it.

Further, terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from other components. For example, the first component may be referred to as a second component without departing from the scope of the present invention, and similarly, the second component may also be referred to as a first component.

In an embodiment of the present invention, a Synchronous Reference Frame Phase Locked Loop (SRF PLL) is used to track the phase angle of a single-phase grid-connected inverter. If the phase angle is followed by using a synchronous coordinate system phase-lock loop (SRF PLL), there is an advantage in that control is easy because the steady state error becomes zero.

First, the influence of DC offset in the synchronous coordinate system phase-locked loop (SRF PLL) is as follows. 2 is a diagram showing a measurement path of a system voltage using a voltage sensor. The system voltage is measured through the path of voltage sensor → LPF → A/D converter → DSP. Here, DC offset and scale errors occur due to imbalance between analog devices and voltage sensors included in the measurement path of the system voltage. In this case, the system voltage including the DC offset may be expressed by Equation 1.

(Equation 1)

는 계통 전압(grid voltage)이고,

은 계통 전압의 피크값이며,

는 계통 각(grid angle)이고,

는 DC 오프셋을 나타낸다. In Equation 1,

Is the grid voltage,

Is the peak value of the grid voltage,

Is the grid angle,

Represents the DC offset.

On the other hand, in the case of a single-phase grid type inverter, unlike a three-phase grid type inverter, the scale error does not affect the phase angle calculation. Actually, there is no influence of the scale error on the d-axis voltage of the stationary coordinate system, which is a reference signal for measuring the phase angle. In addition, if the magnitude of the grid voltage fluctuates, it has the same effect as the scale error and does not cause pulsation in the phase angle followed under the SRF PLL. Therefore, the scale error is not considered in the embodiment of the present invention.

Equation 2 is an equation showing the d-axis and q-axis voltages of the system voltage including the DC offset.

(Equation 2)

은 정지 좌표계 d축 전압이고,

은 정지 좌표계 q축 전압을 나타낸다.here,

Is the d-axis voltage of the stationary coordinate system,

Represents the stationary coordinate system q-axis voltage.

In addition, the stationary coordinate system can be converted into a synchronous coordinate system by the coordinate conversion formula. Equation 3 is an equation showing the d-axis and q-axis voltages of the synchronous coordinate system of the system voltage including the DC offset.

(Equation 3)

은 동기 좌표계의 d축 전압이고,

은 동기 좌표계의 q축 전압을 나타낸다. here,

Is the d-axis voltage of the synchronous coordinate system,

Represents the q-axis voltage of the synchronous coordinate system.

According to Equation 3, the d-axis voltage of the synchronous coordinate system is 0, and the q-axis voltage of the synchronous coordinate system is different from the ideal case in which only DC components exist, the DC offset is the specific harmonic of the system frequency as the d-axis voltage of the synchronous coordinate system. You can see it induce. That is, since the ripple component is included in the d-axis voltage of the synchronous coordinate system due to the DC offset, a method for detecting and compensating the DC offset from the measured system voltage is required.

3 is a diagram showing the configuration of a synchronous coordinate system phase-locked loop (SRF PLL) according to an embodiment of the present invention.

3, the synchronous coordinate system phase-locked loop 100 may include a PI (Proportional Integral) phase controller 102, an offset detection unit 104, an offset compensation unit 106, and a coordinate conversion unit 108. have.

)을 산출할 수 있다. 도 2에 도시된 측정 경로를 통해 계통 전압이 측정되는 경우, 측정된 계통 전압은 정지 좌표계 d축 및 q축 전압으로 변환된 후 다시 동기 좌표계 d축 및 q축 전압으로 변환된다. 여기서, PI 위상 제어기(102)는 동기 좌표계 d축 전압에 기반하여 위상각(

)을 추종할 수 있다. PI 위상 제어기(102)는 적분기(102a)를 포함할 수 있다. SRF PLL의 PI 위상 제어기(102)는 이미 공지된 기술이므로 이에 대한 자세한 설명은 생략하기로 한다. PI phase controller 102 is a phase angle from the measured grid voltage (

) Can be calculated. When the system voltage is measured through the measurement path shown in FIG. 2, the measured system voltage is converted into a stationary coordinate system d-axis and q-axis voltage, and then converted back into a synchronous coordinate system d-axis and q-axis voltage. Here, the PI phase controller 102 is based on the synchronous coordinate system d-axis voltage, the phase angle (

) Can be followed. The PI phase controller 102 may include an integrator 102a. Since the PI phase controller 102 of the SRF PLL is a known technology, a detailed description thereof will be omitted.

The offset detection unit 104 may detect the magnitude of the DC offset included in the measured system voltage. The offset detection unit 104 may include a high pass filter (HPF) 104a, a first all pass filter (APF) 104b, and an offset size calculation unit 104c.

The HPF 104a can detect a DC offset component (ie, a ripple component) included in the system voltage by taking the output of the integrator 102a of the PI phase controller 102 as an input. Here, the reason that the output of the integrator 102a of the PI phase controller 102 is an input to the offset detection unit 104 is, since the integrator 102a has a previously accumulated value, detection is not possible even if the size of the DC offset component is small. Because it is easy. In addition, even if a transient condition occurs in the synchronous coordinate system phase-locked loop 100, the output of the integrator 102a is not significantly affected, so that the DC offset component can be stably detected.

However, the present invention is not limited thereto, and the HPF 104a may have an output of the PI phase controller 102 other than the integrator 102a as an input.

The output value of the HPF 104a may be used as the d-axis voltage of the stationary coordinate system of the DC offset component. Equation 4 is an equation representing the output value of the HPF 104a.

(Equation 4)

는 DC 오프셋 성분의 정지 좌표계 d축 전압을 나타내고,

는 PI 위상 제어기(102)의 적분기(102a) 출력 값을 나타내며,

는 HPF(104a)의 컷 오프(cut off) 주파수를 나타내고, s는 라플라스 변수를 나타낸다. 그리고,

는 적분기(102a)의 비례 이득을 나타내고,

는 PI 위상 제어기(102)에 의해 추종된 각 주파수를 나타낸다.here,

Denotes the d-axis voltage of the stationary coordinate system of the DC offset component,

Represents the output value of the integrator 102a of the PI phase controller 102,

Denotes the cut off frequency of the HPF 104a, and s denotes the Laplace variable. And,

Represents the proportional gain of the integrator 102a,

Represents each frequency followed by the PI phase controller 102.

The first APF (All Pass Filter) 104b may generate a stationary coordinate system q-axis voltage of the DC offset component by inputting the stationary coordinate system d-axis voltage of the DC offset component detected by the HPF 104a as an input. The first APF 104b may phase-delay the output of the HPF 104a by 90 degrees without attenuation in size, thereby generating a stationary coordinate system q-axis voltage of the DC offset component.

Equation 5 is an equation showing the q-axis voltage of the stationary coordinate system of the DC offset component by the first APF 104b.

(Equation 5)

는 DC 오프셋 성분의 정지 좌표계 q축 전압을 나타낸다.here,

Represents the static coordinate system q-axis voltage of the DC offset component.

The offset size calculating unit 104c may detect the size of the DC offset included in the system voltage measured by the voltage sensor. The offset size calculation unit 104c calculates the DC offset based on the stop coordinate system d-axis voltage of the DC offset component detected by the HPF 104a and the stop coordinate system q-axis voltage of the DC offset component generated by the first APF 104b. The size can be detected. The offset size calculating unit 104c may detect the size of the DC offset through Equation 6.

(Equation 6)

는 DC 오프셋의 크기를 나타낸다.here,

Represents the size of the DC offset.

The offset compensation unit 106 may compensate the previously measured system voltage (ie, the system voltage including the DC offset) based on the detected DC offset size. The offset compensation unit 106 may include an offset difference detection unit 106a, an offset difference accumulating unit 106b, a switch unit 106c, and a subtraction unit 106d.

The offset difference detection unit 106a may detect a difference between the nth detected DC offset size and the n+1th (or n-1th) detected DC offset size. In an exemplary embodiment, the offset difference detection unit 106a may detect a difference between the nth detected DC offset size and the n+1th detected DC offset size through Equation 7.

(Equation 7)

The offset difference accumulating unit 106b may accumulate a difference in DC offset magnitude detected by the offset difference detecting unit 106a. The offset difference accumulator 106b may accumulate the difference in DC offset size through an integration operation. The synchronous coordinate system phase-locked loop 100 according to the disclosed embodiment may compensate for the DC offset by allowing the output value of the offset difference accumulator 106b to converge to a preset value (eg, 0).

To this end, the switch unit 106c may determine whether to add (+) or subtract (-) the DC offset difference value according to the switching control signals (+ kcom,-kcom). That is, the switch unit 106c adds the DC offset difference value detected by the offset difference detection unit 106a by the offset difference accumulator 106b so that the output value of the offset difference accumulator 106b converges to zero (+) or You can decide whether to subtract (-) or not.

Specifically, when the first switching control signal (+ kcom) is input, the switch unit 106c may cause the offset difference accumulating unit 106b to add the DC offset difference detected by the offset difference detection unit 106a. That is, when the first switching control signal (+ kcom) is input, the switch unit 106c makes the DC offset difference detected by the offset difference detection unit 106a a + value and is input to the offset difference accumulating unit 106b. I can.

In addition, when the second switching control signal (-kcom) is input, the switch unit 106c may allow the offset difference accumulating unit 106b to subtract the DC offset difference detected by the offset difference detection unit 106a. That is, when the second switching control signal (- kcom) is input, the switch unit 106c makes the DC offset difference detected by the offset difference detection unit 106a a-value and is input to the offset difference accumulating unit 106b. I can.

The subtractor 106d may subtract the output value of the offset difference accumulator 106b from the system voltage measured by the voltage sensor (ie, the system voltage including the DC offset) and input it to the coordinate conversion unit 108. In this case, the DC offset is compensated (ie, removed) from the system voltage measured by the voltage sensor by the subtracting unit 106d and input to the coordinate conversion unit 108. Here, the value input to the coordinate conversion unit 108 becomes the d-axis voltage of the stationary coordinate system of the system voltage compensated for the DC offset. Meanwhile, the output value of the subtractor 106d is input to the second APF 111, and the second APF 111 may generate a stationary coordinate system q-axis voltage of the system voltage compensated for the DC offset.

The coordinate conversion unit 108 may coordinate conversion of the stationary coordinate system d-axis voltage and q-axis voltage of the system voltage compensated for the DC offset, and convert it into a synchronous coordinate system d-axis and q-axis voltage. Coordinate conversion from a stationary coordinate system to a synchronous coordinate system is a known technique, and a detailed description thereof will be omitted. The output value of the coordinate conversion unit 108 may be input to the PI phase controller 102 after noise is removed through the LPF (Low Pass Filter) 113.

4 is a diagram showing a signal waveform of a general SRF-PLL, and FIG. 5 is a diagram showing a signal waveform of an SRF-PLL according to an embodiment of the present invention. Here, the system voltage, the phase angle, the d-axis component of the synchronous coordinate system, and the signal waveform of the integrator output of the PI controller are shown, respectively.

4 and 5, in the case of a general SRF-PLL, it can be seen that the d-axis component of the synchronous coordinate system and the DC offset component are included in the integrator output of the PI controller, but in the case of the SRF-PLL according to the embodiment of the present invention It can be seen that the d-axis component of the synchronous coordinate system and the DC offset component are removed from the integrator output of the PI controller.

6 is a block diagram illustrating and describing a computing environment 10 including a computing device suitable for use in example embodiments. In the illustrated embodiment, each component may have different functions and capabilities in addition to those described below, and may include additional components in addition to those described below.

The illustrated computing environment 10 includes a computing device 12. In one embodiment, the computing device 12 may be a synchronous coordinate system phase-locked loop 100.

The computing device 12 includes at least one processor 14, a computer-readable storage medium 16 and a communication bus 18. The processor 14 may cause the computing device 12 to operate in accordance with the exemplary embodiment mentioned above. For example, processor 14 may execute one or more programs stored on computer readable storage medium 16. The one or more programs can include one or more computer-executable instructions, which, when executed by processor 14, configure computing device 12 to perform operations in accordance with an exemplary embodiment. Can be.

Computer readable storage medium 16 is configured to store computer executable instructions or program code, program data and/or other suitable types of information. The program 20 stored on the computer readable storage medium 16 includes a set of instructions executable by the processor 14. In one embodiment, the computer readable storage medium 16 is a memory (volatile memory such as random access memory, non-volatile memory, or a suitable combination thereof), one or more magnetic disk storage devices, optical disk storage devices, flash Memory devices, other types of storage media that can be accessed by the computing device 12 and store desired information, or suitable combinations thereof.

The communication bus 18 interconnects various other components of the computing device 12, including a processor 14 and a computer readable storage medium 16.

Computing device 12 may also include one or more I/O interfaces 22 and one or more network communication interfaces 26 that provide an interface for one or more I/O devices 24. The input/output interface 22 and the network communication interface 26 are connected to the communication bus 18. The input/output device 24 may be connected to other components of the computing device 12 through the input/output interface 22. Exemplary input/output devices 24 include pointing devices (such as a mouse or trackpad), keyboards, touch input devices (such as touch pads or touch screens), voice or sound input devices, various types of sensor devices, and/or imaging devices. Input devices and/or output devices such as display devices, printers, speakers and/or network cards. The exemplary input/output device 24 may be included in the computing device 12 as a component constituting the computing device 12, and may be connected to the computing device 12 as a separate device distinct from the computing device 12. May be.

Although the exemplary embodiments of the present invention have been described in detail above, those of ordinary skill in the art to which the present invention pertains will understand that various modifications may be made to the above-described embodiments without departing from the scope of the present invention. . Therefore, the scope of the present invention is limited to the described embodiments and should not be determined, and should not be determined by the claims to be described later, but also by those equivalents to the claims.

100: synchronous coordinate system phase synchronization loop
102: PI phase controller
102a: integrator
104: offset detection unit
104a: HPF
104b: first APF
104c: Offset size calculation unit
106: offset compensation unit
106a: offset difference detection unit
106b: offset difference accumulator
106c: switch part
106d: deduction
108: coordinate conversion unit
111: 2nd APF
113: LPF

Claims (19)

As a Synchronous Reference Frame Phase Locked Loop (SRF-PLL) for DC offset compensation of a single-phase grid-connected inverter,
PI (Proportional Integral) phase controller for calculating a phase angle from the measured system voltage;
An offset detection unit that detects d-axis and q-axis voltages of the DC offset component included in the system voltage, and detects the magnitude of the DC offset based on the d-axis and q-axis voltages of the DC offset component; And
Including an offset compensating unit for compensating a DC offset from the pre-measured grid voltage based on the detected DC offset magnitude, synchronous coordinate system phase locked loop.
The method according to claim 1,
The offset detection unit,
A high pass filter (HPF) for detecting a d-axis voltage in a stationary coordinate system of a DC offset component included in the system voltage;
A first All Pass Filter (APF) configured to generate a stationary coordinate system q-axis voltage of the DC offset component by inputting the d-axis voltage of the HPF as an input; And
A phase loop of a synchronous coordinate system comprising an offset magnitude calculator configured to detect the magnitude of the DC offset based on the d-axis and q-axis voltages of the DC offset component.
The method according to claim 2,
The HPF is,
A synchronous coordinate system phase loop for detecting a stationary coordinate system d-axis voltage of the DC offset component by receiving an output of the integrator of the PI phase controller as an input.
The method according to claim 3,
The output of the HPF is represented by the following equation, synchronous coordinate system phase loop.
(Mathematics)

: DC offset component's d-axis voltage

: PI phase controller's integrator output value

: HPF cut off
s: Laplace variable

: Proportional gain of PI phase controller's integrator

: DC offset

: Each frequency followed by PI phase controller
The method according to claim 4,
The stationary coordinate system q-axis voltage of the DC offset component by the first APF is expressed by the following equation.
(Mathematics)

: DC offset component q-axis voltage
t: time
The method according to claim 5,
The offset size calculation unit,
A synchronous coordinate system phase loop for detecting the magnitude of the DC offset by the following equation.
(Mathematics)

_: DC offset size
The method according to claim 1,
The offset compensation unit,
an offset difference detector configured to detect a difference between an n (n is a natural number)-th detected DC offset size and an n+1-th or n-1 th detected DC offset size;
An offset difference accumulator for accumulating the detected DC offset difference value;
A switch unit configured to converge the output value of the offset difference accumulating unit to a preset value according to a switching control signal; And
And a subtraction unit for subtracting an output value of the offset difference accumulating unit from the system voltage.
The method according to claim 7,
The switch unit,
Add the detected DC offset difference value by the offset difference accumulator according to the first switching control signal,
A synchronous coordinate system phase loop provided to subtract the detected DC offset difference value from the offset difference accumulating unit according to a second switching control signal.
The method according to claim 7,
The output of the subtraction unit is a stop coordinate system d-axis voltage of the system voltage for which DC offset is compensated,
The synchronous coordinate system phase loop,
A second APF for generating a stationary coordinate system q-axis voltage of the system voltage compensated for the DC offset by receiving the output of the subtractor as an input; And
The synchronous coordinate system phase loop further comprising a coordinate conversion unit that coordinates the d-axis voltage and the q-axis voltage of the system voltage compensated for the DC offset to a synchronous coordinate system.
As a method for compensating the DC offset of a single-phase grid-connected inverter using SRF-PLL (Synchronous Reference Frame Phase Locked Loop),
Detecting d-axis and q-axis voltages of the DC offset component included in the measured grid voltage;
Detecting the magnitude of the DC offset based on the d-axis and q-axis voltages of the DC offset component; And
Compensating for a DC offset from the previously measured grid voltage based on the detected DC offset magnitude, DC offset compensation method of a single-phase grid type inverter.
The method according to claim 10,
The step of detecting the d-axis voltage of the stationary coordinate system of the DC offset component,
DC offset compensation of a single-phase system inverter, in which the output of the PI (Proportional Integral) phase controller is used as the input of the HPF (High Pass Filter), and the output of the HPF is the d-axis voltage in the stationary coordinate system of the DC offset component. Way.
The method according to claim 11,
The output of the HPF is represented by the following equation, DC offset compensation method of a single-phase grid type inverter.
(Mathematics)

: DC offset component's d-axis voltage

: PI phase controller's integrator output value

: HPF cut off
s: Laplace variable

: Proportional gain of PI phase controller's integrator

: DC offset

: Each frequency followed by PI phase controller
The method of claim 12,
The step of detecting the stationary coordinate system q-axis voltage of the DC offset component,
The DC offset compensation method of a single-phase system type inverter, wherein the output of the HPF is used as an input of a first APF (All Pass Filter), and the output of the first APF is used as the q-axis voltage of the stationary coordinate system of the DC offset component.
The method according to claim 13,
The q-axis voltage of the stationary coordinate system of the DC offset component by the first APF is expressed by the following equation.
(Mathematics)

: DC offset component q-axis voltage
t: time
The method according to claim 14,
The step of detecting the magnitude of the DC offset,
DC offset compensation method of a single-phase grid inverter for detecting the magnitude of the DC offset by the following equation.
(Mathematics)

_: DC offset size
The method according to claim 10,
Compensating for the DC offset,
Detecting a difference between an n (n is a natural number)-th detected DC offset size and an n+1-th or n-1-th detected DC offset size, by the offset difference detection unit;
Accumulating the detected DC offset difference value by an offset difference accumulator;
At a switch unit, allowing an output value of the offset difference accumulating unit to converge to a preset value according to a switching control signal; And
In a subtracting unit, the DC offset compensation method of a single-phase grid type inverter comprising the step of subtracting the output value of the offset difference accumulating unit from the grid voltage.
The method according to claim 16,
The step of allowing the output value of the offset difference accumulator to converge to a preset value,
In the switch unit, the DC offset difference value detected by the offset difference accumulating unit is added according to a first switching control signal, and the DC offset difference value detected by the offset difference accumulating unit according to a second switching control signal DC offset compensation method of single-phase grid type inverter to subtract
The method according to claim 16,
The output of the subtraction unit is a stop coordinate system d-axis voltage of the system voltage for which DC offset is compensated,
The DC offset compensation method of the single-phase grid type inverter,
Generating a stationary coordinate system q-axis voltage of the system voltage compensated for the DC offset by using the output of the subtractor as an input of the second APF; And
The DC offset compensation method of a single-phase grid inverter further comprising the step of converting the coordinate system d-axis voltage and q-axis voltage of the grid voltage compensated for the DC offset into a synchronous coordinate system.
A single-phase grid inverter system comprising the synchronous coordinate system phase loop according to any one of claims 1 to 9.

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