JP7322567B2 - Modular multilevel cascade converter - Google Patents

Description

The present invention relates to a single star bridge cell (SSBC) modular multi-level cascade converter (MMCC) technology interconnected to a three-phase AC system.

FIG. 1 shows the configuration of a single star bridge cell (SSBC) modular multilevel cascade converter (MMCC). A feature of this circuit is that each arm is configured by a module in which the bridge cells B shown in FIG. The MMCC-SSBC can be connected to a high-voltage system without a transformer, and is expected to be used as a reactive power compensator.

However, MMCC-SSBC has a problem that inter-phase cell capacitor voltages become unbalanced when connected to an unbalanced voltage system or when a reversed-phase current is output, that is, when reversed-phase power is output. This imbalance causes excessive voltage applied to switching elements and cell capacitors, distorted voltage and current waveforms output from MMCC-SSBC, burnout of transformers, overheating and breakdown of power factor improvement capacitors. , causes problems such as motor hum and circuit breaker malfunction, which adversely affect other devices. Patent Document 1 and Non-Patent Document 1 disclose methods for improving this imbalance.

JP 2013-5694 A

Ken Yoshii, Shigenori Inoue, Yasufumi Akagi, "6.6 kV Transformerless Cascade PWM STATCOM", 2007, Dengaku Ron D, Vol. 127, No. 8, p. 781-788 Satoshi Ishizuka, Kazuyoshi Nezu, Yukihiko Sato, Hiroshi Yamaguchi, Akio Kataoka, "Power supply current control of voltage source PWM rectifier circuit applying lossless resonator", 1996, Theory of Electrical Engineering D, Vol.116, No.8 , p. 883-884

Patent document 1 is a feedforward control that detects the negative-phase voltage and the negative-phase current, calculates and superimposes the optimum zero-phase voltage for maintaining the cell capacitor voltage balance. Since it uses zero-sequence voltage and does not output extra reverse-sequence current, it has the advantage of maintaining balance without disturbing the system.

However, the amplitude of the zero-sequence voltage to be superimposed increases as the voltage imbalance increases and as the negative-sequence current to be output increases. The MMCC-SSBC needs to output a voltage with a larger amplitude, which requires an increase in the number of cascade-connected bridge cells B and cell capacitor voltages, resulting in an increase in cost and loss.

On the other hand, Non-Patent Document 1 discloses a method of intentionally outputting a reverse-phase current suitable for balance correction when the cell capacitor voltage balance is lost. However, the negative-sequence current that is suitable for balance correction is not always appropriate for the grid, and may exacerbate the voltage imbalance of the grid. Adverse effects such as increased heat generation, increased vibration and noise, and shortened service life. For the convenience of MMCC-SSBC, it is not desirable to output an arbitrary reversed-phase current different from the command value.

As described above, it is a problem to keep the voltage balance of the cell capacitors constant and to use suitable zero-phase voltage and negative-phase voltage in the modular multi-level cascade converter.

The present invention has been devised in view of the above-described conventional problems, and one aspect of the present invention is to configure a single-phase module by connecting a plurality of bridge cell units in series, and to configure a three-phase module having three units of this module. wherein the zero-phase voltage is output as a corrected zero-phase voltage when the amplitude of the zero-phase voltage required for balance control of the cell capacitor voltage is equal to or less than the upper limit value, and the zero-phase voltage is a zero-phase voltage calculator that outputs the upper limit value as the corrected zero-phase voltage when the voltage amplitude is greater than the upper limit value; and the corrected zero-phase voltage when the zero-phase voltage is greater than the upper limit value A current command value calculation unit that outputs a current command value superimposed and superimposed with a corrected reverse-phase current command value necessary for balance control of the cell capacitor voltage; and a gate signal based on the corrected zero-phase voltage and the current command value. and a current control unit that generates

Further, as one aspect thereof, when the output voltage/output current of the modular multi-level cascade converter and the corrected zero-phase voltage to be superimposed are defined by equations (3) and (4), the zero-phase voltage The calculation unit does not input the negative-phase current command value, and calculates the zero based on the positive-phase q-axis current command value, the positive-phase d-axis voltage, the negative-phase d-axis voltage, and the negative-phase q-axis voltage. The phase voltage is calculated to output the corrected zero-phase voltage. It is characterized by calculating a phase q-axis current command value.

Vu, Vv, Vw: U-phase output voltage, V-phase output voltage, W-phase output voltage V1d: Positive phase d-axis voltage V1q: Positive phase q-axis voltage V2d: Negative phase d-axis voltage V2q: Negative phase q-axis Voltage V0d': Corrected zero-phase d-axis voltage V0q': Corrected zero-phase q-axis voltage ωt: System voltage phase iu, iv, iw: U-phase output current, V-phase output current, W-phase output current I1q: Positive-phase q-axis current I2d: Negative-phase d-axis current I2q: Negative-phase q-axis current I1q*: Positive-phase q-axis current command value I2d*': Corrected negative-phase d-axis current command value I2q*': Corrected negative-phase q-axis Current command value.

Further, as another aspect, when the corrected zero-phase voltage on which the output voltage/output current of the modular multilevel cascade converter is superimposed is defined by equations (3) and (4), the zero-phase The voltage calculator calculates a negative-phase d-axis current command value, a negative-phase q-axis current command value, a positive-phase q-axis current command value, a positive-phase d-axis voltage, a negative-phase d-axis voltage, and , the zero-phase voltage is calculated based on the negative-phase q-axis voltage to output the corrected zero-phase voltage, and the current command value calculation unit calculates the corrected negative-phase current command value based on equation (6). A corrected anti-phase d-axis current command value and a corrected anti-phase q-axis current command value are calculated.

Vu, Vv, Vw: U-phase output voltage, V-phase output voltage, W-phase output voltage V1d: Positive phase d-axis voltage V1q: Positive phase q-axis voltage V2d: Negative phase d-axis voltage V2q: Negative phase q-axis Voltage V0d': Corrected zero-phase d-axis voltage V0q': Corrected zero-phase q-axis voltage ωt: System voltage phase iu, iv, iw: U-phase output current, V-phase output current, W-phase output current I1q: Positive-phase q-axis current I2d: Negative-phase d-axis current I2q: Negative-phase q-axis current I1q*: Positive-phase q-axis current command value I2d*': Corrected negative-phase d-axis current command value I2q*': Corrected negative-phase q-axis Current command value.

Further, as one aspect thereof, when the voltage amplitude that can be output from the modular multi-level cascade converter is less than 1.5 times the rated voltage amplitude, the zero-phase voltage calculation unit detects that a line-to-line short circuit has occurred. The upper limit is sometimes set to zero.

According to the present invention, it is possible to keep the voltage balance of the cell capacitors constant and use suitable zero-phase voltage and negative-phase voltage in the modular multi-level cascade converter.

Schematic diagram showing the configuration of MMCC-SSBC. Schematic which shows the structure of a bridge cell. FIG. 3 is a block diagram showing a current control unit according to Embodiments 1 to 3; 4 is a block diagram of a zero-phase voltage calculator in the first embodiment; FIG. FIG. 2 is a block diagram of a current command value calculator in Embodiments 1 to 3; FIG. 10 is a block diagram of a zero-phase voltage calculator according to the second embodiment; FIG. 11 is a block diagram of a zero-phase voltage calculator in Embodiment 3; FIG. 4 is a relational diagram between the amount of superimposed zero-phase voltage and the negative-sequence current amplitude required for balance.

Embodiments 1 to 3 of the modular multilevel cascade converter according to the present invention will be described in detail below with reference to FIGS. 1 to 8. FIG.

[Embodiment 1]
Embodiment 1 shows a method of balancing the cell capacitor voltages by using both balance control based on the zero-phase voltage and balance control based on the negative-phase current. By preferentially using the zero-sequence voltage and outputting the reverse-sequence current only when the amplitude of the zero-sequence voltage that can be superimposed on the command is insufficient, the disturbance given to the system is minimized.

The modular multi-level cascade converter (serial multiple inverter device) of the first embodiment is assumed to be applied to the circuit shown in FIG. 1, for example. In FIG. 1, reference numeral 25 denotes a three-phase alternating current system power supply, and the system voltage is Vs. A plurality of bridge cell B units are connected in series to form a one-phase module. It has three modules and is connected to each phase of the system via a reactor. That is, n bridge cells B are connected to each phase (three phases), and 3n bridge cells B are connected in total for the three phases.

As shown in FIG. 2, in the bridge cell B, one end of the first semiconductor switching element S1 is connected to one connection terminal. One end of the second semiconductor switching element S2 is connected to one end of the first semiconductor switching element S1. The third semiconductor switching element S3 is connected between the other end of the first semiconductor switching element S1 and the other connection terminal. The fourth semiconductor switching element S4 is connected between the other end of the second semiconductor switching element S2 and the other connection terminal. The cell capacitor C is connected between the connection point of the first and third semiconductor switching elements S1 and S3 and the connection point of the second and fourth semiconductor switching elements S2 and S4.

FIG. 3 shows a block diagram of the current controller of the MMCC-SSBC. The low-pass filter LPF removes noise, switching ripples, etc. from the output current detection signals iu, iv, and iw of each phase. A three-to-two phase converter 1 converts the output result of the low-pass filter LPF into three-to-two phases and outputs two-phase output current detection signals Ia and Ib.

Subtractors 2a and 2b calculate deviations between current command values Ia* and Ib* on fixed coordinates after three-phase to two-phase conversion and two-phase output current detection signals Ia and Ib, which will be described later. A P (proportional) R (resonant) amplifier PR amplifies the outputs of the subtractors 2a and 2b. The R amplifier is described in Non-Patent Document 2, and has an infinite gain with respect to a specific frequency. By using this frequency as the system power supply frequency, the deviation of both the positive-sequence current and the negative-sequence current can be made zero. A two-to-three-phase converter 3 converts the output of the PR amplifier PR into two-to-three phases and outputs an output voltage command value for each phase.

The adder 4 adds the products V0d'cos ωt and V0q'sin ωt, which will be described later, to calculate a corrected zero-phase voltage. The adders 5u, 5v, and 5w add the corrected zero-phase voltage, which is the output of the adder 4, to the output voltage command value of each phase output from the two-to-three-phase converter 3, respectively. In addition, the zero-phase voltage obtained by cell capacitor voltage balance feedback control may be added.

The PWM modulator PWM compares the output voltage command value of each phase superimposed with the corrected zero-phase voltage and the carrier triangular wave corresponding to each bridge cell B, and obtains the gate signal of each bridge cell B. FIG. The obtained gate signal is input to each bridge cell B in FIG.

FIG. 4 shows a block diagram of the zero-phase voltage calculator 27 of the first embodiment.

A PLL (Phase Locked Loop) obtains the phase ωt from the system voltage detection signal Vs. The low-pass filter LPF removes noise, switching ripples, etc. from the system voltage detection signal Vs.

The dq converter 6 dq-converts the system voltage detection signal Vs to which the low-pass filter LPF has been applied based on the phase ωt. The moving average filters MAVE1 and MAVE2 remove pulsations at twice the fundamental frequency caused by voltage imbalance from the output of the dq converter 6. FIG. The outputs of the moving average filters MAVE1 and MAVE2 are the positive phase d-axis voltage V1d and the positive phase q-axis voltage V1q. The positive phase q-axis voltage V1q is normally zero in normal operation as long as the PLL operates normally, but may have a value when the system voltage fluctuates.

A multiplier 7 multiplies the phase ωt by −1. The dq converter 8 dq-converts the system voltage detection signal Vs to which the low-pass filter LPF is applied based on the phase -ωt. The moving average filters MAVE3 and MAVE4 remove from the output of the dq converter 8 the pulsation at twice the fundamental frequency caused by the positive phase voltage. The outputs of the moving average filters MAVE3 and MAVE4 are the anti-phase d-axis voltage V2d and the anti-phase q-axis voltage V2q.

The computing unit 9 receives a positive phase q-axis current command value I1q* input from outside in addition to the positive phase d-axis voltage V1d, the negative phase d-axis voltage V2d, the negative phase q-axis voltage V2q. Based on the positive phase d-axis voltage V1d, the negative phase d-axis voltage V2d, the negative phase q-axis voltage V2q, and the positive phase q-axis current command value I1q*, the calculator 9 balances the cell capacitor voltage based on Patent Document 1. Appropriate zero-phase d-axis voltage V0d and zero-phase q-axis voltage V0q are output. In equation (1), V1 is a positive sequence voltage, V2 is a negative sequence voltage, I1 is a positive sequence current, and I2 is a negative sequence current.

The phase difference φ between the positive-phase current and the negative-phase current is the value selected from 0deg, 60deg, 120deg, 180deg, 240deg, and 300deg, and when the phase difference φ is 0deg and 180deg (2-1) The zero-phase d-axis voltage V0d and the zero-phase q-axis voltage V0q are calculated based on the formula (2-2) when the phase difference φ is 120deg and 300deg, and the formula (2-3) when the phase difference φ is 60deg and 240deg. You can calculate.

a': Amplitude ratio of positive phase current and negative phase current a: Correction amplitude ratio where a = a' (φ = 0deg, 120deg, 240deg)
a = -a' (φ = 60deg, 180deg, 300deg)
If the phase difference φ is not 0 deg, 60 deg, 120 deg, 180 deg, 240 deg, or 300 deg, 2 Two zero-phase d-axis voltage V0d and zero-phase q-axis voltage V0q are obtained, and the two zero-phase d-axis voltage V0d and zero-phase q-axis voltage V0q are interpolated to obtain zero-phase d-axis voltage V0d and zero-phase q-axis voltage V0q. may decide.

However, in formula (2-1), a = a' (φ<90deg, 270deg<φ), a = -a' (90deg<φ<270deg), and in formula (2-2), a = a' ( 30deg<φ<210deg), a=-a'(φ<30deg, 210deg<φ), In the formula (2-3), a=a'(150deg<φ<330deg), a=-a'(φ< 150deg, 330deg<φ).

The correction coefficient is set to 2/√3 when the phase difference φ is 30deg, 90deg, 150deg, 210deg, 270deg and 330deg, and the correction coefficient is set to 1 when the phase difference φ is 0deg, 60deg, 120deg, 180deg, 240deg and 300deg. , the gain Gi obtained by linear interpolation of the correction coefficient in the phase difference φ between , is the term dependent on the positive phase d-axis voltage V1d in the equations (2-1), (2-2), and (2-3). can be multiplied by

At this time, the amplitude ratio a of the negative-phase current to the positive-phase current is zero. The same result can be obtained no matter what value the phase difference φ is set to.

An example of the method of calculating the zero-phase d-axis voltage V0d and the zero-phase q-axis voltage V0q has been described above. can be

Multipliers 10d and 10q obtain the squares of the zero-phase d-axis voltage V0d and the zero-phase q-axis voltage V0q. Adder 11 adds the outputs of multipliers 10d and 10q. A square root calculator 12 obtains the square root of the output of the adder 11 . The output of the square root calculator 12 is the amplitude √(V0d ² +V0q ² ) of the zero-phase voltage superimposed on the voltage command value.

The divider 13 divides the upper limit value V0lim that specifies the upper limit of the amplitude of the zero-phase voltage by the amplitude of the zero-phase voltage √(V0d ² +V0q ² ) to obtain the zero-phase voltage for the amplitude √(V0d ² +V0q ² ) of the zero-phase voltage. A ratio of the upper limit value V0lim of the voltage amplitude is obtained.

The subtractor 14 subtracts the amplitude of the zero-phase voltage √(V0d ² +V0q ² ) from the upper limit value V0lim of the amplitude of the zero-phase voltage. The comparator 15 compares the output of the subtractor 14 with 0, and outputs 1 when the output of the subtractor 14 is negative, that is, when the zero-phase voltage amplitude √(V0d ² +V0q ² ) is greater than the upper limit value V0lim. and 0 otherwise. The switch 16 outputs the ratio of the upper limit value V0lim to the amplitude of the zero-phase voltage (the output of the divider 13) if the output of the comparator 15 is 1, and outputs 1 if the output is 0. Multipliers 17d and 17q multiply the output of the switch 16 by the zero-phase d-axis voltage V0d and the zero-phase q-axis voltage V0q. Outputs of the multipliers 17d and 17q are corrected zero-phase voltages V0d' and V0q'.

The corrected zero-phase voltages V0d' and V0q' are V0d'=V0d and V0q'=V0q if the amplitude √(V0d ² +V0q ² ) of the zero-phase voltage obtained from the calculator 9 is smaller than the upper limit value V0lim. If the amplitude of the zero-phase voltage √(V0d ² +V0q ² ) is greater than the upper limit value V0lim, the amplitudes of the corrected zero-phase voltages V0d′ and V0q′ are limited to values equal to the upper limit value V0lim, and the phase is set to the zero-phase d-axis voltage V0d. , the zero-phase q-axis voltage V0q does not change.

FIG. 5 shows a block diagram of the current command value calculator 28 of the first embodiment. Corrected zero-phase voltages V0d' and V0q' in FIG. 5 are values obtained from FIG. The positive phase d-axis current command value I1d* corresponds to active power and is zero in the reactive power compensator. However, the steady-state loss of the device may be included due to the cell capacitor voltage balance feedback control. Also in this case, the positive phase d-axis current command value I1d* is approximately zero.

The calculator 18 calculates a corrected zero-phase d-axis voltage V0d', a corrected zero-phase q-axis voltage V0q', a positive phase d-axis voltage V1d, a positive phase q-axis voltage V1q, a negative phase d-axis voltage V2d, and a negative phase q-axis voltage V2q. , the positive-phase q-axis current command value I1q* is input, and the corrected negative-phase current command value (corrected negative-phase d-axis current command value I2d*', corrected negative-phase q-axis current command value I2q*') is obtained by equation (6). Ask for

The dq inverse converter 19 performs dq inverse conversion on the positive phase d-axis current command value I1d* and the positive phase q-axis current command value I1q* based on the phase ωt to convert them into values on fixed coordinates. A multiplier 20 multiplies the phase ωt by -1. The dq inverse converter 21 performs dq inverse transformation on the corrected anti-phase d-axis current command value I2d*' and the corrected anti-phase q-axis current command value I2q*' based on the phase -ωt to convert them into values on fixed coordinates. do. Adders 22a and 22b add the outputs of the dq inverse transformers 19 and 21 together. The outputs of the adders 22a and 22b become the current command values Ia* and Ib* on the fixed coordinates.

The multiplier cos inputs the corrected zero-phase d-axis voltage V0d' and the phase ωt, and outputs the product V0d'cosωt of the cosine value corresponding to the phase ωt and the corrected zero-phase d-axis voltage V0d'. The multiplier sin inputs the corrected zero-phase q-axis voltage V0q' and the phase ωt, and outputs the product V0q'sinωt of the sine value corresponding to the phase ωt and the corrected zero-phase q-axis voltage V0q'. Adder 4 in FIG. 3 adds the products V0d'cos ωt and V0q'sin ωt, and adders 5u, 5v, and 5w in FIG.

It is assumed that the multipliers cos and sin in FIG. 5 and the adder 4 in FIG.

In the first embodiment, when the negative-phase current command value is zero in the unbalanced voltage system (when the negative-phase current command value is not input), the amplitude of the superimposed zero-phase voltage is set to the upper limit in order to maintain the balance of the cell capacitor voltage. It consists of a zero-sequence voltage calculator 27 that limits the value to V0lim and a current command value calculator 28 that obtains the negative-sequence current required to maintain the balance of the cell capacitor voltage when the amplitude-limited zero-sequence voltage is superimposed. Voltages Vu, Vv, and Vw of each phase are defined by equation (3), and currents iu, iv, and iw of each phase are defined by equation (4).

V1d is a positive phase d-axis voltage, and V1q is a positive phase q-axis voltage. If the PLL is enabled and the control system is synchronized with the phase of the system voltage, the positive phase q-axis voltage V1q is zero in steady state. V2d, V2q, V0d', and V0q' are the anti-phase d-axis voltage, anti-phase q-axis voltage, corrected zero-phase d-axis voltage, and corrected zero-phase q-axis voltage, respectively. The same applies to currents, and I1q, I2d, and I2q are positive-phase q-axis current, negative-phase d-axis current, and negative-phase q-axis current, respectively. The active power per cycle of the fundamental wave of each phase is given by the following equation (5). It is assumed that the active power per cycle of the fundamental wave of each phase is the same value.

When the anti-phase d-axis current I2d and the anti-phase q-axis current I2q that satisfy the equation (5) are obtained, the following equation (6) is obtained.

When the corrected zero-phase d-axis voltage V0d' and the corrected zero-phase q-axis voltage V0q' are equal to the zero-phase d-axis voltage V0d and the zero-phase q-axis voltage V0q obtained by the calculator 9, the correction obtained from the equation (6) is The anti-phase d-axis current I2d*' and the corrected anti-phase q-axis current I2q*' become zero.

That is, if the zero-phase d-axis voltage V0d and the zero-phase q-axis voltage V0q are smaller than the upper limit value V0lim, the negative-sequence current output by the MMCC-SSBC becomes zero, and the balance control of the cell capacitor voltage is performed only by the zero-phase voltage. conduct. If the upper limit value V0lim is smaller, the amplitude of the superimposed zero-sequence voltage is limited to the upper limit value V0lim, and then the negative-sequence current obtained by the equation (6) is used together to control the balance of the cell capacitor voltages.

According to the first embodiment, the amplitude of the negative-phase current can be made smaller than when the balance control is performed using only the negative-phase current. In addition, in order to output an appropriate negative-sequence current by feedforward as in Patent Document 1, formulas (2-1), formulas (2-2), and formulas (2-3), the system voltage fluctuates unlike feedback. Even in this case, the unbalance of the cell capacitor voltage can be reduced.

The amplitude of the superimposed zero-phase voltage can be limited by the upper limit value V0lim. The upper limit value V0lim can be a fixed value designed in advance. For example, the system voltage effective value rating (maximum) is V1, the cell capacitor voltage rating (maximum) is Vc, and the number of bridge cells B per phase It can be obtained by the formula (7), where n.

It may be set to a value smaller than the expression (7) with some margin. The upper limit value V0lim may be a variable value, and in addition to being determined by substituting the current system voltage amplitude for V1 in equation (7), the voltage command value sine wave output from the two-phase three-phase converter 3 in FIG. There is also a method of obtaining from the amplitude, and a method of gradually increasing the upper limit value V0lim if the voltage command value amplitude input to the PWM modulator PWM of FIG.

The upper limit value V0lim may be zero. In this case, the balance control of the cell capacitor voltage is performed only with the negative-phase current without superimposing the zero-phase voltage. By setting the upper limit value V0lim to zero, the first embodiment can be applied even when a zero-phase current flows when a zero-phase voltage is superimposed in a three-phase four-wire system. However, a small amount of reverse-sequence current also flows.

In equation (6), the denominator becomes zero when the amplitudes of the positive-sequence voltage and the corrected zero-sequence voltage are equal, and a negative-sequence current suitable for balance control of the cell capacitor voltage cannot be obtained. However, at this time, the MMCC-SSBC shows that it can output a voltage with twice the rated amplitude, and according to paragraph [0049] of Patent Document 1, the MMCC-SSBC outputs a zero-phase voltage even if an arbitrary negative-phase current is output alone. can balance the cell capacitor voltage due to

If the cell capacitor voltage and the number of bridge cells B are sufficiently large, it can be operated without problems if the amplitudes of the positive-phase current and the negative-phase current are not equal according to paragraph [0051] of Patent Document 1. There is no need to apply the first embodiment. On the other hand, costs and losses will increase significantly. Since the first embodiment is intended to be applied to a device designed with a small margin in the cell capacitor voltage and the number of bridge cells B, the denominator in equation (6) never becomes zero.

As described above, according to the first embodiment, the voltage balance of each cell capacitor C can be kept constant by using both the zero-phase voltage and the negative-phase current in the MMCC-SSBC.

The zero-phase voltage is preferentially used, and the negative-phase current is used only when the amplitude √(V0d ² +V0q ² ) of the zero-phase voltage reaches the upper limit value V0lim that can be set externally. can be kept to a limit.

In addition, since the cell capacitor voltage can be balanced even if there is no margin in the voltage amplitude that the MMCC-SSBC can output, the number of bridge cells B can be reduced and the DC voltage of the bridge cells B can be reduced, thereby suppressing costs and losses. can be done.

In addition, because of feedforward control, fluctuations in the cell capacitor voltage are reduced even when the system voltage or current command value changes suddenly, and the capacity of the cell capacitor can be reduced, resulting in miniaturization and cost reduction.

[Embodiment 2]
FIG. 6 shows a block diagram of the zero-phase voltage calculator 27 of the second embodiment. The difference from the first embodiment is that the reverse phase d-axis current command value I2d* and the reverse phase q-axis current command value I2q* can be input from the outside, and the calculator 9 calculates the reverse phase d-axis current command value I2d* and the reverse phase q-axis current command value I2q*. The point is that the equations (2-1), (2-2), and (2-3) described in Patent Document 1 are calculated based on the phase q-axis current command value I2q*.

The multipliers cos, sin and the current command value calculator 28 use FIG. 5 as in the first embodiment.

Next, the operation of the second embodiment will be explained. In the second embodiment, in addition to a positive phase d-axis voltage V1d, a negative phase d-axis voltage V2d, a negative phase q-axis voltage V2q, and a positive phase q-axis current command value I1q*, a negative phase d-axis current command value I2d from outside is applied. *, the negative-phase q-axis current command value I2q* is used to calculate the zero-phase d-axis voltage V0d and the zero-phase q-axis voltage V0q. Also, after limiting the amplitude to the upper limit value V0lim, the corrected anti-phase d-axis current command value I2d*' and the corrected anti-phase q-axis current command value I2q*' are recalculated using equation (6).

If the amplitude √(V0d ² +V0q ² ) of the zero-phase voltage output from the calculator 9 is smaller than the upper limit value V0lim, the corrected anti-phase d-axis current command output from the calculator 18 according to the equation (6) in FIG. The value I2d*' and the corrected anti-phase q-axis current command value I2q*' match the anti-phase d-axis current command value I2d* and the anti-phase q-axis current command value I2q*. A negative-phase current is output according to the value I2d* and the negative-phase q-axis current command value I2q*.

When the zero-phase voltage amplitude √(V0d ² +V0q ² ) is greater than the upper limit value V0lim, the negative-phase d-axis current command value I2d* and the negative-phase q-axis current command value I2q* are adjusted as much as possible within the range of the upper limit value V0lim. A corrected anti-phase d-axis current command value I2d*' and a corrected anti-phase q-axis current command value I2q*', which are close to each other, are output from the calculator .

If the zero-phase voltage amplitude √(V0d ² +V0q ² ) is greater than the upper limit value V0lim, the negative-phase d-axis current command value I2d* and the negative-phase q-axis current command value I2q* are ignored, and the balance of the cell capacitor voltage is maintained. A corrected anti-phase d-axis current command value I2d*' and a corrected anti-phase q-axis current command value I2q*' required for control are calculated and output from the MMCC-SSBC.

From the above, when there is a margin in the voltage amplitude that can be output from the MMCC-SSBC, the negative phase current is output according to the negative phase d-axis current command value I2d* and the negative phase q-axis current command value I2q*. outputs a negative-phase current that is close to the negative-phase d-axis current command value I2d* and the negative-phase q-axis current command value I2q* as much as possible but has a small amplitude. It is possible to realize the operation of ignoring the negative-phase q-axis current command value I2q* and outputting the negative-phase current required for balance control of the cell capacitor voltage.

When formulas (2-1), (2-2), and (2-3) are applied to the computing unit 9 of Embodiment 2, the inputs are the reverse phase d-axis current command value I2d*, the reverse phase q-axis Instead of the current command value I2q*, it is necessary to use the amplitude ratio a' of the negative-sequence current to the positive-sequence current and the phase difference φ of the negative-sequence current to the positive-sequence current. This can be calculated by the following equation (8).

In the second embodiment, when there is a margin in the voltage amplitude that the MMCC-SSBC can output, a negative-phase current equal to the negative-phase d-axis current command value I2d* and the negative-phase q-axis current command value I2q* input from the outside is generated. can be output. Even if the voltage amplitude does not have much margin, it is possible to output a negative-phase current that is as close as possible to the negative-phase d-axis current command value I2d* and the negative-phase q-axis current command value I2q*, although the amplitude is small. When there is almost no voltage amplitude margin, a reversed-phase current different from the reversed-phase d-axis current command value I2d* and the reversed-phase q-axis current command value I2q* is output, but priority is given to the zero-phase voltage as in the first embodiment. Therefore, unintended outflow of negative-sequence current can be minimized.

[Embodiment 3]
FIG. 7 shows a block diagram of the zero-phase voltage calculator 27 of the third embodiment. The following points are different from the second embodiment.

The RMS calculators 23a, 23b, and 23c obtain effective values of the UV line voltage VsUV, the VW line voltage VsVW, and the WU line voltage VsWU of the system voltage detection signal Vs. The comparators 24a, 24b, 24c determine whether or not the outputs of the RMS calculators 23a, 23b, 23c are greater than a preset threshold value Vth.

The AND element 25 outputs 1 when all three effective values of the UV line voltage VsUV, the VW line voltage VsVW, and the WU line voltage VsWU are greater than the threshold value Vth, and outputs 0 otherwise. . The switch 26 outputs the upper limit value V0lim if the output of the AND element 25 is 1, and outputs 0 if the output is 0. The output of the switch 26 is the upper limit value of the zero-phase voltage amplitude in the third embodiment.

Here, the effect of reducing the negative-sequence current amplitude required for cell capacitor voltage balance control by superimposing a zero-sequence voltage whose amplitude is limited will be verified. For simplification, the negative phase current command value from the outside is set to zero, V1d = 1, V1q = 0, I2d = I2q = 0, and the corrected zero phase d-axis voltage V0d' and the corrected zero phase q that satisfy the equation (5) are calculated. Equation (9) is obtained by obtaining the axial voltage V0q'.

Here, the negative-phase d-axis voltage V2d, the negative-phase q-axis voltage V2q, the corrected zero-phase d-axis voltage V0d', and the corrected zero-phase q-axis voltage V0q' are defined as in equation (10).

x is the ratio of the amplitude of the zero-phase voltage that is actually output to the amplitude of the zero-phase voltage that should be output, and corresponds to equation (11).

Substituting V1d=1, V1q=0 and equation (11) into equation (6) yields equation (12) below.

The amplitude ratio of the negative-sequence current obtained by the formula (12) with respect to the positive-sequence current is obtained by the formula (13).

FIG. 8 shows plot results of the equation (13) when x, V2, and .theta. are changed. The horizontal axis is x, where 0 indicates the case where capacitor balance control is performed using only the negative-phase current without using the zero-phase voltage, and 1 indicates the case where an appropriate zero-phase voltage is superimposed. The vertical axis represents the amplitude ratio of the negative-sequence current required for capacitor balance control based on the amplitude of the positive-sequence current output by the MMCC-SSBC.

V2 is the amplitude of the negative-sequence voltage superimposed on the system voltage. θ is the phase of the negative sequence voltage. It can be seen from FIG. 8 that the necessary negative-sequence current amplitude decreases as x increases, that is, as the amplitude of the superimposed zero-sequence voltage increases. Also, it can be seen that the required negative-sequence current amplitude increases as V2 increases, that is, as the voltage imbalance deteriorates.

However, only at θ=0 and V2=1, increasing x does not change the amplitude of the required anti-sequence current at all. Another condition applicable to this state is θ=±2π/3 (120 deg, 240 deg), which corresponds to line-to-line short circuit.

In the third embodiment, reflecting the above verification results, balance control of the capacitor voltage is performed only with the reverse-phase current when a line-to-line short circuit occurs. The effective value of each line voltage is detected and compared with the threshold value Vth, and if the effective value of any one of the three phases is smaller than the threshold value Vth, the upper limit value V0lim of the zero-phase voltage is set to zero. As a result, the balance control of the cell capacitor voltage is performed using only the negative-phase current without using the zero-phase voltage.

According to the third embodiment, ineffective zero-sequence voltage superimposition is not performed when a short circuit occurs between lines. Therefore, overmodulation in which the amplitude of the voltage command value becomes larger than the amplitude of the carrier triangular wave can be avoided, and the voltage/current waveform can be changed. It is possible to reduce the risk of an increase in THD (Total Harmonic Distortion).

From Patent Document 1 and formulas (2-1), (2-2), and (2-3), if the MMCC-SSBC can output a voltage with an amplitude 1.5 times the rated (maximum) voltage, x = 1, and balance control can be performed using only the zero-phase voltage when a line-to-line short circuit occurs. In this case, there is no need to apply the third embodiment. The third embodiment is assumed to be applied when the voltage amplitude that the MMCC-SSBC can output is less than 1.5 times the rated (maximum) voltage.

As described above, the third embodiment has the same effects as those of the first and second embodiments. Further, when a line-to-line short circuit occurs, even if a zero-phase voltage having an amplitude smaller than the optimum amplitude is superimposed, it is not possible to reduce the negative-phase current required for balance control of the cell capacitor voltages. In the third embodiment, since the zero-phase voltage is not superimposed when a line-to-line short circuit occurs, it is possible to reduce the risk of an increase in voltage/current THD due to overmodulation.

Although the present invention has been described in detail only with respect to the specific examples described above, it is obvious to those skilled in the art that various modifications and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are, of course, covered by the claims.

LPF... Low-pass filter 7, 10d, 10q, 17d, 17q, 20, cos, sin... Multiplier 6, 8... dq converter MAVE1, MAVE2, MAVE3, MAVE4... Moving average filter 9, 18... Calculator 11, 22a, 22b... Adder 12... Square root operator 13... Divider 14... Subtractor 15... Comparator 16... Switch 19, 21... dq inverse converter 27... Zero phase voltage calculator 28... Current command value calculator

Claims (4)

A three-phase modular multi-level cascade converter having three modules, wherein a plurality of bridge cell units are connected in series to form a one-phase module,
When the amplitude of the zero-phase voltage required for phase-to-phase balance control of the cell capacitor voltage is equal to or less than the upper limit, the zero-phase voltage is output as a corrected zero-phase voltage, and when the amplitude of the zero-phase voltage is greater than the upper limit a zero-phase voltage calculator that outputs the upper limit value as the corrected zero-phase voltage;
When the zero-sequence voltage is greater than the upper limit value, a current command outputting a current command value superimposed with the corrected zero-sequence voltage and then superimposed with a corrected reverse-sequence current command value necessary for phase-to-phase balance control of the cell capacitor voltage is output. a value calculator;
An output voltage command value for each phase is generated based on the current command value, and a value obtained by adding the corrected zero-phase voltage to the output voltage command value for each phase is compared with a carrier triangular wave corresponding to each bridge cell unit. a current control unit for generating a gate signal for each bridge cell unit by
A modular multi-level cascade converter, comprising: When the output voltage/output current of the modular multilevel cascade converter and the corrected zero-phase voltage to be superimposed are defined by equations (3) and (4),
The zero-phase voltage calculator calculates the zero-phase voltage based on the positive-phase q-axis current command value, the positive-phase d-axis voltage, the negative-phase d-axis voltage, and the negative-phase q-axis voltage. A d-axis voltage and a zero-phase q-axis voltage are calculated, and a corrected zero-phase d-axis voltage and a corrected zero-phase q-axis voltage are calculated based on the zero-phase d-axis voltage and the zero-phase q-axis voltage. and
The current command value calculation unit calculates a corrected negative-phase d-axis current command value and a corrected negative-phase q-axis current command value, which are the corrected negative-phase current command values, based on equation (6). A modular multi-level cascade converter according to claim 1.

Vu, Vv, Vw: U-phase output voltage, V-phase output voltage, W-phase output voltage V1d: Positive phase d-axis voltage V1q: Positive phase q-axis voltage V2d: Negative phase d-axis voltage V2q: Negative phase q-axis Voltage V0d': Corrected zero-phase d-axis voltage V0q': Corrected zero-phase q-axis voltage ωt: System voltage phase iu, iv, iw: U-phase output current, V-phase output current, W-phase output current I1q: Positive-phase q-axis current I2d: Negative-phase d-axis current I2q: Negative-phase q-axis current I1q*: Positive-phase q-axis current command value I2d*': Corrected negative-phase d-axis current command value I2q*': Corrected negative-phase q-axis Current command value When the output voltage/output current of the modular multi-level cascade converter and the corrected zero-phase voltage superimposed are defined by equations (3) and (4),
The zero-phase voltage calculation unit calculates a negative-phase d-axis current command value, a negative-phase q-axis current command value, a positive-phase q-axis current command value, a positive-phase d-axis voltage, and a negative-phase d-axis current command value. A zero-phase d-axis voltage and a zero-phase q-axis voltage, which are the zero-phase voltage, are calculated based on the voltage and the negative-phase q-axis voltage, and based on the zero-phase d-axis voltage and the zero-phase q-axis voltage, outputting a corrected zero-phase d-axis voltage and a corrected zero-phase q-axis voltage, which are the corrected zero-phase voltage ;
The current command value calculation unit calculates a corrected negative-phase d-axis current command value and a corrected negative-phase q-axis current command value, which are the corrected negative-phase current command values, based on equation (6). A modular multi-level cascade converter according to claim 1.

Vu, Vv, Vw: U-phase output voltage, V-phase output voltage, W-phase output voltage V1d: Positive phase d-axis voltage V1q: Positive phase q-axis voltage V2d: Negative phase d-axis voltage V2q: Negative phase q-axis Voltage V0d': Corrected zero-phase d-axis voltage V0q': Corrected zero-phase q-axis voltage ωt: System voltage phase iu, iv, iw: U-phase output current, V-phase output current, W-phase output current I1q: Positive-phase q-axis current I2d: Negative-phase d-axis current I2q: Negative-phase q-axis current I1q*: Positive-phase q-axis current command value I2d*': Corrected negative-phase d-axis current command value I2q*': Corrected negative-phase q-axis Current command value When the voltage amplitude that can be output from the modular multi-level cascade converter is less than 1.5 times the rated voltage amplitude, the zero-phase voltage calculator reduces the upper limit value to zero when a line-to-line short circuit occurs. 4. A modular multi-level cascade converter according to claim 2 or 3, characterized in that:

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