JP7010162B2 - Modular multi-level cascade converter - Google Patents

Description

The present invention relates to a modular multi-level cascade transducer (MMCC) for a single star bridge cell (SSBC) and, in particular, relates to a technique for keeping the capacitor voltage of each cell constant.

Non-Patent Documents 1 and 2 introduce a modular multi-level cascade transducer (MMCC) of a single star bridge cell (SSBC) as a circuit for a transformerless high voltage application. FIG. 10 shows the configuration of MMCC-SSBC.

The feature of this circuit is that each arm is composed of modules 25u, 25v, 25w in which the bridge cell B shown in FIG. 11 is cascaded, and a higher voltage can be handled by increasing the number of cell connections. MMCC-SSBC is expected to be applied as a static power compensator.

FIG. 12 shows a conventional control block configuration for MMCC-SSBC. The control block of FIG. 12 is intended to be applied to the circuit of FIG. N bridge cells B are connected to each phase, and 3n bridge cells B are used in total for three phases.

First, the block 28 that controls the average value of all cell capacitor voltages to the cell capacitor voltage command value will be described. In the adder 1, the U-phase 1st cell capacitor voltage detection value Vcu1 to the U-phase nth cell capacitor voltage detection value Vkun are all added together. Next, in the slower 2, the output of the adder 1 is multiplied by 1 / n to obtain the U-phase cell capacitor voltage average value VcuAVG.

Although omitted in FIG. 12, similarly, the V-phase cell capacitor voltage average value VcvAVG and the W-phase cell capacitor voltage average value VcwAVG are obtained. In the adder 3, the cell capacitor voltage average values VcuAVG, VcvAVG, and VcwAVG of each phase are added together. In the multiplier 4, the output of the adder 3 is multiplied by 1/3 to obtain the average value VcAVG of all cell capacitors.

In the subtractor 5, the deviation between the average value VcAVG of all cell capacitors and the command value VcAVG of cell capacitors is obtained. In the first PI amplifier PI1, the output of the subtractor 5 is amplified. The output of the first PI amplifier PI1 becomes the d-axis current command value Id * of the modular multi-level cascade converter.

Next, the current control unit 29 will be described. This has almost the same configuration as the current control block of a general inverter. The PLL block PLL inputs the system voltage detection value Vs and outputs the system phase θ synchronized with the system voltage.

The output current detection values Iu, Iv, and Iw are input to the dq converter 6 after the switching ripple and noise are removed in the low-pass filter LPF. The dq converter 6 converts the output of the low-pass filter LPF into d-axis and q-axis current detection values on the rotating coordinates synchronized with the system phase θ.

The subtractors 7d and 7q obtain the deviation between the above-mentioned d-axis current command value Id * and any q-axis current command value Iq * and the d-axis and q-axis current detection values. The q-axis current command value Iq * can be freely set, and may also be determined by a command from a higher level or control that keeps the amplitude of the system voltage Vs constant. The second and third PI amplifiers PI2 and PI3 amplify the outputs of the subtractors 7d and 7q and output them as d-axis and q-axis voltage command values.

The dq inverse converter 8 converts the d-axis and q-axis voltage command values on the rotating coordinates synchronized with the phase θ into U-phase output, V-phase output, and W-phase output on the fixed coordinates. Multipliers 9u, 9v, 9w for multiplying the coefficients described later are connected to the output of the dq inverse converter 8.

The outputs of the multipliers 9u, 9v, 9w become voltage command values Vu *, Vv *, Vw *, are converted into a gate signal through comparison with a carrier triangular wave and addition of a dead time, and are converted into a gate signal. It is input to the 1st to 4th semiconductor switches S1 to S4 (IGBT) (not shown).

Finally, the voltage command value correction block 30 will be described. The divider 10 obtains the reciprocal 1 / VcAVG of the average value VcAVG of all cell capacitors. Then, in the multiplier 9u, the reciprocal 1 / VcAVG is multiplied by the U-phase output of the dq inverse converter 8 to obtain the U-phase voltage command value Vu *. Further, in the multiplier 9v, the reciprocal 1 / VcAVG is multiplied by the V-phase output of the dq inverse converter 8 to obtain the V-phase voltage command value Vv *. Further, the reciprocal 1 / VcAVG is multiplied by the W phase output of the dq inverse converter 8 to obtain the W phase voltage command value Vw *.

The block 28 that controls the cell capacitor voltage average value VcAVG to the cell capacitor voltage command value compares the all cell capacitor voltage average value VcAVG with the cell capacitor voltage command value VcAVG *, and amplifies the deviation by the first PI amplifier PI1. The d-axis current command value Id * is used.

If the average value VcAVG of all cell capacitors is excessive with respect to the cell capacitor voltage command value VcAVG *, the d-axis current command value Id * becomes positive, and the modular multi-level cascade converter outputs a positive d-axis current. .. That is, the active power is output and the cell capacitor C is discharged.

If the average value VcAVG of all cell capacitors is insufficient for the cell capacitor voltage command value VcAVG *, the modular multi-level cascade converter inputs active power and charges the cell capacitors.

Next, the current control unit 29 will be described. This has almost the same configuration as the current control unit of a general inverter. The output current detection values Iu, Iv, and Iw are detected, compared with the d-axis and q-axis current command values Id * and Iq * on the rotational coordinates, and the deviation is processed by the PI amplifier to obtain the d-axis and q-axis voltage command values. obtain.

The d-axis and q-axis voltage command values are returned to the fixed coordinates and converted into a gate signal by PWM modulation for comparison with the carrier triangle wave. This gate signal is input to the first to fourth semiconductor switching elements S1 to S4 (IGBT) of each bridge cell B, and the first to fourth semiconductor switching elements S1 to S4 (IGBT) are turned on and off to turn on and off the voltage command value. Outputs the street voltage. As described above, the modular multi-level cascade converter can output a current that substantially matches the d-axis and q-axis current command values Id * and Iq *.

Finally, the voltage command value correction block 30 will be described. The output voltage of the modular multi-level cascade converter depends on the average value VcAVG of all cell capacitors. Even if the voltage command value is the same, if the average value VcAVG of all cell capacitors becomes smaller, the output voltage of the modular multi-level cascade converter also decreases. Therefore, the output of the dq inverse converter 8 is multiplied by the reciprocal 1 / VcAVG of the all-cell capacitor voltage mean value VcAVG, and if the all-cell capacitor voltage mean value VcAVG is small, the voltage command values Vu *, Vv *, Vw * are increased. As a result, the output voltage of the modular multi-level cascade converter does not depend on the average value VcAVG of all cell capacitors, and can always be made equal to the voltage command values Vu *, Vv *, and Vw.

The operation from the U-phase voltage command value Vu * to the generation of the gate signal will be described. Here, as shown in FIG. 13, it is assumed that two (n = 2) bridge cells B are connected to each phase.

FIG. 14 shows a PWM waveform. The phase difference between the carrier triangle wave of cell U1 and cell U2 (hereinafter referred to as U1 carrier and U2 carrier) is set to 90 deg (180 / n). The U-phase voltage command value Vu * and the U1 carrier are compared, and if Vu *> U1 carrier, GU1 = 1, GX1 = 0, and if Vu * <U1 carrier, GU1 = 0, GX1 = 1. A dead time is added to the comparison result, and the gate signal is input to the corresponding first and second semiconductor switching elements S1 and S2 (IGBT) of the cell U1.

Comparing the U-phase voltage command value -Vu * with the inverted sign and the U1 carrier, GV1 = 1, GY1 = 0 if -Vu *> U1 carrier, GV1 = 0, GY1 = 1 if -Vu * <U1 carrier. And. This also adds a dead time and is input to the corresponding third and fourth semiconductor switching elements S3 and S4 as a gate signal.

Similarly, the U-phase voltage command value Vu * (-Vu *) is compared with the U2 carrier to derive GU2, GX2, GV2, GY2, a dead time is added, and the corresponding first to second cells U2 are used as gate signals. Input to the fourth semiconductor switching elements S1 to S4 (IGBT). The final voltage output Vu has the waveform shown at the bottom of FIG. 14 when the capacitor voltage VCU1 of the cell U1 and the capacitor voltage VCU2 of the cell U2 are equal.

FIG. 15 shows the switching pattern of the bridge cell B (cell U1) during the periods (a) to (d) of FIG. The cell capacitor voltage (+ Vc) is output in the period (a), and the output voltages in the periods (b) and (c) are zero. In the period (d), the cell capacitor voltage (-Vc) is output.

The output voltage of one bridge cell B is three levels. In FIG. 13, since the two units are connected in cascade, the number of output voltage levels is 5 as shown in FIG. Even when the number n of bridge cells B per phase is 3 or more, a gate signal is similarly generated by using n types of triangular wave carriers having a phase difference of (180 / n) deg.

Japanese Unexamined Patent Publication No. 2008-278613 Japanese Unexamined Patent Publication No. 2013-240262 Japanese Unexamined Patent Publication No. 2013-21970

Ken Yoshii, Shigenori Inoue, Hirofumi Akagi, "6.6kV Transformerless Cascade PWM_STATCOM", Institute of Electrical Engineers of Japan D, Vol. 127, No. 8, 2007 Shigenori Inoue, Mahaljan Luxman, Atsushi Asakura, Hirofumi Akagi, "6.6kV transformerless power storage system using cascade PWM converter and secondary battery", Institute of Electrical Engineers of Japan D, Vol. 129, No. 1, 2009

However, in the configuration in which the cell modules are connected in cascade, the cell capacitor voltage Vc may be unbalanced due to conditions such as load and variations in the characteristics of the switching element and the cell capacitor.

This imbalance causes the voltage applied to the semiconductor switching element and cell capacitor to become excessive, the voltage and current waveforms output from the inverter to be distorted, the transformer burns out, the power factor improving capacitor overheats and dielectric breakdown, and the electric machine. It causes problems such as groaning and malfunction of the breaker, which adversely affect other devices connected to the same system. Therefore, it is important to keep the cell capacitor voltage uniform by control.

Non-Patent Document 1 discloses a method of outputting an unbalanced current as a method of uniformly controlling the cell capacitor voltage average value of each phase. However, outputting an unnecessary unbalanced current causes disturbance to the system, which is not desirable for the operation of the static VAR compensator. Further, there is a problem that the control effect is lowered as the output unbalanced current is suppressed.

In Non-Patent Document 2, as a method of uniformly controlling the cell capacitor voltage average value of each phase, the output voltage is unbalanced by superimposing the zero-phase voltage, and the unbalanced power is input / output while the current is balanced. The method of making it is disclosed. This method has the advantage that it does not disturb the system. However, the effect of this control is proportional to the magnitude of the unbalanced power, that is, the magnitude of the current. The balance control of the cell capacitor becomes difficult under the condition that almost no current flows through the modular multi-level cascade converter under light load or no load.

Patent Document 1 discloses a control method in which charging of a cell capacitor is promoted and the cell capacitor voltage is made uniform by setting a long dead time of a cell having a low cell capacitor voltage. However, if the dead time is lengthened, there is a problem that the output voltage and current of the modular multi-level cascade converter are easily distorted.

The fourth embodiment of Patent Document 2 discloses a method of controlling the neutral point potential on the assumption that the three-level inverter has an output (or input) of active power even with no load or light load. In Patent Document 2, the neutral point potential can be balanced even under no load or light load. However, Patent Document 2 is a technique relating to neutral point potential control of a three-level inverter. Therefore, it cannot be applied as it is to the MMCC-SSBC of FIG.

Patent Document 3 discloses a control method for reducing the distortion of the output voltage / current even when the balance of the neutral point potential is lost in the three-level rectifier. Further, Patent Document 3 can balance the neutral point potential at the same time. However, Patent Document 3 cannot be directly applied to the MMCC-SSBC of FIG.

From the above, it is a problem in the modular multi-level cascade converter to reduce the distortion of the output voltage and make the average value of the capacitor voltage of each phase uniform.

The present invention has been devised in view of the above-mentioned conventional problems, and one aspect thereof is that a plurality of bridge cells are connected in series to each phase (three phases) between the system and the load, and the bridge cell is A first semiconductor switching element having one end connected to one of the connection terminals, a second semiconductor switching element having one end connected to one end of the first semiconductor switching element, and the other end and the other of the first semiconductor switching element. A third semiconductor switching element connected between the connection terminals of the second semiconductor, a fourth semiconductor switching element connected between the other end of the second semiconductor switching element and the other connection terminal, and the first and first semiconductor switching elements. 3 A modular multi-level cascade converter comprising a cell capacitor connected between a common connection point of a semiconductor switching element and a common connection point of the second and fourth semiconductor switching elements, and all cells. The current control unit that controls the current based on the d-axis current command value and the q-axis current command value according to the deviation between the capacitor voltage average value and the cell capacitor voltage command value, and the U-phase output, V of the current control unit. It is equipped with a first multiplier that multiplies the phase output and W phase output by the inverse of the U-phase, V-phase, and W-phase cell capacitor voltage average values and outputs them as the voltage command values for each phase. It is characterized in that a gate signal of the first to fourth semiconductor switching elements in each of the bridge cells is generated based on the value.

Further, as one aspect thereof, a first dq inverse converter that inputs 1 as the d-axis and 0 as the q-axis and outputs a U-phase sine wave, a V-phase sine wave, and a W-phase sine wave based on the system phase. The U-phase sine wave, V-phase sine wave, and W-phase sine wave are output to the output of the first subtractor that calculates the deviation between the average value of the cell capacitor voltage of all cells and the average value of the cell capacitor voltage of each phase. A second adder that multiplies the waves, a first adder that adds all the outputs of the second adder, and a third that multiplies the output of the first adder by the gain Gp and outputs it as a zero-phase voltage. A multiplier and a second adder that adds the zero-phase voltage to the voltage command value of each phase and outputs the corrected voltage command value are provided, and each of the above is based on the corrected voltage command value. It is characterized by generating a gate signal of the first to fourth semiconductor switching elements in a bridge cell.

As another embodiment, 1 is output when the absolute value of the q-axis current command value is equal to or less than the first threshold value, and 0 is output when the absolute value of the q-axis current command value is larger than the first threshold value. Or, when the absolute value of the q-axis current command value is equal to or less than the first threshold value, 1 is output, and when the absolute value of the q-axis current command value is larger than the first threshold value and smaller than the fourth threshold value. , The absolute value of the q-axis current command value is changed and output so as to decrease from 1 to 0 as the absolute value of the q-axis current command value increases from the first threshold value to the fourth threshold value, and the absolute value of the q-axis current command value is the first. A first table that outputs 0 when 4 thresholds or more, and 1 is output if the q-axis current command value is smaller than the second threshold, and the q-axis current command value is equal to or greater than the second threshold and equal to or less than the third threshold. If, 0 is output, if the q-axis current command value is larger than the third threshold value, -1 is output, or if the q-axis current command value is equal to or less than the fifth threshold value, 1 is output and the q is output. When the axis current command value is larger than the fifth threshold value and smaller than the second threshold value, the q-axis current command value changes from 1 to 0 as the fifth threshold value increases to the second threshold value. If the q-axis current command value is equal to or greater than the second threshold and equal to or less than the third threshold, 0 is output, and the q-axis current command value is larger than the third threshold and smaller than the sixth threshold. Case: When the q-axis current command value changes from 0 to -1 as it increases from the third threshold value to the sixth threshold value and is output, and when the q-axis current command value is equal to or higher than the sixth threshold value. Input the output of the first table as the d-axis and the output of the second table as the q-axis, and input the output of the second table as the q-axis. The first dq inverse converter that outputs a W-phase sine wave, the first subtractor that calculates the deviation between the average value of the cell capacitor voltage of all cells and the average value of the cell capacitor voltage of each phase, and the output of the first subtractor A second multiplier that multiplies a U-phase sine wave, a V-phase sine wave, and a W-phase sine wave, a first adder that adds all the outputs of the second multiplier, and a gain on the output of the first adder. It includes a third multiplier that multiplies Gp and outputs it as a zero-phase voltage, and a second adder that adds the zero-phase voltage to the voltage command value of each phase and outputs it as a corrected voltage command value. It is characterized in that the gate signal of the first to fourth semiconductor switching elements in each of the bridge cells is generated based on the corrected voltage command value.

Further, as one aspect thereof, a second subtractor for calculating the deviation between the cell capacitor voltage average value of each phase and the cell capacitor voltage detection value, and the U phase obtained by multiplying the output of the second subtractor by the gain Gi. A fourth multiplier that multiplies a sine wave, a V-phase sine wave, and a W-phase sine wave, respectively, and the output of the fourth multiplier are added to the corrected voltage command value, respectively, and output as the voltage command value of each cell. A third adder is provided, and the gate signal of the first to fourth semiconductor switching elements in each bridge cell is generated based on the voltage command value of each cell.

According to the present invention, in a modular multi-level cascade converter, it is possible to reduce the distortion of the output voltage and make the average value of the capacitor voltage of each phase uniform.

The block diagram which shows the control part of the modular multi-level cascade converter in Embodiment 1. FIG. The block diagram which shows the control part of the modular multi-level cascade converter in Embodiment 2. The phaser figure which shows the system voltage, the output current, the zero-phase voltage, and the voltage command value in Embodiment 2. A block diagram showing the control unit of a conventional modular multi-level cascade converter. The block diagram which shows the control part of the modular multi-level cascade converter in Embodiment 3. FIG. The block diagram which shows an example of the control part of the modular multi-level cascade converter in Embodiment 4. FIG. The block diagram which shows the other example of the control part of the modular multi-level cascade converter in Embodiment 4. The figure which shows each waveform of the PWM operation in Embodiment 4. Schematic diagram showing the configuration of a modular multi-level cascade transducer under experimental conditions. The schematic which shows an example of the structure of MMCC-SSBC. The schematic which shows the structure of a bridge cell. A block diagram showing the control unit of a conventional modular multi-level cascade converter. The schematic diagram which shows the structure which connected two bridge cells in cascade. The figure which shows each waveform of the PWM operation by two bridge cells. The schematic which shows the switching pattern of a bridge cell.

Hereinafter, embodiments 1 to 4 of the modular multi-level cascade converter in the present invention will be described in detail with reference to FIGS. 1 to 11.

In the following embodiments 1 to 4, a slight loss occurs due to conduction loss and switching loss in the bridge cell B, leakage current of the cell capacitor, securing of the power supply for driving the IGBT, and the like. It is assumed that the multi-level cascade converter always inputs a small amount of active power from the grid.

[Embodiment 1]
The present embodiment 1 shown below is assumed to be applied to the circuit of FIG. In FIG. 10, n bridge cells B are connected to each phase (three phases) between the system 26 and the load 27. In total of three phases, 3n bridge cells B are connected.

As shown in FIG. 11, in the bridge cell B, one end of the first semiconductor switching element S1 is connected to one of the connection terminals. One end of the second semiconductor switching element S2 is connected to one end of the first semiconductor switching element S1. The third semiconductor switching element S3 is connected between the other end of the first semiconductor switching element S1 and the other connection terminal. The fourth semiconductor switching element S4 is connected between the other end of the second semiconductor switching element S2 and the other connection terminal. The cell capacitor C is connected between the common connection point of the first and third semiconductor switching elements S1 and S3 and the common connection point of the second and fourth semiconductor switching elements S2 and S4.

FIG. 1 shows the control block of the first embodiment. FIG. 1 is different from FIG. 12, which has a conventional configuration, in the voltage command value correction block 30. The same parts as those in FIG. 12 are designated by the same reference numerals, and the description thereof will be omitted.

The dividers 10u, 10v, and 10w obtain the reciprocals 1 / VcuAVG, 1 / VcvAVG, and 1 / VcwAVG of the cell capacitor voltage average values VcuAVG, VcvAVG, and VcwAVG of each phase. The first multiplier 9u multiplies the reciprocal 1 / VcuAVG and the U-phase output of the dq inverse converter 8 to obtain the U-phase voltage command value Vu *. The first multiplier 9v multiplies the reciprocal 1 / VcvAVG by the V-phase output of the dq inverse converter 8 to obtain the V-phase voltage command value Vv *. The first multiplier 9w multiplies the reciprocal 1 / VcwAVG and the W phase output of the dq inverse converter 8 to obtain the W phase voltage command value Vw *.

In the conventional method, the average value VcAVG of all cell capacitors is used for the correction. Therefore, the average value VcAVG of all cell capacitors is as instructed, but the average cell capacitor voltage of each phase cell module 25u, 25v, 25w (for example, when the number of cells in each phase is 2), the average cell capacitor voltage of U phase. If the value ((Vcu1 + Vcu2) / 2) deviates from the cell capacitor voltage command value VcAVG *, it cannot be handled, the amplitude of each phase cell module output voltage deviates from the voltage command value, and an unbalanced current is output. There was a problem that caused a disturbance. However, in the first embodiment, since the cell modules 25u, 25v, 25w of each phase are individually corrected, the cell modules 25u, 25v, 25w can output the voltage according to the voltage command value even in the above case.

Further, unlike the average value VcAVG of all cell capacitors, each phase cell capacitor voltage pulsates at a frequency twice the system voltage due to the input / output of electric power. Therefore, by performing this correction, the output voltage / current is not affected by the pulsation of the cell capacitor voltage, and an output voltage / current waveform with small distortion can be obtained.

Under the condition that the voltage command value V * is positive, the three switching patterns (a), (b), and (c) shown in FIG. 15 appear. Here, since it is assumed that the active power is input from the system 26, the current path is as shown in FIG. In FIG. 15A, the cell capacitor C is charged.

Here, when the above correction is performed for a cell module in which the cell capacitor voltage average values VcuAVG, VcvAVG, and VcwAVG of each phase are smaller than the all-cell capacitor voltage average value VcAVG, the voltage command values (Vu *, Vv) of the corresponding phases are applied. Since either * or Vw *) increases, the switching pattern of FIG. 15A appears for a long time, and charging of the cell capacitor C is promoted.

When the above correction is performed for a cell module in which the average cell capacitor voltage values VcuAVG, VcvAVG, and VcwAVG of each phase are larger than the average cell capacitor voltage VcAVG, the frequency of occurrence of the patterns (b) and (c) in FIG. Will increase and the cell capacitor will not be charged. Therefore, by performing the above correction, not only the strain can be reduced, but also the cell capacitor voltage average values VcuAVG, VcvAVG, and VcwAVG of each phase can be uniformly aligned.

As shown above, according to the first embodiment, the average cell capacitor voltage VcAVG matches the cell capacitor voltage command value VcAVG *, but deviates from the average cell capacitor VcuAVG, VcvAVG, and VcwAVG of each phase. When this occurs, the distortion of the output voltage and current can be reduced.

In principle, the average cell capacitor values VcuAVG, VcvAVG, and VcwAVG of each phase generate pulsations twice the system frequency, but the output voltage and current are not affected by these pulsations, and the strain can be further reduced. ..

Further, the cell capacitor voltage average values VcuAVG, VcvAVG, and VcwAVG of each phase can be uniformly aligned. In particular, it is possible to make the cell capacitor voltage average values VcuAVG, VcvAVG, and VcwAVG of each phase uniform in the no-load / light load, which is very difficult with the conventional control.

[Embodiment 2]
FIG. 2 shows the control block of the second embodiment. The dq inverse converter 11 inputs fixed values 1 and 0 as the d-axis and the q-axis, respectively. The dq inverse converter 11 inputs the system phase θ and outputs a U-phase sine wave, a V-phase sine wave, and a W-phase sine wave synchronized with the system phase voltage.

The low-pass filter LPF removes pulsations at twice the frequency of the system superimposed in principle from the cell capacitor voltage mean values VcuAVG, VcvAVG, VcwAVG, and all cell capacitor voltage mean values VcAVG of each phase. No pulsation is superimposed on the average value VcAVG of all cell capacitors, but LPF processing is performed to match the delay.

The first subtractors 12u, 12v, 12w obtain the deviation between the average cell capacitor voltage VcAVG after pulsation removal and the average cell capacitor voltage VcuAVG, VcvAVG, VcwAVG of each phase.

The second multiplier 13u multiplies the output of the first U-phase subtractor 12u with the U-phase sine wave. The second multiplier 13v multiplies the output of the V-phase first subtractor 12v with the V-phase sine wave. The second multiplier 13w multiplies the output of the first subtractor 12w of the W phase with the W phase sine wave. The first adder 14 adds all the outputs of the second multipliers 13u, 13v, 13w.

The third multiplier 15 multiplies the output of the first adder 14 by the gain Gp. The output of the third multiplier 15 becomes the zero-phase voltage Vcp *. The second adders 16u, 16v, 16w add the voltage command values Vu *, Vv *, Vw * and the zero-phase voltage Vcp * of the first embodiment, respectively, and correct the voltage command values Vu *', Vv *'. , Vw *'is output. The corrected voltage command values Vu *', Vv *', and Vw *'are converted into a gate signal after comparison with a carrier triangular wave and addition of a dead time, and the first to first bridge cells B in FIGS. 10 and 11 are converted into a gate signal. 4 Inputs to the semiconductor switching elements S1 to S4 (IGBT) (not shown).

In the second embodiment, a control function for adjusting the cell capacitor voltage average values VcuAVG, VcvAVG, and VcwAVG of each phase to the cell capacitor voltage average values VcAVG of each phase is added to the first embodiment.

First, the dq inverse converter 11 generates a U-phase sine wave, a V-phase sine wave, and a W-phase sine wave synchronized with the system phase voltage. Since the modular multi-level cascade converter inputs a small amount of active power from the system 26, the U-phase sine wave, V-phase sine wave, and W-phase sine wave are the input currents of the modular multi-level cascade converter. It is in phase with respect to the active power component.

Next, the deviation between the cell capacitor voltage average value VcuAVG, VcvAVG, VcwAVG of each phase and the cell capacitor voltage average value VcAVG of each phase is obtained, and the U-phase sine wave, V-phase sine wave, and W-phase sine wave of each phase are used as the deviations. Multiply. The zero-phase voltage Vcp * is obtained by adding all of these and applying the gain Gp.

FIG. 3 shows an example of the zero-phase voltage Vcp *. In this example, it is assumed that VcuAVG <VcAVG <VcvAVG = VcwAVG. FIG. 3A is a phaser diagram of the system voltage, FIG. 3B is a phaser diagram of the output current, FIG. 3C is a phaser diagram of the zero-phase voltage Vcp *, and FIG. 3D is a phaser of the voltage command value. The figure is shown.

Since the modular multi-level cascade converter assumes that the active power is input from the grid, FIGS. 3 (a) and 3 (b) are in opposite directions. For the U phase, the deviation VcAVG-VcuAVG is positive, and the U phase sine wave has the same phase as the system phase voltage Vu. With respect to the V phase and the W phase, the deviations VcAVG-VcvAVG and VcAVG-VcwAVG are negative, and the sine waves are in the opposite directions to the system phase voltages Vv and Vw (the phase difference is 180 °).

When all of these are added together, the zero-phase voltage Vcp * shown in FIG. 3C is obtained. The phaser diagram of the corrected voltage command values Vu *', Vv *', and Vw *', which is the sum of the zero-phase voltage Vcp * and the voltage command values Vu *, Vv *, and Vw *, is shown in FIG. 3 (d). Looking at the U-phase voltage, the amplitude increases, which increases the inflowing active power and promotes charging of the cell capacitor. As for the V-phase and W-phase voltages, since the amplitudes of the components having the same phase as Iv and Iw are reduced, the inflowing active power is reduced and the charging of the cell capacitor is suppressed.

As described above, the cell capacitor voltage average values VcuAVG, VcvAVG, and VcwAVG of each phase can be uniformly aligned. Further, since the line voltage in FIG. 3 (d) is equal to the line voltage Vu-Vv, Vv-Vw, Vw-Vu in FIG. 3 (a), the system voltage may be disturbed or an unnecessary current may be generated. There is nothing to do.

This control method itself is known from FIG. 6 of Non-Patent Document 2. However, in FIG. 6 of Non-Patent Document 2, since the calculation of tan-1 and the square root is used, there is a problem that the calculation load is high.

When FIG. 6 of Non-Patent Document 2 is realized only by a simple calculation, the configuration of FIG. 4 is obtained. In the multiplier 17, the q-axis current command value Iq * is multiplied by -1 to invert the sign (changed to the input current). The code detector 18 detects and outputs the code of the output of the multiplier 17. That is, if Iq *> 0, -1 is input, and if Iq * <0, 1 is input to the q-axis input terminal of the dq inverse converter 11. However, with no load, Iq * = 0, and the phase of the sine wave to be superimposed cannot be determined. Therefore, the control is stopped.

In the second embodiment, it is assumed that there is a small amount of active power input under all conditions including the case where the input current is zero, and a sine wave synchronized with the active power component of the input current is superimposed. Therefore, the cell capacitor voltage can be controlled even when there is no load.

Under the condition that the modular multi-level cascade converter outputs a large amount of reactive power, the control effect is lower than that of Non-Patent Document 2. However, when dealing with a large amount of reactive power, the conduction loss and switching loss of the semiconductor switching element increase, and the active power input to the modular multi-level cascade converter also increases, so a sufficient cell capacitor voltage control effect can be obtained. be able to.

Further, since the phase of the superposed sine wave may be fixed, the control block configuration can be simplified.

In the second embodiment, by further correcting the voltage command value with respect to the first embodiment, it is possible to balance the cell capacitor voltage average values VcuAVG, VcvAVG, and VcwAVG of each phase as compared with the first embodiment. Even if the variation in the characteristics of the bridge cell B (capacitor capacity, leakage current, etc.) is large and the deviation remains or increases in the first embodiment alone, the deviation can be reduced in the second embodiment.

In the first embodiment, when V *> 0, the frequency of occurrence of the patterns of FIGS. 15 (b) and 15 (c) is increased for a cell module in which the cell capacitor voltage average values VcuAVG, VcvAVG, and VcwAVG of each phase are large. rice field. However, in the second embodiment, since the voltage command value V * can be largely adjusted, the pattern shown in FIG. 15 (d) can be generated even under the condition of V *> 0, and the cell capacitor can be discharged. Therefore, the second embodiment is more effective than the first embodiment.

In the second embodiment, the effect of equalizing the cell capacitor voltage average values VcuAVG, VcvAVG, and VcwAVG of each phase of the first embodiment can be enhanced and the deviation can be reduced. Further, even when the characteristics of the first to fourth semiconductor switching elements S1 to S4 of the bridge cell B and the cell capacitor C have large variations, stable operation can be continued.

[Embodiment 3]
FIG. 5 shows the control block of the third embodiment. In the third embodiment, the input of the dq inverse converter 11 is changed with respect to the second embodiment.

The first table 19 outputs 1 when the absolute value of the q-axis current command value Iq * is equal to or less than the first threshold value, and outputs 0 when the absolute value of the q-axis current command value Iq * is larger than the first threshold value. do. The second table 20 outputs 1 if the q-axis current command value Iq * is smaller than the second threshold value, 0 if it is equal to or greater than the second threshold value and equal to or less than the third threshold value, and -1 if it is larger than the third threshold value. Further, the second threshold value is a value obtained by changing the sign (polarity) of the first threshold value.

The outputs of the first and second tables 19 and 20 may be gradually switched instead of being switched by 0, 1 (or -1). For example, the first table 19 outputs 1 when the absolute value of the q-axis current command value Iq * is equal to or less than the first threshold value, and the absolute value of the q-axis current command value Iq * is larger than the first threshold value. When it is smaller than the threshold value, the absolute value of the q-axis current command value Iq * changes from 1 to 0 as the absolute value increases from the first threshold value to the fourth threshold value and is output, and the q-axis current command value Iq * is output. If the absolute value is equal to or greater than the fourth threshold value, 0 is output.

The second table 20 outputs 1 when the q-axis current command value Iq * is equal to or less than the fifth threshold value, and the q-axis current when the q-axis current command value Iq * is larger than the fifth threshold value and smaller than the second threshold value. As the command value Iq * increases from the 5th threshold value to the 2nd threshold value, the output changes so as to decrease from 1 to 0. Is output, and when the q-axis current command value Iq * is larger than the third threshold value and smaller than the sixth threshold value, the q-axis current command value Iq * decreases from 0 to -1 as the third threshold value increases to the sixth threshold value. When the q-axis current command value Iq * is equal to or greater than the sixth threshold value, -1 is output. Further, the fifth threshold value is a value obtained by changing the sign (polarity) of the fourth threshold value.

The third embodiment will be described. When the load 27 connected to the system 26 is unloaded or lightly loaded, the reactive power output by the modular multi-level cascade converter is very small, so Iq * ≈0. Therefore, if the q-axis current command value Iq * is near zero, the operation is exactly the same as in the second embodiment.

On the other hand, when the absolute value of the q-axis current command value Iq * is large to some extent, a sine wave (in phase with the input current) in the opposite direction to the q-axis current command value Iq * is superimposed and the cell capacitor voltage average value is constant. Take control. This is the operation of Non-Patent Document 2.

The third embodiment can obtain the same effect of constant control of the cell capacitor voltage average value as that of the second embodiment under no load and the same as that of the non-patent document 2 under the condition of outputting a large reactive power.

As shown above, according to the third embodiment, the same effect of equalizing the cell capacitor voltage average value as that of the conventional method (Non-Patent Document 2) can be obtained even under the condition that a large current is input / output in addition to the second embodiment. be able to.

[Embodiment 4]
FIG. 6 shows the U-phase control block of the fourth embodiment. The control blocks for the V phase and the W phase are the same as in FIG. In the fourth embodiment, the following blocks are added to the second embodiment.

The dq inverse converter 11 is shared with the dq inverse converter 11 for obtaining the zero-phase voltage Vcp * of the second embodiment. Further, the input to the dq inverse converter 11 is the same as that in the second embodiment. The phase θ input to the dq inverse converter 11 is a phase synchronized with the U-phase system voltage. The multiplier 21 multiplies the U-phase sine wave output by the dq inverse converter 11 by the gain Gi.

The low-pass filter LPF is based on the U-phase 1st cell capacitor voltage detection value Vcu1 to U-phase n-cell capacitor voltage detection value Vkun and the U-phase cell capacitor voltage average value VcuAVG. To remove.

The second subtractors 22a to 22n obtain deviations between the U-phase first cell capacitor voltage detection value Vcu1 to U-phase n-cell capacitor voltage detection value Vkun and the U-phase cell capacitor voltage average value VcuAVG after pulsation removal, respectively. .. The fourth multipliers 23a to 23n obtain the product of the U-phase sine wave multiplied by the gain Gi and the outputs of the second subtractors 22a to 22n.

The second adders 24a to 24n add the corrected U-phase voltage command value Vu *'= Vu * + Vcp * obtained in the second embodiment and the outputs of the fourth multipliers 23a to 23n, and the corresponding bridge cell B It is output as the voltage command value Vu1 * to Vun * of. The voltage command values Vu1 * to Vun * of the corresponding bridge cell B are converted into a gate signal after comparison with the carrier triangular wave and addition of dead time, and the first to fourth semiconductor switching elements of the corresponding bridge cell B in FIG. 10 are used. It is input to S1 to S4 (IGBT) (not shown).

The fourth embodiment can also be combined with the third embodiment. The control block at that time is shown in FIG. The control blocks for the V phase and the W phase are the same as in FIG. 7. In the case of the V-phase and W-phase control blocks, the sine wave used for control (input to the multiplier 21) is the V-phase and W-phase sine wave output by the dq inverse converter 11.

In the first to third embodiments, the average cell capacitor voltages VcuAVG, VcvAVG, and VcwAVG of each phase can be uniformly controlled, but the individual cell capacitor voltages cannot be made uniform. In the fourth embodiment, an individual cell capacitor voltage control function is added to the second and third embodiments. The operating principle is the same as in the previous embodiments.

Assuming that a small amount of active power is input to the cell from the system 26 to compensate for the loss, for a cell with a low capacitor voltage, it is in phase with the system phase voltage (same as the active power component of the input current). The sine wave of phase) is added to increase the input active power and promote the charging of the cell capacitor.

For a cell with a high capacitor voltage, a sine wave having the same phase as the grid phase voltage (in phase with the active power component of the input current) is subtracted to reduce the input active power and suppress the charging of the cell capacitor. Alternatively, the active power is output and the cell capacitor is discharged.

When combined with the third embodiment, a sine wave having the same phase as the input current is added or subtracted under the condition of outputting a large reactive power.

By the above operation, it is possible to make the individual cell capacitor voltages constant even at the time of no load and light load, which was impossible by the conventional control.

As shown above, according to the fourth embodiment, the individual cell capacitor voltages can be uniformly aligned. In particular, it is possible to equalize the cell capacitor voltage under no load and light load, which was very difficult with conventional control.

FIG. 8 shows the PWM waveform of the fourth embodiment. In FIG. 8, as shown in FIG. 13, it is assumed that two (n = 2) bridge cells B are connected to each phase and Vcu1 <Vcu2. The phase difference between the carrier triangle wave of the cell U1 and the cell U2 is 90 deg (180 / n) as in FIG.

Since the capacitor voltage of the cell U1 is low, a sine wave having the same phase as the system phase voltage is added to the voltage command value Vu * to obtain Vu1 *. On the contrary, since the capacitor voltage of the cell U2 is high, the sine wave is subtracted to obtain Vu2 *. Therefore, the amplitude is Vu1 *> Vu2 *.

In the cell U1, the voltage command values Vu1 * and −Vu1 * are compared with the U1 carrier, and GU1, GX1, GV1, GY1 are obtained. A dead time is added to the GU1, GX1, GV1, and GY1, and they are input as gate signals to the first to fourth semiconductor switching elements S1 to S4 (IGBT) of the cell U1. In cell U2, Vu2 * and −Vu2 * are compared with U2 carriers to obtain GU2, GX2, GV2, GY2. A dead time is added to the GU2, GX2, GV2, and GY2, and the gate signal is input to the first to fourth semiconductor switching elements S1 to S4 (IGBT) of the cell GU2. The final voltage output Vu has the waveform shown at the bottom of FIG.

The effects of the above embodiments 1 to 4 were confirmed by experiments. The experimental conditions are shown in FIG. No load is connected to the system 26. The system voltage is 415 V, the system frequency is 50 Hz, and the converter capacity is 15 kVA. The number of bridge cells B per phase of the modular multi-level cascade converter is four, for a total of twelve.

As a leakage current disturbance applied to the cell capacitor voltage, in (a), a 150 kΩ resistor is connected in parallel to the cell capacitors 1 to 4 of the V phase and W phase, and the cells 1 to 4 of the U phase increase the leakage current. A 15 kΩ resistor was connected in parallel with the cell capacitor to disperse the cell capacitor voltage.

In (b), a resistance of 15 kΩ was connected only to the U-phase cell 1, and a resistance of 150 kΩ was connected to the other cells. Under the above conditions, the capacitor voltages of the U-phase cell 1 and the V-phase cell 1 were measured, and the difference was confirmed. (C) shows the configuration of the bridge cell B. The capacitor capacity was set to 5,600 μF, and the command value of the cell capacitor voltage was set to 91.625 V.

Table 1 shows the results when (a) interphase balance disturbance of FIG. 9 is applied. When the modular multi-level cascade converter was stopped, the U-phase capacitor voltage continued to be discharged, and the capacitor voltage difference between the U-phase cell 1 and the V-phase cell 1 reached 140V. However, if the first embodiment is applied, the voltage difference can be suppressed to 2.1V at Iq * = 0 only by operating the modular multi-level cascade converter.

If the third embodiment is also applied, the voltage difference of 0.1 V can be further reduced. Further, if the output current of the modular multi-level cascade converter is increased by increasing | Iq * |, the voltage difference can be further reduced.

Table 2 shows the results when (b) individual balance disturbance of FIG. 9 is applied. In the state where the modular multi-level cascade converter was stopped, the U-phase cell 1 capacitor voltage continued to be discharged as in the case where the disturbance was applied. In (b) individual balance disturbance of FIG. 9, although the expansion of the voltage difference was suppressed in the case of the first embodiment alone with no load, the difference reached 5.1 V. By applying the third and fourth embodiments, the voltage difference could be reduced to 3.5V. Even in the case of (b) individual balance disturbance in FIG. 9, the voltage difference could be made smaller by increasing the output current of the modular multi-level cascade converter.

Although the above description has been made in detail only for the specific examples described in the present invention, it is obvious to those skilled in the art that various modifications and modifications are possible within the scope of the technical idea of the present invention. It goes without saying that such modifications and modifications fall within the scope of the claims.

1 ... adder 2 ... adder 3 ... adder 4 ... multiplier 5 ... subtractor 6 ... dq converter 7d, 7q ... subtractor 8 ... dq inverse converter 9u, 9v, 9w ... first multiplier 10u, 10v , 10w ... Adder 26 ... System 27 ... Load B ... Bridge cell

Claims (4)

Multiple bridge cells are connected in series to each phase (3 phases) between the grid and the load.
The bridge cell is
A first semiconductor switching element with one end connected to one of the connection terminals,
A second semiconductor switching element having one end connected to one end of the first semiconductor switching element,
A third semiconductor switching element connected between the other end of the first semiconductor switching element and the other connection terminal,
A fourth semiconductor switching element connected between the other end of the second semiconductor switching element and the other connection terminal,
A modular multi-level cascade converter comprising a cell capacitor connected between a common connection point of the first and third semiconductor switching elements and a common connection point of the second and fourth semiconductor switching elements. There,
A current control unit that controls current based on the d-axis current command value and the q-axis current command value according to the deviation between the average value of all cell capacitor voltages and the cell capacitor voltage command value.
A first multiplier that multiplies the U-phase output, V-phase output, and W-phase output of the current control unit by the reciprocal of the U-phase, V-phase, and W-phase cell capacitor voltage average values, and outputs them as voltage command values for each phase. When,
A modular multi-level cascade converter comprising: A first dq inverse converter that inputs 1 as the d-axis and 0 as the q-axis and outputs a U-phase sine wave, a V-phase sine wave, and a W-phase sine wave based on the system phase.
The first subtractor that calculates the deviation between the average value of the cell capacitor voltage of all cells and the average value of the cell capacitor voltage of each phase, respectively.
A second multiplier that multiplies the output of the first subtractor by the U-phase sine wave, V-phase sine wave, and W-phase sine wave, respectively.
The first adder, which adds all the outputs of the second multiplier, and
A third multiplier that multiplies the output of the first adder by the gain Gp and outputs it as a zero-phase voltage.
A second adder that adds the zero-phase voltage to the voltage command value of each phase and outputs it as a corrected voltage command value.
The modular multi-level cascade according to claim 1, wherein the gate signal of the first to fourth semiconductor switching elements in each of the bridge cells is generated based on the corrected voltage command value. converter. When the absolute value of the q-axis current command value is equal to or less than the first threshold value, 1 is output, and when the absolute value of the q-axis current command value is larger than the first threshold value, 0 is output, or the q-axis current is output. When the absolute value of the command value is equal to or less than the first threshold value, 1 is output, and when the absolute value of the q-axis current command value is larger than the first threshold value and smaller than the fourth threshold value, the q-axis current command value is obtained. The absolute value of is changed from 1 to 0 as the absolute value increases from the first threshold to the fourth threshold and is output. When the absolute value of the q-axis current command value is equal to or higher than the fourth threshold, it is 0. The first table that outputs
If the q-axis current command value is smaller than the second threshold value, 1 is output, and if the q-axis current command value is equal to or greater than the second threshold value and equal to or less than the third threshold value, 0 is output. If it is larger than the third threshold value, -1 is output, or if the q-axis current command value is equal to or less than the fifth threshold value, 1 is output, and the q-axis current command value is larger than the fifth threshold value. When it is smaller than the threshold value, the q-axis current command value is changed and output so as to decrease from 1 to 0 as the q-axis current command value increases from the fifth threshold value to the second threshold value, and the q-axis current command value is the second. If it is equal to or greater than the threshold value and equal to or less than the third threshold value, 0 is output. A second table that changes and outputs from 0 to -1 as it increases to 6 thresholds and outputs -1 when the q-axis current command value is equal to or higher than the 6th threshold.
The output of the first table is input as the d-axis, the output of the second table is input as the q-axis, and the U-phase sine wave, the V-phase sine wave, and the W-phase sine wave are output based on the system phase. With a converter,
The first subtractor that calculates the deviation between the average value of the cell capacitor voltage of all cells and the average value of the cell capacitor voltage of each phase,
A second multiplier that multiplies the output of the first subtractor by the U-phase sine wave, V-phase sine wave, and W-phase sine wave, respectively.
The first adder, which adds all the outputs of the second multiplier, and
A third multiplier that multiplies the output of the first adder by the gain Gp and outputs it as a zero-phase voltage.
A second adder that adds the zero-phase voltage to the voltage command value of each phase and outputs it as a corrected voltage command value.
The modular multi-level cascade according to claim 1, wherein the gate signal of the first to fourth semiconductor switching elements in each of the bridge cells is generated based on the corrected voltage command value. converter. A second subtractor that calculates the deviation between the average cell capacitor voltage of each phase and the detected cell capacitor voltage,
A fourth multiplier that multiplies the output of the second subtractor by the gain Gi, and then multiplies the U-phase sine wave, V-phase sine wave, and W-phase sine wave, respectively.
A third adder that adds the output of the fourth multiplier to the corrected voltage command value and outputs it as the voltage command value of each cell.
The modular multi-level according to claim 2 or 3, wherein the gate signal of the first to fourth semiconductor switching elements in each bridge cell is generated based on the voltage command value of each cell. -Cascade converter.

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