JP2021111987A - Power conversion apparatus - Google Patents

Abstract

To provide a power conversion apparatus capable of stably continuing operation even though a power system fails, and a system voltage results in three-phase unbalancing.SOLUTION: A power conversion apparatus 1 comprises a U-phase leg 31U, a V-phase leg 31V and a W-phase leg 31W; a lower side neutral point 32n where end portions of lower arms provided to the U-phase leg 31U, the V-phase leg 31V and the W-phase leg 31W, respectively, are connected to each other; an upper side neutral point 32p where end portions of upper arms provided to the U-phase leg 31U, the V-phase leg 31V and the W-phase leg 31W, respectively, are connected to each other; and a control device 5 for controlling the U-phase leg 31U, the V-phase leg 31V and the W-phase leg 31W. The control device 5 comprises an inter-leg power equilibration control part 5a for controlling a first zero-phase power by adjusting the same voltage component included in each of a zero-phase power VZn of the lower side neutral point 32n, and another zero-phase power VZp of the upper side neutral point 32p.SELECTED DRAWING: Figure 1

Description

The present invention relates to a power conversion device that supplies at least one of active power and ineffective power.

In order to maintain the quality of the power system, a power conversion device that compensates for the ineffective power is in operation. It is desired to increase the capacity of such a power conversion device. A modular multi-level cascade converter is being put into practical use as a power conversion method that can realize a large capacity while reducing the size by using a self-extinguishing semiconductor switch element (for example, a patent). Documents 1 and 2 and Non-Patent Documents 1 and 2).

Japanese Unexamined Patent Publication No. 2012-44839 JP-A-2017-143626

H. Akagi (H. Akagi), "(Multilevel Vehicles: Fundamental Circuits and Systems)", (USA), Journal of the Institute of Electrical and Electronics Engineers of the United States (Proceedings of the IEEE), pp2048-2065, Volume: 105. 2017 T. Tanaka (T. Tanaka), "(Asymmetrical Reactive Power Power Capability of Modular Multilevel Cascade Controller (MMCC) Based STATCOM E. 5164, Volume: 34, Number: 6, June. 2019

An object of the present invention is to provide a power conversion device capable of stably continuing operation even if a power system fails and the system voltage falls into a three-phase imbalance.

In order to achieve the above object, the power conversion device according to one aspect of the present invention includes a plurality of legs each having a first arm and a second arm connected in series, and the first leg provided on each of the plurality of legs. Of the first connecting portion in which the ends of both ends of one arm that are not connected to the second arm are connected to each other, and the both ends of the second arm provided in each of the plurality of legs. A second connection portion in which ends not connected to the first arm are connected to each other and a control device for controlling the plurality of legs are provided, and the first arm is two semiconductor switches connected in series. The second arm has a first power conversion circuit cell having a power storage element connected in parallel to the two semiconductor switches, and a first coil connected in series with the first power conversion circuit cell. , A second power conversion circuit cell having two semiconductor switches connected in series and a power storage element connected in parallel to the two semiconductor switches, and a second coil connected in series to the second power conversion circuit cell. The control device adjusts the same voltage component contained in each of the first voltage of the first connection portion and the second voltage of the second connection portion, and between each of the plurality of legs. It has a power control unit that controls the first power flowing in and out.

According to one aspect of the present invention, stable operation can be continued even if the power system fails and the system voltage falls into a three-phase imbalance.

It is a circuit block diagram which shows the schematic structure of the power conversion apparatus according to 1st Embodiment of this invention. It is a circuit diagram which shows the schematic structure of the power conversion circuit cell provided in each of a plurality of legs provided in the power conversion apparatus according to 1st Embodiment of this invention. It is a simple block diagram which shows the schematic structure of the power conversion apparatus according to 1st Embodiment of this invention. It is a block diagram which shows the schematic structure of the control device provided in the power conversion device according to 1st Embodiment of this invention. It is a block diagram which shows the schematic structure of the voltage suppression part provided in the control device provided in the power conversion device by 1st Embodiment of this invention. It is a block diagram which shows the schematic structure of the arm voltage command value generation part provided in the control device provided in the power conversion device by 1st Embodiment of this invention. It is a block diagram which shows the schematic structure of the control device provided in the power conversion device according to the 2nd Embodiment of this invention. It is a block diagram which shows the schematic structure of the voltage suppression part provided in the control device provided in the power conversion device by 2nd Embodiment of this invention. It is a block diagram which shows the schematic structure of the arm voltage command value generation part provided in the control device provided in the power conversion device by 2nd Embodiment of this invention. It is a figure explaining the effect of the power conversion apparatus by 1st Embodiment of this invention, and is the graph which shows the simulation result of the maximum value of the ineffective power at the time of a system failure. It is a figure explaining the effect of the power conversion apparatus by 2nd Embodiment of this invention, and is the graph which shows the simulation result of the maximum value of the ineffective power at the time of a system failure. It is a graph which shows the simulation result of the maximum value of the ineffective power at the time of a system failure in a reference example. It is a circuit diagram which shows the schematic structure of the power conversion circuit cell provided in each of a plurality of legs provided in the power conversion apparatus according to the 3rd Embodiment of this invention.

[First Embodiment]
The power conversion device according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 6. Regarding the power converter according to the present embodiment, a double star bridge cell type (Double Star Bridge Cells: DSBC) assuming the use of a self-excited static varsator (STATCOM) for a power system. A three-phase modular multi-level converter (hereinafter, "modular multi-level converter" may be abbreviated as "MMCC") will be described as an example.

(Power control system)
The power control system in which the power conversion device according to the present embodiment is used will be described with reference to FIG. FIG. 1 is a circuit block diagram showing a schematic configuration of a power control system PS in which the power conversion device 1 according to the present embodiment is used.

As shown in FIG. 1, the power control system PS is connected to a three-phase power system 2, a load device (not shown) that operates using the power supplied from the three-phase power system 2 as a power source, and a three-phase power system 2. It is provided with a related power conversion device 1. The three-phase power system 2 has a three-phase AC power supply 21 that generates three-phase AC power, and a cable 22 to which the power generated by the three-phase AC power supply 21 is supplied. The three-phase AC power supply 21 includes a U-phase AC power supply 211 that supplies U-phase AC power, a V-phase AC power supply 212 that supplies V-phase AC power, and a W-phase AC power supply 213 that supplies W-phase AC power. Have. The cable 22 includes a U-phase cable 221 to which U-phase AC power generated by the U-phase AC power supply is supplied, and a V-phase cable 222 to which V-phase AC power generated by the V-phase AC power supply 212 is supplied. It has a W-phase cable 223 to which the W-phase AC power generated by the W-phase AC power supply 213 is supplied.

(Power converter)
Next, the configuration of the power conversion device provided in the power control system PS will be described with reference to FIG.
As shown in FIG. 1, in the power conversion device 1 according to the present embodiment, the main circuit unit 3 connected to the three-phase power system 2 and the U-phase leg 31U and V-phase leg 31V provided in the main circuit unit 3 are provided. It also includes a control device 5 (details will be described later) that controls a W-phase leg 31W (an example of a plurality of legs). The main circuit unit 3 provided in the power conversion device 1 has a lower arm (an example of a first arm) 31Un, 31Vn, 31Wn and an upper arm (an example of a second arm) 31Up, 31Vp, 31Wp connected in series. It includes a phase leg 31U, a V-phase leg 31V, and a W-phase leg 31W. As described above, the power converter 1 is a three-phase voltage type power converter using the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W.

The main circuit unit 3 is connected to the upper arms 31Up, 31Vp, 31Wp of both ends of the lower arms 31Un, 31Vn, 31Wn provided on the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W, respectively. It has a lower neutral point (an example of a first connection) 32n with no ends connected to each other. Although the details will be described later, the lower arm 31Un, the lower arm 31Vn, and the lower arm 31Wn are star-connected (Y-connected), and the connection portions of the ends of the lower arms 31Un, 31Vn, and 31Wn are of the star connection. It is a neutral point.

The main circuit unit 3 is connected to the lower arms 31Un, 31Vn, 31Wn of both ends of the upper arms 31Up, 31Vp, 31Wp provided on the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W, respectively. It has an upper neutral point (an example of a second connection) 32p with no ends connected to each other. Although the details will be described later, the upper arm 31Up, the upper arm 31Vp, and the upper arm 31Wp are star-connected (Y-connected), and the connection portions of the ends of the upper arms 31Up, 31Vp, and 31Wp are of the star connection. It is a neutral point.

The U-phase leg 31U has a lower arm 31Un and an upper arm 31Up. The V-phase leg 31V has a lower arm 31Vn and an upper arm 31Vp. The W-phase leg 31W has a lower arm 31Wn and an upper arm 31Wp. The U-phase leg 31U is connected to the U-phase cable 221 of the three-phase power system 2 via a terminal 31Ut provided at a connection portion between the lower arm 31Un and the upper arm Up. The V-phase leg 31V is connected to the V-phase cable 222 of the three-phase power system 2 via a terminal 31Vt provided at a connection portion between the lower arm 31Vn and the upper arm Vp. The W-phase leg 31W is connected to the W-phase cable 223 of the three-phase power system 2 via a terminal 31Wt provided at a connection portion between the lower arm 31Wn and the upper arm Wp.

As shown in FIG. 1, the lower arm 31Un provided on the U-phase leg 31U includes power conversion circuit cells 311Un1, ..., 311Unx (an example of the first power conversion circuit cell), and power conversion circuit cells 311Un1, ... It has an AC reactor 312Un (an example of the first coil) connected in series with 311Unx. Here, x indicates the number of power conversion circuit cells provided in the lower arm 31Un. The upper arm 31Up provided on the U-phase leg 31U is connected in series with the power conversion circuit cells 311Up1, ..., 311Upx (an example of the second power conversion circuit cell) and the power conversion circuit cells 311Up1, ..., 311Upx. It has a connected and AC reactor 312Up (an example of a second coil). Here, x indicates the number of power conversion circuit cells provided on the upper arm 31Up.

The lower arm 31Vn provided on the V-phase leg 31V is connected in series with the power conversion circuit cells 311Vn1, ..., 311Vnx (an example of the first power conversion circuit cell) and the power conversion circuit cells 311Vn1, ..., 311Vnx. It has a connected AC reactor 312Vn (an example of the first coil). Here, x indicates the number of power conversion circuit cells provided in the lower arm 31Vn. The upper arm 31Vp provided on the V-phase leg 31V is connected in series with the power conversion circuit cells 311Vp1, ..., 311Vpx (an example of the second power conversion circuit cell) and the power conversion circuit cells 311Vp1, ..., 311Vpx. It has a connected AC reactor 312Vp (an example of a second coil). Here, x indicates the number of power conversion circuit cells provided on the upper arm 31Vp.

The lower arm 31Wn provided on the W-phase leg 31W includes power conversion circuit cells 311Wn1, ..., 311Wnx (an example of the first power conversion circuit cell) and power conversion circuit cells 311Wn1, ..., 311Wnx (first). It has an AC reactor 312Wn (an example of a first coil) connected in series with an example of a power conversion circuit cell). Here, x indicates the number of power conversion circuit cells provided in the lower arm 31Wn. The upper arm 31Wp provided on the W-phase leg 31W is connected in series with the power conversion circuit cells 311Wp1, ..., 311Wpx (an example of the second power conversion circuit cell) and the power conversion circuit cells 311Wp1, ..., 311Wpx. It has a connected AC reactor 312Wp (an example of a second coil). Here, x indicates the number of power conversion circuit cells provided on the upper arm 31 Wp.

As shown in FIG. 1, in the lower arm 31Un provided on the U-phase leg 31U, the power conversion circuit cell 311Un1 of the power conversion circuit cells 311Un1, ..., 311Unx connected in series is connected to the AC reactor 312Un. ing. In the upper arm 31Up provided on the U-phase leg 31U, the power conversion circuit cell 311Upx of the power conversion circuit cells 311Up1, ..., 311Upx connected in series is connected to the AC reactor 312Up. The connection portion of the AC reactor 312Un and the AC reactor 312Up is connected to the terminal 31Ut. The connection portion of the AC reactor 312Un and the AC reactor 312Up is connected to the U-phase cable 221 of the three-phase power system 2 via the terminal 31Ut.

In the lower arm 31Vn provided on the V-phase leg 31V, the power conversion circuit cell 311Vn1 of the power conversion circuit cells 311Vn1, ..., 311Vnx connected in series is connected to the AC reactor 312Vn. In the upper arm 31Vp provided on the V-phase leg 31V, the power conversion circuit cell 311Vpx of the power conversion circuit cells 311Vp1, ..., 311Vpx connected in series is connected to the AC reactor 312Vp. The connection portion of the AC reactor 312Vn and the AC reactor 312Vp is connected to the terminal 31Vt. The connection portion of the AC reactor 312Vn and the AC reactor 312Vp is connected to the V-phase cable 222 of the three-phase power system 2 via the terminal 31Vt.

In the lower arm 31Wn provided on the W-phase leg 31W, the power conversion circuit cell 311Wn1 of the power conversion circuit cells 311Wn1, ..., 311Wnx connected in series is connected to the AC reactor 312Wn. In the upper arm 31Wp provided on the W-phase leg 31W, the power conversion circuit cell 311Wpx of the power conversion circuit cells 311Wp1, ..., 311Wpx connected in series is connected to the AC reactor 312Wp. The connection portion of the AC reactor 312Wn and the AC reactor 312Wp is connected to the terminal 31Wt. The connection portion of the AC reactor 312Wn and the AC reactor 312Wp is connected to the W-phase cable 223 of the three-phase power system 2 via the terminal 31Wt.

As shown in FIG. 1, the power conversion circuit cell 311Unx provided on the lower arm 31Un and the power conversion circuit cell 311Up1 provided on the upper arm 31Up are arranged at both ends of the U-phase leg 31U. The power conversion circuit cell 311Vnx provided on the lower arm 31Vn and the power conversion circuit cell 311Vp1 provided on the upper arm 31Vp are arranged at both ends of the V-phase leg 31V. The power conversion circuit cell 311Wnx provided on the lower arm 31Wn and the power conversion circuit cell 311Wp1 provided on the upper arm 31Wp are arranged at both ends of the W phase leg 31W.

The end of the power conversion circuit cell 311Unx that is not connected to the power conversion circuit cell (not shown), the end of the power conversion circuit cell 311Vnx that is not connected to the power conversion circuit cell (not shown), and the end of the power conversion circuit cell 311Vnx. The power conversion circuit cell (not shown) of the power conversion circuit cell 311Wnx and the end portion on the side not connected are connected to each other to form a lower neutral point 32n. The end of the power conversion circuit cell 311Up1 that is not connected to the power conversion circuit cell (not shown), and the end of the power conversion circuit cell 311Vp1 that is not connected to the power conversion circuit cell (not shown). The power conversion circuit cell (not shown) of the power conversion circuit cell 311Wp1 and the end portion on the side not connected are connected to each other to form the upper neutral point 32p.

The lower arm 31Un, the lower arm 31Vn, and the lower arm 31Wn are star-connected (Y-connected), and the upper arm 31Up, the upper arm 31Up, and the upper arm 31Wp are star-connected (Y-connected). Therefore, the main circuit unit 3 has a double star connection structure. The lower neutral point 32n is formed in a connection portion in which the lower arm 31Un, the lower arm 31Vn, and the lower arm 31Wn are connected to each other. The upper neutral point 32p is formed in a connection portion in which the upper arm 31Up, the upper arm 31Up, and the upper arm 31Wp are connected to each other. The lower neutral point 32n and the upper neutral point 32p are electrically insulated.

(Power conversion circuit cell)
Next, a specific configuration of the power conversion circuit cells provided in the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W will be described with reference to FIG. 1 with reference to FIG. The power conversion circuit cells provided in the lower arm 31Un and the upper arm 31Up of the U-phase leg 31U, the lower arm 31Vn and the upper arm 31Vp of the V-phase leg 31V, and the lower arm 31Wn and the upper arm 31Wp of the W-phase leg 31W are They have similar configurations to each other. Therefore, as for the specific configuration of the power conversion circuit cells provided in each of the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W, an example of the power conversion circuit cells provided in the lower arm 31Un and the upper arm 31Up. Explain to.

FIG. 2 shows the power conversion circuit cells 311Uni (i is a natural number from 1 to x) and the U-phase leg 31U among the power conversion circuit cells 311Un1, ..., 311Unx provided on the lower arm 31Un of the U-phase leg 31U. It is a figure which shows an example of the circuit structure of the power conversion circuit cell 311Upi (i is a natural number from 1 to x) among the power conversion circuit cells 311Up1, ..., 311Upx provided in the upper arm 31Up.

As shown in FIG. 2, the power conversion circuit cell 311Uni is composed of a plurality of semiconductor modules Ma and semiconductor modules Mb connected in series (two in the present embodiment) and a plurality of semiconductor modules Mb connected in series (2 in the present embodiment). It has a semiconductor module Mc and a semiconductor module Md. The semiconductor module Ma and the semiconductor module Mb, and the semiconductor module Mc and the semiconductor module Md are connected in parallel. Further, the power conversion circuit cell 311Uni has a capacitor C1 connected in parallel to the semiconductor modules Ma and Mb and the semiconductor modules Mc and Md. In the present embodiment, the power storage element provided in the power conversion circuit cell 311Uni has a capacitor C1.

The semiconductor module Ma has a semiconductor switch Qa and a reflux diode Da connected in antiparallel to the semiconductor switch Qa. The semiconductor module Mb has a semiconductor switch Qb and a reflux diode Db connected in antiparallel to the semiconductor switch Qb. The semiconductor module Mc has a semiconductor switch Qc and a freewheeling diode Dc connected in antiparallel to the semiconductor switch Qc. The semiconductor module Md has a semiconductor switch Qd and a reflux diode Dd connected in antiparallel to the semiconductor switch Qd.

Therefore, the power conversion circuit cell 311Uni has two semiconductor switches Qa and Qb connected in series and a capacitor C1 connected in parallel to the two semiconductor switches Qa and Qb. Further, the power conversion circuit cell 311Uni has two semiconductor switches Qc and Qd connected in series. The two semiconductor switches Qc and Qd are connected in parallel to the two semiconductor switches Qa and Qb and the capacitor C1.

In the present embodiment, the semiconductor switches Qa, Qb, Qc, and Qd are composed of, for example, an insulated gate bipolar transistor (IGBT). The collector terminal of the semiconductor switch Qa is connected to the cathode terminal of the recirculation diode Da, the collector terminal of the semiconductor switch Qc, and the cathode terminal of the recirculation diode Dc. The emitter terminal of the semiconductor switch Qa is connected to the anode terminal of the freewheeling diode Da, the collector terminal of the semiconductor switch Qb, and the cathode terminal of the freewheeling diode Db. The gate terminal of the semiconductor switch Qa is connected to the control device 5. As a result, the gate pulse signal S _{Uni_a} output from the control device 5 is input to the gate terminal of the semiconductor switch Qa, and the on / off of the semiconductor switch Qa is controlled.

The emitter terminal of the semiconductor switch Qb is connected to the emitter terminal of the semiconductor switch Qa and the anode terminal of the reflux diode Da. The gate terminal of the semiconductor switch Qb is connected to the control device 5. As a result, the gate pulse signal S _{Uni_b} output from the control device 5 is input to the gate terminal of the semiconductor switch Qb, and the on / off of the semiconductor switch Qb is controlled.

The emitter terminal of the semiconductor switch Qc is connected to the anode terminal of the freewheeling diode Dc, the collector terminal of the semiconductor switch Qd, and the cathode terminal of the freewheeling diode Dd. The gate terminal of the semiconductor switch Qc is connected to the control device 5. _{As a result, the gate pulse signal S Uni_c} output from the control device 5 is input to the gate terminal of the semiconductor switch Qb, and the on / off of the semiconductor switch Qc is controlled.

The gate terminal of the semiconductor switch Qd is connected to the control device 5. As a result, the gate pulse signal S _{Uni_d} output from the control device 5 is input to the gate terminal of the semiconductor switch Qd, and the on / off of the semiconductor switch Qd is controlled.

One electrode of the capacitor C1 is connected to the collector terminal of the semiconductor switch Qa, the cathode terminal of the recirculation diode Da, the collector terminal of the semiconductor switch Qc, and the cathode terminal of the recirculation diode Dc. The other electrode of the capacitor C1 is connected to the emitter terminal of the semiconductor switch Qb, the anode terminal of the recirculation diode Db, the emitter terminal of the semiconductor switch Qd, and the anode terminal of the recirculation diode Dd.

The connection portion between the semiconductor module Ma and the semiconductor module Mb is connected to the terminal T1 of the power conversion circuit cell 311Uni. The connection portion between the semiconductor module Mc and the semiconductor module Md is connected to the terminal T2 of the power conversion circuit cell 311Uni. The terminal T1 of the power conversion circuit cell 311Uni (i = 2,3, ..., X-1) is the terminal T2 of the power conversion circuit cell 311Uni-1 (i = 2,3, ..., X-1). It is connected to the. The terminal T2 of the power conversion circuit cell 311Uni (i = 1, 2, ..., X-1) is connected to the terminal T1 of the power conversion circuit cell 311Uni + 1 (i = 1, 2, ..., X-1). Has been done. The terminal T1 of the power conversion circuit cell 311Un1 is connected to one terminal of the AC reactor 312Un. The terminal T2 of the power conversion circuit cell 311Unx is connected to the lower neutral point 32n. The terminal T2 of the power conversion circuit cell 311Unx is the terminal T2 (not shown) and W of the power conversion circuit cell 311Vnx (see FIG. 1) provided on the lower arm 31Vn of the V-phase leg 31V via the lower neutral point 32n. It is connected to the terminal T2 (not shown) of the power conversion circuit cell 311Wnx (see FIG. 1) provided on the lower arm 31Wn of the phase leg 31W.

_{The voltage v Uni,} which is the potential difference between the terminal T1 and the terminal T2, is a positive voltage when the potential of the terminal T1 is higher than the potential of the terminal T2, and when the potential of the terminal T1 is lower than the potential of the terminal T2. Let be a negative voltage.

The power conversion circuit cell 311Uni has a voltage detection unit 313 that detects a voltage between both electrodes of the capacitor C1. The voltage detection unit 313 is connected to the control device 5. The voltage detection unit 313 is _{configured to output the detected voltage v c_Uni} to the control device 5. The voltage v _{c_Uni} is defined as a positive voltage when the potential of one electrode connected to the semiconductor modules Ma and Mc is higher than the potential of the other electrode connected to the semiconductor modules Mb and Md. The case where the potential of is lower than the potential of the other electrode is defined as a negative voltage.

As shown in FIG. 2, the power conversion circuit cell 311Upi has the same configuration as the power conversion circuit cell 311Uni. Therefore, with respect to the power conversion circuit cell 311Upi, the components having the same functions and functions as the power conversion circuit cell 311Uni are designated by the same reference numerals and the description thereof will be omitted.

The power conversion circuit cell 311Upi has two semiconductor switches Qa and Qb connected in series and a capacitor C1 connected in parallel to the two semiconductor switches Qa and Qb. Further, the power conversion circuit cell 311Upi has two semiconductor switches Qc and Qd connected in series. The two semiconductor switches Qc and Qd are connected in parallel to the two semiconductor switches Qa and Qb and the capacitor C1. In the present embodiment, the power storage element provided in the power conversion circuit cell 311Upi has a capacitor C1.

The gate terminal of the semiconductor switch Qa is connected to the control device 5. As a result, the gate pulse signal _{SUpi_a} output from the control device 5 is input to the gate terminal of the semiconductor switch Qa, and the on / off of the semiconductor switch Qa is controlled. The gate terminal of the semiconductor switch Qb is connected to the control device 5. As a result, the gate pulse signal _{SUpi_b} output from the control device 5 is input to the gate terminal of the semiconductor switch Qb, and the on / off of the semiconductor switch Qb is controlled. The gate terminal of the semiconductor switch Qc is connected to the control device 5. As a result, the gate pulse signal _{SUpi_c} output from the control device 5 is input to the gate terminal of the semiconductor switch Qc, and the on / off of the semiconductor switch Qc is controlled. The gate terminal of the semiconductor switch Qd is connected to the control device 5. As a result, the gate pulse signal _{SUpi_d} output from the control device 5 is input to the gate terminal of the semiconductor switch Qd, and the on / off of the semiconductor switch Qd is controlled.

The connection portion between the semiconductor module Ma and the semiconductor module Mb provided in the power conversion circuit cell 311Upi is connected to the terminal T1 of the power conversion circuit cell 311Upi. The connection portion between the semiconductor module Mc and the semiconductor module Md provided in the power conversion circuit cell 311Upi is connected to the terminal T2 of the power conversion circuit cell 311Upi. The terminal T1 of the power conversion circuit cell 311Upi (i = 2,3, ..., X-1) is the terminal T2 of the power conversion circuit cell 311Upi-1 (i = 2,3, ..., X-1). It is connected to the. The terminal T2 of the power conversion circuit cell 311Upi (i = 1,2, ..., X-1) is connected to the terminal T1 of the power conversion circuit cell 311Upi + 1 (i = 1,2, ..., X-1). Has been done. The terminal T2 of the power conversion circuit cell 311Upx is connected to another terminal of the AC reactor 312Up. One terminal of the AC reactor 312Up is connected to another terminal of the AC reactor 312Un. The terminal T1 of the power conversion circuit cell 311Up1 is connected to the upper neutral point 32p. The terminal T1 of the power conversion circuit cell 311Up1 is the terminal T1 (not shown) and the W phase of the power conversion circuit cell 311Vp1 (see FIG. 1) provided on the upper arm 31Vp of the V phase leg 31V via the upper neutral point 32p. It is connected to the terminal T1 (not shown) of the power conversion circuit cell 311Wp1 (see FIG. 1) provided on the upper arm 31Wp of the leg 31W.

_{The voltage v Upi,} which is the potential difference between the terminals T1 and T2 of the power conversion circuit cell 311Upi, is a positive voltage when the potential of the terminal T1 is higher than the potential of the terminal T2, and the potential of the terminal T1 is the terminal T2. The voltage lower than the potential of is defined as a negative voltage.

The voltage detection unit 313 provided in the power conversion circuit cell 311Upi _{is configured to output the detected voltage vc_Upi} to the control device 5. The voltage v _{c_Upi} is defined as a positive voltage when the potential of one electrode connected to the semiconductor modules Ma and Mc is higher than the potential of the other electrode connected to the semiconductor modules Mb and Md. The case where the potential of is lower than the potential of the other electrode is defined as a negative voltage.

In the present embodiment, the number of power conversion circuit cells provided in each arm in series is determined according to the maximum output voltage, which is one of the device specifications of the power conversion device 1. Therefore, the power conversion device 1 may have one or a plurality (two or more) of power conversion circuit cells for each arm. Further, in the present embodiment, the power conversion circuit cell has a circuit configuration of a two-level type full-bridge converter cell, but if a voltage of both polarities can be output, another type (for example, a neutral point). It may be a clamp 3-level type full bridge converter cell or the like).

(Control device)
Next, with respect to the control device (an example of the control unit) 5 provided in the power conversion device 1 and controlling the semiconductor switches Qa, Qb, Qc, and Qd, FIGS. 3 to 6 are used with reference to FIGS. 1 and 2. Will be explained. In explaining the control device 5, the voltage and current of each part of the power conversion device 1 are defined. FIG. 3 shows the main circuit unit 3 provided in the power conversion device 1 as a simple equivalent circuit, and shows the voltage and current of each unit. Further, in FIG. 3, the illustration of the control device 5 is omitted. In the following description, for the sake of simplicity, the influence of harmonics generated by pulse width modulation (PWM) for generating a gate pulse signal for controlling semiconductor switches Qa, Qb, Qc, and Qd is ignored. .. Further, the lower arms 31Un, 31Vn, 31Wn and the upper arms 31Up, 31Vp, 31Wp provided in each of the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W have only the voltage component and the current component as commanded values. Suppose you want to output.

As shown in FIG. 3, the system voltage and system current related to the three-phase power system 2 are as follows. As for the polarity of the system current of each phase, the current flowing from the three-phase power system 2 toward the power conversion device 1 is positive, and the current flowing from the power conversion device 1 toward the three-phase power system 2 is negative.
v _u : System voltage output by U-phase AC power supply 211 v _v : System voltage output by V-phase AC power supply 212 v _w : System voltage output by W-phase AC power supply 213 i _u : U-phase AC power supply 211 to U-phase the system current i _v flows into the leg 31U: the system current flows from the V-phase AC power supply 212 to the V-phase leg 31V i _w: the system current that flows from the W-phase AC power supply 213 to the W-phase leg 31W

Each of the lower arm (hereinafter, may be referred to as "U-phase lower arm") 31Un and the upper arm (hereinafter, may be referred to as "U-phase upper arm") 31Up provided on the U-phase leg 31U. The voltage across the ends (output voltage) is as follows. Further, the lower arm (hereinafter, may be referred to as "V-phase lower arm") 31Vn and the upper arm (hereinafter, may be referred to as "V-phase upper arm") 31Vp provided on the V-phase leg 31V. The voltage across each (output voltage) is as follows. Further, the lower arm (hereinafter, may be referred to as "W-phase lower arm") 31Wn and the upper arm (hereinafter, may be referred to as "W-phase upper arm") 31Wp provided on the W-phase leg 31W. The voltage across each (output voltage) is as follows.
v _Un : Voltage across U-phase lower arm 31Un v _Up : Voltage across U-phase upper arm 31Up v _Vn : Voltage across V-phase lower arm 31Vn v _Vp : Voltage across V-phase upper arm 31Vp v _Wn : Voltage across W phase lower arm 31 Wn v _Wp : Voltage across W phase upper arm 31 Wp

From one terminal of each of the U-phase lower arm 31Un, the U-phase upper arm 31Up, the V-phase lower arm 31Vn, the V-phase upper arm 31Vp, the W-phase lower arm 31Wn, and the W-phase upper arm 31Wp to the other terminal. The output current that flows is as follows. The polarity of the output current of each arm is such that the current flowing from the terminal T1 to the terminal T2 (see FIG. 2) of the power conversion circuit cell is positive, and the current flowing from the terminal T2 toward the terminal T1 is negative.
i _Un : Output current of U-phase lower arm 31 _{Un i Up} : Output current of U-phase upper arm 31 _{Up i Vn} : Output current of V-phase lower arm 31 _{Vn i Vp} : Output current of V-phase upper arm 31 _{Vp i Wn} : Output current of W-phase lower arm 31Wn i _Wp : Output current of W-phase upper arm 31Wp

The circulating current circulating in each of the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W is as follows. The polarity of the circulating current in each leg is such that the current flowing from the upper arm to the lower arm is positive and the current flowing from the lower arm to the upper arm is negative.
i _{ir_u} : Circulating current circulating in the U-phase leg 31U i _{ir_v} : Circulating current circulating in the V-phase leg 31V i _{ir_w} : Circulating current circulating in the W-phase leg 31W

The zero-phase voltage, which is the potential difference between the potential of the lower neutral point 32n and the ground potential, and the zero-phase voltage, which is the potential difference between the potential of the upper neutral point 32p and the ground potential, are as follows.
v _Zn : Zero-phase voltage at the lower neutral point 32n v _Zp : Zero-phase voltage at the upper neutral point 32p

AC reactor 312Un provided on the U-phase lower arm 31Un, AC reactor 312Up provided on the U-phase upper arm 31Up, AC reactor 312Vn provided on the V-phase lower arm 31Vn, and AC reactor 312Vn provided on the V-phase upper arm 31Vp. The induced voltages generated by the AC reactor 312Vp provided, the AC reactor 312Wn provided on the lower arm 31Wn of the W phase, and the AC reactor 312Wp provided on the upper arm 31Wp of the W phase are as follows.
v _{L_Un:} AC reactor 312Un of the induced voltage v _{L_Up:} AC reactor 312Up of the induced voltage v _{L_Vn:} AC reactor 312Vn of the induced voltage v _{L_Vp:} AC reactor 312Vp of the induced voltage v _{L_Wn:} the induced voltage of the AC reactor 312Wn v _{L_Wp:} AC reactor Induced voltage of 312 Wp

The voltage average value of the capacitor C1 provided in the power conversion circuit cell of each arm is as follows.
v _{C_Un:} average voltage of the capacitor in the lower arm 31Un the U-phase leg 31U v _{C_Up:} average voltage of the capacitor in the arm 31Up of the U-phase leg 31U v _{C_Vn:} average voltage of the capacitor in the lower arm 31Vn the V-phase leg 31V Value v _{C_Vp} : Voltage average value of the capacitor in the upper arm 31Vp of the V-phase leg 31V v _{C_Wn} : Voltage average value of the capacitor in the lower arm 31Wn of the _{W-phase leg 31W v C_Wp} : Voltage of the capacitor in the upper arm 31Wp of the W-phase leg 31W Average value

As shown in FIG. 1, among these voltages and currents, the system voltages v _u , v _v , v _w are voltage detectors (not shown), system currents i _u , _iv , i _w, and output currents i _Un , i _Up , i _Vn , i _Vp , i _Wn , and i _Wp are detected by the current detection unit (not shown) and input to the control device 5. Furthermore, the power conversion circuit cell 311Uni, 311Upi, 311Vni, 311Vpi, 311Wni, voltage _V C_Uni of the capacitor C1 provided in each _{311Wpi, V C_Upi, V C_Vni,} V C_Vpi, V C_Wni, V C_Wpi the voltage detection unit 313 (See FIG. 2) is detected and input to the control device 5.
The voltage detection unit that detects the system voltage v _u , v _v , v _w , the current detection unit that detects the output currents i _Un , i _Up , i _Vn , i _Vp , i _Wn , and i _Wp , and the voltage detection unit 313 store electricity. It corresponds to the detection unit that detects the stored energy of the element or the amount equivalent to the stored energy. Although details will be described later, in the present embodiment, the voltage detection unit 313, for example, a voltage _V C_Uni of the capacitor C1 as the amount equivalent to the accumulated _{energy, V C_Unp, V C_Vni, V} C_Vnp, V C_Wni, detects the _{V C_Wpi.} The control device 5 is configured to control the semiconductor switches Qa, Qb, Qc, and Qd so that the electric power between the arms is balanced based on these currents and voltages input from the main circuit unit 3.

Specifically, as shown in FIG. 4, the control device 5 has a zero-phase voltage v _{Zn (an example of the first voltage) at the lower neutral point 32n and a zero-phase voltage v Zp} (an example of the first voltage) at the upper neutral point 32p. The first zero-phase power (of the first power) that flows in and out between each of the U-phase leg 31U, V-phase leg 31V, and W-phase leg 31W by adjusting the same voltage component contained in each of the two voltages. It has an inter-leg power balancing control unit (an example of a power control unit) 5a that controls an example). The first zero-phase power is the system current (an example of current) flowing between each of the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W and the three-phase power system 2, and the power generated by the voltage component. be.

_{Further, the control device 5 has an arm voltage command value v u_acr_ref of} the voltage across the lower arm 31Un and the upper arm 31Up of the U-phase leg 31U, and an arm voltage command value of the voltage across the lower arm 31Vn and the upper arm 31Vp of the V-phase leg 31V. _v v_acr_ref, and has a current adjusting section 5b for generating an arm voltage command value _{v w_acr_ref,} the voltage across the lower arm 31Wn and the upper arm 31Wp the W-phase leg 31W. Further, the control device 5 has a gate pulse signal generation unit 5c that generates a gate pulse signal. Further, the control device 5 has a carrier wave generation unit 5d that generates a carrier wave.

The inter-leg power balancing control unit 5a has the average value of the voltage of the capacitor C1 provided on the U-phase leg 31U and the voltage of the capacitor C1 provided on each of the U-phase leg 31U, the V-phase leg 31V and the W-phase leg 31W. And the average value of the voltage of the capacitor C1 provided on the V-phase leg 31V and the average value of the voltage of the capacitor C1 provided on each of the U-phase leg 31U, the V-phase leg 31V and the W-phase leg 31W. And the difference between the average value of the voltage of the capacitor C1 provided on the W-phase leg 31W and the difference between the average value of the voltage of the capacitor C1 provided on each of the U-phase leg 31U, the V-phase leg 31V and the W-phase leg 31W. It has a capacitor voltage balancing control unit 51 that controls so that the balance of the above is maintained.

Leg between the power balancing control unit 5a, U-phase leg voltage across the lower arm Un of 31U _{v Un} and the voltage across the upper arm 31Up _{v Up,} the voltage across the lower arm Vn of V-phase leg 31V _{v Vn} and the upper arm 31Vp It has an arm voltage command value generation unit 52 that generates command values for the _{voltage across v Vp} across the voltage v _{Vp, and the voltage v Wn} across the lower arm Wn of the W phase leg 31 W _{and the voltage v Wp} across the upper arm 31 Wp.

The capacitor voltage balancing control unit 51 is the average value of the voltage of the capacitor C1 provided on the lower arm Un of the U-phase leg 31U (voltage average value) and the average value of the voltage average value of the capacitor C1 provided on the upper arm 31Up. It also has a capacitor voltage average difference detection unit 511 that detects a capacitor voltage average difference value which is a difference from the voltage average values of all the capacitors C1 provided in the main circuit unit 3. The voltage average values of all the capacitors C1 provided in the main circuit unit 3 are the voltage average values of the capacitors C1 provided in the lower arm Un of the U-phase leg 31U and the capacitors provided in the upper arm 31Up of the U-phase leg 31U. The voltage average value of C1, the voltage average value of the capacitor C1 provided on the lower arm Vn of the V-phase leg 31V, the voltage average value of the capacitor C1 provided on the upper arm 31Vp of the V-phase leg 31V, and below the W-phase leg 31W. It is the average value of the voltage average value of the capacitor C1 provided in the arm Wn and the average value of the voltage average value of the capacitor C1 provided in the upper arm 31Wp of the W phase leg 31W.

The capacitor voltage average difference detection unit 511 includes the average value of the voltage average value of the capacitor C1 provided on the lower arm Vn of the V-phase leg 31V and the voltage average value of the capacitor C1 provided on the upper arm 31Vp, and the main circuit unit 3. It is configured to detect the difference from the voltage average value of all the capacitors C1 provided in. Further, the capacitor voltage average difference detection unit 511 includes an average value of the voltage average value of the capacitor C1 provided on the lower arm Wn of the W phase leg 31W and the average value of the voltage average value of the capacitor C1 provided on the upper arm 31Wp, and a main circuit. It is configured to detect the difference from the voltage average value of all the capacitors C1 provided in the unit 3.

Further, the capacitor voltage balancing control unit 51 adjusts the same voltage component contained in each of _{the zero-phase voltage v Zn at} the lower neutral point 32n and the zero-phase voltage v _{Zp at the upper neutral point 32p to adjust the capacitor voltage.} It has a voltage suppression unit 512 that suppresses the capacitor voltage average difference value detected by the average difference detection unit 511.

Details of the inter-leg power balancing control unit 5a, the current adjustment unit 5b, the gate pulse signal generation unit 5c, the carrier wave generation unit 5d, and the like will be described later.

Next, the function of the inter-leg power balancing control unit 5a provided in the control device 5 will be described first by a mathematical formula, and then the configuration in which the function is exhibited will be described by using a block diagram.

Here, as an example, focus on the lower arm 31Un of the U phase. The voltage across the lower arm 31Un of the U phase v _Un can be defined by the following equation (1), where _{v L_Un} is the voltage across the AC reactor 312Un.

_{Further, the voltage average value v c_Up} of the capacitor C1 of the lower arm of the U phase can be defined by the following equation (2).

“I” in equations (1) and (2) is a natural number. Further, the voltages across the U-phase upper arm 31Up, the V-phase lower arm 31Vn and the upper arm 31Vp, and the W-phase lower arm 31Wn and the upper arm 31Wp are expressed by the formulas v _Up , v _Vn , v _Vp , v _Wn , v _Wp . It can be defined in the same way as (1). Further, the voltage average values of the capacitors C1 of the U-phase upper arm 31Up, the V-phase lower arm 31Vn and the upper arm 31Vp, and the W-phase lower arm 31Wn and the upper arm 31Wp v _{C_Up} , v _{C_Vn} , v _{C_Vp} , v _{C_Wn} , v. _{C_Wp} can be defined in the same manner as in Eq. (1).

Circulating current _{i Cir_u} circulating U-phase leg 31U, the circulating current _{i Cir_w} circulating the circulating current _{i Cir_v} and W-phase leg 31W circulating V-phase leg 31V, is limited as shown in formula (3).

_{The capacitor voltage average difference value v C_U, which} is the difference between the voltage average value of the capacitor C1 in the U-phase leg 31U and the voltage average value of the capacitor C1 in the entire main circuit unit 3, can be defined by the following equation (4). .. _{Further, the capacitor voltage average difference value Δv C_V, which} is the difference between the voltage average value of the capacitor C1 in the V-phase leg 31V and the voltage average value of the capacitor C1 in the entire main circuit unit 3, is defined by the following equation (5). Can be done. _{Further, the capacitor voltage average difference value Δv C_W, which} is the difference between the voltage average value of the capacitor C1 in the W phase leg 31W and the voltage average value of the capacitor C1 in the entire main circuit unit 3, is defined by the following equation (6). Can be done.

In equations (4) to (6), the first term on the right side indicates the average voltage value of the capacitor C1 in each leg, that is, the average value of the voltage average values of the capacitors C1 of the upper arm and the lower arm. .. Further, in the equations (4) to (6), the second term on the right side is the voltage average value of the capacitor C1 in the entire main circuit unit 3, that is, all the upper arms and the lower arm provided in the main circuit unit 3. The average value of the voltage average value of each capacitor C1 of the arm is shown.

_{The capacitor voltage average difference values Δv C_U} , Δv _{C_V} , and Δv _{C_W} in each leg represented by the equations (4) to (6) are conveniently shown in the equation (7) by performing a three-phase two-phase coordinate conversion. Can be expressed as capacitor voltage average difference values Δv _{C_α} , Δv _{C_β} , and Δv _{C_0.}

Under the ideal condition that the power conversion device 1 outputs three-phase balanced power and the characteristics of the parts used constituting the power conversion device 1 do not vary, the average difference values of the capacitor voltages in each leg Δv _{C_α} , Δv _{C_β} , Δv _{C_0} becomes zero. However, for example, when the operation of the power conversion device 1 is continued under the condition that the three-phase power system 2 fails and the system voltages v _u , v _v , v _{w are three-phase unbalanced, the power conversion device 1 is used.} Three-phase unbalanced power will be output. Under the condition that the system voltage v _u , v _v , v _{w are three-phase unbalanced, the voltage v c_Uni} , between both electrodes of the capacitor C1 between the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W. v _{c_Upi} , v _{c_Vni} , v _{c_Vpi} , v _{c_Wni} , v _{c_Wpi} become unbalanced (unbalanced). Therefore, it is necessary to keep the capacitor voltage average difference values Δv _{C_U} , Δv _{C_V} , and Δv _{C_W} in each leg within the range specified in the specifications of the power conversion device 1. _{The power conversion device 1 according to the present embodiment obtains capacitor voltage average difference values Δv C_α} and Δv _{C_β} in the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W even under the condition of outputting the three-phase unbalanced power. It is possible to keep it within a predetermined range, and stable operation can be continued. The predetermined range is, for example, 1% to 2% of the absolute maximum ratings of _{the voltages v c_Uni} , v _{c_Upi} , v _{c_Vni} , v _{c_Vpi} , v _{c_Wni} , and v _{c_Wpi between both electrodes of the capacitor C1.}

Therefore, the power conversion device 1 according to the present embodiment utilizes the same voltage component contained in each of _{the zero-phase voltage v Zn at} the lower neutral point 32n and the zero-phase voltage v _{Zp at the upper neutral point 32p.} It is configured. As a result, the power conversion device 1 can continue to operate stably even if the three-phase power system 2 fails and the system voltages v _u , v _v , and v _{w fall into a three-phase imbalance.}

Table 1 shows the voltage (output voltage), output current, and output voltage across the U-phase lower arm 31Un and upper arm 31Up, the V-phase lower arm 31Vn and upper arm 31Vp, and the W-phase lower arm 31Wn and upper arm 31Wp. It is a list showing the output power.

In Table 1, the output power that can be output by each arm is as follows.
p Un: Output power of the lower arm 31 _{Un of the} U phase p Up: Output power of the upper arm 31 _{Up of the} U phase p Vn: Output power of the lower arm 31 _{Vn of the} V phase p Vp: Output power of the upper arm 31 _{Vp of the V phase p Wn} : Output power of W-phase lower arm 31Wn p _Wp : Output power of V-phase upper arm 31Vp

The inflow power flowing from the U-phase leg 31U to a three-phase power system 2 and Delta] p _{_U,} V-phase leg inflow power flowing into the three-phase power system 2 and Delta] p _{_V} from 31V, W three-phase from phase leg 31W power system 2 the inflow power flowing When Delta] p _{_W,} the respective inflow power Δp _{_U,} Δp _{_V,} Δp _{_W} can be defined as the following equation (8).

Here, the first term on the right side of the equation (8) is the power flowing in and out between the power conversion device 1 and the three-phase power system 2. Each of the first terms on the right side of the equation (8) has a pulsation twice the system frequency under the condition that the power conversion device 1 outputs positive phase invalid power, but becomes zero when the time is accumulated. .. However, under the condition that the power conversion device 1 continues to operate and outputs the reverse-phase invalid power when the three-phase power system 2 fails, each of the first terms on the right side of the equation (8) accumulates time. And has a finite value. This finite value has a unit of joule (J) and is an energy value. That is, when the power conversion device 1 continues to operate when the three-phase power system 2 fails, the voltage of the capacitor C1 becomes unbalanced between the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W. become. Therefore, by adjusting the values of _{the zero-phase voltages v Zp} , v _Zn of the second term on the right side of the _{equation (8) and the circulating currents i ir_u} , i _{ir_v} , i _{ir_w} of the third term on the right side of the equation (8). to adjust the value of the second and third terms, the inflow power Delta] p _{_U,} Delta] p _{_V,} the unbalanced state of Delta] p _{_W} can be suppressed. The power conversion device 1 according to the present embodiment adjusts the value of the second term on the right side of the equation (8) to adjust the capacitor voltage between the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W (capacitor between legs). voltage) of the unbalanced state (i.e. inflow power Δp _{_U,} Δp _{_V,} is characterized in that for controlling the unbalanced) of Delta] p _{_W.}

U-phase leg 31U inflow power Delta] p _{_U,} Delta] p _{_W} inflow power of inflow power Delta] p _{_V} and W-phase leg 31W of V-phase leg 31V, by converting three-phase to two-phase coordinate, conveniently formula (9 ) Can be written.

In the present embodiment, the second term on the right side of the equation (8), that is, the zero-phase voltage v _{Zn at} the lower neutral point 32n, the zero-phase voltage v _{Zp at} the upper neutral point 32p, and the three-phase power system 2 to U phase leg 31U, system current _i u flowing to the V-phase leg 31V and W-phase leg _31W, i v, by the first zero-phase power generated by _{i w,} capacitor voltage average difference value Delta] v _{C_arufa} in each _leg, Δv C_β, Δv _{C_0} is balanced. _{The power conversion device 1 balances the capacitor voltage average difference values Δv C_α} , Δv _{C_β} , and Δv _{C_0} in each leg in the capacitor voltage balancing control unit 51 provided in the inter-leg power balancing control unit 5a of the control device 5. It is designed to be balanced). The power conversion device 1 can control the power balance between the legs by suppressing the capacitor voltage average difference values Δv _{C_U} , Δv _{C_V} , and Δv _{C_W in each leg within a predetermined range.}

Specifically, the system voltage _{v u,} v v, _v the angular frequency of _w omega _S, the effective value _{V S_p} the positive phase component, a phase difference of the effective value of the reverse-phase component _{V S_n} and reverse phase component Φ _{Assuming vn} , the system voltages v _u , v _v , v _w can be defined as the following equation (10).

Under the condition that no failure has occurred in the three-phase power system 2, _{the effective value VS_n} of the opposite-phase components of _{the system voltages v u} , v _v , and v _w is zero. However, when a system failure that causes a three-phase imbalance such as a single-phase ground fault or a two-phase short circuit occurs in the three-phase power system 2, _{the effective value VS_n} of the opposite-phase components of _{the system voltages v u} , v _v , v _w is finite. Will have a value.

System current _{i u,} i v, _i the effective value _{I S} of _w, the system voltage _{v u,} v v, _v Placing the phase difference [Phi _pf for _w phase, the system current _{i u} flowing into the power conversion apparatus 1 , _i v, _{i w} can be defined as the following equation (11). When the power conversion device 1 according to the present embodiment is assumed to operate as a static power compensator, the phase difference Φ _{pf of the system currents i u} , _iv , i _w is either ± π / 2. Will be taken.

_{The phase difference between the zero-phase voltage v Zp} of the upper neutral point 32p and the zero-phase voltage v _Zn of the lower neutral point 32n to be injected into the power converter 1 with respect to the system voltage v _u is set as Φ _z , and the effective value is V. _{Assuming z} , the zero-phase voltage v _Zp and the zero-phase voltage v _Zn can be defined by the following equation (12). The effective value V _z corresponds to the same voltage component contained in each of the zero-phase voltages v _Zp and v _Zn.

Equation (10), equation (11) and formula when the (12) into equation (9), the DC component [Delta] P _{_Beta} DC component [Delta] P _{_Arufa} and inflow power Delta] p _{_Beta} inflow power Delta] p _{_Arufa} has the following formula (13) It is decided like.

As shown in the equation (13), the power conversion device 1 according to the present embodiment adjusts the effective values V _{z of the zero-phase voltages v Zp} and v _Zn , controls the ineffective power, and controls the system voltages v _u , v _v , v by adjusting the effective value _{V S_p} the positive phase component of _w, the inflow power Delta] p _{_Arufa} between legs, the difference in _{p _Beta,} i.e. capacitor voltage average differential value Delta] v _{C_U} between legs, Delta] v _{C_V,} a Delta] v _{C_W} predetermined It can be suppressed within the range.

Next, the control block of the control device 5 provided in the power conversion device 1 according to the present embodiment will be described with reference to FIGS. 4 to 6.

As shown in FIG. 4, the capacitor voltage average difference detecting unit 511 provided in the capacitor voltage balancing control unit 51 of the inter-leg power balancing control unit 5a is provided with a power conversion circuit cell 311Uni of the U-phase lower arm 31Un. _{The voltage v c_Uni} detected by the voltage detection unit 313 (see FIG. 2) provided in each of i is a natural number from 1 to x) is input. Further, the capacitor voltage average difference detection unit 511 is provided with voltage detection units 313 (see FIG. 2) provided in each of the power conversion circuit cells 311Upi (i is a natural number from 1 to x) of the U-phase upper arm 31Up. The detected voltage v _{c_Upi} is input. Further, in the capacitor voltage average difference detection unit 511, the power conversion circuit cell 311Vni of the lower arm 31Vn of the V phase and the power conversion circuit cell 311Vpi (i is a natural number from 1 to x) provided in the upper arm 31Vp are respectively used. _{The voltages v c_Vni} and v _{c_Vpi} detected by the provided voltage detection unit 313 are input. Further, in the capacitor voltage average difference detection unit 511, the power conversion circuit cell 311Wni of the lower arm 31Wn of the W phase and the power conversion circuit cell 311Wpi (i is a natural number from 1 to x) provided in the upper arm 31Wp are respectively used. _{The voltages v c_Wni} and v _{c_Wpi} detected by the provided voltage detection unit 313 are input.

The capacitor voltage average difference detection unit 511 executes the calculation based on the equation (2) using the _{voltage v c_Uni} and the voltage v _{c_Upi input from the voltage detection unit 313, and the voltage of the capacitor C1 provided on the lower arm 31 Un.} The average value of v _{c_Uni and the average value of the voltage v c_Upi} of the capacitor C1 provided on the upper arm 31Up are calculated. Further, the capacitor voltage average difference detection unit 511 executes the calculation based on the equation (2) using the _{voltage v c_Vni} and the voltage v _{c_Vpi input from the voltage detection unit 313, and the capacitor C1 provided on the lower arm 31Vn.} calculating the average value of the voltage _{v c_Vni,} the average value of the voltage _{v C_Vpi} of the capacitor C1 provided in the upper arm 31Vp. Further, the capacitor voltage average difference detection unit 511 executes the calculation based on the equation (2) using the _{voltage v c_Wni} and the voltage v _{c_Wpi input from the voltage detection unit 313, and the capacitor C1 provided on the lower arm 31 Wn.} calculating the average value of the voltage _{v c_Wni,} the average value of the voltage _{v C_Wpi} of the capacitor C1 provided in the upper arm 31Wp. Further, the capacitor voltage average difference detection unit 511 uses the voltages v _{c_Uni} , v _{c_Upi} , v _{c_Vni} , v _{c_Vpi} , v _{c_Wni} , v _{c_Wpi} input from the voltage detection unit 313, and is provided in the main circuit unit 3. Calculate the voltage average value of the capacitor C1 of.

The capacitor voltage average difference detection unit 511 executes calculations based on the equations (4) to (6) using these calculated average values, and calculates the capacitor voltage average difference values Δv _{C_U} , Δv _{C_V} , and Δv _{C_W} . do. Further, the capacitor voltage average difference detection unit 511 executes an operation based on the equation (7) using these calculated average values, and the capacitor voltage average difference values Δv _{C_α} and Δv _{C_β converted into three-phase and two-phase coordinates.} , Δv _{C_0} is calculated. The capacitor voltage average difference detection unit 511 outputs the calculated capacitor voltage average difference values Δv _{C_α} and Δv _{C_β} to the voltage suppression unit 512. As described above, the capacitor voltage average difference detection unit 511 uses the voltages v _{c_Uni} , v _{c_Upi} , v _{c_Vni} , v _{c_Vpi} , v _{c_Wni} , v _{c_Wpi} input from the voltage detection unit 313, and the capacitor voltage average difference value Δv _{C_α} , It is _{configured to detect Δv C_β and output the} detected capacitor voltage average difference values Δv _{C_α} and Δv _{C_β} to the voltage suppression unit 512.

As shown in FIG. 5, the voltage suppression unit 512 provided in the capacitor voltage balancing control unit 51 includes a feedback unit 512FB and a feedforward unit 512FF. _{The feedback unit 512FB has a zero-phase voltage v Zp at} the upper neutral point 32p and zero at the lower neutral point 32n _{based on the capacitor voltage average difference values Δv C_α} and Δv _{C_β} input from the capacitor voltage average difference detecting unit 511. It is configured to generate a command value for the phase voltage v _Zn. The feedforward unit 512FF is configured to correct the unbalanced state of the output power between the legs generated by the reverse phase voltage component before the capacitor voltage between the legs becomes unbalanced.

As shown in FIG. 5, the feedback unit 512FB provided in the voltage suppression unit 512 passes through a low-pass _{filter to which the capacitor voltage average difference value Δv C_α output from the capacitor voltage average difference detection unit 511 (see FIG. 4) is input.} It has a filter (Low Pass Filter: LPF) 512FBa. Further, the feedback unit 512FB has a low-pass filter 512FBf to _{which the capacitor voltage average difference value Δv C_α} output from the capacitor voltage average difference detection unit 511 is input. _{The voltages v c_Uni} , v _{c_Upi} , v _{c_Vni} , v _{c_Vpi} , v _{c_Wni} , and v _{c_Wpi} detected by the voltage detection unit 313 include the U-phase AC power supply 211, the V-phase AC power supply 212, and the W-phase AC power supply 213 (see FIG. 1). The pulsation of the component twice the frequency of the AC power supply output from each is superimposed. Therefore, the power conversion device 1 is provided with low-pass filters 512FBa and 512FBf for the purpose of attenuating the pulsation so that the pulsation does not affect the balancing control of the capacitor voltage of the upper and lower arms.

The feedback unit 512FB passes through the low-pass filter 512FBa and inputs a signal in which the polarity of _{the capacitor voltage average difference value ΔV C_α} in which the high frequency pulsation is removed from the _{capacitor voltage average difference value Δv C_α is input.} have. A voltage of 0 volts (for example, a voltage having the same potential as ground) is also input to the adder 512FBb. The adder 512FBb adds a 0 volt DC signal and a polarity-inverted capacitor voltage average difference value ΔV _{C_α} signal, that is, outputs a signal obtained by subtracting the _{capacitor voltage average difference value ΔV C_α} signal from the 0 volt DC signal. It is configured to do.

The feedback unit 512FB has a PI control unit 512FBc connected to the addition unit 512FBb. The PI control unit 512FBc is configured to perform proportional integration control on the signal input from the addition unit 512FBb. The proportional calculation performed by the PI control unit 512FBc includes a parameter for converting the unit of the addition result in the addition unit 512FBb from voltage to electric power. As a result, the PI control unit 512FBc can output the _{DC component command value P α_ref} , which is the command value of the DC component ΔP _{_α of the inflow power Δp _α.} The DC component command value P _{α_ref} is a command value for bringing the capacitor voltage average difference value ΔV _{C_α} close to zero.

The feedback unit 512FB passes through the low-pass filter 512FBf, and a signal in which the polarity of _{the capacitor voltage average difference value ΔV C_β} in which the high frequency pulsation is removed from the _{capacitor voltage average difference value Δv C_β is input is input.} have. A voltage of 0 volts (for example, a voltage having the same potential as ground) is also input to the adder 512FBg. The adder 512FBg outputs a signal obtained by adding a 0 volt DC signal and a polarity-inverted capacitor voltage average difference value ΔV _{C_β} signal, that is, subtracting a _{capacitor voltage average difference value ΔV C_β} signal from a 0 volt DC signal. It is configured to do.

The feedback unit 512FB has a PI control unit 512FBh connected to the addition unit 512FBg. The PI control unit 512FBh is configured to perform proportional integration control on the signal input from the addition unit 512FBg. The proportional calculation performed by the PI control unit 512FBh includes a parameter for converting the unit of the addition result by the addition unit 512FBg from voltage to electric power. As a result, the PI control unit 512FBh can output the _{DC component command value P β_ref} , which is the command value of the DC component ΔP _{_β of the inflow power Δp _β.} The DC component command value P _{β_ref} is a command value for bringing the capacitor voltage average difference value ΔV _{C_β} close to zero.

As shown in FIG. 5, in the feedback unit 512FB, the DC component command value P _{α_ref} output from the PI control unit 512FBc and the DC component command value P _{β_ref} output from the PI control unit 512FBh are input to the first zero. It has an amplitude calculation unit 512FBd that calculates the amplitude of the phase power. The amplitude calculation unit 512FBd calculates the amplitude of the first zero-phase power by the square root of the sum of the square of the _{DC component command value P α_ref and} the square of the DC component command value P _{β_ref.}

Feedback unit 512FB is division unit for dividing the first zero-phase power amplitude of the signal system current _i u _of, i v, _{i w} polarity signal obtained by inverting the effective value _{I S} for output from the amplitude calculating unit 512FBd It has 512 FBe. Divider 512FBe the first zero-phase power amplitude of the signal system current _i u of output from the amplitude calculating unit _{512FBd, i v,} i _w rms _I polarity signal obtained by inverting the _S (negative polarity signal ), It is possible to calculate a signal (negative signal) in which the polarity of the signal having the effective value V _z of the zero-phase voltages v _Zp and v _{Zn is inverted.} The voltage suppression unit 512 uses the amplitude calculation unit 512FBd and the division unit 512FBe to obtain the effective values V _z of _{the zero-phase voltages v Zp} and v _Zn corresponding to the same voltage components contained in _{the zero-phase voltages v Zp} and v _{Zn, respectively.} Can be extracted.

The feedback unit 512FB receives input of the capacitor voltage average difference value ΔV _{C_α} output from the low-pass filter 512FBa and the capacitor voltage average difference value ΔV _{C_β} output from the low-pass filter 512FBf, and the inflow power _{Δp_α} , Δp. _It has a phase difference calculation unit 512FBi that calculates the phase difference between the DC component command values P _{α_ref} and P _{β_ref of _β.} Here, the inflow power Delta] p _{_Arufa,} DC component command value P _{Arufa_ref} of _{p _Beta,} the phase difference between the P _{Beta_ref} is flowing power Delta] p _{_Arufa} respect to the phase of the system voltage _{v u} of U-phase, _{p _Beta} DC component command value P _{Arufa_ref,} It is the phase difference of P _{β_ref.} The phase difference calculation unit 512FBi has a calculation unit 512FBi-1 for calculating the ratio of the capacitor voltage average difference value ΔV _{C_β to the capacitor voltage average difference value ΔV C_α.} The phase difference calculation unit 512FBi calculates the inverse function (arc tangent) of the tangent of the calculation result input from the calculation unit 512FBi-1, and calculates the command value of the phase of the first zero-phase power. Has -2. The zero-phase voltages v _Zp and v _Zn are in phase with the capacitor voltage average difference values ΔV _{C_α} and ΔV _{C_β} . Therefore, the command value of the phase of the first zero-phase power can be calculated by using the _{capacitor voltage average difference values ΔV C_α} and ΔV _{C_β.}

The feedback unit 512FB includes a signal (negative electrode signal) in which the polarity of the signal of the phase command value of the first zero-phase power input from the phase difference calculation unit 512FBi is inverted, and the system currents i _u , _iv , i. _It has an addition unit 512FBj that adds a signal having a phase difference Φ _{pf of w.} That is, the addition unit 512FBj the system current _{i u,} i v, and performing the calculation of the equivalent to subtracting the phase from the phase difference [Phi _pf the first zero-phase power _{i w.} Thus, the addition unit 512FBj calculates the line current _{i u,} i v, first zero-phase power phase difference with respect to _{i w,} i.e. the system voltage _v zero-phase voltage with respect to _{u v Zp, v Zn} phase difference [Phi _z ..

Feedback unit 512FB is, division section an inverted signal (signal of negative polarity) the polarity of the effective value _{V z} of the zero-phase voltage outputted from 512FBe, zero-phase voltage _v Zp output from the addition unit _{512FBj, v Zn} It has a zero-phase voltage calculation unit 512FBk to which a signal having a phase difference of Φ _{z is input.} The zero-phase voltage calculation unit 512FBk is configured to execute the calculation represented by the equation (12) and output the command values of _{the zero-phase voltages v Zp} and v _Zn. The value input to the zero-phase voltage calculation unit 512FBk is based on the average difference value of the capacitor voltage. _{Therefore, the command values of the zero-phase voltages v Zp} and v _Zn output by the zero-phase voltage calculation unit 512FBk are correction values for correcting the current capacitor voltage average difference value so as to be small.

As shown in FIG. 5, the feed forward unit 512FF provided in the voltage suppression unit 512 has _{an effective value VS_n} and a system current i _u , i _v , i of the opposite phase components of _{the system voltages v u} , v _v , v _{w. w} rms I _S signals the system current i _u calculated by multiplying the division by and -1 multiplication value _√3, i _v, i _w effective value I _S of the signal polarity signal obtained by inverting the of It has a dividing unit 512FFa that divides by (negative signal). Power is controlled in the opposite direction to the unbalanced state of the voltage of the capacitor C1 provided on the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W (for example, when the voltage of the capacitor C1 is high, the capacitor C1 is controlled. In order to control the power in the discharging direction), a value obtained by multiplying one of the dividing units 512FFa by -1 is input. The division unit 512FFa calculates the two input signals and outputs the effective values V _{z of the zero-phase voltages v Zp} and v _Zn.

In the feed forward unit 512FF, a signal having an effective value V _{z of the zero-phase voltages v Zp} and v _Zn input from the dividing unit 512FFa and a signal having a phase difference Φ _z of the zero-phase voltages v _Zp and v _Zn are input. It has a zero-phase voltage calculation unit 512FFb. Zero-phase voltage is inputted to the zero-phase voltage calculation unit 512FFb _{v Zp, v} signal of the phase difference [Phi _z of _Zn, the first term of the right side of the expression (11), i.e., the power generated by the influence of a reverse-phase voltage It is set to a value that cancels the imbalance. That is, the phase difference Φ _z of the zero-phase voltages v _Zp and v _Zn is a value obtained by inverting the second term on the right side of the equation (13) by 180 degrees with the first term on the right side of the equation (13), and is “Φ _z”. = 2 × Φ _pf −Φ _vn ”. Here, Φ _vn is the phase difference of the negative phase voltage when the phase of the positive phase voltage of the U phase leg 31U is used as a reference. The zero-phase voltage calculation unit 512FFb uses a signal of the effective value V _{z of the zero-phase voltage v Zp} , v _Zn and a signal of the phase difference Φ _z of the zero-phase voltage v _Zp to perform the calculation represented by the equation (12). It is configured to run.

In the power conversion device 1, if _{the effective value VS_n} of the anti-phase components of _{the system voltages v u} , v _v , and v _w is known, the degree of voltage imbalance of the capacitor C1 generated between the legs can be predicted. System voltage _{v u, v v, v} reverse phase component of the effective value _{V S_n} of _w, the system current _{i u, i v,} the effective value _{I S} for _{i w,} the phase difference [Phi _pf of the system current _{i u,} the upper neutral point circulating current _{i Cir_n} signal input to the feedforward portion 512FF such phase difference [Phi _{Cir_n} of the output flowing into 32p and the lower neutral point 32n is detected by the voltage detecting section provided in the power converter 1 line It is obtained from the detected values such as the voltage v _u , v _v , v _w and the system current i _u , i _v , i _{w detected by the current detector.} Therefore, the feedforward unit 512FF outputs the command values of the zero-phase voltages _{v Zp} and v _Zn based on the unbalanced state of the voltage of the capacitor C1 predicted from the detected values from the zero-phase voltage calculation unit 512FFb.

As shown in FIG. 5, the voltage suppression unit 512 has _{a command value of the zero-phase voltage v Zp} , v _Zn input from the zero-phase voltage calculation unit 512FBk and a zero-phase voltage v input from the zero-phase voltage calculation unit 512FFb. _It has an addition unit 512F that adds the command values of Zp and v _{Zn. The signal of the command value of the zero-phase voltage v Zp} , v _Zn input from the zero-phase voltage calculation unit 512FBk is a negative signal, and the command value of the _{zero-phase voltage v Zp} input from the zero-phase voltage calculation unit 512FFb. The signal of is a positive signal. Therefore, the addition unit 512F receives the zero-phase voltage v _Zp , v _Zn input from the zero-phase voltage calculation unit 512FBk from the signal of the command value of the zero-phase voltage v _Zp , v _{Zn input from the zero-phase voltage calculation unit 512FFb.} Performs an operation equivalent to subtracting the signal of the command value of. As a result, the addition unit 512F corrects _{the signal of the command value of the zero-phase voltage v Zp} , v _Zn based on the detected value so that the current capacitor voltage average difference value becomes small, and the zero-phase voltage v as a correction value. _{Corrected by the command values of Zp} and v _Zn , the zero-phase voltage command value v _{Zp_ref} is output. As a result, the zero-phase voltage command value v _{Zp_ref} output from the voltage suppression unit 512 becomes a command value for suppressing the average difference value of the capacitor voltage. The zero-phase voltage command value v _{Zp_ref} is used as a command value for both the zero-phase voltage v _Zp and the zero-phase voltage v _Zn.

As described above, the power conversion device 1 includes a voltage detection unit 313 that detects the stored energy of the capacitor C1 as a power storage element or an amount equivalent to the stored energy, and the inter-leg power balancing control provided in the power conversion device 1. parts 5a may have a 512 (an example of an adjustment unit) voltage suppression unit for adjusting the effective value V _z of the zero-phase voltage v _Zp in response to the detection value detected by the voltage detection unit 313 _(an example of a voltage component) There is. In the present embodiment, the voltage detection unit 313 detects the voltage between both electrodes of the capacitor C1 as an amount equivalent to the stored energy of the power storage element. The voltage suppression unit 512 uses the capacitor voltage average difference value based on the voltage of the capacitor C1 detected by the voltage detection unit 313 to adjust the effective value V _{z of the zero phase voltage v Zp} , and the zero phase voltage command value v _{Zp_ref.} Is configured to generate.

FIG. 6 is a block diagram showing an example of a schematic configuration of an arm voltage command value generation unit 52 provided in the inter-leg power balancing control unit 5a. In FIG. 6, for easy understanding, the capacitor voltage balancing control unit 51, the current adjustment unit 5b, the gate pulse signal generation unit 5c, and the gate pulse signal generation unit 5c connected to the arm voltage command value generation unit 52 are connected. The carrier wave generation unit 5d is also shown in the figure.

As shown in FIG. 6, the arm voltage command value generating unit 52, the output current i _Up arm 31Up on the output current i _Un and U-phase lower arm 31Un of the detected U-phase by the current detection unit (not shown) It has an addition unit 521u that adds the current signals of the above. Further, the arm voltage command value generation unit 52 has a subtraction unit 522u that subtracts the addition signal output from the addition unit 521u by half. The arm voltage command value generation unit 52 can calculate the _{circulating current i cil_u} circulating in the U-phase leg 31U at present by the addition unit 521u and the subtraction unit 522u. The addition unit 521u and the subtraction unit 522u are examples of a calculation unit that calculates the circulating current i _{cil_u using the output current i Un} flowing through the lower arm 31 Un of the U phase and the output current i _{Up flowing through the upper arm 31 Up of the U phase.} Equivalent to. In the present embodiment, _{the current value of the circulating current i ir_u} is half the sum of the current values of the _{output current i Un} flowing in the lower arm 31 _{Un of the U phase and the output current i Up} flowing in the upper arm 31 Up.

The arm voltage command value generation unit 52 has a P control unit 524u connected to the subtraction unit 522u. The P control unit 524u is configured to perform proportional control on the signal of the _{circulating current i cil_u input from the subtraction unit 522u.} The proportional calculation performed by the P control unit 524u includes a parameter for converting a current into a voltage. Thus, P control unit 524u can generate an arm voltage command correction value _{v U_cir_ref} for correcting the arm voltage command value _{v U_acr_ref} generated by the current controller 5b. The arm voltage command value v _{u_acr_ref} is a command value of an invalid voltage that flows in and out between the U-phase AC power supply 211 and the U-phase leg 31U of the three-phase power system 2.

As shown in FIG. 6, the current adjusting unit 5b connected to the arm voltage command value generating unit 52 is composed of, for example, an ACR (Auto Current Regulator). _{The system voltages v u} , v _v , v _w detected by the voltage detection unit (not shown) provided in the power conversion device 1 are input to the current adjustment unit 5b. Moreover, the current adjustment section 5b, system current i _u flowing current detection unit provided in the electric power converter 1 by a three-phase power system 2 detected by the (not shown) to the main circuit unit _3, i _v, i _w is input. Furthermore, the current controller 5b, the system current _{i u,} i v, the command value a is the system current command value _i U_ref of _{i w, i v_ref, i w_ref} is input. The current adjusting unit 5b commands arm voltage based on the _{input system voltage v u} , v _v , v _w , system current i _u , i _v , i _w, and system current command values i _{u_ref} , i _{v_ref} , i _{w_ref.} It is configured to generate the values v _{u_acr_ref} , v _{v_acr_ref} , v _{w_acr_ref.} The arm voltage command value v _{v_acr_ref} is a command value of an invalid voltage that flows in and out between the V-phase AC power supply 212 of the three-phase power system 2 and the V-phase leg 31V. The arm voltage command value v _{w_acr_ref} is a command value of an invalid voltage that flows in and out between the W-phase AC power supply 213 of the three-phase power system 2 and the W-phase leg 31W.

As shown in FIG. 6, the arm voltage command value generation unit 52 has a first addition unit 525u and a second addition unit 526u to which the _{arm voltage command correction value vu_cil_ref output from the P control unit 524u is input.} There is. The first adding unit 525U, the signal obtained by inverting the polarity of the arm voltage command value _{v U_acr_ref} the U-phase leg 31U output from the current adjuster 5b is also input. The second addition unit 526U, not to reverse the polarity of the arm voltage command value _{v U_acr_ref} the U-phase leg 31U output from the current adjuster 5b signal is also inputted.

The first addition unit 525u adds the signal of the arm voltage command correction value v _{u_cil_ref to} the signal in which the polarity of the arm voltage command value v _{u_acr_ref of the U-phase leg 31U is inverted.} Thus, the first adder unit 525u is a signal obtained by inverting the polarity of the arm voltage command value _{v U_acr_ref} and voltage shifted to the positive side by the arm voltage command correction value _{v U_cir_ref} min, arm-voltage pre-arm 31Up of the U-phase The command value v _{up_pre_ref} is generated. The second addition unit 526u adds the signal of the arm voltage command correction value v _{u_cil_ref to} the signal of _{the arm voltage command value v u_acr_ref of the U-phase leg 31U.} As a result, the second addition unit 526u _shifts the signal of the arm voltage command value v _{u_acr_ref to the} positive side by the arm voltage command correction value v u_cil_ref, and sets the arm voltage preliminary command value v _{un_pre_ref} of the lower arm 31 Un of the U phase. Generate.

As shown in FIG. 6, the arm voltage command value generation unit 52 has the arm voltage preliminary command value v _{up_pre_ref} generated by the first addition unit 525u and the zero-phase voltage command value v output from the capacitor voltage balancing control unit 51. _It has a first calculation unit 527u to which Zp_ref is input. Further, the arm voltage command value generation unit 52 inputs the arm voltage preliminary command value v _{un_pre_ref generated by the second addition unit 526u and the zero-phase voltage command value v Zp_ref} output from the capacitor voltage balancing control unit 51. It has a second calculation unit 528u.

The first calculation unit 527u is configured to execute an addition process for adding a signal of the arm voltage preliminary command value v _{up_pre_ref and} a signal of the zero-phase voltage command value v _{Zp_ref. The first calculation unit 527u applies} a signal of the zero-phase voltage command value v _{Zp_ref to} the signal of the arm voltage preliminary command value v up_pre_ref generated by the first addition unit 525u. Thus, the first calculation unit 527u generates the arm voltage command value _{v Up_ref} signal components to suppress the unbalanced state of the capacitor C1 to the signal of the arm-voltage pre-command value _{v Up_pre_ref} is consideration. Further, the second calculation unit 528u is configured to execute an addition process for adding the signal _{of the arm voltage preliminary command value v un_pre_ref and} the signal of the zero-phase voltage command value v _{Zp_ref. The second calculation unit 528u applies} a signal of the zero-phase voltage command value v _{Zp_ref to} the signal of the arm voltage preliminary command value v un_pre_ref generated by the second addition unit 526u. Thereby, the second calculation unit 528u generates the arm voltage command value _{v Un_ref} signal components to suppress the unbalanced state of the capacitor C1 to the signal of the arm-voltage pre-command value _{v Un_pre_ref} is consideration. Arm voltage command value _{v Un_ref} generated by the first calculation unit arm voltage command value generated by the 527u _{v Up_ref} and second arithmetic unit 528u is input to the gate pulse signal generation unit 5c.

As shown in FIG. 6, the arm voltage command value generating unit 52, the output current of the arm 31Vp on the output current i _Vn and V-phase lower arm 31Vn current detection part (not shown) detected by the V-phase i _Vp It has an addition unit 521v that adds the current signals of the above. Further, the arm voltage command value generation unit 52 has a subtraction unit 522v that subtracts the addition signal output from the addition unit 521v by half. The arm voltage command value generation unit 52 can calculate the _{circulating current i cil_v} circulating in the V-phase leg 31V at present by the addition unit 521v and the subtraction unit 522v. The addition unit 521v and the subtraction unit 522v are examples of a calculation unit that calculates the circulating current i _{ir_v using the output current i Vn} flowing through the lower arm 31 Vn of the V phase and the output current i _{Vp flowing through the upper arm 31 Vp of the V phase.} Equivalent to. In the present embodiment, _{the current value of the circulating current i ir_v} is half the sum of the current values of the _{output current i Vn} flowing through the lower arm 31 Vn of the V phase and the output current i _{Vp flowing through the upper arm 31 Vp of the V phase.} become.

The arm voltage command value generation unit 52 has a P control unit 524v connected to the subtraction unit 522v. The P control unit 524v is configured to perform proportional control on the signal of the _{circulating current i cil_v input from the subtraction unit 522v.} The proportional calculation performed by the P control unit 524v includes a parameter for converting a current into a voltage. Thus, P control unit 524v may generate an arm voltage command correction value _{v V_cir_ref} for correcting the arm voltage command value _{v V_acr_ref} generated by the current controller 5b.

As shown in FIG. 6, the arm voltage command value generation unit 52 has a first addition unit 525v and a second addition unit 526v _{into which the arm voltage command correction value v v_cil_ref output from the P control unit 524v is input.} There is. A signal in which the polarity _{of the arm voltage command value vv_acr_ref} of the V-phase leg 31V output from the current adjusting unit 5b is inverted is also input to the first adding unit 525v. A signal that does not invert the polarity _{of the arm voltage command value vv_acr_ref} of the V-phase leg 31V output from the current adjusting unit 5b is also input to the second adding unit 526v.

The first addition unit 525v adds the signal of the arm voltage command correction value v _{v_cil_ref to} the signal in which the polarity of the arm voltage command value v _{v_acr_ref of the V-phase leg 31V is inverted.} Thus, the first adder unit 525v is a signal obtained by inverting the polarity of the arm voltage command value _{v V_acr_ref} and voltage shifted to the positive side by the arm voltage command correction value _{v V_cir_ref} min, arm-voltage pre-arm 31Vp on the V-phase The command value v _{vp_pre_ref} is generated. The second addition unit 526v adds the signal of the arm voltage command correction value v _{v_cil_ref to} the signal of _{the arm voltage command value v v_acr_ref of the V phase leg 31V.} As a result, the second addition unit 526v _shifts the signal of the arm voltage command value v _{v_acr_ref to the} positive side by the arm voltage command correction value v v_cil_ref, and sets the arm voltage preliminary command value v _{vn_pre_ref} of the lower arm 31Vn of the V phase. Generate.

As shown in FIG. 6, the arm voltage command value generation unit 52 has the arm voltage preliminary command value v _{vp_pre_ref} generated by the first addition unit 525v and the zero-phase voltage command value v output from the capacitor voltage balancing control unit 51. _It has a first calculation unit 527v into which Zp_ref is input. Further, the arm voltage command value generation unit 52 inputs the arm voltage preliminary command value v _{vn_pre_ref generated by the second addition unit 526v and the zero-phase voltage command value v Zp_ref} output from the capacitor voltage balancing control unit 51. It has a second calculation unit 528v.

The first calculation unit 527v is configured to execute an addition process for adding a signal of the arm voltage preliminary command value v _{vp_pre_ref and} a signal of the zero-phase voltage command value v _{Zp_ref. The first calculation unit 527v applies} the signal of the zero-phase voltage command value v _{Zp_ref to} the signal of the arm voltage preliminary command value v vp_pre_ref generated by the first addition unit 525v. Thus, the first calculation unit 527v generates the arm voltage command value _{v Vp_ref} signal components to suppress the unbalanced state of the capacitor C1 to the signal of the arm-voltage pre-command value _{v Vp_pre_ref} is consideration. Further, the second calculation unit 528v is configured to execute an addition process for adding the signal _{of the arm voltage preliminary command value v vn_pre_ref and} the signal of the zero-phase voltage command value v _{Zp_ref. The second calculation unit 528v applies} the signal of the zero-phase voltage command value v _{Zp_ref to} the signal of the arm voltage preliminary command value v vn_pre_ref generated by the second addition unit 526v. Thus, the second arithmetic unit 528v generates the arm voltage command value _{v Vn_ref} signal components to suppress the unbalanced state of the capacitor C1 to the signal of the arm-voltage pre-command value _{v Vn_pre_ref} is consideration. Arm voltage command value _{v Vn_ref} generated by the first calculation unit arm voltage command value generated by the 527v _{v Vp_ref} and second arithmetic unit 528v is input to the gate pulse signal generation unit 5c.

As shown in FIG. 6, the arm voltage command value generation unit 52 has an output current i _Wn of the lower arm 31 Wn of the W phase and an output current i _{Wp of the upper arm 31 Wp of the W phase detected by the current detection unit (not shown).} It has an addition unit 521w that adds the current signals of the above. Further, the arm voltage command value generation unit 52 has a subtraction unit 522w that subtracts the addition signal output from the addition unit 521w by half. The arm voltage command value generation unit 52 can calculate the _{circulating current i cil_w} circulating in the W phase leg 31W at present by the addition unit 521w and the subtraction unit 522w. The addition unit 521w and the subtraction unit 522w are examples of a calculation unit that calculates the circulating current i _{ir_w using the output current i Wn} flowing through the lower arm 31 Wn of the W phase and the output current i _{Wp flowing through the upper arm 31 Wp of the W phase.} Equivalent to. In the present embodiment, _{the current value of the circulating current i ir_w} is half the sum of the current values of the _{output current i Wn} flowing through the lower arm 31 Wn of the W phase and the output current i _{Wp flowing through the upper arm 31 Wp of the W phase.} become.

The arm voltage command value generation unit 52 has a P control unit 524w connected to the subtraction unit 522w. The P control unit 524w is configured to perform proportional control on the signal input from the subtraction unit 522w. The proportional calculation performed by the P control unit 524w includes a parameter for converting a current into a voltage. Thus, P control unit 524w may generate an arm voltage command correction value _{v W_cir_ref} for correcting the arm voltage command value _{v W_acr_ref} generated by the current controller 5b.

As shown in FIG. 6, the arm voltage command value generation unit 52 has a first addition unit 525w and a second addition unit 526w _{into which the arm voltage command correction value v w_cil_ref output from the P control unit 524w is input.} There is. A signal in which the polarity _{of the arm voltage command value v w_acr_ref} of the W phase leg 31W output from the current adjusting unit 5b is inverted is also input to the first adding unit 525w. A signal that does not invert the polarity _{of the arm voltage command value v w_acr_ref} of the W phase leg 31W output from the current adjusting unit 5b is also input to the second adding unit 526w.

The first addition unit 525w adds the signal of the arm voltage command correction value v _{w_cil_ref to} the signal in which the polarity of the arm voltage command value v _{w_acr_ref of the W phase leg 31W is inverted.} Thus, the first adder unit 525w is a signal obtained by inverting the polarity of the arm voltage command value _{v W_acr_ref} and voltage shifted to the positive side by the arm voltage command correction value _{v W_cir_ref} min, arm-voltage pre-arm 31Wp on the W-phase The command value v _{wp_pre_ref} is generated. The second addition unit 526w adds the signal of the arm voltage command correction value v _{w_cil_ref to} the signal of _{the arm voltage command value v w_acr_ref of the W phase leg 31W.} As a result, the second addition unit 526w _shifts the signal of the arm voltage command value v _{w_acr_ref to the} positive side by the arm voltage command correction value v w_cil_ref, and sets the arm voltage preliminary command value v _{wn_pre_ref} of the lower arm 31 Wn of the W phase. Generate.

As shown in FIG. 6, the arm voltage command value generation unit 52 has the arm voltage preliminary command value v _{pp_pre_ref} generated by the first addition unit 525w and the zero-phase voltage command value v output from the capacitor voltage balancing control unit 51. _It has a first calculation unit 527w into which Zp_ref is input. Further, the arm voltage command value generation unit 52 inputs the arm voltage preliminary command value v _{wn_pre_ref generated by the second addition unit 526w and the zero-phase voltage command value v Zp_ref} output from the capacitor voltage balancing control unit 51. It has a second calculation unit 528w.

The first calculation unit 527w is configured to execute an addition process for adding a signal of the arm voltage preliminary command value v _{pp_pre_ref and} a signal of the zero-phase voltage command value v _{Zp_ref. The first calculation unit 527w applies} a signal of the zero-phase voltage command value v _{Zp_ref to} the signal of the arm voltage preliminary command value v pp_pre_ref generated by the first addition unit 525w. Thus, the first calculation unit 527w generates the arm voltage command value _{v Wp_ref} signal components to suppress the unbalanced state of the capacitor C1 to the signal of the arm-voltage pre-command value _{v Wp_pre_ref} is consideration. Further, the second calculation unit 528w is configured to execute an addition process for adding the signal _{of the arm voltage preliminary command value v wn_pre_ref and} the signal of the zero-phase voltage command value v _{Zp_ref. The second calculation unit 528w applies} a signal of the zero-phase voltage command value v _{Zp_ref to} the signal of the arm voltage preliminary command value v wen_pre_ref generated by the second addition unit 526w. Thus, the second arithmetic unit 528w generates the arm voltage command value _{v Wn_ref} signal components to suppress the unbalanced state of the capacitor C1 to the signal of the arm-voltage pre-command value _{v Wn_pre_ref} is consideration. Arm voltage command value _{v Wn_ref} generated by the first calculation unit arm voltage command value generated by 527w _{v Wp_ref} and second adding unit 526w is input to the gate pulse signal generation unit 5c.

As shown in FIG. 6, the arm voltage command value generation unit 52 has a carrier wave generation unit 5d. The carrier wave generation unit 5d generates a carrier wave SCui for the U-phase leg 31U, a carrier wave SCvi for the V-phase leg 31V, and a carrier wave SCwi for the W-phase leg 31W, and outputs the carrier wave SCwi to the gate pulse signal generation unit 5c. do. The carrier wave SCui, the carrier wave SCvi, and the carrier wave SCwi are in phase with each other, and the phases are shifted by 1 / (x + 1) degrees within the phase.

The gate pulse signal generation unit 5c is provided on the upper arm 31Up of the U-phase leg 31U based on the arm voltage command value vUp_ref input from the first calculation unit 527u _{and the carrier wave SCui input from the carrier wave generation unit 5d.} was power conversion circuit cell 311Upi (i is a natural number from 1 to x) gate pulse signal for controlling the semiconductor switches Qa provided in each _{S Upi_a,} the gate pulse signal _{S Upi_b} for controlling the semiconductor switch Qb , it generates a gate pulse signal _{S Upi_d} for controlling the gate pulse signal _{S Upi_c} and semiconductor switch Qd for controlling the semiconductor switch Qc.

The gate pulse signal generation unit 5c is provided on the lower arm 31Un of the U-phase leg 31U based on the arm voltage command value vun_ref input from the second calculation unit 528u _{and the carrier wave SCui input from the carrier wave generation unit 5d.} was power conversion circuit cell 311Uni (i is a natural number from 1 to x) gate pulse signal for controlling the semiconductor switches Qa provided in each _{S Uni_a,} the gate pulse signal _{S Uni_b} for controlling the semiconductor switch Qb , it generates a gate pulse signal _{S Uni_d} for controlling the gate pulse signal _{S Uni_c} and semiconductor switch Qd for controlling the semiconductor switch Qc.

The gate pulse signal generation unit 5c is provided on the upper arm 31Vp of the V-phase leg 31V based on the arm voltage command value vv_ref input from the first calculation unit 527v _{and the carrier wave SCvi input from the carrier wave generation unit 5d.} was power conversion circuit cell 311Vpi (i is a natural number from 1 to x) gate pulse signal for controlling the semiconductor switches Qa provided in each _{S Vpi_a,} the gate pulse signal _{S Vpi_b} for controlling the semiconductor switch Qb , it generates a gate pulse signal _{S Vpi_d} for controlling the gate pulse signal _{S Vpi_c} and semiconductor switch Qd for controlling the semiconductor switch Qc.

The gate pulse signal generation unit 5c is provided on the lower arm 31Vn of the V-phase leg 31V based on the arm voltage command value vvn_ref input from the second calculation unit 528v _{and the carrier wave SCvi input from the carrier wave generation unit 5d.} was power conversion circuit cell 311Vni (i is a natural number from 1 to x) gate pulse signal for controlling the semiconductor switches Qa provided in each _{S Vni_a,} the gate pulse signal _{S Vni_b} for controlling the semiconductor switch Qb , it generates a gate pulse signal _{S Vni_d} for controlling the gate pulse signal _{S Vni_c} and semiconductor switch Qd for controlling the semiconductor switch Qc.

The gate pulse signal generation unit 5c is provided on the upper arm 31Wp of the W phase leg 31W based on the arm voltage command value vwp_ref input from the first calculation unit 527w _{and the carrier wave SCwi input from the carrier wave generation unit 5d.} was power conversion circuit cell 311Wpi (i is a natural number from 1 to x) gate pulse signal for controlling the semiconductor switches Qa provided in each _{S Wpi_a,} the gate pulse signal _{S Wpi_b} for controlling the semiconductor switch Qb , it generates a gate pulse signal _{S Wpi_d} for controlling the gate pulse signal _{S Wpi_c} and semiconductor switch Qd for controlling the semiconductor switch Qc.

The gate pulse signal generation unit 5c is provided on the lower arm 31Wn of the W phase leg 31W based on the _{arm voltage command value v Wn_ref input from the second calculation unit 528w and the carrier wave SCwi input from the carrier wave generation unit 5d.} was power conversion circuit cell 311Wni (i is a natural number from 1 to x) gate pulse signal for controlling the semiconductor switches Qa provided in each _{S Wni_a,} the gate pulse signal _{S Wni_b} for controlling the semiconductor switch Qb , it generates a gate pulse signal _{S Wni_d} for controlling the gate pulse signal _{S Wni_c} and semiconductor switch Qd for controlling the semiconductor switch Qc.

Thus, the gate pulse signal _{S Uni_a ~SU ni_d, S Upi_a ~S} Upi_d, S Vni_a ~S Vni_d, S Vpi_a ~S Vpi_d, S Wni_a ~S Wni_d, S Wpi_a ~S Wpi_d the output power difference between the legs It is generated based on _{the arm voltage command values v Un_ref} , v _{Up_ref} , v _{Vn_ref} , v _{Vp_ref} , v _{Wn_ref} , v _{Wp_ref} for suppressing (that is, the average difference value of the capacitor voltage between the legs). Therefore, the semiconductor switches Qa, Qb, Qc, and Qd provided on the lower arm 31Un and the upper arm 31Up of the U phase, the lower arm 31Vn and the upper arm Vp of the V phase, and the lower arm 31Wu and the upper arm Wp of the W phase, respectively. There gate pulse signal _{S Uni_a ~SU ni_d, S Upi_a ~S} Upi_d, S Vni_a ~S Vni_d, S Vpi_a ~S Vpi_d, S Wni_a ~S Wni_d, by operating on / off by _{S Wpi_a ~S Wpi_d,} between legs Output power difference (that is, capacitor voltage average difference value between legs) is suppressed.

In other words, leg between the power balancing controller 5a, the arms voltage command value generated by the arm voltage command value generating unit 52 _v Un_ref ~v gate pulse signal based on _{Wp_ref S} Uni_a _{~S Wpi_d} by U-phase leg 31U, V-phase By controlling the semiconductor switches Qa, Qb, Qc, and Qd provided on the leg 31V and the W-phase leg 31W, respectively, the power of the first zero-phase power of the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W. Suppress the difference. That is, the inter-leg power balancing control unit 5a is detected as an amount equivalent to the stored energy so as to suppress the power imbalance state between the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W. The power difference between the first zero-phase power of the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W is adjusted. As a result, the power conversion device 1 can continue to operate stably even if the system voltage falls into a three-phase imbalance.

As described above, the power conversion device 1 according to the present embodiment has a U-phase leg 31U having a lower arm 31Un and an upper arm 31Up connected in series, and a V-phase leg having a lower arm 31Vn and an upper arm 31Vp connected in series. It has a W-phase leg 31W with 31V and a lower arm 31Wn and an upper arm 31Wp connected in series. Further, the power conversion device 1 is connected to the upper arms 31Up, 31Vp, 31Wp of both ends of the lower arms 31Un, 31Vn, 31Wn provided on the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W. The lower neutral point 32n whose ends are connected to each other, and the lower arm 31Un of both ends of the upper arms 31Up, 31Vp, 31Wp provided on the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W. , 31Vn, 31Wn with upper neutral points 32p whose ends not connected to each other are connected to each other. Further, the power conversion device 1 includes a control device 5 for controlling the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W.

The lower arms 31Un, 31Vn, 31Wn are a power conversion circuit cell 311Un1, ..., 311Unx having a semiconductor switch Qa, Qb connected in series and a capacitor C1 connected in parallel to the semiconductor switches Qa, Qb, and a power conversion circuit cell. It has an AC reactor 312Un connected in series with 311Un1, ..., 311Unx.
The upper arms 31Up, 31Vp, 31Wp are connected in series with the power conversion circuit cells 311Up1, ..., 311Upx having the capacitors C1 connected in parallel to the semiconductor switches Qa and Qb, and the power conversion circuit cells 311Up1, ..., 311Upx. It has a connected AC reactor 312Up.
The control device 5 adjusts the _{effective value V z} corresponding to the same voltage component contained in each of the zero-phase voltage v _{Zn at} the lower neutral point 32n and the zero-phase voltage v _{Zp at the upper neutral point 32p to U.} It has an inter-leg power balancing control unit 5a that adjusts the first zero-phase power flowing in and out between each of the phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W.

A power conversion device having such a configuration can continue to operate stably even if the system voltage falls into a three-phase imbalance.

[Second Embodiment]
The power conversion device according to the second embodiment of the present invention will be described with reference to FIGS. 7 to 9. The power conversion device according to the present embodiment is different from the power conversion device 1 according to the first embodiment, and is characterized in that the power between the legs is balanced by the power generated by the zero-phase voltage, the system current, and the circulating current. have. Hereinafter, in the description of the power conversion device according to the present embodiment, FIGS. 1 to 3 are referred to, and the components having the same functions and functions as those of the power conversion device 1 according to the first embodiment are designated by the same reference numerals. The description thereof will be omitted.

In this embodiment, as an example, as a method of balancing the capacitor voltage between the legs, the capacitor voltage average difference values Δv _{C_α} and Δv _{C_β} are used in combination with the second and third terms on the right side of the equation (8). That is, a method of balancing the power between the legs by the power generated by the zero-phase voltages v _Zp , v _Zn , the system currents i _u , i _v , i _w and the circulating currents i _{ir_u} , i _{ir_v} , i _{ir_ w will be described.} Here, as a specific example of the third term on the right side of the equation (8), a DC circulating current and a DC voltage component of the zero-phase voltage ( _{difference between the zero-phase voltage v _Zp} and the zero-phase voltage v _{_Zn} ) are used. The method will be described. DC circulating current _{i cir_u, i cir_v,} the amplitude of the _{i cir_w I cir} Distant, placing the phase [Phi _cir, circulating current _{i cir_u, i cir_v, i cir_w} shall be defined as the following equation (14) Can be done. The phase Φ _ir is the phase difference of the circulating current with respect to the system current. Here, the circulating current _{i cir_u, i cir_v, i cir_w} is defined using convenience phase [Phi _cir. Phase [Phi _cir corresponds to a parameter which determines the U-phase leg 31U, between legs of the V-phase leg 31V and W-phase leg 31W the current sharing (interphase).

The amplitude V of the difference between the zero-phase voltage of the upper neutral point 32p v _Zp DC voltage component and the lower neutral point 32n zero-phase voltage v _{Zn DC voltage component injected into the power conversion device 1 according to the present embodiment. zpn} is defined as the following equation (15). Hereinafter, the difference between the DC voltage component of the zero-phase voltage v _{Zp and} the DC voltage component of the zero-phase voltage v _Zn may be abbreviated as “difference between the DC voltage components of the _{zero-phase voltage v Zp} and v _Zn”.

Equation (10), the equation (14) and (15) into equation (9), combined with derivation result of the expression (13), a direct current DC component [Delta] P _{_Arufa} and inflow power Delta] p _{_Beta} inflow power Delta] p _{_Arufa} The component _{ΔP_β} is determined by the equation (16).

The first term of the right side of the expression (16) corresponds to the first term on the right hand side of (8), three-phase power system 2 of the system voltage _{v u, v v, v w} and the system current _i u, _{i v} , _Iw- based power. The second term on the right side of the equation (16) corresponds to the second term on the right side of the equation (8), _{and the power based on the zero-phase voltages v Zp} , v _Zn and the system currents i _u , _iv , i _w , that is, It is the first zero-phase power. The third term of the right side of the expression (16) corresponds to the third term of the right side of the expression (8), the voltage difference between the zero-phase voltage _{v Zp} and the zero-phase voltage _{v Zn} and circulating current _{i u_cir, i v_cir,} It is electric power based on i _{w_cil} (second zero-phase electric power).

As described above, the inter-leg power balancing control unit 5a provided in the power conversion device 1 according to the present embodiment has a zero-phase voltage v _Zn (an example of the first voltage) at the lower neutral point 32n and an upper neutral point. The same voltage component contained in each of the 32p zero-phase voltage v _Zp (an example of the second voltage) is adjusted to flow in and out between the U-phase leg 31U, the V-phase leg 31V, and the W-phase leg 31W, respectively. It is configured to control one-zero phase power (an example of first power). Further, the inter-leg power balancing control unit 5a determines _{the voltage difference between the zero-phase voltage v Zn at} the lower neutral point 32n and the zero-phase voltage v _Zp at the upper neutral point 32p, and the circulating current i flowing through the U-phase leg 31U. _It is configured to control the second zero-phase power (an example of the second power) by adjusting at least one of _{u_cil} , the circulating current i v_cil flowing through the V-phase leg 31V, and the circulating current i _{w_cil} flowing through the W-phase leg 31W. There is. Leg between the power balancing controller 5a in the present embodiment, by controlling the first zero-phase power and a second zero-phase power, the inflow power Delta] p _{_U,} Delta] p _{_V,} controls the equilibrium (balance) of Delta] p _{_W.}

Next, the control block of the control device 5 provided in the power conversion device 1 according to the present embodiment will be described with reference to FIGS. 7 to 9. The control device 5 in the present embodiment will be mainly described with a configuration different from that of the control device 5 in the first embodiment, and the same configuration will be described as appropriate as necessary. Control device 5 in this embodiment, the zero-phase voltage v _Zp, v and capacitor voltage balance control between leg using the effective value V _z of _Zn, zero-phase voltage v _Zp, v amplitude of the difference between the DC voltage component of the _Zn It is configured to exert a function combined with the capacitor voltage balance control between the legs using V _zpn.

The power conversion device 1 according to the present embodiment has a voltage / current suppression unit 513 instead of the voltage suppression unit 512 (see FIG. 4) provided in the power conversion device 1 according to the first embodiment.

As shown in FIG. 7, the capacitor voltage balancing control unit 51 provided in the inter-leg power balancing control unit 5a of the control device 5 includes a capacitor voltage average difference detection unit 511 and a voltage / current suppression unit 513. ing. The capacitor voltage average difference detection unit 511 in the present embodiment has the same configuration as the capacitor voltage average difference detection unit 511 in the first embodiment, and exhibits the same function.

Here, an example of a specific configuration of the voltage / current suppression unit 513 will be described with reference to FIG.
As shown in FIG. 8, the voltage / current suppression unit 513 has a feedback unit 513FB and a feedforward unit 513FF. The feedback unit 513FB is configured to generate a command value of a DC circulating current based on the _{capacitor voltage average difference values Δv C_α} and Δv _{C_β} input from the capacitor voltage average difference detection unit 511. Similar to the first embodiment, the feedforward unit 513FF sets the unbalanced state of the output power between the legs generated by the reverse phase voltage component before the capacitor voltage between the legs becomes unbalanced (unbalanced). It is configured to correct.

As shown in FIG. 8, the feedback unit 513FB uses a signal of the amplitude of the first zero-phase power output from the amplitude calculation unit 512FBd as a signal of _{the amplitude V zpn} of the difference between the DC voltage components of the _{zero-phase voltages v Zp} and v _Zn. It has a division unit 513FBe that divides by. The division unit 513FBe divides the signal of the amplitude of the first zero-phase power output from the amplitude calculation unit 512FBd by the signal of _{the amplitude V zpn} of the difference between the DC voltage components of the _{zero-phase voltages v Zp} and v _{Zn. The amplitude command value I ir_FB} , which is the command value of the amplitude of the circulating current of the above, can be calculated.

The feedback unit 512FB is input with the capacitor voltage average difference value ΔV _{C_α} output from the low-pass filter 512FBa and the capacitor voltage average difference value ΔV _{C_β output from the low-pass filter 512FBf,} and is the order of the DC circulating current. It has a phase difference calculation unit 513FBi that calculates _{a phase difference command value Φ cil_FB} , which is a phase difference command value. The phase difference calculation unit 513FBi has a calculation unit 513FBi-1 that calculates the ratio of the capacitor voltage average difference value ΔV _{C_β to the capacitor voltage average difference value ΔV C_α. The phase difference calculation unit 513FBi is a calculation unit that calculates the phase difference command value Φ cil_FB} of the DC circulating current by calculating the inverse function (arc tangent) of the tangent of the calculation result input from the calculation unit 513FBi-1. It has 513 FBi-2. The DC circulating current has the same phase as the capacitor voltage average difference values ΔV _{C_α} and ΔV _{C_β.} Therefore, the phase difference command value Φ _{ir_FB} of the DC circulating current can be calculated by using the capacitor voltage average difference values ΔV _{C_α} and ΔV _{C_β.}

The feedback unit 513FB has a signal of the direct current circulating current amplitude command value I _{cil_FB} input from the dividing unit 513FBe and a signal of the DC circulating current phase difference command value Φ _{cil_FB input from the phase difference calculation unit 512FBi.} It has an input circulating current calculation unit 513FBk. Circulating current calculation unit 513FBk the formula (14) performs an operation represented by the by the circulating current _{i cir_u, i cir_v,} circulating current _{i Cir_w} first command value _{i cir_u_FB, i cir_v_FB,} to output _{i Cir_w_FB} It is configured. The value input to the circulating current calculation unit 513FBk is based on the capacitor voltage average difference value. Therefore, the circulating current first command values i _{ir_u_FB} , i _{ir_v_FB} , and i _{ir_w_FB} output by the circulating current calculation unit 513FBk are correction values for correcting so that the current capacitor voltage average difference value becomes smaller.

As shown in FIG. 8, the feed forward unit 513FF provided in the voltage / current suppression unit 513 has a zero-phase voltage v _Zp , which is output from the division unit 512FFa having the same configuration as the division unit 512FFa in the first embodiment. v signal pre effective value _{V zz} of _Zn has an upper limit portion 513FFb inputted. The upper limit limiting unit 513FFb, when pre effective value _{V zz} inputted is larger than the upper limit value BetaVmax, have limited value to the upper limit value BetaVmax, to output the effective value _{V z} of the zero-phase voltage _{v Zp, v Zn} It is configured in. On the other hand, the upper limit limiting unit 513FFb, when pre effective value _{V zz} to be input is less than the upper limit βVmax is to output a pre-rms _{V zz} zero-phase voltage _{v Zp,} as the effective value _{V z} of _{v Zn} It is configured.

Here, "Vmax" of the upper limit value βVmax can be output from the lower arm 31Un and the upper arm 31Up of the U phase, the lower arm 31Vn and the upper arm 31Vp of the V phase, and the lower arm 31Wn and the upper arm 31Wp of the W phase. It is the residual voltage, and is, for example, a value of about 15% of the _{system voltage v u} , v _v , v _w. Of the upper limit value βVmax "β" is the zero-phase voltage _{v Zp, v} a first zero-phase electric power based on the effective value _{V z} which corresponds to the same voltage component of _Zn, zero-phase voltage _{v Zp, v Zn} DC It is the injection ratio of the second zero-phase power based on the _{amplitude V zpn} of the difference of the voltage components. In the power conversion device 1 according to the present embodiment, for example, the initial value of the injection ratio β is set to, for example, 0.7 by placing more emphasis on the first zero-phase power than the second zero-phase power in the initial state. The details of the injection ratio β will be described later.

As shown in FIG. 8, the zero-phase voltage calculation unit 512FFb provided in the feed-forward unit 513FF includes a signal of the effective values V _{z of the zero-phase voltages v Zp} and v _Zn input from the upper limit limiting unit 513FFb and a feed forward. The operation represented by the equation (12) is executed by using the signal of the phase difference Φ _{z of the zero-phase voltages v Zp} and v _Zn input from the outside of the unit 513FF.

As shown in FIG. 8, the feedforward unit 513FF has an amplitude calculation unit 513FFd in which a signal of the residual voltage Vmax and a signal of the injection ratio β are input. The amplitude calculation unit 513FFd executes, for example, an operation represented by “(1-β) × Vmax” to calculate the amplitude V _zpn / 2 of _{the zero-phase voltages v Zp} and v _Zn. Zero-phase voltage _{v Zp, v} amplitude _{V ZPN} / 2 of _Zn is zero-phase voltage _{v Zp,} corresponds to half the difference between the amplitude _{V ZPN} of the DC voltage component of _{v Zn.}

The feed-forward unit 513FF has an amplification unit 513FFe that doubles the signal of the amplitude V _{zpn / 2 of the zero-phase voltages v Zp} and v _{Zn input from the amplitude calculation unit 513FFd.} Amplifying section 513FFe the zero-phase voltage _{v Zp, v Zn} amplitude _{V ZPN} / 2 the zero-phase voltage is amplified twice _{v Zp, v} and outputs a differential signal of amplitude _{V ZPN} of the DC voltage component of _Zn.

The feed-forward unit 513FF is used between the leg and the signal (negative signal) in which the polarity of the signal of the difference between the DC voltage components of _{the zero-phase voltages v Zp} and v _{Zn output from the amplification unit 513FFe and the amplitude V zpn is reversed.} It has a division unit 513FFf to which a signal of the remaining power required for balancing the power of the above (hereinafter, may be abbreviated as "required residual power") is input. Need remaining power system voltage _{v u,} v v, _v effective value _V of the reverse phase component of the _{w S_n} and system current _{i u,} i v, a value obtained by multiplying the effective value _{I S} for _{i w} divided by √3 zero-phase voltage the value from the value _{v Zp, v} zero-phase voltage to the pre effective value _{V zz} of _{Zn v Zp, v} is obtained by subtracting a value obtained by integrating the ratio between the effective value _{V z} of _Zn. The division unit 513FFf divides the signal of the required residual power by the signal of the amplitude V _{zpn / 2 of the zero-phase voltage v Zp} and v _Zn to calculate the _{amplitude command value I cil_FF} which is the command value of the amplitude of the DC circulating current. ..

The feed forward unit 513FF has a circulation current calculation unit 513FFg in which _{the signal of the amplitude command value I ir_FF} of the DC circulating current input from the division unit 513FFf and the signal of the phase difference Φ _{cil_FF of the DC circulation current are input.} is doing. _{The phase difference Φ cil_FF} of the direct current circulating current input to the circulating current calculation unit 513FFg sets the phase difference Φ _pf of the system current i _u with respect to the phases of the system voltages v _u , v _v , v _w to the system voltages v _u , v _v. , V _w It is obtained by subtracting from _{the phase difference Φ vn} of the opposite phase component. The circulating current calculation unit 513FFg executes the calculation represented by the equation (14) by using the signal _{of the amplitude command value I ir_FF} of the direct current circulating current and the signal of the phase difference Φ _{chill_FF of the direct current circulating current.} circulating current _{i cir_u, i cir_v,} circulating current second command value _{i Cir_u_FF} of _{i cir_w, i cir_v_FF,} and is configured to output a _{i cir_w_FF.}

In the power conversion device 1 according to the present embodiment, similarly to the power conversion device 1 according to the first embodiment, when _{the effective values VS_n} of the opposite phase components of _{the system voltages v u} , v _v , v _w are known, between the legs. The degree of voltage imbalance of the resulting capacitor C1 can be predicted. Thus, feedforward module 513FF is circulating current _i Cir_u based on unbalanced state of the voltage of the capacitor C1 which is predicted from the detected _{value, i cir_v,} i _{cir_w} circulating current second command value _{i cir_u_FF, i cir_v_FF, i cir_w_FF} Is output from the circulating current calculation unit 513FFg.

As shown in FIG. 8, the voltage / current suppression unit 513 is input from _{the signals of the circulation current first command values i ir_u_FB} , i _{ir_v_FB} , and i _{cil_w_FB} input from the circulation current calculation unit 513FBk, and the circulation current calculation unit 513FFg. It has an adder 513Fa that adds the signals of the second command value of the circulating current, i _{cil_u_FF} , i _{cil_v_FF} , and i _{cil_w_FF.} The adder 513Fa is a circulating current first command value as a correction value for correcting the signals of the circulating current second command values i _{ir_u_FF} , i _{ir_v_FF} , and i _{ir_w_FF based on the detected values so that the current capacitor voltage average difference value is small. i} cir_u_FB, i cir_v_FB, corrected by _{i cir_w_FB,} and outputs the circulating current command value _{i cir_u_ref, i cir_v_ref,} the _{i cir_w_ref.} As a result, the circulating current command values i _{ir_u_ref} , i _{ir_v_ref} , and i _{ir_w_ref} output from the voltage / current suppression unit 513 become command values for suppressing the average difference value of the capacitor voltage. The circulating current command value i _{ir_u_ref} is the command value of the circulating current i _{ir_u} , the circulating current command value i _{ir_v_ref} is the command value of the circulating current i _{ir_v} , and the circulating current command value i _{ir_w_ref} is the command of the circulating current i _{ir_w.} The value.

As shown in FIG. 8, the voltage / current suppression unit 513 is input from the zero-phase voltage v _Zp , v _Zn amplitude V _zpn / 2 signal input from the amplitude calculation unit 513FFd and the zero-phase voltage calculation unit 512FFb. It has an adder 513Fb that adds signals with command values of zero-phase voltages v _Zp and v _Zn. The adder 513Fb adds the signal of the zero-phase voltage v _Zp , v _Zn amplitude V _zpn / 2 and the signal of the zero-phase voltage v _Zp , v _Zn command value, and adds the zero-phase voltage v _Zp voltage command value. v _{Zp_ref} is output.

As shown in FIG. 8, the voltage / current suppression unit 513 is a signal (negative signal) in which the polarity of the signal of the _{zero-phase voltage v Zp} , v _Zn amplitude V _{zpn / 2 input from the amplitude calculation unit 513FFd is inverted. ) And the signal of the command value of the zero-phase voltage v Zp} , v _Zn input from the zero-phase voltage calculation unit 512FFb, and has an addition unit 513Fc. Adding section 513Fc the zero-phase voltage _{v Zp, v} zero-phase voltage from the signal of the command value of _{Zn v Zp, v Zn} amplitude _{V ZPN} / 2 of the execution to the zero-phase voltage calculation equivalent to subtracting the signal v The voltage command value of _{Zn v Zn_ref} is output.

By the way, depending on the system conditions, the value of the first term on the right side of the equation (16) becomes too large, and when the injection ratio β is the initial value (for example, 0.7), the control of the power equilibrium between the legs cannot catch up. In some cases. Here, when the control of the power equilibrium between the legs cannot keep up, the seriousness of the defect failure described later is 0.5 [p. u. ], Which is a serious system failure condition. The exact value depends on the design specifications of the power conversion device as STATCOM, the type of system failure, the type of transformer winding installed between the system failure point and the power conversion device as STATCOM, and the like. In that case, the power conversion device 1 is configured to recalculate and reset the optimum injection ratio β so that the power balancing control capability between the legs is maximized. Here, a method for calculating the optimum injection ratio β will be described.

In the control device 5 provided in the power conversion device 1, _{at least one of the circulating currents i ir_u} , i _{ir_v} , and i _{ir_w} is a maximum value determined from the heat generation upper limit value and the peak current upper limit value of the components constituting the main circuit unit 3. When Imax is reached, the injection ratio β is updated to the optimum value. As shown in equation (17), by adjusting the second and third terms on the right side so that the left side becomes zero in equation (16), the power between the legs generated by the three-phase unbalanced system condition The imbalance can be offset.

When the circulating currents i _{ir_u} , i _{ir_v} , and i _{ir_w} reach the maximum value Imax, the equation (17) can be expressed as the equation (18). The injection ratio β satisfying the equation (18) is the optimum value.

In this way, the control device 5 controls the first zero-phase power based on the adjustment of the respective voltage components of _{the zero-phase voltage v Zn at} the lower neutral point 32n and the zero-phase voltage v _{Zp at the upper neutral point 32p.} And the injection ratio β with the second zero phase power based on the adjustment of the circulating currents i _{ir_u} , i _{ir_v} , i _{ir_w} to the maximum voltage that the lower arm 31Un, 31Vn, 31Wn and the upper arm 31Up, 31Vp, 31Wp can output. and based value (i.e. residual voltage Vmax), AC reactor 312Un, 312Vn, 312Wn (first example of a coil) and AC reactors 312Up, 312Vp, 312Wp voltage (i.e. grid voltage at the connection of (an example of a second coil) _{v u} , V _v , v _w ), the voltage component, and the voltage difference between _{the zero-phase voltage v Zn} and the zero-phase voltage v _Zp. The value based on the maximum voltage that can be output by the lower arms 31Un, 31Vn, 31Wn and the upper arms 31Up, 31Vp, 31Wp corresponds to the residual voltage Vmax shown on the right side of the equations (17) and (18). The values based on the voltages of the AC reactors 312Un, 312Vn, 312Wn and the AC reactors 312Up, 312Vp, 312Wp correspond to the electric power represented by the first term in the right side of the equations (17) and (18). Zero-phase voltage _{v Zn,} voltage component of _Zp of the formula (17) and the zero-phase voltage shown in the right side of the equation (18) _{v Zn,} corresponding to the effective value _{V z} in _Zp. The voltage difference between the zero-phase voltage v _Zn and the zero-phase voltage v _{Zp is the amplitude V zpn} of the difference between the DC voltage components of the zero-phase voltage v _Zp and v _Zn , that is, in the right side of equations (17) and (18). It corresponds to the indicated "(1-β) Vmax".

FIG. 9 is a block diagram showing an example of a schematic configuration of an arm voltage command value generation unit 52 provided in the inter-leg power balancing control unit 5a. In FIG. 9, for easy understanding, the capacitor voltage balancing control unit 51, the current adjustment unit 5b, the gate pulse signal generation unit 5c, and the gate pulse signal generation unit 5c connected to the arm voltage command value generation unit 52 are connected. The carrier wave generation unit 5d is also shown in the figure.

As shown in FIG. 9, the arm voltage command value generation unit 52 receives an output current i _Un of the U-phase lower arm 31 _{Un and an output current i of the U-phase upper arm 31 Up input from the capacitor voltage balancing control unit 51. It} has an addition unit 521u that adds each current signal of Up. Further, the arm voltage command value generation unit 52 has a subtraction unit 522u that subtracts the addition signal output from the addition unit 521u by half. The arm voltage command value generation unit 52 can calculate the _{circulating current i cil_u} circulating in the U-phase leg 31U at present by the addition unit 521u and the subtraction unit 522u. The addition unit 521u and the subtraction unit 522u are examples of a calculation unit that calculates the circulating current i _{cil_u using the output current i Un} flowing through the lower arm 31 Un of the U phase and the output current i _{Up flowing through the upper arm 31 Up of the U phase.} Equivalent to. In the present embodiment, _{the current value of the circulating current i ir_u} is half the sum of the current values of the _{output current i Un} flowing through the lower arm 31 Un of the U phase and the output current i _{Up flowing through the upper arm 31 Up of the U phase.} become.

The arm voltage command value generation unit 52 is input from the circulating current i _{cil_u} output from the subtraction unit 522u and the addition unit 513Fa (see FIG. 8) provided in the voltage current suppression unit 513 of the capacitor voltage balancing control unit 51. It has an adder 523u to which a signal obtained by reversing the polarity of the circulating current command value i _{cil_u_ref is input.} Addition unit 523u is a signal of the circulating current command value _{i Cir_u_ref} the current signal and a polarity obtained by inverting the circulating current _{icir_u} addition, that subtracts the signal of the circulating current command value _{i Cir_u_ref} from the current signal of the circulating current _{i cir_u.}

The arm voltage command value generation unit 52 has a P control unit 524u connected to the addition unit 523u. The P control unit 524u is configured to perform proportional control on the signal input from the addition unit 523u. The proportional calculation performed by the P control unit 524u includes a parameter for converting the unit of the addition result in the addition unit 523u from current to voltage. Thus, P control unit 524u can generate an arm voltage command correction value _{v U_cir_ref} for correcting the arm voltage command value _{v U_acr_ref} generated by the current controller 5b. The arm voltage command value v _{u_acr_ref} is a command value of an invalid voltage that flows in and out between the U-phase AC power supply 211 and the U-phase leg 31U of the three-phase power system 2.

The configuration of the arm voltage command value generation unit 52 after the P control unit 524u in the present embodiment is the same as the configuration of the arm voltage command value generation unit 52 after the P control unit 524u according to the first embodiment. Omit.

As shown in FIG. 9, the arm voltage command value generating unit 52, the output current _{i Up} arm 31Vp on the output current _{i Vn} and V-phase lower arm 31Vn the V-phase input from the capacitor voltage balancing controller 51 It has an addition unit 521v that adds the current signals of the above. Further, the arm voltage command value generation unit 52 has a subtraction unit 522v that subtracts the addition signal output from the addition unit 521v by half. The arm voltage command value generation unit 52 can calculate the _{circulating current i cil_v} circulating in the V-phase leg 31V at present by the addition unit 521v and the subtraction unit 522v. Calculating adder unit 521v and subtraction portion 522v is to calculate the circulating current _{i Cir_v} by using the output current _{i Vp} flowing to the upper arm 31Vp output current _{i Vn} and V-phase leg 31V flowing through the lower arm 31Vn the V-phase leg 31V Corresponds to an example of the part. In the present embodiment, _{the current value of the circulating current i cil_v} is the sum of the current values of the output current i _Vn flowing through the lower arm 31 Vn of the V phase leg 31 V and the output current i _Vp flowing through the upper arm 31 Vp of the V phase leg 31 V. It becomes half the value of.

The arm voltage command value generation unit 52 is input from the circulating current i _{cil_v} output from the subtraction unit 522v and the addition unit 513Fa (see FIG. 8) provided in the voltage current suppression unit 513 of the capacitor voltage balancing control unit 51. It has an adder 523v to which a signal obtained by reversing the polarity of the circulating current command value i _{cil_v_ref is input.} Adding section 523v is circulating current _i adds the signal of the current signal and the polarity circulating current command value _{i Cir_v_ref} obtained by inverting the _{Cir_v,} i.e. subtracts the signal of the circulating current command value _{i Cir_v_ref} from the current signal of the circulating current _{i Cir_v.}

The arm voltage command value generation unit 52 has a P control unit 524v connected to the addition unit 523v. The P control unit 524v is configured to perform proportional control on the signal input from the addition unit 523v. The proportional calculation performed by the P control unit 524v includes a parameter for converting the unit of the addition result in the addition unit 523v from current to voltage. Thus, P control unit 524v may generate an arm voltage command correction value _{v V_cir_ref} for correcting the arm voltage command value _{v V_acr_ref} generated by the current controller 5b. The arm voltage command value v _{v_acr_ref} is a command value of an invalid voltage that flows in and out between the V-phase AC power supply 212 of the three-phase power system 2 and the V-phase leg 31V.

The configuration of the arm voltage command value generation unit 52 after the P control unit 524v in the present embodiment is the same as the configuration of the arm voltage command value generation unit 52 after the P control unit 524v according to the first embodiment. Omit.

As shown in FIG. 9, the arm voltage command value generation unit 52 has an output current i _Wn of the lower arm 31 Wn of the W phase and an output current i _{Wp of the upper arm 31 Wp of the W phase input from the capacitor voltage balancing control unit 51.} It has an addition unit 521w that adds the current signals of the above. Further, the arm voltage command value generation unit 52 has a subtraction unit 522w that subtracts the addition signal output from the addition unit 521w by half. The arm voltage command value generation unit 52 can calculate the _{circulating current i cil_w} circulating in the W phase leg 31W at present by the addition unit 521w and the subtraction unit 522w. The addition unit 521w and the subtraction unit 522w are examples of a calculation unit that calculates the circulating current i _{ir_w using the output current i Wn} flowing through the lower arm 31 Wn of the W phase and the output current i _{Wp flowing through the upper arm 31 Wp of the W phase.} Equivalent to. In the present embodiment, _{the current value of the circulating current i ir_w} is half the sum of the current values of the _{output current i Wn} flowing through the lower arm 31 Wn of the W phase and the output current i _{Wp flowing through the upper arm 31 Wp of the W phase.} become.

The arm voltage command value generation unit 52 is input from the circulating current i _{cil_w} output from the subtraction unit 522w and the addition unit 513Fa (see FIG. 8) provided in the voltage current suppression unit 513 of the capacitor voltage balancing control unit 51. It has an adder 523w to which a signal obtained by reversing the polarity of the circulating current command value i _{cil_w_ref is input.} Addition unit 523w is a signal of the circulating current command value _{i Cir_w_ref} the current signal and a polarity obtained by inverting the circulating current _{icir_w} addition, that subtracts the signal of the circulating current command value _{i Cir_w_ref} from the current signal of the circulating current _{i cir_w.}

The arm voltage command value generation unit 52 has a P control unit 524w connected to the addition unit 523w. The P control unit 524w is configured to perform proportional control on the signal input from the addition unit 523w. The proportional calculation performed by the P control unit 524w includes a parameter for converting the unit of the addition result in the addition unit 523w from current to voltage. Thus, P control unit 524w may generate an arm voltage command correction value _{v W_cir_ref} for correcting the arm voltage command value _{v W_acr_ref} generated by the current controller 5b. The arm voltage command value v _{w_acr_ref} is a command value of an invalid voltage that flows in and out between the W-phase AC power supply 213 of the three-phase power system 2 and the W-phase leg 31W.

The configuration of the arm voltage command value generation unit 52 after the P control unit 524w in the present embodiment is the same as the configuration of the arm voltage command value generation unit 52 after the P control unit 524w according to the first embodiment. Omit.

As described above, the arm voltage command value generation unit 52 in the present embodiment is based on the circulating current command values i _{ir_u_ref} , i _{ir_v_ref} , i _{ir_w_ref} and the voltage command values v _{Zp_ref} , v _{Zn_ref} , and the arm voltage command values v _{Un_ref} , _{Vn_ref.} , _{Wn_ref} is configured to generate. As a result, the arm voltage command value generation unit 52 _adjusts the circulating currents i ir_u, i _{ir_v} , i _{ir_w} and the zero-phase voltages v _Zp , v _Zn to suppress the unbalanced state of the capacitor C1, and the inflow power Δp _{_U} , The equilibrium of Δp _{_V} and Δp _{_W} can be controlled.

As described above, in the power conversion device 1 according to the present embodiment, in addition to the configuration of the power conversion device 1 according to the first embodiment, the zero-phase voltage v _{Zn at} the lower neutral point 32n and the upper neutral point 32p the voltage difference and the circulating current _{i U_cir} flowing through the U-phase leg 31U, by adjusting at least one of the circulating current _{i W_cir} flowing through the circulating current _{i V_cir} and W-phase leg 31W flowing through the V-phase leg 31V of the zero-phase voltage _{v Zp} The inter-leg power balancing control unit 5a capable of controlling the second zero-phase power (an example of the second power) is provided.

As a result, the power conversion device 1 according to the present embodiment has the same effect as the power conversion device 1 according to the first embodiment. Furthermore, the power conversion apparatus 1 according to the present embodiment, the inflow power Delta] p _{_U,} Delta] p _{_V,} in order to control the equilibrium (balance) of Delta] p _{_W,} the circulating current _{i cir_u, i cir_v, i cir_w} can also be used.

(Effect of power conversion device according to the first embodiment and the second embodiment)
Next, the effects of the power conversion device according to the first embodiment and the second embodiment will be described with reference to FIGS. 10 to 12. FIG. 10 shows a method similar to that of the power conversion device according to the first embodiment, that is, an ineffective power at the time of a system failure when an injection power based on a zero-phase voltage is injected to control an unbalanced state of power between legs. It is a graph which shows the simulation result of the maximum value. FIG. 11 shows a method similar to that of the power conversion device according to the second embodiment, that is, injection power based on the zero-phase voltage and injection power based on the voltage difference between the circulating current and the zero-phase voltage are injected to prevent power between the legs. It is a graph which shows the simulation result of the maximum value of the ineffective power at the time of a system failure when the equilibrium state is controlled. As a reference example, FIG. 12 shows a simulation result of the maximum value of ineffective power at the time of system failure when injection power based on the voltage difference between the circulating current and the zero-phase voltage is injected to control the unbalanced state of the power between the legs. It is a graph which shows.

The horizontal axis of the graph shown in FIGS. 10 to 12 is the severity of the system failure (Voltage Dip Severity) [p. u. ], And the vertical axis of the graph is the reactive current [p. u. ] Is represented. The severity of the system failure indicates that the closer to "1", the smaller the system voltage drop due to the system short-circuit failure, and the closer to "0", the larger the system voltage drop. The curve L1 connecting the triangular marks shown in FIG. 10 represents the characteristic of the maximum value of the ineffective power at the time of system failure of the one-phase ground fault. The straight line L2 connecting the circles shown in FIG. 10 represents the characteristics of the maximum value of the ineffective power at the time of system failure of the two-phase short circuit. The straight line L3 connecting the cross marks shown in FIG. 10 represents the characteristics of the maximum value of the ineffective power at the time of system failure of the two-phase ground fault. The curve L4 connecting the triangular marks shown in FIG. 11 represents the characteristics of the maximum value of the ineffective power at the time of system failure of the one-phase ground fault. The straight line L5 connecting the circles shown in FIG. 11 represents the characteristics of the maximum value of the ineffective power at the time of system failure of the two-phase short circuit. The straight line L6 connecting the cross marks shown in FIG. 11 represents the characteristics of the maximum value of the ineffective power at the time of system failure of the two-phase ground fault. The curve L7 connecting the triangular marks shown in FIG. 12 represents the characteristics of the maximum value of the ineffective power at the time of system failure of the one-phase ground fault. The curve L8 connecting the circles shown in FIG. 12 represents the characteristics of the maximum value of the ineffective power at the time of system failure of the two-phase short circuit. The curve L9 connecting the cross marks shown in FIG. 12 represents the characteristics of the maximum value of the ineffective power at the time of system failure of the two-phase ground fault.

In FIGS. 10 to 12, the vertical axis is the reactive current [p. u. ], But since the reactive power is proportional to the reactive current, the vertical axis is equivalent to representing the reactive power. The graphs shown in FIGS. 10 to 12 are simulation results assuming a STATCOM rated at 80 Mvar for a large-scale offshore power plant.

As shown in FIG. 10, when the capacitor equilibrium state control (balance control) method in the power conversion device according to the first embodiment is applied, a two-phase short circuit (see straight line L2) and a two-phase ground fault (see straight line L3) are applied, respectively. Under the conditions, the rated power can be output because the power is the maximum value regardless of the severity of the system failure. However, when the capacitor equilibrium state control (balance control) method in the power conversion device according to the first embodiment is applied, the seriousness of the system failure is less than 0.4 under the condition of one-phase ground fault (see straight line L1). Since the reactive current drops sharply in the range, the reactive power that can be output also drops sharply. Therefore, the capacitor equilibrium state control (balance control) method in the power conversion device according to the first embodiment is more effective for a two-phase short circuit and a two-phase ground fault than a one-phase ground fault.

As shown in FIG. 11, when the capacitor equilibrium state control (balance control) method in the power conversion device according to the second embodiment is applied, a two-phase short circuit (see straight line L5) and a two-phase ground fault (see straight line L6) are applied, respectively. Under the conditions, the injected power based on the zero-phase voltage is mainly used, so that the rated power can be output with the maximum value of the disabled power regardless of the seriousness of the system failure. Further, when the capacitor equilibrium state control (balance control) method in the power conversion device according to the second embodiment is applied, injection based on the voltage difference between the circulating current and the zero-phase voltage under the condition of one-phase ground fault (see straight line L4). Electric power can also be injected. Therefore, when this method is applied, the reactive current does not sharply decrease in the range where the seriousness of the system failure is less than 0.4, so that the reactive power that can be output does not sharply decrease. As a result, when this method is applied, the output of reactive power of about 70% of the rated reactive current can be maintained even when the seriousness of the system failure is the highest.

When the capacitor equilibrium state control (balance control) method according to the reference example is applied, any of the conditions of 1-phase ground fault (see curve L7), 2-phase short circuit (see curve L8) and 2-phase ground fault (see curve L9) is satisfied. However, since the reactive current decreases in the range where the severity of the system failure is smaller than the predetermined value, the reactive power that can be output also decreases. Therefore, the equilibrium state control (balance control) method according to the reference example has a problem that the rated ineffective power cannot be maintained in case of any system failure. Further, since the capacitor equilibrium state control (balance control) method according to the reference example uses a circulating current, there is also a problem that a loss due to the circulating current occurs when controlling the capacitor equilibrium state.

The capacitor equilibrium state control (balance control) method in the power conversion device according to the first embodiment can maintain the rated ineffective power against a system failure of a two-phase short circuit and a two-phase ground fault. Therefore, the method according to the first embodiment is superior to the method according to the reference example for a system failure of a two-phase short circuit and a two-phase ground fault.

The capacitor equilibrium state control (balance control) method in the power conversion device according to the first embodiment can maintain the rated ineffective power against a system failure of a two-phase short circuit and a two-phase ground fault. Further, in the capacitor equilibrium state control (balance control) method in the power conversion device according to the second embodiment, in the case of a system failure of a one-phase ground fault, the injection ratio β is reset to suppress a decrease in the rated invalid power. can. Therefore, the method according to the second embodiment is superior to the method according to the reference example for system failure.

[Third Embodiment]
The power conversion device according to the third embodiment of the present invention will be described with reference to FIG. The power conversion device according to the present embodiment is characterized in that the remaining capacity of the secondary battery provided as the power storage element is controlled to suppress the output power difference between the upper and lower arms within a predetermined range. The power conversion device according to the present embodiment has the same schematic configuration as the power conversion device according to the first embodiment, except that the configuration of the power conversion circuit cell is different. Hereinafter, in the description of the power conversion device according to the present embodiment, FIG. 1 is referred to, and the components having the same functions and functions as those of the power conversion device 1 according to the first embodiment are designated by the same reference numerals. The description is omitted.

As shown in FIG. 13, the power storage element provided in the power conversion circuit cell 311Uni (i is a natural number from 1 to x) of the lower arm 31Un of the U-phase leg 31U is connected in parallel to the capacitor C2 and the capacitor C2. It also has a secondary battery 314. Further, the power conversion circuit cell 311Uni has a battery management system (Battery Management System: BMS) 315 that detects the remaining capacity (State-Of-Charge: SOC) of the secondary battery 314. The battery management system 315 is connected to the control device 5. Information on the remaining capacity of the secondary battery 314 detected by the battery management system 315 is transmitted to the control device 5.

Similarly, the power storage element provided in the power conversion circuit cell 311Upi (i is a natural number from 1 to x) of the upper arm 31Up of the U-phase leg 31U is parallel to the capacitor C2 and the two semiconductor switches Qa and Qb. It has a connected secondary battery 314. Further, the power conversion circuit cell 311Upi has a battery management system 315 that detects the remaining capacity of the secondary battery 314. The battery management system 315 is connected to the control device 5. Information on the remaining capacity of the secondary battery 314 detected by the battery management system 315 is transmitted to the control device 5.

Although not shown, the power conversion circuit cells provided in the lower arm 31Vn and the upper arm 31Vp of the V-phase leg 31V and the lower arm 31Wn and the upper arm 31Wp of the W-phase leg 31W are also similarly provided with two capacitors C2. It has a battery management system 315 that detects the remaining capacity of the secondary battery 314 and the secondary battery 314 connected in parallel to the semiconductor switches Qa and Qb.

The voltage between both electrodes of the capacitor C2 is determined by the voltage across the secondary battery 314. Therefore, the power conversion device according to the present embodiment does not need to output the DC voltage between both electrodes of the capacitor C2 to the control device 5. The power conversion device according to the present embodiment is configured to transmit information on the remaining capacity of the secondary battery 314 detected by the battery management system 315 to the control device 5 instead of the DC voltage between both electrodes of the capacitor C2. There is. The control device 5 is configured to be able to suppress the difference in the remaining capacity of the secondary battery 314 of the power conversion circuit cell input from the battery management system 315.

The inter-leg power balancing control unit (an example of the power control unit) provided in the control device 5 is provided in the remaining capacity of the secondary battery 314 provided in the lower arm 31Uni of the U phase and in the upper arm 31Upi of the U phase. It is configured to detect the difference in the remaining capacity of the secondary battery 314. Further, the inter-leg power balancing control unit determines the difference between the remaining capacity of the secondary battery 314 provided in the lower arm 31Vni of the V phase and the remaining capacity of the secondary battery 314 provided in the upper arm 31Vpi of the V phase. It is configured to detect. Further, the inter-leg power balancing control unit determines the difference between the remaining capacity of the secondary battery 314 provided in the lower arm 31Wni of the W phase and the remaining capacity of the secondary battery 314 provided in the upper arm 31Wpi of the W phase. It is configured to detect.

The inter-leg power balancing control unit is configured to be able to convert the remaining capacity of the detected secondary battery 314 into a voltage. The inter-leg power balancing control unit can operate in the same manner as the inter-leg power balancing control unit 5a provided in the power conversion device according to the first embodiment and the second embodiment by using the converted voltage. Become. As a result, the power conversion device according to the present embodiment operates in the same manner as any of the power conversion devices according to the first embodiment and the second embodiment, and the capacitor voltage average difference values between the legs are Δv _{C_U} , Δv _{C_V} , Δv _{C_W.} Can be suppressed within a predetermined range.

As a result, the power conversion device according to the present embodiment has the same effect as the power conversion device according to the first embodiment and the second embodiment. Further, the power conversion device according to the present embodiment has the secondary battery 314 in parallel with the capacitor C2, so that the surge voltage can be suppressed by the capacitor C2 and the active power can be compensated for a longer period of time.

The present invention is not limited to the above embodiment and can be modified in various ways.
The power conversion device 1 according to the first to third embodiments is configured to detect the voltage of the capacitor C1 as an amount equivalent to the stored energy, but the present invention is not limited to this. For example, even if the power conversion device 1 detects the stored energy stored in the capacitor C1 and controls so that the detected stored energy is balanced, the above-mentioned first embodiment to the above-mentioned third embodiment are applied. The same effect as that of the power conversion device 1 can be obtained.

The power conversion device 1 according to the first to third embodiments includes a plurality of power conversion circuit cells having four semiconductor switches, but the present invention is not limited to this. For example, the same effect can be obtained even if the power conversion device has a plurality of power conversion circuit cells having two semiconductor switches connected in series.

The power conversion device 1 according to the first to third embodiments has semiconductor switches Qa, Qb, Qc, and Qd composed of IGBTs, but the present invention is not limited to this. The power conversion device 1 includes, for example, a gate turn-off thyristor (GTO), an integrated gate commutated turn-off thyristor (GCT), or a MOS field effect transistor (Metal-Oxide). It may have a semiconductor switch configured by (Semiconductor Field-Effective Transistor) or the like.

The power conversion device according to the first embodiment and the second embodiment may be designed so that the capacitance of the capacitor C1 is larger than the capacitance required for balancing the electric power between the upper and lower arms. In this case, the power conversion device can supply active power to the load of the power system for a short time even when the power system has a momentary power failure, for example.

The technical scope of the present invention is not limited to the exemplary embodiments illustrated and described, but also includes all embodiments that provide an effect equal to that intended by the present invention. Further, the technical scope of the present invention is not limited to the combination of the features of the invention defined by the claims, but is defined by any desired combination of the specific features of all the disclosed features. sell.

1 Power conversion device 2 Three-phase power system 3 Main circuit unit 5 Control device 5a Leg-to-leg power balancing control unit 5b Current adjustment unit 5c Gate pulse signal generation unit 5d Carrier wave generation unit 21 Three-phase AC power supply 22 Cable 31U U-phase leg 31Un, 31Vn, 31Wn Lower arm 31Up, 31Vp, 31Wp Upper arm 31Ut, 31Vt, 31Wt, T1, T2 terminal 31V V-phase leg 31W W-phase leg 32n Lower neutral point 32p Upper neutral point 51 Condenser voltage balancing control unit 52 Arm voltage command value generator 211 U-phase AC power supply 212 V-phase AC power supply 213 W-phase AC power supply 221 U-phase cable 222 V-phase cable 223 W-phase cable 311Un1,311Uni, 311Uni-1,311Unx, 311Up, 311Up1,311Upi, 311Upi-1,311Upx, 311Vn1,311Vni, 311Vnx, 311Vp, 311Vp1,311Vpi, 311Wn1,311Wni, 311Wnx, 311Wp, 311Wp1,311Wpi Power conversion circuit cell 312Un, 312Wpi 314 Secondary battery 315 Battery management system 511 Condenser voltage average difference detection unit 512 Voltage suppression unit 513 Voltage current suppression unit 512F, 512FBb, 512FBg, 512FBj, 513Fa, 513Fb, 513Fc, 521u, 521v, 521w, 523u, 523v, 523w Part 512FB, 513FB Feedback part 512FBa, 512FBf Low frequency pass filter 512FBc, 512FBh PI control part 512FBd, 513FFd Fluctuation calculation part 512FBe, 512FFa, 513FBe, 513FFf Dividing part 512FBi, 513FBi 512FBi-2, 513FBi-2 Calculation unit 512FBk, 512FFb Zero-phase voltage calculation unit 512FF, 513FF Feed forward unit 513 Voltage current suppression unit 513FBk, 513FFg Circulation current calculation unit 513FFb Upper limit limit unit 513FFe Amplification unit 522u, 522v, 522w , 524v, 524w P control unit 525u, 525v, 525w First addition unit 526u, 526v, 526w Second addition unit 527u, 527v, 527w First calculation unit 528u, 5 28v, 528w Second calculation unit C1, C2 Capacitors Da, Db, Dc, Dd Refluxing diodes Ma, Mb, Mc, Md Semiconductor module PS Power control system Qa, Qb, Qc, Qd Semiconductor switch

Claims (10)

Multiple legs each with a first arm and a second arm connected in series,
A first connection portion in which ends of both ends of the first arm provided on each of the plurality of legs, which are not connected to the second arm, are connected to each other.
A second connecting portion in which the ends of both ends of the second arm provided on each of the plurality of legs, which are not connected to the first arm, are connected to each other.
It is equipped with a control device that controls the plurality of legs.
The first arm is connected in series to the first power conversion circuit cell having two semiconductor switches connected in series and a power storage element connected in parallel to the two semiconductor switches, and the first power conversion circuit cell. With the first coil
The second arm is connected in series to the second power conversion circuit cell having two semiconductor switches connected in series and a power storage element connected in parallel to the two semiconductor switches, and the second power conversion circuit cell. Has a second coil and
The control device adjusts the same voltage component contained in each of the first voltage of the first connection portion and the second voltage of the second connection portion, and flows in and out between each of the plurality of legs. (I) A power conversion device having a power control unit that controls electric power. The power conversion device according to claim 1, wherein the first electric power is electric power generated by a current flowing between each of the plurality of legs and the electric power system and the voltage component. A detection unit for detecting the stored energy of the power storage element or an amount equivalent to the stored energy is provided.
The power conversion device according to claim 1 or 2, wherein the power control unit includes an adjustment unit that adjusts the voltage component according to a detected value detected by the detection unit. The power conversion device according to claim 3, wherein the power storage element has a capacitor. The power conversion device according to claim 4, wherein the detection unit detects the voltage of the capacitor as the equivalent amount. The power conversion device according to claim 4 or 5, wherein the power control unit adjusts the first power of the plurality of legs so as to suppress an unbalanced state of power between the plurality of legs. The power control unit controls the second power by adjusting at least one of the voltage difference between the first voltage and the second voltage and the circulating current flowing through each of the plurality of legs. The power conversion device according to any one item. The power conversion device according to claim 7, wherein the power control unit includes a calculation unit that calculates the circulating current using the current flowing through the first arm and the current flowing through the second arm. The control device can output the injection ratio of the first power controlled based on the adjustment of the voltage component and the second power based on the adjustment of the circulating current to the first arm and the second arm. The power according to claim 7 or 8, which is adjusted based on a value based on the maximum voltage, a value based on the voltage of the connection portion of the first coil and the second coil, the voltage component, and the voltage difference. Conversion device. The power storage element has a secondary battery connected in parallel to the two semiconductor switches.
The power control unit is any of claims 1 to 9 that detects the difference between the remaining capacity of the secondary battery provided in the first arm and the remaining capacity of the secondary battery provided in the second arm. The power conversion device according to one item.

Images