CN117439395A - Bus voltage equalizing method, device, equipment and storage medium - Google Patents
Bus voltage equalizing method, device, equipment and storage medium Download PDFInfo
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- CN117439395A CN117439395A CN202311716728.XA CN202311716728A CN117439395A CN 117439395 A CN117439395 A CN 117439395A CN 202311716728 A CN202311716728 A CN 202311716728A CN 117439395 A CN117439395 A CN 117439395A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
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Abstract
The invention relates to the technical field of control of power electronic equipment, and discloses a bus voltage equalizing method, a device, equipment and a storage medium, wherein the method comprises the following steps: acquiring a voltage deviation value between positive and negative buses of a target converter to determine a voltage adjustment value; proportional integral processing is carried out on the voltage adjustment value, and a target harmonic current amplitude is obtained; acquiring a fundamental wave phase angle of the grid voltage on the fundamental wave component to determine a target harmonic current phase angle; processing the target harmonic current amplitude based on the target harmonic current phase angle to obtain d and q axis current instruction compensation values; adjusting the pre-acquired d and q axis current command original values based on the d and q axis current command compensation values to obtain d and q axis current command target values; and driving the target converter based on the d-axis current command target value and the q-axis current command target value so as to balance the voltages of the positive bus and the negative bus. The invention can solve the problem of poor bus voltage equalizing capability of the multi-level topological converter.
Description
Technical Field
The invention relates to the technical field of control of power electronic equipment, in particular to a bus voltage equalizing method and device, electronic equipment and a computer readable storage medium.
Background
In a multilevel topology converter, positive and negative bus capacitors are usually arranged, and if the difference between the positive and negative buses is too large, the voltage of the bus capacitors exceeds the rated withstand voltage, so that the withstand voltage of each component is insufficient and damage occurs. Therefore, in the related art, a common-mode voltage injection method is mainly adopted to perform voltage equalizing on positive and negative buses of the multi-level topological converter. However, in this mode of common-mode voltage injection, the bus voltage equalizing capability is positively correlated with the load current, and when the load current is small, the bus voltage equalizing capability is poor.
Disclosure of Invention
In view of the above, the invention provides a bus voltage equalizing method, a device, equipment and a storage medium, which are used for solving the problem of poor bus voltage equalizing capability of a multilevel topological converter.
In order to achieve the above object, the present invention provides a bus voltage equalizing method, including:
acquiring a voltage deviation value between positive and negative buses of a target converter to determine a voltage adjustment value;
proportional integral processing is carried out on the voltage adjustment value, and a target harmonic current amplitude value is obtained;
acquiring a fundamental wave phase angle of the grid voltage on the fundamental wave component to determine a target harmonic current phase angle;
processing the target harmonic current amplitude based on the target harmonic current phase angle to obtain d and q axis current instruction compensation values;
adjusting the pre-acquired d and q axis current command original values based on the d and q axis current command compensation values to obtain d and q axis current command target values;
and driving the target converter based on the d-axis current command target value and the q-axis current command target value so as to balance the voltages of the positive bus and the negative bus.
As an improvement of the above solution, the proportional-integral processing is performed on the voltage adjustment value to obtain a target harmonic current amplitude, including:
obtaining an integral control coefficient based on the ratio of a preset integral coefficient to a Laplacian;
obtaining a proportional integral coefficient based on the sum of a preset proportional coefficient and the integral control coefficient;
and obtaining the target harmonic current amplitude based on the product of the voltage adjustment value and the proportional-integral coefficient.
As an improvement of the above solution, the obtaining the fundamental phase angle of the grid voltage on the fundamental component to determine the target harmonic current phase angle includes:
acquiring an initial value of a harmonic current phase angle;
obtaining a target phase angle based on the product of the preset harmonic frequency and the fundamental wave phase angle;
and obtaining the target harmonic current phase angle based on the sum of the target phase angle and the initial value.
As an improvement of the above solution, the processing the target harmonic current amplitude based on the target harmonic current phase angle to obtain d-axis and q-axis current command compensation values includes:
calculating cosine and sine values of the phase angle of the target harmonic current;
obtaining a d-axis current instruction compensation value based on the product of the target harmonic current amplitude and the cosine value;
and obtaining a q-axis current command compensation value based on the product of the target harmonic current amplitude and the sine value.
As an improvement of the above solution, the adjusting the pre-obtained d and q axis current command original values based on the d and q axis current command compensation values to obtain d and q axis current command target values includes:
obtaining a d-axis current instruction target value based on a sum of a d-axis current instruction compensation value and a d-axis current instruction original value obtained in advance;
and obtaining a q-axis current command target value based on the sum of the q-axis current command compensation value and a pre-obtained q-axis current command original value.
As an improvement of the above-mentioned aspect, the driving the target converter based on the d-axis current command target value and the q-axis current command target value to equalize the voltages of the positive and negative buses includes:
three-phase currents on the alternating current side of the target converter are obtained, and coordinate transformation is carried out on the three-phase currents to obtain d-axis and q-axis target currents;
inputting the d and q-axis target currents and the d and q-axis current instruction target values into a target current loop, and outputting to obtain d and q-axis modulation waves;
coordinate transformation is carried out on the d and q axis modulation waves to obtain three-phase modulation waves;
and driving the target converter based on the three-phase modulation wave so as to balance the voltages of the positive bus and the negative bus.
As an improvement of the above solution, the obtaining the voltage deviation value between the positive bus and the negative bus of the target converter to determine the voltage adjustment value includes:
acquiring positive bus voltage and negative bus voltage of the target converter;
obtaining a voltage deviation value based on the difference value of the positive bus voltage and the negative bus voltage;
and obtaining the voltage adjustment value based on a difference value between a preset voltage deviation instruction value and the voltage deviation value.
In order to achieve the above object, an embodiment of the present invention further provides a busbar capacitance voltage equalizing device, including:
the bus voltage detection module is used for acquiring a voltage deviation value between the positive bus and the negative bus of the target converter so as to determine a voltage adjustment value;
the harmonic amplitude generation module is used for carrying out proportional integral processing on the voltage adjustment value to obtain a target harmonic current amplitude;
the harmonic phase angle generating module is used for acquiring the fundamental phase angle of the power grid voltage on the fundamental component so as to determine a target harmonic current phase angle;
the current command compensation module is used for processing the target harmonic current amplitude based on the target harmonic current phase angle to obtain d and q axis current command compensation values;
the current instruction generation module is used for adjusting the pre-acquired d and q axis current instruction original values based on the d and q axis current instruction compensation values to obtain d and q axis current instruction target values;
and the bus voltage balancing module is used for driving the target converter based on the d-axis current command target value and the q-axis current command target value so as to balance the voltages of the positive bus and the negative bus.
In order to achieve the above object, an embodiment of the present invention further provides an electronic device, including: the bus voltage equalizing method comprises a memory and a processor, wherein the memory and the processor are in communication connection, computer instructions are stored in the memory, and the processor executes the computer instructions, so that the bus voltage equalizing method of any embodiment is executed.
To achieve the above object, an embodiment of the present invention further provides a computer-readable storage medium, on which computer instructions are stored, the computer instructions being configured to cause a computer to execute the bus bar voltage equalizing method according to any one of the above embodiments.
Compared with the prior art, the bus voltage equalizing method, device, equipment and storage medium provided by the embodiment of the invention have the advantages that firstly, the voltage adjustment value is determined through the voltage deviation value between the positive bus and the negative bus so as to calculate and obtain the target harmonic current amplitude; secondly, calculating a target harmonic current phase angle to convert the target harmonic current amplitude into d-axis and q-axis current instruction compensation values; then, adjusting the original values of the d and q-axis current instructions according to the d and q-axis current instruction compensation values; and finally, driving the target converter according to the adjusted d-axis current and q-axis current instruction target values. According to the invention, the d-axis current command compensation value and the q-axis current command compensation value of the harmonic current are superposed on the basis of the universal d-axis current command original value and the q-axis current command original value, so that the current command original value can be actively compensated when the voltages of the positive bus and the negative bus are unbalanced, and the corresponding harmonic current is injected, so that the expected midpoint current flowing into the midpoint of the bus or flowing out of the midpoint of the bus is generated, and the purpose of bus voltage equalizing is achieved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a bus bar voltage equalizing method according to an embodiment of the invention;
FIG. 2 is a block diagram of a three-phase three-level diode neutral point clamped topology current transformer in accordance with an embodiment of the present invention;
FIG. 3 is a control block diagram of a bus bar voltage equalizing method according to an embodiment of the present invention;
FIG. 4 is a control block diagram of a bus bar equalizing ring according to an embodiment of the present invention;
fig. 5 is a waveform diagram of positive and negative bus voltages of a current transformer according to an embodiment of the present invention;
fig. 6 is a block diagram of a busbar capacitance equalizing device according to an embodiment of the present invention;
fig. 7 is a block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The multilevel topological structure is widely applied to the fields of industrial transmission, electrified traffic, new energy power generation, energy storage and the like by virtue of the advantages of higher voltage level and better electric energy quality. In the current transformer with multilevel topology, a positive bus capacitor and a negative bus capacitor are usually provided, and if the difference between the positive bus capacitor and the negative bus capacitor is too large, the voltage of the bus capacitor exceeds the rated withstand voltage, so that the withstand voltage of each component is insufficient and damage occurs. Therefore, the voltage equalizing capability of the positive and negative buses under all working conditions is critical to the long-term safe and stable operation of the system.
Currently, in the related art, a common-mode voltage injection method is mainly adopted to perform voltage equalizing on positive and negative buses of a multi-level topological converter. However, in this mode of common-mode voltage injection, the bus voltage equalizing capability is positively correlated with the load current, and when the load current is small, the bus voltage equalizing capability is poor.
In view of the foregoing, it will be appreciated that in accordance with embodiments of the present invention there is provided a bus bar grading method embodiment, it will be appreciated that the steps illustrated in the flowchart of the figures may be performed in a computer system, such as a set of computer executable instructions, and that, although a logical sequence is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in a different order than what is illustrated herein.
In this embodiment, a bus voltage equalizing method is provided, which may be used for the above-mentioned multilevel topology converter, for example: fig. 1 is a flowchart of a bus voltage equalizing method according to an embodiment of the present invention, as shown in fig. 1, the flowchart includes the following steps:
and S11, acquiring a voltage deviation value between the positive bus and the negative bus of the target converter to determine a voltage adjustment value.
And step S12, performing proportional integral processing on the voltage adjustment value to obtain a target harmonic current amplitude.
And step S13, acquiring a fundamental wave phase angle of the grid voltage on the fundamental wave component so as to determine a target harmonic current phase angle.
And step S14, processing the target harmonic current amplitude based on the target harmonic current phase angle to obtain d and q axis current instruction compensation values.
And step S15, the d and q-axis current command original values obtained in advance are adjusted based on the d and q-axis current command compensation values, so as to obtain d and q-axis current command target values.
And S16, driving the target converter based on the d-axis current command target value and the q-axis current command target value so as to balance the voltages of the positive bus and the negative bus.
According to the busbar voltage equalizing method provided by the embodiment, firstly, a voltage adjustment value is determined through a voltage deviation value between positive and negative busbars so as to calculate and obtain a target harmonic current amplitude; secondly, calculating a target harmonic current phase angle to convert the target harmonic current amplitude into d-axis and q-axis current instruction compensation values; then, adjusting the original values of the d and q-axis current instructions according to the d and q-axis current instruction compensation values; and driving the target converter according to the adjusted d-axis current and q-axis current command target values. According to the invention, the d-axis current command compensation value and the q-axis current command compensation value of the harmonic current are superposed on the basis of the universal d-axis current command original value and the q-axis current command original value, so that the current command original value can be actively compensated when the voltages of the positive bus and the negative bus are unbalanced, and the corresponding harmonic current is injected, so that the expected midpoint current flowing into the midpoint of the bus or flowing out of the midpoint of the bus is generated, and the purpose of bus voltage equalizing is achieved.
By way of example, as shown in fig. 2, a three-phase three-level diode neutral-point clamped topology converter is exemplified, which consists of 12 insulated gate bipolar transistors and 6 diodes, as shown in fig. 2For midpoint current +.>For DC bus voltage +.>Positive bus voltage, ">Negative bus voltage, ">Is a bus capacitor>For phase A current, +.>For B-phase current, ">Is the C phase current. In the bus voltage equalizing method based on common mode voltage injection, bus voltage equalizing capability is related to the injection capability of the midpoint current of fig. 2, and the midpoint current is positively related to the load current. Therefore, it is often difficult to achieve a small or even zero load currentTo actively generate additional midpoint current for bus voltage equalizing, thereby resulting in poor bus voltage equalizing capability. Compared with the bus voltage equalizing method of common mode voltage injection, the invention calculates the target harmonic current amplitude and the target harmonic current phase angle according to the positive and negative bus voltage and the fundamental wave phase angle of the grid voltage on the fundamental wave component to generate d and q axis current command compensation values of the harmonic current, adjusts the original d and q axis current command original values through the d and q axis current command compensation values and controls the bus voltage equalizing method based on the adjusted d and q axis current command target values, thus the invention can actively inject the harmonic current to generate the midpoint current expected to flow into or flow out of the midpoint of the bus, and realize the voltage equalizing control of the bus/bus capacitor. Therefore, compared with a bus voltage equalizing method of common-mode voltage injection, the bus voltage equalizing method has stronger voltage equalizing capability even under low load current, and is beneficial to improving the long-term safe and stable operation capability of the multi-level topology under all working conditions.
As an alternative embodiment, the step S11 includes: acquiring positive bus voltage and negative bus voltage of a target converter; obtaining a voltage deviation value based on the difference value of the positive bus voltage and the negative bus voltage; and obtaining a voltage adjustment value based on a difference value between the preset voltage deviation command value and the voltage deviation value.
The voltage deviation command value is usually 0, so as to control the voltage of the positive bus to be equal to the voltage of the negative bus, and the voltage deviation command value may be determined according to an allowable deviation value between the positive bus and the negative bus, and the specific value of the voltage deviation command value is not limited.
As an alternative embodiment, the step S12 includes: obtaining an integral control coefficient based on the ratio of a preset integral coefficient to a Laplacian; obtaining a proportional integral coefficient based on the sum of a preset proportional coefficient and an integral control coefficient; and obtaining the target harmonic current amplitude based on the product of the voltage adjustment value and the proportional-integral coefficient.
Optionally, the preset scaling factor isThe preset integral coefficient is +.>The method comprises the steps of carrying out a first treatment on the surface of the Wherein C is the capacitance value of the bus capacitor, < >>To control bandwidth +.>Is a preset proportionality coefficient. Optionally, ->100rad/s.
As an alternative embodiment, the step S13 includes: acquiring an initial value of a harmonic current phase angle; obtaining a target phase angle based on the product of the preset harmonic frequency and the fundamental phase angle; and obtaining the target harmonic current phase angle based on the sum of the target phase angle and the initial value.
Optionally, the preset harmonic frequency is 3, and the range of the initial value of the phase angle of the harmonic current isTo->。
It should be noted that, the fundamental phase angle of the grid voltage on the fundamental component is usually obtained by a control link such as a phase-locked loop, and the specific acquisition method can refer to other related documents, which are not repeated here.
As an alternative embodiment, the step S14 includes: calculating cosine and sine values of a target harmonic current phase angle; obtaining a d-axis current instruction compensation value based on the product of the target harmonic current amplitude and the cosine value; and obtaining a q-axis current command compensation value based on the product of the target harmonic current amplitude and the sine value.
In some alternative embodiments, the step S15 includes: obtaining a d-axis current instruction target value based on a sum of a d-axis current instruction compensation value and a d-axis current instruction original value obtained in advance; and obtaining a q-axis current command target value based on the sum of the q-axis current command compensation value and a pre-obtained q-axis current command original value.
The d-axis current command original value and the q-axis current command original value are universal active and reactive d-axis current commands and q-axis current command original values can be obtained by other given methods of d-axis current commands and q-axis current commands in related multi-level topologies. For example: the d-axis current command original value is obtained by dividing active power by voltage, or is the output value of a direct-current voltage outer ring.
It can be understood that, in the embodiment of the invention, when general reactive power d and q axes are instructed, harmonic current instruction values (i.e. current instruction compensation values) are overlapped, and the busbar voltage equalizing control is realized by the newly increased degree of freedom of regulation.
In some alternative embodiments, the step S16 includes: three-phase currents on the alternating current side of the target converter are obtained, and coordinate transformation is carried out on the three-phase currents to obtain d-axis and q-axis target currents; d, q-axis target currents and d, q-axis current instruction target values are input into a target current loop, and d, q-axis modulation waves are output; coordinate transformation is carried out on the d and q-axis modulated waves to obtain three-phase modulated waves; and driving the target converter based on the three-phase modulation wave so as to balance the voltages of the positive bus and the negative bus.
Specifically, the driving of the target converter based on the three-phase modulation wave to equalize the voltages of the positive and negative bus bars includes: generating a driving signal based on the three-phase modulated wave; and driving the target converter based on the driving signal so as to balance the voltages of the positive bus and the negative bus.
Illustratively, as shown in fig. 3, the overall flow of the bus bar voltage equalizing method of the present invention is as follows: 1. sampling three-phase current to obtain three-phase current of alternating current side of the converter: phase A currentB phase current->C phase current->. 2. Transforming the three-phase current through abc/dq coordinates to obtain d-axis target current in dq synchronous coordinate system>Q-axis target current->. 3. Target current +.>、As input to the current loop. 4. Current loop control->And->D-axis current command target value +.>And q-axis current command target value +.>. 5. D-axis modulation wave +/in current loop output dq synchronous coordinate system>Q-axis modulated wave->. 6. Modulating the wave with d-axis->Q-axis modulated wave->Three-phase modulation waves are obtained through dq/abc coordinate transformation: a phase modulated wave->B-phase modulated wave->C-phase modulated wave->. 7. In the modulation and driving module, three-phase modulation waves are compared with carrier waves to generate driving signals to drive the converter, so that electric energy conversion is realized.
Further, as shown in fig. 4, the specific control flow of the bus equalizing ring is as follows:
1. collecting the positive bus voltageMinus bus voltage +.>Obtaining a voltage deviation value->。
2. Command value of voltage deviationMinus the voltage deviation value>Obtaining an error value of bus voltage deviation +.>I.e. the voltage adjustment value. In fig. 4, the voltage deviation command value is 0.
3. Voltage regulation valueThe target harmonic current amplitude is obtained through a proportional integral link (namely PI control in figure 4)。
Specifically, the target harmonic current amplitudeThe method comprises the steps of carrying out a first treatment on the surface of the Wherein (1)>For a preset integral coefficient s is Laplacian,/and>is a preset proportionality coefficient.
4. Acquiring fundamental wave phase angle of grid voltage in fundamental wave componentFundamental phase angle->Obtaining the target harmonic current phase angle through a target harmonic current phase angle generation link>。
Specifically, taking 3 preset harmonic times as an example, the target harmonic current phase angleThe method comprises the steps of carrying out a first treatment on the surface of the Wherein (1)>For fundamental phase angle>Is the initial value of the phase angle of the harmonic current.
5. Amplitude of target harmonic currentCosine value multiplied by the phase angle of the target harmonic current +.>Obtaining d-axis current command compensation value +.>The method comprises the steps of carrying out a first treatment on the surface of the Target harmonic current amplitude +.>Sine value multiplied by the phase angle of the target harmonic current +.>Obtaining the q-axis current command compensation value +.>。
6. Obtaining the original value of d-axis current instructionAnd q-axis current command original value +.>The d-axis current command original value is +.>Add d-axis current command compensation value +.>Obtaining d-axis current instruction target value +.>The method comprises the steps of carrying out a first treatment on the surface of the The q-axis current is instructed to be the original valuePlus q-axis current command offset value +.>Obtaining a q-axis current command target value +.>。
7. Commanded d-axis current target valueAnd q-axis current command target value +.>And fed back to the current loop.
For example, in order to embody the beneficial effects of the bus voltage equalizing method provided by the embodiment of the invention, the voltage of the direct current bus is used1000V, the capacitance value of the bus capacitor of the positive bus and the negative bus is C, and the bandwidth is controlled +.>The ratio coefficient is preset to be 100rad/s>2->C, preset integral coefficient->Is->An initial value of the phase angle of the harmonic current +.>For 45 ° as an example, a bus voltage waveform using a common mode voltage injection voltage equalizing method and a bus voltage equalizing method of the present invention was compared and analyzed. When the load current is small, as shown in fig. 5, the bus voltage equalizing method using common mode voltage injection is adopted at the left side of time t1, and as can be seen from fig. 5, at this time, the positive bus voltage +.>And negative bus voltage>There is a significant deviation. On the right side of time t1, the busbar equalizing method of the present invention is adopted, and as can be seen from FIG. 5, after time t1, the positive busbar voltage +.>And negative bus voltage>Gradually restoring consistency. Therefore, the bus voltage equalizing method based on harmonic current injection can effectively improve the bus voltage equalizing capability of the multi-level topological converter when the load current is smaller, so as to ensure the long-term safe and stable operation capability of the multi-level topological converter under all working conditions.
In this embodiment, a busbar capacitance voltage equalizing device is further provided, and the device is used to implement the foregoing embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The present embodiment provides a busbar capacitance voltage equalizing device, as shown in fig. 6, including:
the busbar voltage detection module 21 is used for acquiring a voltage deviation value between the positive busbar and the negative busbar of the target converter so as to determine a voltage adjustment value;
the harmonic amplitude generating module 22 is configured to perform proportional integral processing on the voltage adjustment value to obtain a target harmonic current amplitude;
a harmonic phase angle generating module 23, configured to obtain a fundamental phase angle of the grid voltage on the fundamental component, so as to determine a target harmonic current phase angle;
the current command compensation module 24 is used for processing the target harmonic current amplitude based on the target harmonic current phase angle to obtain d and q axis current command compensation values;
the current command generating module 25 is configured to adjust the pre-acquired d-axis current command original values and q-axis current command original values based on the d-axis current command compensation values and q-axis current command target values;
and the bus voltage balancing module 26 is used for driving the target converter based on the d-axis current command target value and the q-axis current command target value so as to balance the voltages of the positive bus and the negative bus.
In some alternative embodiments, the bus voltage detection module 21 includes:
the bus voltage acquisition unit is used for acquiring the positive bus voltage and the negative bus voltage of the target converter;
the voltage deviation calculating unit is used for obtaining a voltage deviation value based on the difference value of the positive bus voltage and the negative bus voltage;
the deviation error calculation unit is used for obtaining a voltage adjustment value based on a difference value between a preset voltage deviation instruction value and a voltage deviation value.
In some alternative embodiments, the harmonic amplitude generation module 22 includes:
the first coefficient calculation unit is used for obtaining an integral control coefficient based on the ratio of a preset integral coefficient to the Laplacian;
the second coefficient calculation unit is used for obtaining a proportional integral coefficient based on the sum value of a preset proportional coefficient and an integral control coefficient;
and the harmonic amplitude generating unit is used for obtaining the target harmonic current amplitude based on the product of the voltage adjustment value and the proportional integral coefficient.
In some alternative embodiments, the harmonic phase angle generation module 23 includes:
the initial value acquisition unit is used for acquiring an initial value of a harmonic current phase angle;
the target phase angle calculation unit is used for obtaining a target phase angle based on the product of the preset harmonic frequency and the fundamental phase angle;
and the harmonic phase angle calculation unit is used for obtaining the target harmonic current phase angle based on the sum value of the target phase angle and the initial value.
In some alternative embodiments, the current command compensation module 24 includes:
the harmonic current phase angle processing unit is used for calculating a cosine value and a sine value of a target harmonic current phase angle;
the first compensation value calculation unit is used for obtaining a d-axis current instruction compensation value based on the product of the target harmonic current amplitude and the cosine value;
and the second compensation value calculation unit is used for obtaining a q-axis current command compensation value based on the product of the target harmonic current amplitude and the sine value.
In some alternative embodiments, the current command generation module 25 includes:
the first current instruction calculation unit is used for obtaining a d-axis current instruction target value based on a sum of a d-axis current instruction compensation value and a d-axis current instruction original value obtained in advance;
and a second current command calculation unit for obtaining a q-axis current command target value based on a sum of the q-axis current command compensation value and a q-axis current command original value obtained in advance.
In some alternative embodiments, bus voltage equalization module 26 includes:
the current acquisition unit is used for acquiring three-phase current of the alternating-current side of the target converter, and carrying out coordinate transformation on the three-phase current to obtain d-axis and q-axis target current;
the current modulation unit is used for inputting d and q-axis target currents and d and q-axis current instruction target values into a target current loop and outputting d and q-axis modulation waves;
the coordinate transformation unit is used for carrying out coordinate transformation on the d-axis modulated wave and the q-axis modulated wave to obtain a three-phase modulated wave;
and the voltage balancing unit is used for driving the target converter based on the three-phase modulation wave so as to balance the voltages of the positive bus and the negative bus.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The busbar capacitance equalizing device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit ) circuit, a processor and a memory executing one or more software or fixed programs, and/or other devices that can provide the above functions.
Referring to fig. 7, a schematic structural diagram of an electronic device according to an embodiment of the present invention is provided.
An electronic device provided in an embodiment of the present invention includes a processor 31, a memory 32, and a computer program stored in the memory 32 and configured to be executed by the processor 31, where the processor 31 executes the computer program to implement the bus bar voltage equalizing method according to any one of the embodiments.
The processor 31, when executing a computer program, implements the steps of the busbar grading method embodiment described above, such as all the steps of the busbar grading method shown in fig. 1. Alternatively, the processor 31, when executing a computer program, performs the functions of the modules/units of the busbar capacitance grading device embodiment described above, such as the functions of the modules of the busbar capacitance grading device shown in fig. 6.
By way of example, a computer program may be split into one or more modules, which are stored in the memory 32 and executed by the processor 31 to complete the present invention. One or more of the modules may be a series of computer program instruction segments capable of performing particular functions for describing the execution of the computer program in an electronic device.
The electronic device may be a computing device such as a desktop computer, a notebook computer, a palm computer, a cloud server, and the like. The electronic device may include, but is not limited to, a processor 31, a memory 32. It will be appreciated by those skilled in the art that fig. 7 is merely an example of an electronic device and is not meant to be limiting, and that more or fewer components than shown may be included, or that certain components may be combined, or that different components may be included, for example, an electronic device may also include an input-output device, a network access device, a bus, etc.
The processor 31 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, and the processor 31 is a control center of the electronic device, with various interfaces and lines connecting various parts of the overall electronic device.
The memory 32 may be used to store computer programs and/or modules, and the processor 31 implements various functions of the electronic device by running or executing the computer programs and/or modules stored in the memory 32 and invoking data stored in the memory 32. The memory 32 may mainly include a storage program area that may store an operating system, application programs required for at least one function, and the like, and a storage data area; the storage data area may store data created according to the use of the electronic device, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, smart Media Card (SMC), secure Digital (SD) Card, flash Card (Flash Card), at least one disk storage device, flash memory device, or other volatile solid-state storage device.
Wherein the integrated modules/units of the electronic device may be stored in a computer readable storage medium if implemented in the form of software functional units and sold or used as stand alone products. Based on such understanding, the present invention may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, and the computer program may be stored in a computer readable storage medium, where the computer program, when executed by a processor, may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, executable files or in some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software development medium, and so forth.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (10)
1. A bus voltage equalizing method, characterized in that the method comprises:
acquiring a voltage deviation value between positive and negative buses of a target converter to determine a voltage adjustment value;
proportional integral processing is carried out on the voltage adjustment value, and a target harmonic current amplitude value is obtained;
acquiring a fundamental wave phase angle of the grid voltage on the fundamental wave component to determine a target harmonic current phase angle;
processing the target harmonic current amplitude based on the target harmonic current phase angle to obtain d and q axis current instruction compensation values;
adjusting the pre-acquired d and q axis current command original values based on the d and q axis current command compensation values to obtain d and q axis current command target values;
and driving the target converter based on the d-axis current command target value and the q-axis current command target value so as to balance the voltages of the positive bus and the negative bus.
2. The bus voltage equalizing method according to claim 1, wherein the proportional-integral processing of the voltage adjustment value to obtain a target harmonic current amplitude comprises:
obtaining an integral control coefficient based on the ratio of a preset integral coefficient to a Laplacian;
obtaining a proportional integral coefficient based on the sum of a preset proportional coefficient and the integral control coefficient;
and obtaining the target harmonic current amplitude based on the product of the voltage adjustment value and the proportional-integral coefficient.
3. The bus bar voltage grading method according to claim 1 wherein the acquiring the fundamental phase angle of the grid voltage on the fundamental component to determine the target harmonic current phase angle comprises:
acquiring an initial value of a harmonic current phase angle;
obtaining a target phase angle based on the product of the preset harmonic frequency and the fundamental wave phase angle;
and obtaining the target harmonic current phase angle based on the sum of the target phase angle and the initial value.
4. The bus voltage equalizing method according to claim 1, wherein said processing said target harmonic current amplitude based on said target harmonic current phase angle to obtain d, q-axis current command compensation values comprises:
calculating cosine and sine values of the phase angle of the target harmonic current;
obtaining a d-axis current instruction compensation value based on the product of the target harmonic current amplitude and the cosine value;
and obtaining a q-axis current command compensation value based on the product of the target harmonic current amplitude and the sine value.
5. The bus bar equalizing method according to claim 1, wherein said adjusting the pre-acquired d, q-axis current command original values based on the d, q-axis current command compensation values to obtain d, q-axis current command target values comprises:
obtaining a d-axis current instruction target value based on a sum of a d-axis current instruction compensation value and a d-axis current instruction original value obtained in advance;
and obtaining a q-axis current command target value based on the sum of the q-axis current command compensation value and a pre-obtained q-axis current command original value.
6. The bus bar voltage equalizing method according to claim 1, wherein driving the target converter based on the d, q-axis current command target values to equalize the voltages of the positive and negative bus bars comprises:
three-phase currents on the alternating current side of the target converter are obtained, and coordinate transformation is carried out on the three-phase currents to obtain d-axis and q-axis target currents;
inputting the d and q-axis target currents and the d and q-axis current instruction target values into a target current loop, and outputting to obtain d and q-axis modulation waves;
coordinate transformation is carried out on the d and q axis modulation waves to obtain three-phase modulation waves;
and driving the target converter based on the three-phase modulation wave so as to balance the voltages of the positive bus and the negative bus.
7. The bus bar voltage equalizing method as set forth in claim 1, wherein the obtaining a voltage deviation value between positive and negative bus bars of the target converter to determine the voltage adjustment value comprises:
acquiring positive bus voltage and negative bus voltage of the target converter;
obtaining a voltage deviation value based on the difference value of the positive bus voltage and the negative bus voltage;
and obtaining the voltage adjustment value based on a difference value between a preset voltage deviation instruction value and the voltage deviation value.
8. A busbar capacitance voltage equalizing device, characterized in that the device comprises:
the bus voltage detection module is used for acquiring a voltage deviation value between the positive bus and the negative bus of the target converter so as to determine a voltage adjustment value;
the harmonic amplitude generation module is used for carrying out proportional integral processing on the voltage adjustment value to obtain a target harmonic current amplitude;
the harmonic phase angle generating module is used for acquiring the fundamental phase angle of the power grid voltage on the fundamental component so as to determine a target harmonic current phase angle;
the current command compensation module is used for processing the target harmonic current amplitude based on the target harmonic current phase angle to obtain d and q axis current command compensation values;
the current instruction generation module is used for adjusting the pre-acquired d and q axis current instruction original values based on the d and q axis current instruction compensation values to obtain d and q axis current instruction target values;
and the bus voltage balancing module is used for driving the target converter based on the d-axis current command target value and the q-axis current command target value so as to balance the voltages of the positive bus and the negative bus.
9. An electronic device, comprising:
a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the bus bar voltage sharing method of any one of claims 1 to 7.
10. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the bus bar voltage equalizing method according to any one of claims 1 to 7.
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