JP2017059783A - Semiconductor device - Google Patents
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- JP2017059783A JP2017059783A JP2015185917A JP2015185917A JP2017059783A JP 2017059783 A JP2017059783 A JP 2017059783A JP 2015185917 A JP2015185917 A JP 2015185917A JP 2015185917 A JP2015185917 A JP 2015185917A JP 2017059783 A JP2017059783 A JP 2017059783A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000004020 conductor Substances 0.000 claims abstract description 24
- 230000000694 effects Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- 239000011521 glass Substances 0.000 description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 12
- 229910052698 phosphorus Inorganic materials 0.000 description 12
- 239000011574 phosphorus Substances 0.000 description 12
- 239000005380 borophosphosilicate glass Substances 0.000 description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 10
- 229910052796 boron Inorganic materials 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 8
- 239000012535 impurity Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
本発明は、活性領域の外側に耐圧を改善するエッジ領域を備える半導体装置に関する。 The present invention relates to a semiconductor device including an edge region that improves a breakdown voltage outside an active region.
第１導電型の半導体基体とｐｎ接合するように、第１導電型と反対の導電型の第２導電型から成るリサーフ領域と、リサーフ領域上に容量性フィールドプレートを設けた半導体装置の構造が特許文献１の図１１等に開示されている。 A semiconductor device having a resurf region composed of a second conductivity type opposite to the first conductivity type and a capacitive field plate on the resurf region so as to form a pn junction with the first conductivity type semiconductor substrate. It is disclosed in FIG.
例えば、スイッチング素子を含む活性領域の外側の半導体基体のエッジ領域に、不純物濃度が１×１０１７〜１×１０１８[／cm3]のベース領域よりも薄い不純物濃度（１×１０15〜１×１０17[／cm3]）のリサーフ領域がある。リサーフ領域は、半導体基体の空乏層を活性領域よりも離れる方向へとより延伸させて、空乏層の曲率をなだらかにする事ができる。しかし、リサーフ領域の不純物濃度は低く、半導体基体の外側の外部イオンの影響をリサーフ領域は受け易いので、リサーフ領域は容易に空乏化してしまう。その結果、リサーフ領域の表面電位が外部イオンの影響を受けて安定化しないという問題があった。 For example, in the edge region of the semiconductor substrate outside the active region including the switching element, the impurity concentration (1 × 10 15 -1) is lower than the base region having an impurity concentration of 1 × 10 17 to 1 × 10 18 [/ cm 3 ]. × 10 17 [/ cm 3 ]). In the RESURF region, the depletion layer of the semiconductor substrate can be further extended in a direction away from the active region, and the curvature of the depletion layer can be made gentle. However, since the impurity concentration of the RESURF region is low and the RESURF region is easily affected by external ions outside the semiconductor substrate, the RESURF region is easily depleted. As a result, there has been a problem that the surface potential of the RESURF region is not stabilized under the influence of external ions.
そこで、この問題を解決するため、リサーフ領域の上方に容量性のＦＰを設ける構造が特許文献１の図１１等で知られている。容量性ＦＰは隣り合うポリシリコン等の導体膜の間にコンデンサ（容量）が生じる。よって、容量性フィールドプレートは、この多数のコンデンサが高電位（コレクタ又はドレイン電位）側から低電位（ゲート又はエミッタ又はソース電位）側に直列に接続される構造となっている。この導体膜に印加された電位が半導体基体上のリサーフ領域の表面電位を安定化させる。その結果、外部イオンによるリサーフ領域表面における電位の影響を抑制することができる。 In order to solve this problem, a structure in which a capacitive FP is provided above the RESURF region is known from FIG. In the capacitive FP, a capacitor (capacitance) is generated between adjacent conductive films such as polysilicon. Therefore, the capacitive field plate has a structure in which a large number of capacitors are connected in series from the high potential (collector or drain potential) side to the low potential (gate or emitter or source potential) side. The potential applied to the conductor film stabilizes the surface potential of the RESURF region on the semiconductor substrate. As a result, the influence of the potential on the surface of the RESURF region due to external ions can be suppressed.
ｎ−領域内にリサーフ領域がある場合、リサーフ領域の端からｎ−領域端（半導体基体の端）までの距離が短くなる。リサーフ領域の外側のｎ−領域表面と容量性ＦＰを構成する導体膜との間に設けた絶縁膜の厚みが、リサーフ領域上の容量性ＦＰを構成する導体膜と基板表面までの絶縁膜の厚みと同じであると、容量性ＦＰによる電位分割の効果が強く、ｎ−領域端に空乏層が容易に到達してしまうという問題があった。 When there is a RESURF region in the n− region, the distance from the end of the RESURF region to the end of the n− region (end of the semiconductor substrate) is shortened. The thickness of the insulating film provided between the n-region surface outside the RESURF region and the conductive film constituting the capacitive FP is such that the insulating film extending from the conductive film constituting the capacitive FP on the RESURF region to the substrate surface If the thickness is the same, the potential division effect by the capacitive FP is strong, and there is a problem that the depletion layer easily reaches the end of the n− region.
本発明は、かかる問題点に鑑みてなされたものであり、上記問題点を解決する発明を提供することを目的とする。 The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.
本発明は、上記課題を解決すべく、以下に掲げる構成とした。
本発明の半導体装置は、
活性領域と、活性領域の外側のエッジ領域と、
を備え、
エッジ領域は、
第１導電型の半導体基体と
半導体基体内にｐｎ接合するように配置され、第１導電型とは反対導電型である第２導電型の半導体領域と、
半導体領域上と半導体領域の外側の領域上に、半導体領域と半導体領域の外側の領域から絶縁された複数の並置された導体層と、
を有し、
半導体基体上の導体層と半導体基体上面との距離は、半導体領域上の導体層と半導体領域上面との距離より大きい事を特徴とする。
In order to solve the above problems, the present invention has the following configurations.
The semiconductor device of the present invention is
An active region, an edge region outside the active region, and
With
The edge region is
A first conductivity type semiconductor substrate and a second conductivity type semiconductor region disposed in a pn junction in the semiconductor substrate and having a conductivity type opposite to the first conductivity type;
A plurality of juxtaposed conductor layers insulated from the semiconductor region and the region outside the semiconductor region on the semiconductor region and the region outside the semiconductor region;
Have
The distance between the conductor layer on the semiconductor substrate and the upper surface of the semiconductor substrate is larger than the distance between the conductor layer on the semiconductor region and the upper surface of the semiconductor region.
本発明は以上のように構成されているので、リサーフ領域である半導体領域の外側の半導体基体上の導体膜と半導体基体上面との間の距離は厚くなっているので、導体膜の電位の影響を受け難くなり、リサーフ領域を設けてリサーフ領域の端からｎ−領域端（半導体基体の端）までの距離が短くなったとしても、空乏層が半導体基体の端に達することを抑制し、半導体装置の耐圧が低下することを抑制することができる。 Since the present invention is configured as described above, since the distance between the conductor film on the semiconductor substrate outside the semiconductor region that is the RESURF region and the upper surface of the semiconductor substrate is thick, the influence of the potential of the conductor film Even if the distance from the end of the RESURF region to the end of the N− region (end of the semiconductor substrate) is shortened by providing a RESURF region, the depletion layer is prevented from reaching the end of the semiconductor substrate. It can suppress that the proof pressure of an apparatus falls.
以下、本発明の実施の形態となる半導体装置１について説明する。 Hereinafter, a semiconductor device 1 according to an embodiment of the present invention will be described.
半導体装置１の断面図を図１で示す。この半導体装置１は、シリコンで構成された半導体基体２に形成されたトレンチゲート型の素子部（活性領域）を含む。この半導体基体２においては、コレクタ領域となるＰ層７の上に、ドリフト領域となるｎ−層（第1の半導体領域）３、ベース領域となるｐ−層（第2の半導体領域）４が順次形成されている。半導体基体２の表面側には、ｐ−層４を貫通して底部がｎ−層３に達する溝（ゲートトレンチ）１００が形成されている。溝１００は、図１における紙面と垂直方向に延伸し、図２の平面図において図示していないが、紙面の縦方向に並行な複数の溝１００が形成される。ここで、溝１００の幅ｂは隣り合う溝１００間の半導体領域の幅ａよりも広い事が望ましい。更に、溝１００の幅ｂは溝の深さｃよりも広い事が望ましい。このような半導体装置１によれば、Ｐ層７からｎ−層へ移動するホールをｎ−層の溝１００の底部近傍により多く蓄積させることができ、半導体装置１のオン抵抗を低減する事ができる。 A cross-sectional view of the semiconductor device 1 is shown in FIG. The semiconductor device 1 includes a trench gate type element (active region) formed in a semiconductor substrate 2 made of silicon. In this semiconductor substrate 2, an n− layer (first semiconductor region) 3 serving as a drift region and a p− layer (second semiconductor region) 4 serving as a base region are formed on a P layer 7 serving as a collector region. It is formed sequentially. On the surface side of the semiconductor substrate 2, a groove (gate trench) 100 that penetrates the p− layer 4 and reaches the bottom of the n− layer 3 is formed. The groove 100 extends in a direction perpendicular to the paper surface in FIG. 1, and a plurality of grooves 100 parallel to the vertical direction of the paper surface are formed, although not shown in the plan view of FIG. Here, the width b of the groove 100 is preferably wider than the width a of the semiconductor region between the adjacent grooves 100. Furthermore, the width b of the groove 100 is desirably wider than the depth c of the groove. According to such a semiconductor device 1, more holes moving from the P layer 7 to the n− layer can be accumulated in the vicinity of the bottom of the trench 100 of the n− layer, and the on-resistance of the semiconductor device 1 can be reduced. it can.
半導体基体２の表面側の溝１００の両側に、エミッタ領域となるｎ＋層５が形成されている。溝１００の内面（側面及び底面）には絶縁膜１０１が形成されている。 N + layers 5 serving as emitter regions are formed on both sides of the groove 100 on the surface side of the semiconductor substrate 2. An insulating film 101 is formed on the inner surface (side surface and bottom surface) of the groove 100.
ゲート電極６０は、絶縁膜１０１を介してｐ−層４と対向するように設けられている。ゲート電極６０は、例えば高濃度にドープされた導電性の多結晶シリコンで構成される。ゲート電極６は溝１００の左右の側壁部に形成され、左右のゲート電極６の各々は互いに電気的に接続されている。 Gate electrode 60 is provided to face p − layer 4 with insulating film 101 interposed therebetween. The gate electrode 60 is made of, for example, conductive polycrystalline silicon doped at a high concentration. The gate electrode 6 is formed on the left and right side walls of the trench 100, and the left and right gate electrodes 6 are electrically connected to each other.
ゲート電極６の下にはゲート電極６と分離（絶縁）された補助電極１２が形成されている。溝１００の底面においても絶縁膜１０１が形成されているため、補助電極１２はその下のｎ−層３とも絶縁される。補助電極１２とゲート電極６の上面には、シリコン酸化膜の絶縁膜８が形成され、その上に層間膜９が溝１００の隙間を埋めるように形成されている。 Under the gate electrode 6, an auxiliary electrode 12 separated (insulated) from the gate electrode 6 is formed. Since the insulating film 101 is also formed on the bottom surface of the groove 100, the auxiliary electrode 12 is also insulated from the n-layer 3 below. An insulating film 8 made of a silicon oxide film is formed on the upper surfaces of the auxiliary electrode 12 and the gate electrode 6, and an interlayer film 9 is formed on the insulating film 8 so as to fill the gap of the groove 100.
半導体基板２の表面上に、エミッタ電極（第１の主電極）１０が形成されており、エミッタ電極１０は半導体基板２の表面においてｎ＋層５と接続される。ソース電極１０とゲート電極６との間は層間膜９で絶縁されている。半導体基板２の裏面全面には、Ｐ層（コレクタ領域）７と電気的に接続されるコレクタ電極（第２の主電極）１１が形成されている。 An emitter electrode (first main electrode) 10 is formed on the surface of the semiconductor substrate 2, and the emitter electrode 10 is connected to the n + layer 5 on the surface of the semiconductor substrate 2. The source electrode 10 and the gate electrode 6 are insulated by the interlayer film 9. A collector electrode (second main electrode) 11 electrically connected to the P layer (collector region) 7 is formed on the entire back surface of the semiconductor substrate 2.
この構造においては、ゲート電極６が溝１００の底面側に形成されず、溝１００の底部には補助電極１２がソース電極１０と同電位（接地電位）となるよう配置されているため、ゲート・ドレイン間の容量Ｃｇｄ（帰還容量）が低減される。 In this structure, the gate electrode 6 is not formed on the bottom surface side of the groove 100, and the auxiliary electrode 12 is disposed at the bottom of the groove 100 so as to have the same potential (ground potential) as the source electrode 10. The capacitance Cgd (feedback capacitance) between the drains is reduced.
また、補助電極１２を溝１００の底部に配置しているので、補助電極１２によって溝１００の底部及び側面からｎ−層３側に空乏層が良好に広がり、耐圧を向上させることが可能である。 In addition, since the auxiliary electrode 12 is disposed at the bottom of the groove 100, the depletion layer can be satisfactorily spread from the bottom and side surfaces of the groove 100 to the n− layer 3 side by the auxiliary electrode 12, and the breakdown voltage can be improved. .
スイッチング素子を含む活性領域２００の外側にはエッジ領域３００が形成されている。半導体装置１のエッジ領域３００を図３で示す。図３において、右端に半導体基体２の端部があり、左側のさらに先の方に活性領域がある。エッジ領域３００内には、エッジトレンチ１０２が活性領域を囲むように形成されており、エッジトレンチ１０２内にｎ−層３とは電気的に絶縁された補助電極１０３が形成されている。補助電極１０３は図示しない領域でソース電極１０と電気的に接続していても良い。
エッジトレンチ１０２の外側には第１のリサーフ領域４１と第１のリサーフ領域４１から半導体基体の端部側へと延伸し、且つ第１のリサーフ領域４１よりも深くまで延伸する第２のリサーフ領域４２が形成されている。第２のリサーフ領域４２の不純物濃度は１×１０１５〜１×１０１７[／cm3]であり、第１のリサーフ領域４１よりも不純物濃度が低い。
エッジトレンチ１０２が溝１００と同じ幅の場合、エッジトレンチ１０２の幅が従来のエッジトレンチ１０２の幅よりも広くなっている。リサーフ領域４１、４２から延びる空乏層と活性領域２００側から延びる空乏層の連結によって、エッジトレンチ１０２の下方の空乏層が形成されるが、リサーフ領域４２をエッジトレンチ１０２底部の深さよりも深くすることで、リサーフ領域４２から延びる空乏層がエッジトレンチ１０２の底部の方へと延びやすくなり、エッジ領域３００において良好な空乏層を生成することができる。これにより、エッジ領域３００における耐圧を高める事が出来る。
半導体装置１のエッジ領域には、半導体基体２上には絶縁膜５５を介して導体膜５１、５２、５３、５４が設けられており、導体膜５１、５２、５３、５４の内で最も半導体基体の端部側の導体膜５１、５２、５３、５４がコレクタ電極１１と電気的に接続し、導体膜５１、５２、５３、５４の内で最も活性領域側の導体膜５１、５２、５３、５４がエミッタ電極１０と電気的に接続されている。従って、コレクタ電極１１とエミッタ電極１０に電圧を印加すると、隣合う導体膜５１、５２、５３、５４間に容量が生じ、容量性のフィールドプレートとして機能する。
ここで、導体膜５１、５２はリサーフ領域４２上に設けられており、導体膜５３、５４はリサーフ領域４２の外側のｎ−層３上に設けられている。導体膜５３、５４とｎ−層との間の距離（又は絶縁膜５５の厚み）は、導体膜５１、５２とリサーフ領域４２との間の距離（又は絶縁膜５５の厚み）よりも大きくなっている。リサーフ領域４２上は絶縁膜５５の厚みを薄くして、容量性ＦＰの電位の影響がリサーフ領域４２表面に受け易くする。これにより、リサーフ領域４２表面の電位を安定化させることができる。リサーフ領域４２の外側のｎ領域３上は絶縁膜５５の厚みをリサーフ領域４２上の絶縁膜５５よりも厚くして、容量性ＦＰの電位の影響を受け難くする。これにより、半導体基体２の外周端に空乏層が容易に到達し難くすることができる。
導体膜５１、５２とリサーフ領域４２との間の距離（又は絶縁膜５５の厚み）はリサーフ領域４２の端部近傍において徐々に大きくなっている事が望ましい。リサーフ領域４２のｎ領域３との界面近傍は不純物濃度が低くなっているが、半導体装置１によればリサーフ領域４２のｎ領域３との界面近傍における容量性ＦＰの電位の影響を受け難くして、リサーフ領域４２のｎ領域３との界面近傍で空乏層が不容易に延び過ぎて空乏層の曲率が変化するのを抑制することができる。
An edge region 300 is formed outside the active region 200 including the switching element. An edge region 300 of the semiconductor device 1 is shown in FIG. In FIG. 3, the end of the semiconductor substrate 2 is on the right end, and the active region is further on the left side. An edge trench 102 is formed in the edge region 300 so as to surround the active region, and an auxiliary electrode 103 that is electrically insulated from the n− layer 3 is formed in the edge trench 102. The auxiliary electrode 103 may be electrically connected to the source electrode 10 in a region not shown.
Outside the edge trench 102, a first resurf region 41 and a second resurf region extending from the first resurf region 41 to the end of the semiconductor substrate and extending deeper than the first resurf region 41. 42 is formed. The impurity concentration of the second resurf region 42 is 1 × 10 15 to 1 × 10 17 [/ cm 3 ], which is lower than that of the first resurf region 41.
When the edge trench 102 has the same width as the groove 100, the width of the edge trench 102 is wider than the width of the conventional edge trench 102. The depletion layer extending from the RESURF regions 41 and 42 and the depletion layer extending from the active region 200 are connected to form a depletion layer below the edge trench 102. The RESURF region 42 is made deeper than the depth of the bottom of the edge trench 102. As a result, the depletion layer extending from the RESURF region 42 tends to extend toward the bottom of the edge trench 102, and a good depletion layer can be generated in the edge region 300. Thereby, the breakdown voltage in the edge region 300 can be increased.
In the edge region of the semiconductor device 1, conductor films 51, 52, 53, 54 are provided on the semiconductor substrate 2 via an insulating film 55, and the most semiconductor among the conductor films 51, 52, 53, 54. Conductor films 51, 52, 53, 54 on the end side of the substrate are electrically connected to the collector electrode 11, and among the conductor films 51, 52, 53, 54, conductor films 51, 52, 53 on the most active region side , 54 are electrically connected to the emitter electrode 10. Therefore, when a voltage is applied to the collector electrode 11 and the emitter electrode 10, a capacitance is generated between the adjacent conductor films 51, 52, 53, and 54 and functions as a capacitive field plate.
Here, the conductor films 51 and 52 are provided on the RESURF region 42, and the conductor films 53 and 54 are provided on the n− layer 3 outside the RESURF region 42. The distance between the conductor films 53 and 54 and the n− layer (or the thickness of the insulating film 55) is larger than the distance between the conductor films 51 and 52 and the RESURF region 42 (or the thickness of the insulating film 55). ing. On the RESURF region 42, the insulating film 55 is thinned so that the surface of the RESURF region 42 is easily affected by the potential of the capacitive FP. Thereby, the potential of the surface of the RESURF region 42 can be stabilized. On the n region 3 outside the RESURF region 42, the insulating film 55 is made thicker than the insulating film 55 on the RESURF region 42 so that it is not easily affected by the potential of the capacitive FP. Thereby, it is possible to make it difficult for the depletion layer to easily reach the outer peripheral edge of the semiconductor substrate 2.
It is desirable that the distance between the conductor films 51 and 52 and the RESURF region 42 (or the thickness of the insulating film 55) be gradually increased in the vicinity of the end of the RESURF region 42. Although the impurity concentration is low near the interface between the RESURF region 42 and the n region 3, the semiconductor device 1 is less susceptible to the potential of the capacitive FP in the vicinity of the interface between the RESURF region 42 and the n region 3. Thus, it is possible to prevent the depletion layer from extending too easily in the vicinity of the interface between the RESURF region 42 and the n region 3 and changing the curvature of the depletion layer.
層間膜９はノンドープのシリコンガラス（ＮＳＧ）膜と、この上に形成されたボロンとリンを含むシリコンガラス（ＢＰＳＧ）膜と、この上に形成されたノンドープのシリコンガラス（ＮＳＧ）膜を設けた構造となっている。ボロンとリンを含むシリコンガラス（ＢＰＳＧ）膜はその厚みが１．７５〜２．７５μｍであって、層間膜上面に生じる段差を下面に生じている段差よりも緩和する。
ボロンとリンを含むシリコンガラス（ＢＰＳＧ）膜の下にノンドープのシリコンガラス（ＮＳＧ）膜が形成されている。この膜の厚みは０．４μｍ〜０．６μｍであって、ＮＳＧ膜は半導体装置の外部から侵入した水分がその下側の基板側へと侵入することを抑制する効果がある。
ボロンとリンを含むシリコンガラス（ＢＰＳＧ）膜の上にノンドープのシリコンガラス（ＮＳＧ）膜が形成されている。この膜の厚みは０．４μｍ〜０．６μｍである。
The interlayer film 9 is provided with a non-doped silicon glass (NSG) film, a silicon glass (BPSG) film containing boron and phosphorus formed thereon, and a non-doped silicon glass (NSG) film formed thereon. It has a structure. The silicon glass (BPSG) film containing boron and phosphorus has a thickness of 1.75 to 2.75 μm, and the step formed on the upper surface of the interlayer film is more relaxed than the step formed on the lower surface.
A non-doped silicon glass (NSG) film is formed under a silicon glass (BPSG) film containing boron and phosphorus. The thickness of this film is 0.4 μm to 0.6 μm, and the NSG film has an effect of suppressing the intrusion of moisture from the outside of the semiconductor device into the lower substrate side.
A non-doped silicon glass (NSG) film is formed on a silicon glass (BPSG) film containing boron and phosphorus. The thickness of this film is 0.4 μm to 0.6 μm.
ボロンとリンを含むシリコンガラス（ＢＰＳＧ）膜の上にノンドープのシリコンガラス（ＮＳＧ）膜を形成することによって、半導体装置１の外部から層間膜９の上面に水分が侵入したとしても、層間膜９の上部側に形成したシリコンガラス（ＢＰＳＧ）膜によって、ボロンとリンを含むシリコンガラス（ＢＰＳＧ）膜へ水分が達することを抑制することができる。 Even if moisture enters the upper surface of the interlayer film 9 from the outside of the semiconductor device 1 by forming a non-doped silicon glass (NSG) film on the silicon glass (BPSG) film containing boron and phosphorus, the interlayer film 9 The silicon glass (BPSG) film formed on the upper side of the metal can prevent moisture from reaching the silicon glass (BPSG) film containing boron and phosphorus.
また、ボロンとリンを含むシリコンガラス（ＢＰＳＧ）膜に水分が達したとしても、ボロンとリンを含むシリコンガラス（ＢＰＳＧ）膜の上部にノンドープのシリコンガラス（ＮＳＧ）膜が形成されているので、ボロンとリンを含むシリコンガラス（ＢＰＳＧ）膜内に含まれるリンが遊離したとしても、近傍のソース電極やバスライン等のＡｌ電極の表面にリンが達する事を抑制し、近傍のソース電極やバスライン等のＡｌ電極の表面を腐食させることを抑制することができる。
また、半導体基体２の端部近傍の絶縁膜５５は厚く形成されている。これにより、半導体基体２の外部からやってくる外部イオンによる半導体基体２への影響を抑制することができる。
Moreover, even if moisture reaches the silicon glass (BPSG) film containing boron and phosphorus, a non-doped silicon glass (NSG) film is formed on the silicon glass (BPSG) film containing boron and phosphorus. Even if the phosphorus contained in the silicon glass (BPSG) film containing boron and phosphorus is released, the phosphorus is prevented from reaching the surface of the Al electrode such as the nearby source electrode or bus line, and the nearby source electrode or bus Corrosion of the surface of the Al electrode such as a line can be suppressed.
In addition, the insulating film 55 in the vicinity of the end of the semiconductor substrate 2 is formed thick. Thereby, the influence on the semiconductor substrate 2 by the external ions coming from the outside of the semiconductor substrate 2 can be suppressed.
以上から、ボロンとリンを含むシリコンガラス（ＢＰＳＧ）膜上にノンドープのシリコンガラス（ＮＳＧ）膜を形成した層間膜９とすることによって、ソース電極やバスラインのＡｌ電極の表面の腐食を低減することができる。従って、半導体装置１の信頼性を高めることができる。 From the above, by using the interlayer film 9 in which a non-doped silicon glass (NSG) film is formed on a silicon glass (BPSG) film containing boron and phosphorus, corrosion of the surface of the source electrode and the Al electrode of the bus line is reduced. be able to. Therefore, the reliability of the semiconductor device 1 can be improved.
なお、上記において、活性領域２００の素子構造がトレンチゲート型のＩＧＢＴであるものとしたが、パワーＭＯＳＦＥＴやダイオードなど図１以外のデバイス構造を活性領域２００に備える場合においても同様の構造を用いることができる。 In the above description, the element structure of the active region 200 is a trench gate type IGBT. However, the same structure is used when the active region 200 includes a device structure other than that shown in FIG. Can do.
また、上記の構成は、いずれもｎチャネル型の素子であったが、導電型（ｐ型、ｎ型）を逆転させ、ｐチャネル型の素子を同様に得ることができることは明らかである。 In addition, each of the above configurations is an n-channel element, but it is apparent that a p-channel element can be similarly obtained by reversing the conductivity type (p-type and n-type).
１ 半導体装置
２ 半導体基体
３ ｎ−層
４ ｐ―層
５ ｎ＋層
６ ゲート電極
７ Ｐ層
８ 酸化膜
９ 層間膜
１０ エミッタ電極
１１ コレクタ電極
１２ 補助電極
１３ 保護膜
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor base | substrate 3 n-layer 4 p-layer 5 n + layer 6 Gate electrode 7 P layer 8 Oxide film 9 Interlayer film 10 Emitter electrode 11 Collector electrode 12 Auxiliary electrode 13 Protective film
Claims (2)
を備え、
前記エッジ領域は、
第１導電型の半導体基体と、
前記半導体基体内にｐｎ接合するように配置され、第１導電型とは反対導電型である第２導電型の半導体領域と、
前記半導体領域上と前記半導体領域の外側の領域上に、前記半導体領域と前記半導体領域の外側の領域から絶縁された複数の並置された導体層と、
を有し、
前記半導体基体上の前記導体層と前記半導体基体上面との距離は、前記半導体領域上の前記導体層と前記半導体領域上面との距離より大きい事を特徴とする半導体装置。 An active region, an edge region outside the active region, and
With
The edge region is
A first conductivity type semiconductor substrate;
A semiconductor region of a second conductivity type disposed so as to form a pn junction in the semiconductor substrate and having a conductivity type opposite to the first conductivity type;
A plurality of juxtaposed conductor layers insulated from the semiconductor region and a region outside the semiconductor region on the semiconductor region and on a region outside the semiconductor region;
Have
A distance between the conductor layer on the semiconductor substrate and the upper surface of the semiconductor substrate is larger than a distance between the conductor layer on the semiconductor region and the upper surface of the semiconductor region.
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| JP2011124464A (en) * | 2009-12-14 | 2011-06-23 | Toshiba Corp | Semiconductor device and method for manufacturing the same |
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| JPH03116976A (en) * | 1989-09-29 | 1991-05-17 | Fuji Electric Co Ltd | Planar type semiconductor device |
| JP2005286023A (en) * | 2004-03-29 | 2005-10-13 | Nec Electronics Corp | Super junction semiconductor element and its manufacturing method |
| JP2006080368A (en) * | 2004-09-10 | 2006-03-23 | Fuji Electric Holdings Co Ltd | Semiconductor device |
| JP2011512676A (en) * | 2008-02-14 | 2011-04-21 | マックスパワー・セミコンダクター・インコーポレイテッド | Edge termination for improved breakdown voltage |
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