CN116364758B - SiC MOS device - Google Patents

SiC MOS device Download PDF

Info

Publication number
CN116364758B
CN116364758B CN202310330662.4A CN202310330662A CN116364758B CN 116364758 B CN116364758 B CN 116364758B CN 202310330662 A CN202310330662 A CN 202310330662A CN 116364758 B CN116364758 B CN 116364758B
Authority
CN
China
Prior art keywords
bpsg layer
layer
bpsg
source
mos device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202310330662.4A
Other languages
Chinese (zh)
Other versions
CN116364758A (en
Inventor
韩小朋
彭虎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Longchi Semiconductor Technology Co ltd
Original Assignee
Suzhou Longchi Semiconductor Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Longchi Semiconductor Technology Co ltd filed Critical Suzhou Longchi Semiconductor Technology Co ltd
Priority to CN202310330662.4A priority Critical patent/CN116364758B/en
Publication of CN116364758A publication Critical patent/CN116364758A/en
Application granted granted Critical
Publication of CN116364758B publication Critical patent/CN116364758B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a SiC MOS device, which comprises an epitaxial structure, and a source electrode, a drain electrode and a grid electrode which are matched with the epitaxial structure, wherein the source electrode is arranged above the grid electrode, an isolation structure is arranged between the source electrode and the grid electrode and is electrically isolated through the isolation structure, the isolation structure comprises a first BPSG layer and a protective layer which are sequentially stacked, the first BPSG layer covers the grid electrode, the source electrode covers the protective layer, and the first BPSG layer and the source electrode are isolated by the protective layer. The SiC MOS device provided by the invention eliminates the corrosion of acid formed after the first BPSG layer is wetted to the source metal, and simultaneously improves the gettering capability of the first BPSG layer, thereby improving the reliability of the device.

Description

SiC MOS device
Technical Field
The invention particularly relates to a SiC MOS device, and belongs to the technical field of semiconductors.
Background
In the SiC production and manufacturing process, a BPSG layer (borophosphosilicate glass is used as an important interlayer medium, and is widely used in semiconductor integrated circuits, and the B, P content (mass fraction) of a BPSG film deposited by normal pressure chemical vapor deposition has a significant effect on the performance of BPSG) is used as a medium layer for isolating POLY (polysilicon gate) and source metal, which plays an important role in device reliability. Wherein, P in BPSG plays a role of gettering, and the increase of P content can increase the gettering effect of the impurity element of BPSG, but after the increase of P content, H generated by the reaction of water vapor with P in BPSG after penetrating the source metal 3 PO 4 The concentration of (2) correspondingly increases, which results in H 3 PO 4 The source metal is more corrosive, thereby affecting the reliability of the device.
Disclosure of Invention
The invention mainly aims to provide a SiC MOS device, so as to overcome the defects in the prior art.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention comprises the following steps:
the invention provides a SiC MOS device, which comprises an epitaxial structure, and a source electrode, a drain electrode and a grid electrode which are matched with the epitaxial structure, wherein the source electrode is arranged above the grid electrode, an isolation structure is arranged between the source electrode and the grid electrode, and the source electrode and the grid electrode are electrically isolated through the isolation structure; the isolation structure comprises a first BPSG layer and a protective layer which are sequentially stacked, wherein the first BPSG layer covers the grid electrode, the source electrode covers the protective layer, and the first BPSG layer and the source electrode are isolated by the protective layer.
Compared with the prior art, the invention has the advantages that:
1) According to the SiC MOS device provided by the invention, the isolation medium layer is added between the source metal and the first BPSG layer, so that the contact between the source metal and the first BPSG layer is isolated, corrosion of acid formed after the first BPSG layer is wetted to the source metal is avoided, meanwhile, the content of P component in the first BPSG layer is increased, the gettering capability of the first BPSG layer is further improved, and the reliability of the device is further improved.
2) According to the SiC MOS device provided by the invention, the problem of corrosion of acid formed after the first BPSG layer is wetted to the source metal is avoided by controlling the distribution of the P component in the first BPSG layer between the source metal and the grid electrode, and other structures are not required to be introduced, so that the reliability of the device is improved on the premise of avoiding influencing the gettering characteristic of the first BPSG layer.
Drawings
Fig. 1 is a schematic cross-sectional structure of a SiC MOS device provided in embodiment 1 of the present invention;
fig. 2 to 6 are schematic structural views of SiC MOS device according to embodiment 1 of the present invention formed at each stage of fabrication;
fig. 7 is a schematic cross-sectional structure of a SiC MOS device according to embodiment 2 of the present invention.
Detailed Description
In view of the shortcomings in the prior art, the inventor of the present invention has long studied and practiced in a large number of ways to propose the technical scheme of the present invention. The technical scheme, the implementation process, the principle and the like are further explained as follows.
The invention provides a SiC MOS device, which comprises an epitaxial structure, and a source electrode, a drain electrode and a grid electrode which are matched with the epitaxial structure, wherein the source electrode is arranged above the grid electrode, an isolation structure is arranged between the source electrode and the grid electrode, and the source electrode and the grid electrode are electrically isolated through the isolation structure; the isolation structure comprises a first BPSG layer and a protective layer which are sequentially stacked, the first BPSG layer covers the grid electrode, the source electrode covers the protective layer, the first BPSG layer and the source electrode are isolated by the protective layer, and the protective layer is mainly used for protecting the source electrode so as to prevent the source electrode from being corroded by phosphoric acid formed by the reaction of the first BPSG layer and water.
In a more specific embodiment, the protective layer includes a second BPSG layer, and the average content of the P component in the second BPSG layer is less than the average content of the P component in the first BPSG layer, and the average content of the P component in the second BPSG layer is at least: the P component of the second BPSG layer reacts with sufficient water to form phosphoric acid at a concentration of less than 0.1wt% that is insufficient to chemically react with the metal in the source.
The P in BPSG can adsorb impurity cations, and particularly has an excellent adsorption effect on Na ions.
Further, the average content of the P component in the first BPSG layer is 3 to 6at.%, and the average content of the P component in the second BPSG layer is 0.2 to 1at.%.
Further, the P component in the second BPSG layer is uniformly distributed; alternatively, the P-component content in the second BPSG layer is graded down a selected direction, the selected direction being the direction the gate is pointing toward the source.
Further, the P-component content in the second BPSG layer gradually decreases from 4at.% to 0.1at.% in the selected direction.
Further, the gradient of the P-component content in the second BPSG layer along the selected direction is 0.1 to 1at.%.
Further, the thickness of the second BPSG layer is smaller than the thickness of the first BPSG layer.
Further, the ratio of the thickness of the second BPSG layer to the first BPSG layer is (1:2) - (1:5).
Further, the thickness of the first BPSG layer is 2-5 μm, and the thickness of the second BPSG layer is 0.5-1.5.
In another specific embodiment, the protection layer is an isolation medium layer made of a material different from that of the first BPSG layer, and neither the isolation medium layer itself nor a product formed by the reaction of the isolation medium layer and water is chemically reacted with the source electrode, or the isolation medium layer itself is not chemically reacted with the source electrode and water.
Further, the thickness of the isolation dielectric layer is 0.1-1 μm, so that the gettering capability of the first BPSG layer is not affected, and the source metal and the first BPSG layer can be effectively isolated.
Further, the isolation medium layer is made of SiO 2 Etc.
Further, the average content of the P component in the first BPSG layer is 3 to 6at.%.
Further, the thickness of the first BPSG layer is 2-5 μm.
Further, the material of the gate electrode includes polysilicon, and the material of the source electrode includes aluminum, although other materials can be used 3 PO 4 And (3) corroding metal materials.
The following description will further explain the technical solution, implementation process and principle of the present invention with reference to the accompanying drawings and specific embodiments, and unless otherwise stated, the semiconductor growth and etching processes and devices used in the present invention, and the manufacturing process and devices of the epitaxial structure of the MOS device used in the present invention are all known to those skilled in the art, and further, the epitaxial structure of the MOS device used in the present invention may also be manufactured by known processes or directly obtained by commercial purchase.
Example 1
Referring to fig. 1, a SiC MOS device includes an epitaxial structure 100, and a source 200, a drain 300, and a gate 400 that are mated with the epitaxial structure 100.
In this embodiment, the epitaxial structure 100 includes a SiC substrate 110 and a SiC epitaxial layer 120 that are sequentially stacked along a longitudinal direction of the device, a plurality of P-well regions 130 and a plurality of channel regions (JFETs) 140 are disposed in the SiC epitaxial layer 120, the plurality of P-well regions 130 and the plurality of channel regions (JFETs) 140 are sequentially and alternately disposed along a lateral direction of the device, an n+ emitter region 150 and a p+ collector region 160 are disposed in the P-well regions 130, top surfaces of the P-well regions 130, the channel regions (JFETs) 140, the n+ emitter region 150 and the p+ collector region 160 are flush with the top surface of the epitaxial structure, wherein the drain 300 is connected to the SiC substrate 110, the gate 400 is disposed along the longitudinal direction of the device in the direction of the channel regions (JFETs) 140, and a portion of the gate 140 also extends along the lateral direction of the device and is disposed over a portion of the P-well regions 130, n+ emitter region 150, and the source 200 is disposed over the epitaxial structure and is connected to the n+ emitter region 150 and the p+ collector region 160.
In this embodiment, the SiC substrate 110 has a first face and a second face opposite to each other along a longitudinal direction of the device (or understood as a thickness direction of the SiC substrate), the SiC epitaxial layer 120 is stacked on the first face of the SiC substrate 110, and the drain 300 is disposed on the second face of the SiC substrate 110, and illustratively, the material of the SiC substrate 110 may be 4H-SiC.
In this embodiment, the source 200 and the drain 300 are both metal electrodes, and the source 200 may be an aluminum electrode and the gate 400 may be a polysilicon gate, for example.
In this embodiment, a gate oxide layer 500 is further disposed on the epitaxial structure 100, and the gate 400 is disposed on the gate oxide layer 500, and illustratively, the gate oxide layer 500 may be made of silicon oxide or the like.
In this embodiment, an isolation structure 600 is disposed between the source 200 and the gate 400 and is electrically isolated by the isolation structure 600, where the isolation structure 600 includes a first BPSG (borophosphosilicate glass) layer 610 and an isolation dielectric layer 620 that are sequentially stacked, the first BPSG layer 610 covers the gate 400, the source 200 covers the isolation dielectric layer 620, the isolation dielectric layer 620 is disposed between the first BPSG layer 610 and the source 200, the first BPSG layer 610 and the source 200 are isolated by the isolation dielectric layer 620, and the first BPSG layer 610 has a gettering effect and can perform passivation protection on the gate, and the isolation dielectric layer 620 is disposed between the first BPSG layer 610 and the source 200The mass layer 620 is mainly used to isolate the first BPSG layer 610 from the source 200 to prevent phosphoric acid (H) formed by the reaction of the first BPSG layer 610 with water after being wetted 3 PO 4 ) And the source metal is corroded to cause the problem of reduced device reliability.
Specifically, the isolation medium layer 620 itself or the product formed by the reaction of the isolation medium layer 620 with water will not react with the source electrode, or the isolation medium layer 620 itself will not react with the source electrode and water, and the isolation medium layer 620 is made of silicon oxide (SiO 2 ) After the first BPSG layer is wetted, phosphoric acid formed by the reaction of the P component and water does not corrode silicon oxide, and after the first BPSG layer and the source electrode are isolated, the content of the P component in the first BPSG layer can be increased to 6 at%, so that the gettering effect of the first BPSG layer is improved, and the reliability of the SiC MOS device is further improved.
In this embodiment, the thickness of the first BPSG layer is 2-5 μm, and the P content in the first BPSG layer is 3-6at.%, so as to achieve the effect of reducing the reflow temperature, wherein the P component in the first BPSG layer may be uniformly distributed.
In this embodiment, the thickness of the isolation dielectric layer is 0.1-1 μm, and the width of the isolation dielectric layer is 0.1-1 μm, so as to not only not affect the gettering capability of the first BPSG layer, but also effectively isolate the source metal from the first BPSG layer, and it should be noted that the width of the isolation dielectric layer refers to the dimension along the lateral direction of the device.
In this embodiment, a method for manufacturing a SiC MOS device may include the following steps:
1) The SiC wafer with the epitaxial structure of the SiC MOS device is manufactured, and a stacked silicon oxide layer and a stacked polysilicon layer are sequentially grown on the surface of the SiC wafer, as shown in fig. 2, where the epitaxial structure of the SiC MOS device is described in the foregoing, and the parameters such as the thickness of the silicon oxide layer and the polysilicon can be adjusted according to specific requirements, which are not limited in detail herein.
2) Removing the silicon oxide layer and the polysilicon layer in the selected area by adopting processes such as Inductively Coupled Plasma (ICP) etching and the like, thereby forming a window or an opening exposing the N+ emission region 150 and the P+ collector region 160, wherein the remained silicon oxide layer is used as a gate oxide layer 500, and the remained polysilicon layer is used as a gate 400, as shown in FIG. 3; specifically, the source end power of ICP selection is 1000w, the power at the bisa is 10w, the etching depth is 1.5um, and the width is 1um.
3) Adopting Chemical Vapor Deposition (CVD) mode, etc. to make the volume ratio be 3:2:5: PH of 10 3 、BH 3 、SIH 4 、O 2 Forming a first BPSG layer 610 with a P content of 6at.% on the surface of the SiC wafer by reactive growth at 400 ℃, filling the windows or openings with BPSG, and carrying out planarization treatment on the formed first BPSG layer 610, as shown in FIG. 4; specifically, the thickness of the first BPSG layer is formed to be 2 μm.
4) A photoresist is coated on a designated area of the surface of the first BPSG layer 610 as a mask, and the first BPSG layer not coated with the mask is removed by an Inductively Coupled Plasma (ICP) etching or the like to form an electrode hole exposing the n+ emitter region 150 and the p+ collector region 160, as shown in fig. 5, and specific etching processes and conditions may refer to step 2.
5) A silicon oxide layer with a thickness of 0.2 μm is formed on the surface of the first BPSG layer 610 by Chemical Vapor Deposition (CVD) or the like as an isolation dielectric layer 620, and the isolation dielectric layer 620 is made to cover the first BPSG layer 610, as shown in fig. 6.
6) Sputtering metal aluminum on the surface of the structure formed in the step 5) by Physical Vapor Deposition (PVD) and the like, so as to form a source electrode 200, and connecting the source electrode 200 with an N+ emission region 150 and a P+ collector region 160 from the electrode hole, as shown in FIG. 1.
Example 2
Referring to fig. 7, a SiC MOS device includes an epitaxial structure 100, and a source 200, a drain 300, and a gate 400 that are mated with the epitaxial structure 100.
In this embodiment, the epitaxial structure 100 includes a SiC substrate 110 and a SiC epitaxial layer 120 that are sequentially stacked along a longitudinal direction of the device, a plurality of P-well regions 130 and a plurality of channel regions (JFETs) 140 are disposed in the SiC epitaxial layer 120, the plurality of P-well regions 130 and the plurality of channel regions (JFETs) 140 are sequentially and alternately disposed along a lateral direction of the device, an n+ emitter region 150 and a p+ collector region 160 are disposed in the P-well regions 130, top surfaces of the P-well regions 130, the channel regions (JFETs) 140, the n+ emitter region 150 and the p+ collector region 160 are flush with the top surface of the epitaxial structure, wherein the drain 300 is connected to the SiC substrate 110, the gate 400 is disposed along the longitudinal direction of the device in the direction of the channel regions (JFETs) 140, and a portion of the gate 140 also extends along the lateral direction of the device and is disposed over a portion of the P-well regions 130, n+ emitter region 150, and the source 200 is disposed over the epitaxial structure and is connected to the n+ emitter region 150 and the p+ collector region 160.
In this embodiment, the SiC substrate 110 has a first face and a second face opposite to each other along a longitudinal direction of the device (or understood as a thickness direction of the SiC substrate), the SiC epitaxial layer 120 is stacked on the first face of the SiC substrate 110, and the drain 300 is disposed on the second face of the SiC substrate 110, and illustratively, the material of the SiC substrate 110 may be 4H-SiC.
In this embodiment, the source 200 and the drain 300 are both metal electrodes, and the source 200 may be an aluminum electrode and the gate 400 may be a polysilicon gate, for example.
In this embodiment, a gate oxide layer 500 is further disposed on the epitaxial structure 100, and the gate 400 is disposed on the gate oxide layer 500, and illustratively, the gate oxide layer 500 may be made of silicon oxide or the like.
In this embodiment, an isolation structure 600 is disposed between the source 200 and the gate 400 and is electrically isolated by the isolation structure 600, where the isolation structure 600 includes a first BPSG layer 610 and a second BPSG layer 630 that are sequentially stacked, the first BPSG layer 610 covers the gate 400, the second BPSG layer 630 covers the first BPSG layer 610, and the source 200 covers the second BPSG layer 630, where an average content of a P component in the second BPSG layer 630 is smaller than an average content of a P component in the first BPSG layer 610, and an average content of a P component in the second BPSG layer 630 at least satisfies: the P-component in the second BPSG layer 630 reacts with sufficient water to form phosphoric acid at a concentration of less than 0.1wt% that is insufficient to chemically react with the metal in the source 200.
Specifically, the first BPSG layer 610 and the second BPSG layer 630 have a gettering effect, but the gettering effect of the first BPSG layer 610 is significantly higher than that of the second BPSG layer 630, the first BPSG layer 610 also has a passivation protection effect on the gate, and the average content of the P component in the second BPSG layer 630 is 0.2-1 at%, so that the gettering effect and the metal electrode protection effect can be achieved, and even if the second BPSG layer 630 is wetted, the second BPSG layer 630 reacts with water to form phosphoric acid (H) 3 PO 4 ) And the source electrode is not corroded by chemical reaction with the source electrode metal.
In this embodiment, the average content of the P component in the first BPSG layer 610 is 3-6at%, and the average content of the P component in the second BPSG layer 630 is 0.2-1at%, where the P component in the second BPSG layer is uniformly distributed; alternatively, the P-component content in the second BPSG layer 630 is graded down in a selected direction, the selected direction being the direction in which the gate points toward the source; it should be noted that the electrode metal is protected no matter the P component is uniformly distributed or changed in gradient, because the P component content in the contact area is very low and no more H is generated 3 PO 4 And therefore does not corrode metals.
In this embodiment, the P-component content in the second BPSG layer 630 gradually decreases from 4at.% to 0.1at.% in the selected direction, and the gradient of the P-component content in the second BPSG layer in the selected direction is 0.1-lat.%.
In this embodiment, the thickness of the second BPSG layer 630 is smaller than the thickness of the first BPSG layer 610, specifically, the thickness of the first BPSG layer is 3 μm, the thickness of the second BPSG layer is 1 μm, the first BPSG layer and the second BPSG layer are used together as the gettering layer, and the thickness of the gettering layer is thickened at this time, so that the gettering capability of the isolation structure is higher, further, the thickness of the first BPSG layer is 3 μm, and the thickness of the second BPSG layer is 1 μm.
Note that the SiC MOS device in embodiment 2 is obtained using a SiC wafer containing the same epitaxial structure.
Comparative example 1
The structure of one SiC MOS device in comparative example 1 is substantially the same as that in example 1, except that: the SiC MOS device of comparative example 1 does not include an isolation dielectric layer, and the first BPSG layer 610 is in direct contact with the source 200.
Comparative example 2
The structure of one SiC MOS device in comparative example 2 is substantially the same as that in example 2, except that: the average content of the P component in the second BPSG layer 630 in comparative example 2 is 2at.%.
The SiC MOS devices of example 1, example 2, comparative example 1, and comparative example 2 were kept in a high humidity environment with a humidity of 85% for 500 hours, in a high temperature and high humidity environment with a humidity of 85% for 500 hours at 175 ℃, then taken out and subjected to performance test, and the resistance (Rdson) between the drain and the source when the drain and the source are turned on was mainly tested and the corrosion condition of the source metal (Al) was analyzed, and the results are shown in table 1:
table 1 shows the results of the moisture test of the SiC MOS devices of examples 1-2 and comparative examples 1-2
According to the SiC MOS device provided by the invention, the isolation medium layer is added between the source metal and the first BPSG layer, so that the contact between the source metal and the first BPSG layer is isolated, corrosion of acid formed after the first BPSG layer is wetted to the source metal is avoided, meanwhile, the content of P component in the first BPSG layer is increased, the gettering capability of the first BPSG layer is further improved, and the reliability of the device is further improved.
According to the SiC MOS device provided by the invention, the problem of corrosion of acid formed after the first BPSG layer is wetted to the source metal is avoided by controlling the distribution of the P component in the first BPSG layer between the source metal and the grid electrode, and other structures are not required to be introduced, so that the reliability of the device is improved on the premise of avoiding influencing the gettering characteristic of the first BPSG layer.
It should be understood that the above embodiments are merely for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and implement the same according to the present invention without limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.

Claims (6)

1. The utility model provides a SiC MOS device, includes epitaxial structure and with epitaxial structure complex source, drain electrode and grid, the source sets up the grid top, just be provided with isolation structure between source and the grid, and pass through isolation structure electric isolation, its characterized in that: the isolation structure comprises a first BPSG layer and a protective layer which are sequentially stacked, wherein the first BPSG layer covers the grid electrode, the source electrode covers the protective layer, the first BPSG layer and the source electrode are isolated by the protective layer, and the average content of P components in the first BPSG layer is 3-6 at%;
the protective layer includes a second BPSG layer having a P-component content gradually decreasing from 4at.% to 0.1at.% in a selected direction, the second BPSG layer having a gradient of 0.1-1at.% in the selected direction, the second BPSG layer having an average P-component content less than an average P-component content of the first BPSG layer, and the second BPSG layer having an average P-component content of at least: the P component of the second BPSG layer reacts with sufficient water to form phosphoric acid at a concentration of less than 0.1wt% to chemically react the phosphoric acid with the metal of the source, the selected direction being the direction of the gate toward the source.
2. The SiC MOS device of claim 1, wherein: the average content of the P component in the second BPSG layer is 0.2-1 at%.
3. The SiC MOS device of claim 1, wherein: the second BPSG layer has a thickness less than a thickness of the first BPSG layer.
4. The SiC MOS device of claim 3, wherein: the ratio of the thickness of the second BPSG layer to the first BPSG layer is (1:2) - (1:5).
5. The SiC MOS device of claim 4, wherein: the thickness of the first BPSG layer is 2-5 mu m, and the thickness of the second BPSG layer is 0.5-1.5 mu m.
6. The SiC MOS device of claim 1, wherein: the material of the grid electrode comprises polysilicon, and the material of the source electrode comprises aluminum.
CN202310330662.4A 2023-03-30 2023-03-30 SiC MOS device Active CN116364758B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310330662.4A CN116364758B (en) 2023-03-30 2023-03-30 SiC MOS device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310330662.4A CN116364758B (en) 2023-03-30 2023-03-30 SiC MOS device

Publications (2)

Publication Number Publication Date
CN116364758A CN116364758A (en) 2023-06-30
CN116364758B true CN116364758B (en) 2023-11-14

Family

ID=86914781

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310330662.4A Active CN116364758B (en) 2023-03-30 2023-03-30 SiC MOS device

Country Status (1)

Country Link
CN (1) CN116364758B (en)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1566072A (en) * 1977-03-28 1980-04-30 Tokyo Shibaura Electric Co Semiconductor device
JP2004253780A (en) * 2003-01-31 2004-09-09 Nec Electronics Corp Semiconductor device and its manufacturing method
CN101174569A (en) * 2006-10-30 2008-05-07 株式会社电装 Method of manufacturing silicon carbide semiconductor device
CN105931970A (en) * 2016-06-30 2016-09-07 杭州士兰集成电路有限公司 Planar gate power device structure and formation method therefor
CN106549044A (en) * 2015-09-18 2017-03-29 三垦电气株式会社 Semiconductor device
JP2018082054A (en) * 2016-11-16 2018-05-24 富士電機株式会社 Method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device
CN109585564A (en) * 2018-12-26 2019-04-05 芜湖启迪半导体有限公司 A kind of silicon carbide MOSFET device and preparation method thereof
CN111316406A (en) * 2017-11-13 2020-06-19 三菱电机株式会社 Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
JP2021093496A (en) * 2019-12-12 2021-06-17 三菱電機株式会社 Silicon carbide semiconductor device and power conversion device
CN114420758A (en) * 2021-12-08 2022-04-29 西安理工大学 SiC MOSFET with high threshold voltage and method of manufacture

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1566072A (en) * 1977-03-28 1980-04-30 Tokyo Shibaura Electric Co Semiconductor device
JP2004253780A (en) * 2003-01-31 2004-09-09 Nec Electronics Corp Semiconductor device and its manufacturing method
CN101174569A (en) * 2006-10-30 2008-05-07 株式会社电装 Method of manufacturing silicon carbide semiconductor device
CN106549044A (en) * 2015-09-18 2017-03-29 三垦电气株式会社 Semiconductor device
CN105931970A (en) * 2016-06-30 2016-09-07 杭州士兰集成电路有限公司 Planar gate power device structure and formation method therefor
JP2018082054A (en) * 2016-11-16 2018-05-24 富士電機株式会社 Method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device
CN111316406A (en) * 2017-11-13 2020-06-19 三菱电机株式会社 Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
CN109585564A (en) * 2018-12-26 2019-04-05 芜湖启迪半导体有限公司 A kind of silicon carbide MOSFET device and preparation method thereof
JP2021093496A (en) * 2019-12-12 2021-06-17 三菱電機株式会社 Silicon carbide semiconductor device and power conversion device
CN114420758A (en) * 2021-12-08 2022-04-29 西安理工大学 SiC MOSFET with high threshold voltage and method of manufacture

Also Published As

Publication number Publication date
CN116364758A (en) 2023-06-30

Similar Documents

Publication Publication Date Title
CN1033543C (en) Electric circuit having superconducting multilayered structure and manufacturing method for same
EP0486047A2 (en) Thin film semiconductor device, process for fabricating the same, and silicon film
KR20080025209A (en) Silicon carbide semiconductor device and method for producing the same
US5814545A (en) Semiconductor device having a phosphorus doped PECVD film and a method of manufacture
CN106206273A (en) The manufacture method of semiconductor device
KR100380890B1 (en) Semiconductor device and method for manufacturing the same
EP0078173B1 (en) Process for fabricating a semiconductor device having a phosphosilicate glass layer
CN116364758B (en) SiC MOS device
CN107369716B (en) Thin film transistor, manufacturing method and display device
EP4136671A1 (en) Methods of dielectric material fill and treatment
US7811928B2 (en) Semiconductor devices and fabrication methods thereof
CN101197281A (en) Production method for silicide contact in semiconductor element
CN106684132A (en) Silicon carbide bipolar transistor based on active region trench structure and manufacturing method thereof
CN102254936B (en) Compound semiconductor device and method for manufacturing compound semiconductor device
KR100275733B1 (en) Method for forming MOS transistor having bi-layer spacer
CN1146033C (en) Improved SAC process flow method using isolating spacer
CN113025991B (en) Method for manufacturing semiconductor structure
JP2023553733A (en) Method for producing electronic device precursor
CN113707713A (en) Multi-stage petal-shaped body region metal oxide semiconductor power device and manufacturing method thereof
CN105140285B (en) A kind of vertical conductive structure SiC MOSFET power devices
KR100564415B1 (en) Contact hole formation method of semiconductor device
JPH0232545A (en) Manufacture of semiconductor device
KR970007968B1 (en) Formation method of layer insulator of semiconductor device
KR100472855B1 (en) Polycrystalline silicon thin film manufacturing method of semiconductor device
CN110867410A (en) Display panel and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant