JP2017027541A - 半導体装置及び電子機器 - Google Patents
半導体装置及び電子機器 Download PDFInfo
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- JP2017027541A JP2017027541A JP2015148430A JP2015148430A JP2017027541A JP 2017027541 A JP2017027541 A JP 2017027541A JP 2015148430 A JP2015148430 A JP 2015148430A JP 2015148430 A JP2015148430 A JP 2015148430A JP 2017027541 A JP2017027541 A JP 2017027541A
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- G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
- G01K1/00—Details of thermometers not specially adapted for particular types of thermometer
- G01K1/02—Means for indicating or recording specially adapted for thermometers
- G01K1/022—Means for indicating or recording specially adapted for thermometers for recording
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
【解決手段】実施形態の半導体装置は、ホスト装置と接続可能な基板と、前記基板に実装されたメモリと、前記基板に実装されるとともに、前記メモリを制御するコントローラと、周辺温度を計測する温度監視部と、を有し、前記コントローラは、前記温度監視部で計測された第一温度と前記ホスト装置からのデータとを前記メモリに書き込むとともに、前記第一温度に応じて前記データを読み出す。
【選択図】図9
Description
図1乃至図3は、第1実施形態に係る半導体装置1と該半導体装置1が組み込まれたシステム100を示す。システム100は、「電子機器」の一例である。半導体装置1は、「半導体モジュール」及び「半導体記憶装置」の其々一例である。本実施形態に係る半導体装置1は、例えばSSD(Solid State Drive)等のメモリシステムであるが、これに限られるものではない。
Claims (6)
- ホスト装置と接続可能な基板と、
前記基板に実装されたメモリと、
前記基板に実装されるとともに、前記メモリを制御するコントローラと、
周辺温度を計測する温度監視部と、
を有し、
前記コントローラは、前記温度監視部で計測された第一温度と前記ホスト装置からのデータとを前記メモリに書き込むとともに、前記第一温度に応じて前記データを読み出す半導体装置。 - 前記コントローラは、
前記第一温度が第一値よりも低い場合、または前記第一温度が前記第一値より値が大きい第二値よりも高い場合、補正処理を行って前記メモリから前記データを読み出すことを特徴とする請求項1に記載の半導体装置。 - 前記補正処理は、
前記第一温度に応じた補正値を取得し、該補正値に応じて前記データを読み出す際の電圧値を変更する処理であることを特徴とする請求項2に記載の半導体装置。 - 前記メモリは、
前記データが記憶される記憶領域と、
前記温度監視部で計測された前記第一温度を含んだ温度情報が記憶される冗長領域と、
を有することを特徴とする請求項1乃至請求項3に記載の半導体装置。 - 基板と、
周辺温度を監視し、温度情報を取得する温度監視部と、
前記基板に実装され、データと前記温度情報とを記憶するメモリと、
前記基板に実装されるとともに、前記温度情報を参照して前記メモリから前記データを読み出すコントローラと、
を有した半導体装置。 - 筐体と、
前記筐体に収容された表示モジュールと、
前記表示モジュールと重なる位置で前記筐体に収容された回路基板と、
前記表示モジュールと重なる位置で前記筐体に収容され、前記回路基板と電気的に接続された第一基板と、
前記第一基板に実装された温度監視部と、
データと前記温度監視部が取得した温度情報とを記憶するメモリと、
前記温度情報を参照して前記メモリから前記データを読み出すコントローラと、
を有した電子機器。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015148430A JP2017027541A (ja) | 2015-07-28 | 2015-07-28 | 半導体装置及び電子機器 |
US15/056,612 US20170030777A1 (en) | 2015-07-28 | 2016-02-29 | Semiconductor device that writes temperature data for subsequent data reading |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2015148430A JP2017027541A (ja) | 2015-07-28 | 2015-07-28 | 半導体装置及び電子機器 |
Publications (1)
Publication Number | Publication Date |
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JP2017027541A true JP2017027541A (ja) | 2017-02-02 |
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ID=57885930
Family Applications (1)
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JP2015148430A Abandoned JP2017027541A (ja) | 2015-07-28 | 2015-07-28 | 半導体装置及び電子機器 |
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US (1) | US20170030777A1 (ja) |
JP (1) | JP2017027541A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10539988B2 (en) | 2017-09-05 | 2020-01-21 | Toshiba Memory Corporation | Memory system |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10952327B2 (en) | 2018-04-27 | 2021-03-16 | Samsung Electronics Co., Ltd. | Semiconductor module |
JP2020017133A (ja) * | 2018-07-26 | 2020-01-30 | キオクシア株式会社 | ストレージ装置及び制御方法 |
CN113448489A (zh) * | 2020-03-25 | 2021-09-28 | 慧荣科技股份有限公司 | 控制闪存卡存取的计算机可读取存储介质、方法及装置 |
JP2022014710A (ja) * | 2020-07-07 | 2022-01-20 | キオクシア株式会社 | メモリシステム |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009289278A (ja) * | 2009-08-31 | 2009-12-10 | Toshiba Corp | 多値型半導体記憶装置 |
JP2011028827A (ja) * | 2009-06-25 | 2011-02-10 | Toshiba Corp | 半導体記憶装置 |
WO2011055749A1 (ja) * | 2009-11-06 | 2011-05-12 | 株式会社 東芝 | メモリシステム |
JP2014509769A (ja) * | 2011-03-02 | 2014-04-21 | アップル インコーポレイテッド | メモリ装置での温度センサの使用 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7184313B2 (en) * | 2005-06-17 | 2007-02-27 | Saifun Semiconductors Ltd. | Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells |
US7702935B2 (en) * | 2006-01-25 | 2010-04-20 | Apple Inc. | Reporting flash memory operating voltages |
EP2120189B1 (en) * | 2007-01-30 | 2013-01-16 | Panasonic Corporation | Nonvolatile storage device, nonvolatile storage system, and access device |
JP2013050818A (ja) * | 2011-08-30 | 2013-03-14 | Toshiba Corp | メモリシステム |
-
2015
- 2015-07-28 JP JP2015148430A patent/JP2017027541A/ja not_active Abandoned
-
2016
- 2016-02-29 US US15/056,612 patent/US20170030777A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011028827A (ja) * | 2009-06-25 | 2011-02-10 | Toshiba Corp | 半導体記憶装置 |
JP2009289278A (ja) * | 2009-08-31 | 2009-12-10 | Toshiba Corp | 多値型半導体記憶装置 |
WO2011055749A1 (ja) * | 2009-11-06 | 2011-05-12 | 株式会社 東芝 | メモリシステム |
JP2014509769A (ja) * | 2011-03-02 | 2014-04-21 | アップル インコーポレイテッド | メモリ装置での温度センサの使用 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10539988B2 (en) | 2017-09-05 | 2020-01-21 | Toshiba Memory Corporation | Memory system |
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