JP2017022263A - Manufacturing method of wide bandgap semiconductor device, wide bandgap semiconductor wafer, and wide bandgap semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a wide bandgap semiconductor device capable of reducing a drain leakage defect rate.SOLUTION: On a principal surface, a dicing region DR and an alignment mark region 30 are formed. The alignment mark region 30 is used to perform alignment of a wide bandgap semiconductor wafer and a photomask. After the step of performing the alignment, a p-type region 71 is formed so as to be overlapped with the alignment mark region 30. By cutting the wide bandgap semiconductor wafer along the dicing region DR, a plurality of chips are formed. In a portion of the dicing region DR that remains in the plurality of chips, the p-type region 71 is not present.SELECTED DRAWING: Figure 27

Description

  The present invention relates to a method for manufacturing a wide band gap semiconductor device, a wide band gap semiconductor wafer, and a wide band gap semiconductor chip.

  In recent years, in order to enable a semiconductor device to have a high breakdown voltage, low loss, use under a high temperature environment, etc., silicon carbide is being adopted as a material constituting the semiconductor device. For example, Japanese Patent Laying-Open No. 2015-2198 (Patent Document 1) describes a method for manufacturing a silicon carbide semiconductor device including a step of performing alignment using alignment marks provided on a silicon carbide substrate.

Japanese Patent Laid-Open No. 2015-2198

  Usually, after the wafer process is completed, the wafer is divided into a plurality of chips by cutting the wafer along a dicing line. After being divided into a plurality of chips, the drain leakage current of each chip is evaluated. Chips having a drain leakage current value higher than the reference value are screened as defective. The drain leak defect rate is calculated by dividing the number of chips determined to be defective by the number of all chips for which the drain leak current has been measured.

  An object of one embodiment of the present invention is to provide a method for manufacturing a wide band gap semiconductor device, a wide band gap semiconductor wafer, and a wide band gap semiconductor chip that can reduce a drain leak defect rate.

  A manufacturing method of a wide band gap semiconductor device according to one embodiment of the present invention includes the following steps. A wide band gap semiconductor wafer including a main surface and having an n-type conductivity is prepared. A dicing region is formed on the main surface. An alignment mark region is formed on the main surface. The wide band gap semiconductor wafer and the photomask are aligned using the alignment mark region. After the alignment process, a p-type region is formed so as to overlap the alignment mark region. After the p-type region is formed, a plurality of chips are formed by cutting the wide band gap semiconductor wafer along the dicing region. There is no p-type region in the portion of the dicing region left on the plurality of chips.

  The wide band gap semiconductor wafer according to one embodiment of the present invention is a wide band gap semiconductor wafer in which a dicing region is formed on a main surface. The wide band gap semiconductor wafer includes an alignment mark region located in the dicing region and a p-type region located in the alignment mark region. The value obtained by dividing the width of the p-type region by the width of the dicing region in the direction perpendicular to the extending direction of the dicing region is 1/12 or more and 2/3 or less, and in the direction perpendicular to the extending direction. The width of the p-type region satisfies at least one of 10 μm or more and 80 μm or less.

  The wide band gap semiconductor wafer according to one embodiment of the present invention is a wide band gap semiconductor wafer in which a dicing region is formed on a main surface. The wide band gap semiconductor wafer includes an alignment mark region located in a region surrounded by a dicing region and a p-type region located in the alignment mark region. The p-type region does not exist in the dicing region.

  According to one embodiment of the present invention, it is possible to provide a method for manufacturing a wide band gap semiconductor device, a wide band gap semiconductor wafer, and a wide band gap semiconductor chip that can reduce the drain leak defect rate.

It is a cross-sectional schematic diagram which shows the structure of the wide band gap semiconductor device which concerns on this Embodiment. It is a flowchart which shows schematically the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 1st process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a plane schematic diagram which shows the 2nd process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. FIG. 5 is an enlarged view of a shot area 1 in FIG. 4. FIG. 6 is an enlarged view of a region VI in FIG. 5. It is a cross-sectional schematic diagram along the VII-VII line of FIG. It is a cross-sectional schematic diagram along the VIII-VIII line of FIG. It is a cross-sectional schematic diagram which shows the 2nd process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 3rd process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 4th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 5th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 6th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 7th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 8th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 9th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 10th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 11th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 12th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 13th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 14th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 15th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a plane schematic diagram which shows the 15th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 16th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 17th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the 18th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a plane schematic diagram which shows the 19th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a plane schematic diagram which shows the 20th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a plane schematic diagram which shows the modification of the 2nd process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. FIG. 30 is an enlarged view of a region XXX in FIG. 29. It is a plane schematic diagram which shows the modification of the 15th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a plane schematic diagram which shows the modification of the 20th process of the manufacturing method of the wide band gap semiconductor device which concerns on this Embodiment. It is a figure which shows the relationship between drain leakage current and application time.

  As a result of intensive studies on the cause of the occurrence of a drain leakage current failure, the inventors have obtained the following knowledge and found one embodiment of the present invention. First, as a result of comparing a plurality of different wafers, the inventors have noted that a chip in which a drain leak defect occurs is a chip at a specific position in the wafer surface. Furthermore, as a result of a detailed comparison between the structure of the chip where the drain leak failure has occurred and the structure of the chip where the drain leak failure has not occurred, the portion of the dicing region of the chip where the drain leak failure has occurred It has been found that the p-type region is not formed in the portion of the dicing region of the chip where the p-type region is formed and the drain leak defect does not occur.

  Usually, in the wafer process, alignment is performed in order to reduce a relative positional shift between different processes. For example, when the body region is formed by ion implantation, an ion implantation mask having an opening on the body region is formed. In order to form the ion implantation mask, patterning of the ion implantation mask is performed. The patterning of the ion implantation mask is performed by a photolithography process.

  In the photolithography process, for example, a photomask such as a reticle and the wafer are aligned using alignment marks. Specifically, the alignment between the photomask and the wafer is performed such that the alignment mark provided on the photomask and the alignment mark provided on the wafer are overlapped. When the alignment mark formed on the photomask is formed by the translucent part, alignment is performed so that the translucent part overlaps the alignment mark of the wafer. When exposure is performed in this state, exposure is performed not only on the resist portion on the region where the body region is formed but also on the resist portion on the alignment mark of the wafer. Next, in the developing process, the exposed resist portion is removed. As a result, an opening is formed in the portion of the resist on the region where the body region is formed, and an opening is also formed in the portion of the resist on the alignment mark on the wafer.

  Next, the ion implantation mask is patterned using the resist pattern as a mask. In the patterned ion implantation mask, an opening is formed above both the body region and the alignment mark. Next, ion implantation is performed on the wafer using the ion implantation mask. As a result, a body region is formed on the wafer and a p-type region is also formed on the alignment mark.

  Usually, the alignment mark is formed in a dicing area on the wafer surface. Therefore, when a plurality of chips are formed by cutting the wafer along the dicing area, most of the p-type area is removed together with the alignment mark. However, a part of the p-type region may be left around the chip. If the p-type region remains around the chip, a depletion layer spreads in the p-type region when a voltage is applied between the source electrode and the drain electrode. It is considered that drain leakage current is generated by the concentration of the electric field in the p-type region.

[Description of Embodiment]
(1) The manufacturing method of the wide band gap semiconductor device 100 according to one aspect of the present invention includes the following steps. A wide band gap semiconductor wafer 10 including a main surface 10a and having an n-type conductivity is prepared. Dicing region DR is formed on main surface 10a. Alignment mark region 30 is formed on main surface 10a. The alignment between the wide band gap semiconductor wafer 10 and the photomask 61 is performed using the alignment mark region 30. After the alignment process, a p-type region 71 is formed so as to overlap the alignment mark region 30. After the p-type region 71 is formed, a plurality of chips 5 are formed by cutting the wide band gap semiconductor wafer 10 along the dicing region DR. The p-type region 71 does not exist in the portion of the dicing region DR left on the plurality of chips 5.

  Here, the “wide band gap semiconductor” is a semiconductor having a larger band gap than silicon (Si), and includes, for example, silicon carbide (SiC), gallium nitride (GaN), and diamond.

  According to the method for manufacturing the wide band gap semiconductor device 100 according to (1) above, the p-type region 71 does not exist in the portion of the dicing region DR remaining on the plurality of chips 5. Therefore, it is possible to suppress the occurrence of drain leakage current due to the concentration of the electric field in the p-type region 71. As a result, the drain leak defect rate can be reduced.

  (2) In the method of manufacturing the wide band gap semiconductor device 100 according to (1) above, in the step of forming the alignment mark region 30, the alignment mark region 30 may be formed in the dicing region DR. In the step of forming the plurality of chips 5, the p-type region 71 may be removed. Thereby, since it is not necessary to form an alignment mark in the element region 2, a large area of the element region 2 can be secured.

  (3) In the method of manufacturing the wide band gap semiconductor device 100 according to (2), the width W2 of the p-type region 71 is divided by the width W1 of the dicing region DR in a direction perpendicular to the extending direction of the dicing region DR. The value obtained is not less than 1/12 and not more than 2/3, and the width W2 of the p-type region 71 in the direction perpendicular to the stretching direction satisfies at least one of not less than 10 μm and not more than 80 μm. Good. By ensuring a wide width of the p-type region 71, it is possible to reduce the drain leak defect rate while maintaining high alignment accuracy.

  (4) In the method of manufacturing the wide band gap semiconductor device 100 according to (2) or (3), the cutting width W3 of the wide band gap semiconductor wafer 10 in the step of forming the plurality of chips 5 is extended to the dicing region DR. The value divided by the width W1 of the dicing region DR in the direction perpendicular to the direction satisfies at least one of ¼ to 5/6 and the cutting width W3 of 30 μm to 100 μm. It may be. As a result, even if the position of the p-type region 71 varies, the p-type region 71 can be effectively removed.

  (5) In the method of manufacturing the wide band gap semiconductor device 100 according to any one of the above (1) to (4), the dicing region DR and the alignment mark region 30 may be formed simultaneously. Thereby, the manufacturing process of the wide band gap semiconductor device 100 can be simplified.

  (6) In the method of manufacturing the wide band gap semiconductor device 100 according to any one of (1) to (5), the wide band gap semiconductor wafer 10 includes at least one of silicon carbide, gallium nitride, and diamond. Also good. Silicon carbide, gallium nitride, and diamond can be suitably used for, for example, a power semiconductor device that controls a large current.

  (7) In the method for manufacturing the wide band gap semiconductor device 100 according to any one of (1) to (6), the maximum diameter of the main surface 10a may be 100 mm or more. The manufacturing method of the wide band gap semiconductor device 100 according to the present embodiment can be suitably used for a large-diameter wafer having a large number of alignment marks because the number of shots is large.

  (8) In the method of manufacturing the wide band gap semiconductor device 100 according to the above (1), in the step of forming the alignment mark region 30, the alignment mark region 30 is formed in a region surrounded by the dicing region DR on the main surface 10a. It may be formed. Thereby, since it is not necessary to form the p-type region 71 in the dicing region DR, it is possible to suppress the occurrence of drain leakage current due to the concentration of the electric field in the p-type region 71.

  (9) The wide band gap semiconductor wafer 10 according to one aspect of the present invention is a wide band gap semiconductor wafer 10 in which a dicing region DR is formed on the main surface 10a. The wide band gap semiconductor wafer 10 includes an alignment mark region 30 located in the dicing region and a p-type region 71 located in the alignment mark region 30. The value obtained by dividing the width W2 of the p-type region 71 by the width W1 of the dicing region DR in the direction perpendicular to the extending direction of the dicing region DR is 1/12 or more and 2/3 or less and The width W2 of the p-type region 71 in the vertical direction satisfies at least one of 10 μm or more and 80 μm or less. By ensuring a wide width of the p-type region 71, it is possible to reduce the drain leak defect rate while maintaining high alignment accuracy.

  (10) The wide band gap semiconductor wafer 10 according to one aspect of the present invention is a wide band gap semiconductor wafer in which a dicing region is formed on the main surface 10a. Wide band gap semiconductor wafer 10 includes an alignment mark region 30 located in a region surrounded by dicing region DR, and a p-type region 71 located in alignment mark region 30. The p-type region 71 does not exist in the dicing region DR. Thereby, since it is not necessary to form the p-type region 71 in the dicing region DR, it is possible to suppress the occurrence of drain leakage current due to the concentration of the electric field in the p-type region 71.

  (11) In the wide band gap semiconductor wafer 10 according to (9) or (10), the wide band gap semiconductor wafer 10 may include at least one of silicon carbide, gallium nitride, and diamond. Silicon carbide, gallium nitride, and diamond can be suitably used for, for example, a power semiconductor device that controls a large current.

  (12) In the wide band gap semiconductor wafer 10 according to any one of (9) to (11) above, the maximum diameter of the main surface 10a may be 100 mm or more. The manufacturing method of the wide band gap semiconductor device 100 according to this embodiment can be suitably used for a large diameter wafer having a large number of shots and a large number of alignment marks.

  (13) The wide band gap semiconductor chip 5 according to one aspect of the present invention is manufactured by cutting the wide band gap semiconductor wafer 10 according to any one of the above (9) to (12) along the dicing region DR. Is done. Thereby, the drain leakage current of the wide band gap semiconductor chip 5 can be reduced.

[Details of the embodiment]
Hereinafter, the present embodiment will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding a “-” (bar) above a number, but in this specification a negative sign is added before the number. Yes.

  First, a configuration of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example of a silicon carbide semiconductor device according to the present embodiment will be described.

  MOSFET 100 according to the present embodiment includes silicon carbide substrate 10, gate electrode 27, gate insulating film 15, interlayer insulating film 22, source electrode 16, surface protection electrode 19, drain electrode 21, and back surface protection. The electrode 23 is mainly included. Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b opposite to the first main surface 10a. Silicon carbide substrate 10 mainly includes a silicon carbide single crystal substrate 11 and a silicon carbide epitaxial layer 24 provided on silicon carbide single crystal substrate 11.

  Silicon carbide single crystal substrate 11 is made of, for example, polytype 4H hexagonal silicon carbide. The maximum diameter S of the first major surface 10a is, for example, 50 mm (about 2 inches) or more, preferably 75 mm (about 3 inches) or more, more preferably 100 mm (about 4 inches) or more, and further preferably 150 mm (about 6 inches) or more. The first major surface 10a is, for example, a surface that is off by 4 ° or less from the {0001} plane or {0001} plane. The first main surface 10a is, for example, a surface that is off by about 4 ° or less from the (0001) surface or the (0001) surface. The second main surface 10b is, for example, a surface that is off by about 4 ° or less from the (000-1) plane or the (000-1) plane.

Silicon carbide epitaxial layer 24 includes drift region 12, body region 13, source region 14, contact region 18, and guard ring region 17. Drift region 12 includes an n-type impurity such as nitrogen and has an n-type (first conductivity type) conductivity type. The concentration of the n-type impurity contained in drift region 12 is, for example, about 5.0 × 10 ¹⁵ cm ⁻³ . Body region 13 includes a p-type impurity such as Al (aluminum) or B (boron), for example, and has a p-type (second conductivity type) conductivity type. The concentration of the p-type impurity contained in body region 13 is, for example, about 1 × 10 ¹⁷ cm ⁻³ .

Source region 14 includes an n-type impurity such as phosphorus and has n-type conductivity. The source region 14 is formed so as to be surrounded by the body region 13 in a visual field (plan view) viewed along a direction perpendicular to the first main surface 10a. The concentration of the n-type impurity included in the source region 14 may be higher than the concentration of the n-type impurity included in the drift region 12. The concentration of the n-type impurity contained in the source region 14 is, for example, 1 × 10 ¹⁹ cm ⁻³ . Source region 14 is separated from drift region 12 by body region 13.

Contact region 18 includes a p-type impurity such as aluminum and has p-type conductivity. The contact region 18 is provided so as to be surrounded by the source region 14 in plan view. Contact region 18 is in contact with body region 13. The concentration of the p-type impurity included in the contact region 18 may be higher than the concentration of the p-type impurity included in the body region 13. The concentration of the p-type impurity contained in contact region 18 is, for example, 1 × 10 ¹⁹ cm ⁻³ .

Guard ring region 17 includes a p-type impurity such as aluminum and has p-type conductivity. The dose amount of the guard ring region 17 is, for example, 1 × 10 ¹³ cm ⁻² . The guard ring region 17 is in contact with the drift region 12. The guard ring region 17 is annular. Each of the plurality of guard ring regions 17 may be provided concentrically. Each of the plurality of guard ring regions 17 may be provided so as to surround the body region 13, the source region 14, and the contact region 18 in plan view.

  The gate insulating film 15 is provided on the first main surface 10a. Gate insulating film 15 is in contact with source region 14, body region 13, and drift region 12 on first main surface 10 a. The gate insulating film 15 may be in contact with the guard ring region 17 on the first main surface 10a. Gate insulating film 15 is made of, for example, silicon dioxide. The thickness of the gate insulating film 15 is, for example, not less than 40 nm and not more than 60 nm.

  The gate electrode 27 is provided on the gate insulating film 15. Gate insulating film 15 is sandwiched between gate electrode 27 and silicon carbide substrate 10. Gate electrode 27 is provided to face source region 14, body region 13, and drift region 12. The gate electrode 27 is made of a conductor such as polysilicon doped with impurities.

  Source electrode 16 is in contact with source region 14 and contact region 18 on first major surface 10a. The source electrode 16 includes, for example, TiAlSi. Preferably, source electrode 16 is in ohmic contact with each of source region 14 and contact region 18. The surface protective electrode 19 is in contact with the source electrode 16. The surface protection electrode 19 is provided so as to cover the interlayer insulating film 22. The surface protection electrode 19 is electrically connected to the source region 14 through the source electrode 16.

  The interlayer insulating film 22 covers the gate electrode 27. The interlayer insulating film 22 is provided in contact with the gate electrode 27 and the gate insulating film 15. The interlayer insulating film 22 electrically insulates the gate electrode 27 and the source electrode 16 from each other. Interlayer insulating film 22 is made of, for example, silicon dioxide.

  The drain electrode 21 is provided in contact with the second major surface 10b. Drain electrode 21 is made of, for example, a material such as NiSi (nickel silicide) capable of ohmic contact with n-type silicon carbide single crystal substrate 11. The back surface protective electrode 23 is electrically connected to the drain electrode 21. The back surface protective electrode 23 is made of, for example, a material containing aluminum.

  Next, the operation of MOSFET 100 as the silicon carbide semiconductor device according to the present embodiment will be described. In a state where the voltage applied to the gate electrode 27 is less than the threshold voltage, that is, in the off state, even if a voltage is applied between the source electrode 16 and the drain electrode 21, it is formed between the body region 13 and the drift region 12. The pn junction is reverse-biased and becomes non-conductive. On the other hand, when a voltage higher than the threshold voltage is applied to the gate electrode 27, a channel is formed in the body region 13. As a result, the source region 14 and the drift region 12 are electrically connected, and a current flows between the source electrode 16 and the drain electrode 21. As described above, the MOSFET 100 operates.

Next, a method for manufacturing MOSFET 100 according to the present embodiment will be described.
First, a step of preparing a semiconductor wafer (S10: FIG. 2) is performed. For example, an ingot (not shown) made of polytype 4H hexagonal silicon carbide is sliced to prepare n-type (first conductivity type) silicon carbide single crystal substrate 11. Next, n type drift region 12 is formed on silicon carbide single crystal substrate 11 by epitaxial growth. For example, a silicon carbide single crystal substrate 11 in an atmospheric gas containing hydrogen (H ₂ ) as a carrier gas and monosilane (SiH ₄ ), propane (C ₃ H ₈ ) and nitrogen (N ₂ ) as source gases. Is heated at a temperature of 1500 ° to 1700 °, for example. Thus, a wide band gap semiconductor wafer 10 including the first main surface 10a and the second main surface 10b opposite to the first main surface 10a and having the n-type conductivity is prepared (see FIG. 3). Drift region 12 constitutes first main surface 10a. Silicon carbide single crystal substrate 11 constitutes second main surface 10b (see FIG. 3). The wide band gap semiconductor wafer 10 may contain at least one of silicon carbide, gallium nitride, and diamond. For example, a gallium nitride substrate or a diamond substrate may be used instead of the silicon carbide single crystal substrate 11.

  Silicon carbide single crystal substrate 11 is made of, for example, polytype 4H hexagonal silicon carbide. The maximum diameter S (see FIG. 4) of the first main surface 10a is, for example, 50 mm (about 2 inches) or more, preferably 75 mm (about 3 inches) or more, more preferably 100 mm (about 4 inches) or more. More preferably 150 mm (about 6 inches) or more. The first major surface 10a is, for example, a surface that is off by 4 ° or less from the {0001} plane or {0001} plane. The first main surface 10a is, for example, a surface that is off by about 4 ° or less from the (0001) surface or the (0001) surface. The second main surface 10b is, for example, a surface that is off by about 4 ° or less from the (000-1) plane or the (000-1) plane.

Next, a step of forming a dicing region (S20: FIG. 2) is performed. For example, an etching mask (not shown) having an opening is formed on a region where dicing region DR is to be formed on first main surface 10a. The etching mask is made of a material containing, for example, silicon dioxide. Next, the first major surface 10a is etched using the etching mask. For example, reactive ion etching may be performed on silicon carbide wafer 10 using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas.

  In FIG. 4, a rectangular area 1 surrounded by a broken line is a shot area when exposed in an exposure process described later. That is, in the exposure process, reduced projection exposure is performed, the first main surface 10a is divided into a plurality of shot areas, and exposure is performed in each shot area. As shown in FIGS. 5 and 6, dicing region DR is formed on first main surface 10 a. The dicing region DR has a lattice shape when viewed from a direction perpendicular to the first main surface 10a. The dicing region DR may be formed so as to extend along the <11-20> direction, or may be formed so as to extend along the <1-100> direction. In other words, the <11-20> direction or the <1-100> direction is the extending direction of the dicing region DR. The dicing region DR may be formed in a lattice shape extending along the <11-20> direction and extending along the <1-100> direction. The element region 2 surrounded by the dicing region DR is a region where a semiconductor element such as a MOSFET is to be formed. As shown in FIG. 7, the dicing region DR may be a groove defined by the side surface SW3 and the bottom surface BT3 provided continuously with the side surface SW3.

Next, a step of forming alignment mark regions (S30: FIG. 2) is performed. For example, an area where the alignment mark 31 is to be formed on the first main surface 10a is covered, and an etching mask (not shown) having an opening around the area is formed. The etching mask is made of a material containing, for example, silicon dioxide. Next, the first major surface 10a is etched using the etching mask. For example, reactive ion etching may be performed on silicon carbide substrate 10 using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas. Thereby, the alignment mark 31 is formed in the 1st main surface 10a (refer FIG. 6).

  The alignment mark 31 may be convex or concave. As shown in FIG. 8, the alignment mark region 30 includes, for example, a convex alignment mark 31 and a first recess TR1 and a second recess TR2 formed around the alignment mark 31. First recess TR1 is defined by side surface SW1 and bottom surface BT1. The second recess TR2 is defined by the side surface SW2 and the bottom surface BT2. As shown in FIG. 6, the alignment mark region 30 may be formed in the dicing region DL. The convex alignment mark 31 may be a region formed between the first recess TR1 and the second recess TR2.

  Preferably, the first alignment mark 31, the second alignment mark 32, and the third alignment mark 33 are formed simultaneously. The first alignment mark 31, the second alignment mark 32, the third alignment mark 33, the first recess TR1, and the second recess TR2 constitute an alignment mark region 30. As shown in FIG. 6, the number of alignment mark regions 30 in the shot region 1 may be smaller than the number of element regions 2. The alignment mark region 30 is provided adjacent to one element region 2, but may not be provided around another element region 2.

  Preferably, the step of forming the dicing region (S20: FIG. 2) and the step of forming the alignment mark region (S30: FIG. 2) are performed simultaneously. For example, the first alignment mark 31, the second alignment mark 32, the third alignment mark 33, and the region where the element region 2 is to be formed are covered on the first main surface 10a, and the first alignment mark 31 and the second alignment mark are formed. An etching mask (not shown) having an opening in a region other than the mark 32, the third alignment mark 33, and the element region 2 is formed. Next, the first main surface 10a is etched using the etching mask as a mask. Thereby, the dicing region DR, the first alignment mark 31, the second alignment mark 32, and the third alignment mark 33 may be formed simultaneously.

  Region VIII, region IXA, region IXB, and region IXC in FIG. 9 correspond to region VIII, region IXA, region IXB, and region IXC in FIG. 6, respectively. As shown in FIGS. 6 and 9, a first alignment mark 31 used in the alignment process of the body region 13 (see FIG. 1) is formed in the region VIII. In the region IXA, a second alignment mark 32 used in the alignment process of the contact region 18 (see FIG. 1) is formed. In the region IXB, a third alignment mark 33 used in the alignment process of the guard ring region 17 (see FIG. 1) is formed. As shown in FIG. 6, the first alignment mark 31, the second alignment mark 32, and the third alignment mark 33 may be positioned on a straight line on the dicing region DR.

  Next, a step of forming an ion implantation mask (S40: FIG. 2) is performed. The ion implantation mask 41 is formed on the first major surface 10a. For example, at a temperature of 600 ° C. or higher and 800 ° C. or lower, TEOS (Tetraethylorthosilicate) gas is introduced onto the first main surface 10a, whereby the ion implantation mask 41 is formed. Ion implantation mask 41 is made of a material containing, for example, silicon dioxide. The thickness of the ion implantation mask 41 is, for example, 1.8 μm. The ion implantation mask 41 may be formed on the entire first main surface 10a. Specifically, the ion implantation mask 41 is formed in the element region 2, the alignment mark region 30, and the dicing region DR. That is, the ion implantation mask 41 is formed in contact with the first alignment mark 31, the second alignment mark 32, and the third alignment mark 33. The ion implantation mask 41 may be formed so as to fill the first recess TR1 and the second recess TR2.

  Next, a step of forming a mask layer (S50: FIG. 2) is performed. For example, a mask layer 51 made of a material including a resist is formed on the ion implantation mask 41. The thickness of mask layer 51 is, for example, 3 μm. Specifically, the mask layer 51 is formed in the element region 2, the alignment mark region 30, and the dicing region DR. The mask layer 51 is formed at a position facing the first alignment mark 31, the second alignment mark 32, and the third alignment mark 33 (see FIG. 10). As described above, mask layer 51 is formed on first main surface 10a. As shown in FIG. 10, the mask layer 51 is formed on the first major surface 10 a via the ion implantation mask 41.

  Next, an alignment step (S60: FIG. 2) is performed. Specifically, the alignment mark region 30 formed on the wide band gap semiconductor wafer 10 and the alignment mark formed on the photomask 61 are overlapped in a direction perpendicular to the first main surface 10a. The alignment of the wide band gap semiconductor wafer 10 and the photomask 61 is performed. More specifically, the wide band gap semiconductor wafer 10 and the photomask 61 are aligned using the first alignment mark 31 in the alignment mark region 30.

  As shown in FIG. 11, the photomask 61 has translucent parts 61a and 61b and a light shielding part 61c. The translucent part 61a is an alignment mark formed on a photomask, for example. For example, when viewed from a direction perpendicular to the first main surface 10 a, the wide band gap semiconductor so that the translucent portion 61 a of the photomask 61 overlaps the first alignment mark 31 formed on the wide band gap semiconductor wafer 10. The alignment between the wafer 10 and the photomask 61 is performed. Preferably, the wide band gap semiconductor wafer 10 and the photomask 61 are aligned so that the translucent portion 61a is surrounded by the outer edge of the first alignment mark 31 when viewed from the direction perpendicular to the first major surface 10a. Is done.

  The recognition method of the alignment mark 31 may be an LSA (Laser Step Alignment) method or an FIA (Field Image Alignment) method. The LSA method is an optical alignment method in which a laser is applied to an alignment mark and the reflected light of the laser is analyzed for alignment. The FIA method is an image recognition method and is a method for performing alignment by recognizing an edge of an image recognized by a camera.

  Next, a step of forming an opening in the mask layer (S70: FIG. 2) is performed. After the alignment step (S60: FIG. 2), the mask layer 51 is exposed using the photomask 61. For example, exposure is performed using a light source (not shown) disposed on the side opposite to the wide band gap semiconductor wafer 10 when viewed from the photomask 61. The light used for exposure is, for example, ultraviolet light. The light used for exposure may be g-line, h-line, i-line or electron beam. Light from the light source is irradiated in a direction substantially perpendicular to the first main surface 10a (the direction of the arrow in FIG. 12). As shown in FIG. 12, the light passes through the light transmitting portions 61 a and 61 b of the photomask 61 and is applied to the mask layer 51. The portion of the mask layer 51 that faces the light shielding portion 61c is not irradiated with light.

  The exposure of the wide band gap semiconductor wafer 10 is performed by, for example, a step-and-repeat method. As shown in FIG. 4, after exposure is performed in a certain shot region 1, the wide band gap semiconductor wafer 10 moves in a direction parallel to the first main surface 10a. Next, exposure is performed in another shot region 1. Thus, the exposure and the movement of the wide band gap semiconductor wafer 10 are repeatedly performed.

  Next, development of the mask layer 51 is performed. For example, by immersing the wide band gap semiconductor wafer 10 on which the mask layer 51 is formed in a developing solution, a part of the mask layer 51 is etched. When the mask layer 51 is a positive photoresist, the portions 51 a and 51 b irradiated with light are etched, and the portion 51 c not irradiated with light remains on the ion implantation mask 41 without being etched. On the other hand, when the mask layer 51 is a negative photoresist, the portion 51c not irradiated with light is etched, and the portions 51a and 51b irradiated with light remain on the ion implantation mask 41 without being etched. As described above, the openings O11 and O12 are formed in the mask layer 51. Specifically, the opening O11 is formed at a position facing the first alignment mark 31, and the opening O12 is formed at a position facing the region where the body region 13 is to be formed in the element region 2 (FIG. 13).

Next, the ion implantation mask is etched. For example, the mask layer 51c in which the openings O11 and O12 are formed is used as a mask, and the ion implantation mask 41 is dry-etched with a gas containing CF ₄ . Specifically, the portions 41a and 41b of the ion implantation mask 41 corresponding to the openings O11 and O12 are etched. Thus, openings O21 and O22 are formed in the ion implantation mask 41. Specifically, the opening O21 is formed at a position facing the first alignment mark 31, and the opening O22 is formed at a position facing the region where the body region 13 is to be formed in the element region 2. Next, the mask layer 51c is removed from the ion implantation mask 41 (see FIG. 14).

  Next, a step of forming a first p-type region (S80: FIG. 2) is performed. As shown in FIG. 15, using the ion implantation mask 41c in which the openings O21 and O22 are formed as a mask, a p-type impurity such as aluminum is applied to the first main surface 10a with respect to the first main surface 10a. Are implanted along a direction substantially perpendicular to the direction (the direction of the arrow in FIG. 15). Thereby, the first p-type region 71 is formed in the region of the wide band gap semiconductor wafer 10 that overlaps the openings O11 and O21. That is, the first p-type region 71 is formed so as to overlap with the alignment region 30. The first p-type region 71 is formed in the dicing region DR.

  Specifically, a first p-type region 71 is formed in the first alignment mark 31. The depth of the first p-type region 71 may be larger, smaller, or the same as the depth of the first recess TR1 and the second recess TR2. Similarly, the body region 13 is formed in the region of the wide band gap semiconductor wafer 10 that overlaps the openings O12 and O22. The body region 13 is formed in the element region 2. First p-type region 71 and body region 13 are formed simultaneously. The depth of the first p-type region 71 and the depth of the body region 13 are substantially the same. Next, the ion implantation mask 41c is removed from the first main surface 10a.

  Next, a step of forming a source region is performed. First, an ion implantation mask having an opening is formed on a region where the source region 14 is formed. Next, an n-type impurity such as phosphorus or nitrogen is ion-implanted into the body region 13. Thereby, the source region 14 in contact with the body region 13 is formed.

  Next, a step of forming a second p-type region (S90: FIG. 2) is performed. First, ion implantation mask 42 made of, for example, a material containing silicon dioxide is formed on first main surface 10a. Next, a mask layer 52 made of a material including a resist, for example, is formed on the ion implantation mask 42. Next, the alignment of the wide band gap semiconductor wafer 10 and the photomask 62 is performed using the second alignment mark 32 in the alignment mark region 30. For example, when viewed from a direction perpendicular to the first main surface 10 a, the wide band gap semiconductor so that the translucent portion 62 a of the photomask 62 overlaps with the second alignment mark 32 formed on the wide band gap semiconductor wafer 10. The alignment between the wafer 10 and the photomask 62 is performed.

  Next, the mask layer 52 is exposed using the photomask 62. Light from the light source is irradiated in a direction substantially perpendicular to the first major surface 10a (the direction of the arrow in FIG. 16). As shown in FIG. 16, the light passes through the light transmitting portions 62 a and 62 b of the photomask 62 and is applied to the mask layer 52. The portion of the mask layer 52 that faces the light shielding portion 62c is not irradiated with light.

Next, development of the mask layer 52 is performed. When the mask layer 52 is a positive photoresist, the portions 52a and 52b irradiated with light are etched, and the portion 52c not irradiated with light remains on the ion implantation mask 42 without being etched. Thereby, openings O31 and O32 are formed in the mask layer 52c. Specifically, the opening O31 is formed at a position facing the second alignment mark 32, and the opening O32 is formed at a position facing the region where the contact region 18 is to be formed in the element region 2 (FIG. 17). Next, the ion implantation mask is etched. For example, the mask layer 52c in which the openings O31 and O32 are formed is used as a mask, and the ion implantation mask 42 is dry-etched with a gas containing CF ₄ . Thereby, openings O41 and O42 are formed in the ion implantation mask. Next, the mask layer 52 c is removed from the ion implantation mask 42.

  As shown in FIG. 18, using the ion implantation mask 42c in which the openings O41 and O42 are formed as a mask, a p-type impurity such as aluminum is introduced into the first main surface 10a with respect to the first main surface 10a. Are implanted along a direction substantially perpendicular to the direction (the direction of the arrow in FIG. 18). As a result, the second p-type region 72 is formed in the region of the wide band gap semiconductor wafer 10 overlapping the openings O31 and O41. That is, the second p-type region 72 is formed so as to overlap with the alignment region 30. Second p-type region 72 is formed in dicing region DR.

  Specifically, the second p-type region 72 is formed in the second alignment mark 32. The depth of the second p-type region 72 may be smaller than the depth of the first p-type region 71. Similarly, the contact region 18 is formed in the region of the wide band gap semiconductor wafer 10 that overlaps the openings O32 and O42. The contact region 18 is formed in the element region 2. Second p-type region 72 and contact region 18 are formed simultaneously. The depth of the second p-type region 72 and the depth of the contact region 18 are substantially the same. Next, the ion implantation mask 42c is removed from the first main surface 10a.

  Next, a step of forming a third p-type region (S100: FIG. 2) is performed. First, ion implantation mask 43 made of, for example, a material containing silicon dioxide is formed on first main surface 10a. Next, a mask layer 53 made of, for example, a material containing a resist is formed on the ion implantation mask 43. Next, alignment of the wide band gap semiconductor wafer 10 and the photomask 63 is performed using the third alignment mark 33 in the alignment mark region 30. For example, when viewed from the direction perpendicular to the first main surface 10 a, the wide band gap semiconductor so that the light transmitting portion 63 a of the photomask 63 overlaps with the third alignment mark 33 formed on the wide band gap semiconductor wafer 10. The alignment between the wafer 10 and the photomask 63 is performed.

  Next, the mask layer 53 is exposed using the photomask 63. Light from the light source is irradiated in a direction substantially perpendicular to the first major surface 10a (the direction of the arrow in FIG. 19). As shown in FIG. 19, the light passes through the light transmitting parts 63 a and 63 b of the photomask 63 and is applied to the mask layer 53. The portion 53c of the mask layer 53 that faces the light shielding portion 63c is not irradiated with light.

Next, development of the mask layer 53 is performed. When the mask layer 53 is a positive photoresist, the portions 53 a and 53 b irradiated with light are etched, and the portion 53 c not irradiated with light remains on the ion implantation mask 43 without being etched. Thereby, openings O51 and O52 are formed in the mask layer 53. Specifically, the opening O51 is formed at a position facing the third alignment mark 33, and the opening O52 is formed at a position facing the region where the guard ring region 17 is to be formed in the element region 2 ( FIG. 20). Next, the ion implantation mask 43 is etched. For example, the mask layer 53c in which the openings O51 and O52 are formed is used as a mask, and the ion implantation mask 43 is dry-etched with a gas containing CF ₄ . Thus, openings O61 and O62 are formed in the ion implantation mask 43. Next, the mask layer 53 c is removed from the ion implantation mask 43.

  As shown in FIG. 21, using the ion implantation mask 43 in which the openings O61 and O62 are formed as a mask, a p-type impurity such as aluminum is introduced into the first main surface 10a with respect to the first main surface 10a. Are implanted along a direction substantially perpendicular to the direction (the direction of the arrow in FIG. 21). As a result, a third p-type region 73 is formed in the region of the wide band gap semiconductor wafer 10 overlapping the openings O51 and O61. That is, the third p-type region 73 is formed so as to overlap with the alignment region 30. The third p-type region 73 is formed in the dicing region DR.

  Specifically, a third p-type region 73 is formed in the third alignment mark 33. The depth of the third p-type region 73 may be smaller than the depth of the first p-type region 71. Similarly, the guard ring region 17 is formed in the region of the wide band gap semiconductor wafer 10 that overlaps the openings O52 and O62. The guard ring region 17 is formed in the element region 2. Third p-type region 73 and guard ring region 17 are formed simultaneously. The depth of the third p-type region 73 and the depth of the guard ring region 17 are substantially the same. Next, the ion implantation mask 43c is removed from the first main surface 10a (see FIG. 22).

  Region XXA, region XXB, region XXC, and region XXD in FIG. 22 correspond to region XXA, region XXB, region XXC, and region XXD in FIG. 23, respectively. As shown in FIG. 23, the first p-type region 71 is formed so as to be surrounded by the first alignment mark 31 when viewed from the direction perpendicular to the first major surface 10a. Similarly, the second p-type region 72 is formed so as to be surrounded by the second alignment mark 32 when viewed from the direction perpendicular to the first major surface 10a. Similarly, the third p-type region 73 is formed so as to be surrounded by the third alignment mark 33 when viewed from the direction perpendicular to the first major surface 10a. The first p-type region 71, the second p-type region 72, and the third p-type region 73 may be positioned on a straight line.

  Next, an activation annealing step is performed. For example, the wide band gap semiconductor wafer 10 is heated to about 1800 ° C. in an argon atmosphere. As a result, the p-type impurity introduced into the body region 13, the contact region 18 and the guard ring region 17 and the n-type impurity introduced into the source region 14 are activated. As a result, desired carriers are generated in the body region 13, the source region 14, the contact region 18, and the guard ring region 17.

  Next, a step of forming a gate insulating film (S110: FIG. 2) is performed. For example, the wide band gap semiconductor wafer 10 is heated to about 1300 ° C. in an atmosphere containing oxygen. Thus, the first main surface 10a of the wide band gap semiconductor wafer 10 is thermally oxidized, and the gate insulating film 15 made of a material containing silicon dioxide is formed on the first main surface 10a. Gate insulating film 15 is provided in contact with drift region 12, body region 13, source region 14, contact region 18, and guard ring region 17 on first main surface 10a (see FIG. 24).

  Next, a step of forming a gate electrode (S120: FIG. 2) is performed. For example, gate electrode 27 made of polysilicon containing an impurity such as phosphorus is formed on gate insulating film 15 by low-pressure CVD. The gate electrode 27 is formed at a position facing the source region 14, the body region 13, and the drift region 12. Next, interlayer insulating film 22 is formed so as to cover gate electrode 27 by, for example, plasma CVD. The interlayer insulating film 22 is provided in contact with the gate electrode 27 and the gate insulating film 15. Interlayer insulating film 22 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 22 may be provided at a position facing the guard ring region 17.

  Next, a step of forming a source electrode (S130: FIG. 2) is performed. For example, parts of gate insulating film 15 and interlayer insulating film 22 are removed by, for example, dry etching, so that contact region 18 and source region 14 are exposed from gate insulating film 15 and interlayer insulating film 22 (see FIG. 25). ). Next, the source electrode 16 is formed in contact with the contact region 18 and the source region 14 by, for example, sputtering. The source electrode 16 is made of a material containing, for example, Ti, Al, and Si.

  Next, silicon carbide substrate 10 provided with source electrode 16 is heated to about 1000 ° C., for example. As a result, the source electrode 16 is silicided, and the source electrode 16 that is in ohmic contact with the source region 14 is formed. Preferably, the source electrode 16 is in ohmic contact with the contact region 18. Next, a surface protective electrode 19 in contact with the source electrode 16 is formed. The surface protection electrode 19 is made of a material containing aluminum, for example. The surface protective electrode 19 is formed so as to cover the interlayer insulating film 22 (see FIG. 26).

  Next, a step of forming a drain electrode (S140: FIG. 2) is performed. For example, the drain electrode 21 made of a material containing NiSi is formed so as to be in contact with the second main surface 10b. Next, the back surface protective electrode 23 in contact with the drain electrode 21 is formed. The back surface protective electrode 23 is made of, for example, a material containing aluminum.

  Next, a step of forming a plurality of chips (S150: FIG. 2) is performed. After the p-type region 71 is formed, a plurality of chips 5 are formed by cutting the wide band gap semiconductor wafer 10 along the dicing region DR. The wide band gap semiconductor wafer 10 is cut by, for example, a blade. Specifically, a part of the dicing area DR is removed by the blade. The width of the region BR to be removed (in other words, the cutting width W3) is smaller than the width W1 of the dicing region DR. The cutting width W3 may be substantially the same as the width of the blade.

  The value obtained by dividing the cutting width W3 of the wide band gap semiconductor wafer 10 by the width W1 of the dicing region DR in the direction perpendicular to the extending direction of the dicing region DR is not less than 1/4 and not more than 5/6. The width W3 may satisfy at least one of 30 μm or more and 100 μm or less. Preferably, a value obtained by dividing the cutting width W3 of the wide band gap semiconductor wafer 10 by the width W1 of the dicing region DR is not less than 1/4 and not more than 2/3. Preferably, the cutting width W3 is not less than 30 μm and not more than 80 μm.

  By cutting the wide band gap semiconductor wafer 10, the first p-type region 71, the second p-type region 72, and the third p-type region 73 are removed. A value obtained by dividing the width W2 of the first p-type region 71 by the width W1 of the dicing region DR in a direction perpendicular to the extending direction of the dicing region DR is not less than 1/12 and not more than 2/3. The width W2 of the first p-type region 71 in the direction perpendicular to the direction may satisfy at least one of not less than 10 μm and not more than 80 μm. Preferably, a value obtained by dividing the width W2 of the first p-type region 71 by the width W1 of the dicing region DR is not less than 1/12 and not more than 1/2. Preferably, the width W2 of the first p-type region 71 is not less than 10 μm and not more than 60 μm.

  The width W2 of the first p-type region 71 may be the same as or different from the width of the second p-type region 72. Similarly, the width W2 of the first p-type region 71 may be the same as or different from the width of the third p-type region 73. Preferably, the cutting width W3 is larger than the maximum value among the width W2 of the first p-type region 71, the width of the second p-type region 72, and the width of the third p-type region 73. Thereby, the width W2 of the first p-type region 71, the width of the second p-type region 72, and the third p-type region 73 are completely removed by the blade.

  As shown in FIG. 28, after the wide band gap semiconductor wafer 10 is cut along the dicing region DR, the portion 4 of the dicing region DR may be left around the element region 2 of the chip 5. The portion 4 of the dicing region DR is provided so as to surround the element region 2 in a direction perpendicular to the first main surface 10a. The first p-type region 71, the second p-type region 72, and the third p-type region 73 do not exist in the portion of the dicing region DR left on the chip 5. FIG. 1 is a schematic cross-sectional view taken along the line II of FIG.

  Next, a method for manufacturing MOSFET 100 according to a modification of the present embodiment will be described. The manufacturing method of MOSFET 100 according to the modification differs from the manufacturing method of MOSFET 100 according to the above-described embodiment in that the alignment region is not formed on the dicing region DR but in a region surrounded by the dicing region DR. The other points are almost the same as the method for manufacturing MOSFET 100 according to the above embodiment. Hereinafter, points different from the method of manufacturing MOSFET 100 according to the above embodiment will be mainly described.

  As shown in FIGS. 29 and 30, in the step of forming the alignment mark region (S30: FIG. 2), the alignment mark region 30 may be formed in a region other than the dicing region DR. For example, alignment mark region 30 may be formed in a region surrounded by dicing region DR on first main surface 10a. That is, the first p-type region 71, the second p-type region 72, and the third p-type region 73 may be formed in a region surrounded by the dicing region DR in the first main surface 10a. . The alignment mark region 30 may be formed so as to be surrounded by the element region 2 when viewed from a direction perpendicular to the first major surface 10a. The alignment mark region 30 is formed so as to be surrounded by a certain element region 2 and may not be formed in the other element region 2. As shown in FIG. 29, when, for example, 16 element regions 2 exist in the shot region 1, the alignment mark region 30 is formed only in the two element regions 2, and the other 14 elements It does not need to be formed in the element region 2.

  As shown in FIG. 31, after the step of forming the third p-type region (S100: FIG. 2), the first p-type region 71 as viewed from the direction perpendicular to the first main surface 10a, The second p-type region 72 and the third p-type region 73 are provided so as to be surrounded by the element region 2. The first p-type region 71, the second p-type region 72, and the third p-type region 73 are surrounded by the dicing region DR when viewed from the direction perpendicular to the first major surface 10a. May be provided. The first p-type region 71, the second p-type region 72, and the third p-type region 73 may be positioned on a straight line or may not be positioned on a straight line.

  Next, the configuration of the wide band gap semiconductor wafer 10 according to the present embodiment will be described.

  As shown in FIG. 23, a dicing region DR is formed on the first main surface 10 a of the wide band gap semiconductor wafer 10. The wide band gap semiconductor wafer 10 includes an alignment mark region 30 located in the dicing region DR, a first p-type region 71, a second p-type region 72, and a third p-type region 73. . First p-type region 71, second p-type region 72, and third p-type region 73 are located in alignment mark region 30.

  As described above, the alignment mark region 30 includes the convex region (that is, the first alignment mark 31, the second alignment mark 32, and the third alignment mark 33) and the concave region that surrounds the convex region (that is, the first alignment mark 31). 1 recess TR1 and second recess TR2). The first p-type region 71, the second p-type region 72, and the third p-type region 73 may be located in the convex region of the alignment mark region 30 or the concave shape of the alignment mark region 30. It may be located in the area. As shown in FIG. 23, the number of alignment mark regions 30 in the shot region 1 may be smaller than the number of element regions 2. Similarly, the number of first p-type regions 71, second p-type regions 72, and third p-type regions 73 in the shot region 1 may be smaller than the number of element regions 2.

  The value obtained by dividing the width W2 of the p-type region 71 by the width W1 of the dicing region DR in the direction perpendicular to the extending direction of the dicing region DR is 1/12 or more and 2/3 or less and The width W2 of the p-type region 71 in the vertical direction satisfies at least one of 10 μm to 80 μm. Preferably, a value obtained by dividing the width W2 of the p-type region 71 by the width W1 of the dicing region DR is not less than 1/12 and not more than 1/2. Preferably, the width W2 of the p-type region 71 is not less than 10 μm and not more than 60 μm. As described above, the wide band gap semiconductor wafer 10 may include at least one of silicon carbide, gallium nitride, and diamond. The maximum diameter S (see FIG. 4) of the first major surface 10a is, for example, 100 mm (about 4 inches) or more, and preferably 150 mm (about 6 inches) or more.

  Next, the configuration of the wide band gap semiconductor wafer 10 according to a modification of the present embodiment will be described. The wide band gap semiconductor wafer 10 according to the modification has the wide band gap semiconductor wafer according to the above embodiment in that the alignment region is not formed on the dicing region DR but in a region surrounded by the dicing region DR. 10 is substantially the same as the wide band gap semiconductor wafer 10 according to the above embodiment in other points. Hereinafter, the points different from the wide band gap semiconductor wafer 10 according to the above embodiment will be mainly described.

  As shown in FIG. 31, the wide band gap semiconductor wafer 10 includes an alignment mark region 30 located in a region surrounded by the dicing region DR, a first p-type region 71, and a second p-type region 72. And the third p-type region 73 may be included. First p-type region 71, second p-type region 72, and third p-type region 73 are located in alignment mark region 30. The first p-type region 71, the second p-type region 72, and the third p-type region 73 do not exist in the dicing region DR.

  Next, the configuration of the wide band gap semiconductor chip 5 according to the present embodiment will be described.

  As shown in FIGS. 27 and 28, the wide band gap semiconductor chip 5 is manufactured by cutting the wide band gap semiconductor wafer 10 along the dicing region DR. In the wide band gap semiconductor wafer 10, the alignment mark region 30 may be positioned in the dicing region DR as shown in FIG. 27, or the alignment mark region 30 is surrounded by the dicing region DR as shown in FIG. It may be located in the designated area. The wide band gap semiconductor chip 5 shown in FIG. 28 is manufactured by cutting the wide band gap semiconductor wafer 10 shown in FIG. 27 along the dicing region DR. Similarly, the wide band gap semiconductor chip 5 shown in FIG. 32 is manufactured by cutting the wide band gap semiconductor wafer 10 shown in FIG. 31 along the dicing region DR.

As shown in FIGS. 28 and 32, the wide band gap semiconductor chip 5 has an element region 2 and a portion 4 of a dicing region DR. As shown in FIG. 1, the element region 2 is provided with a semiconductor element such as a MOSFET 100, for example. The portion 4 of the dicing region DR is provided so as to surround the element region 2 in a direction perpendicular to the first main surface 10a. In the portion 4 of the dicing region DR, the first p-type region 71, the second p-type region 72, and the third p-type region 73 do not exist. Therefore, the drain leakage current can be reduced. For example, the current density of the drain leakage current when a voltage of 1700 V is applied between the source electrode 16 and the drain electrode 21 of the MOSFET 100 is 10 μA / cm ² or less. By removing all the dicing region DR, the portion 4 of the dicing region DR may not be present.

  As shown in FIG. 32, the wide band gap semiconductor chip 5 may have an alignment mark region 30 surrounded by the portion 4 of the dicing region DR. As shown in FIG. 28, the wide band gap semiconductor chip 5 may not have the alignment mark region 30.

  Although the case where silicon carbide semiconductor device 100 is a planar MOSFET has been described in the above embodiment, silicon carbide semiconductor device 100 is not limited to a planar MOSFET. Silicon carbide semiconductor device 100 may be, for example, a trench MOSFET, Schottky barrier diode, IGBT (Insulated Gate Bipolar Transistor), or JFET (Junction Field Effect Transistor). In the above embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type is p-type and the second conductivity type is n-type. There may be.

  Next, functions and effects of the method for manufacturing the wide band gap semiconductor device, the wide band gap semiconductor wafer, and the wide band gap semiconductor chip according to the present embodiment will be described.

  According to the method for manufacturing wide band gap semiconductor device 100 according to the present embodiment, p-type region 71 does not exist in the portion of dicing region DR remaining on the plurality of chips 5. Therefore, it is possible to suppress the occurrence of drain leakage current due to the concentration of the electric field in the p-type region 71. As a result, the drain leak defect rate can be reduced.

  Further, according to the method for manufacturing wide band gap semiconductor device 100 according to the present embodiment, alignment mark region 30 is formed in dicing region DR. In the step of forming the plurality of chips 5, the p-type region 71 is removed. Thereby, since it is not necessary to form the alignment mark 31 in the element region 2, a large area of the element region 2 can be secured.

  Furthermore, according to the method for manufacturing wide band gap semiconductor device 100 according to the present embodiment, in the direction perpendicular to the extending direction of dicing region DR, width W2 of p-type region 71 is divided by width W1 of dicing region DR. The measured value satisfies at least one of 1/12 or more and 2/3 or less and the width W2 of the p-type region 71 in the direction perpendicular to the stretching direction is 10 μm or more and 80 μm or less. By ensuring a wide width of the p-type region 71, it is possible to reduce the drain leak defect rate while maintaining high alignment accuracy.

  Furthermore, according to the manufacturing method of wide band gap semiconductor device 100 according to the present embodiment, the cutting width W3 of wide band gap semiconductor wafer 10 in the step of forming a plurality of chips 5 is set with respect to the extending direction of dicing region DR. The value divided by the width W1 of the dicing region DR in the vertical direction satisfies at least one of ¼ to 5/6 and the cutting width W3 of 30 μm to 100 μm. As a result, even if the position of the p-type region 71 varies, the p-type region 71 can be effectively removed.

  Furthermore, according to the method for manufacturing wide band gap semiconductor device 100 according to the present embodiment, dicing region DR and alignment mark region 30 are formed simultaneously. Thereby, the manufacturing process of the wide band gap semiconductor device 100 can be simplified.

  Furthermore, according to the method for manufacturing wide band gap semiconductor device 100 according to the present embodiment, wide band gap semiconductor wafer 10 includes at least one of silicon carbide, gallium nitride, and diamond. Silicon carbide, gallium nitride, and diamond can be suitably used for, for example, a power semiconductor device that controls a large current.

  Furthermore, according to the method for manufacturing wide band gap semiconductor device 100 according to the present embodiment, the maximum diameter of main surface 10a is 100 mm or more. The manufacturing method of the wide band gap semiconductor device 100 according to the present embodiment can be suitably used for a large-diameter wafer having a large number of alignment marks because the number of shots is large.

  Furthermore, according to the method for manufacturing wide band gap semiconductor device 100 according to the present embodiment, alignment mark region 30 is formed in a region surrounded by dicing region DR on main surface 10a. Thereby, since it is not necessary to form the p-type region 71 in the dicing region DR, it is possible to suppress the occurrence of drain leakage current due to the concentration of the electric field in the p-type region 71.

  The wide band gap semiconductor wafer 10 according to the present embodiment is a wide band gap semiconductor wafer 10 in which a dicing region DR is formed on the main surface 10a. The wide band gap semiconductor wafer 10 includes an alignment mark region 30 located in the dicing region and a p-type region 71 located in the alignment mark region 30. The value obtained by dividing the width W2 of the p-type region 71 by the width W1 of the dicing region DR in the direction perpendicular to the extending direction of the dicing region DR is 1/12 or more and 2/3 or less and The width W2 of the p-type region 71 in the vertical direction satisfies at least one of 10 μm or more and 80 μm or less. By ensuring a wide width of the p-type region 71, it is possible to reduce the drain leak defect rate while maintaining high alignment accuracy.

  The wide band gap semiconductor wafer 10 according to the present embodiment is a wide band gap semiconductor wafer in which a dicing region is formed on the main surface 10a. Wide band gap semiconductor wafer 10 includes an alignment mark region 30 located in a region surrounded by dicing region DR, and a p-type region 71 located in alignment mark region 30. The p-type region 71 does not exist in the dicing region DR. Thereby, since it is not necessary to form the p-type region 71 in the dicing region DR, it is possible to suppress the occurrence of drain leakage current due to the concentration of the electric field in the p-type region 71.

  Further, according to the wide band gap semiconductor wafer 10 according to the present embodiment, the wide band gap semiconductor wafer 10 includes at least one of silicon carbide, gallium nitride, and diamond. Silicon carbide, gallium nitride, and diamond can be suitably used for, for example, a power semiconductor device that controls a large current.

  Furthermore, according to the wide band gap semiconductor wafer 10 according to the present embodiment, the maximum diameter of the main surface 10a is 100 mm or more. The manufacturing method of the wide band gap semiconductor device 100 according to this embodiment can be suitably used for a large diameter wafer having a large number of shots and a large number of alignment marks.

  The wide band gap semiconductor chip 5 according to the present embodiment is manufactured by cutting the wide band gap semiconductor wafer 10 along the dicing region DR. Thereby, the drain leakage current of the wide band gap semiconductor chip 5 can be reduced.

(Sample preparation)
First, two types of groups of wide band gap semiconductor chips 5 are prepared. The wide band gap semiconductor chip 5 includes a MOSFET 100 (FIG. 1) having a breakdown voltage specification of 1700V. The wide band gap semiconductor chip 5 of the first group is a wide band gap semiconductor chip 5 in which no p-type region exists in the portion 4 of the dicing region DR. The wide band gap semiconductor chip 5 of the second group is a wide band gap semiconductor chip 5 in which the p-type region remains in the portion 4 of the dicing region DR.

  The first group of wide band gap semiconductor chips 5 includes a first p-type region 71, a second p-type region 72, and a third p-type region 73 formed in the dicing region DR, The first p-type region 71, the second p-type region 72, and the third p-type region 73 are manufactured by being completely removed. On the other hand, after the first p-type region 71, the second p-type region 72, and the third p-type region 73 are formed in the dicing region DR, the second group of wide band gap semiconductor chips 5 is formed. The first p-type region 71, the second p-type region 72, and the third p-type region 73 are manufactured so as to remain in the portion 4 of the dicing region DR.

(Experiment)
The wide band gap semiconductor chip 5 including the MOSFET 100 is disposed at a temperature of 150 ° C. With the gate closed, a voltage of 1700 V is applied between the source electrode 16 and the drain electrode 21 for 10 hours. In a state where a voltage of 1700 V is applied between the source electrode 16 and the drain electrode 21, the drain leakage current is measured at regular intervals.

(result)
As shown in FIG. 33, the second group of wide bandgap semiconductor chips 5 having the p-type region in the dicing region DR 4 has the application time of about 0.5 hours to about 1 hour. The drain leakage current increases, and after about 3 hours of application time, the drain leakage current becomes substantially constant. The drain leakage current of the second group of wide band gap semiconductor chips 5 after the application time of 10 hours is greater than 1 × 10 ⁻⁷ A.

On the other hand, in the first group of wide band gap semiconductor chips 5 in which the p-type region is not present in the portion 4 of the dicing region DR, the drain leakage current is kept low until the application time of 10 hours elapses. The drain leakage current of the first group of wide band gap semiconductor chips 5 after 10 hours of application time is less than 1 × 10 ⁻⁷ A.

For example, when a wide band gap semiconductor chip 5 having a drain leakage current of less than 1 × 10 ⁻⁷ A is a good product and a wide band gap semiconductor chip 5 having a drain leakage current of 1 × 10 ⁻⁷ A or more is a defective product, the first The wide band gap semiconductor chips 5 in the second group are all judged to be non-defective products, and all the wide band gap semiconductor chips 5 in the second group are judged to be defective. From the above results, it can be seen that the drain leak defect rate can be reduced by forming the wide band gap semiconductor chip 5 so that the p-type region does not exist in the portion 4 of the dicing region DR.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 Shot region 2 Element region 4 Dicing region part 5 Wide band gap semiconductor chip (chip)
10 Wide band gap semiconductor wafer (silicon carbide wafer, silicon carbide substrate)
10a First main surface (main surface)
10b Second main surface 11 Silicon carbide single crystal substrate 12 Drift region 13 Body region 14 Source region 15 Gate insulating film 16 Source electrode 17 Guard ring region 18 Contact region 19 Surface protective electrode 21 Drain electrode 22 Interlayer insulating film 23 Back surface protective electrode 24 Silicon carbide epitaxial layer 27 Gate electrode 30 Alignment mark region 31 First alignment mark (alignment mark)
32 Second alignment mark 33 Third alignment mark 41, 41c, 42, 42c, 43, 43c Ion implantation mask 51, 51c, 52, 52c, 53, 53c Mask layers 61, 62, 63 Photomasks 61a, 62a, 63a Light part 61c, 62c, 63c Light shielding part 71 1st p-type area | region (p-type area | region)
72 Second p-type region 73 Third p-type region 100 Wide band gap semiconductor device (silicon carbide semiconductor device, MOSFET)
BT1, BT2, BT3 Bottom surface DR Dicing region O11, O12, O21, O22, O31, O32, O41, O42, O51, O52, O61, O42 Opening S Maximum diameter SW1, SW2, SW3 Side surface TR1 First recess TR2 Second Recess W1, W2 Width W3 Cutting width

Claims (13)

Providing a wide bandgap semiconductor wafer including a main surface and having an n-type conductivity;
Forming a dicing region on the main surface;
Forming an alignment mark region on the main surface;
A step of performing alignment between the wide band gap semiconductor wafer and a photomask using the alignment mark region;
After the alignment step, forming a p-type region so as to overlap the alignment mark region;
And a step of forming a plurality of chips by cutting the wide band gap semiconductor wafer along the dicing region after the step of forming the p-type region,
A method of manufacturing a wide band gap semiconductor device, wherein the p-type region does not exist in a portion of the dicing region left on the plurality of chips. In the step of forming the alignment mark region, the alignment mark region is formed in the dicing region,
The method of manufacturing a wide band gap semiconductor device according to claim 1, wherein the p-type region is removed in the step of forming the plurality of chips.   In a direction perpendicular to the extending direction of the dicing region, a value obtained by dividing the width of the p-type region by the width of the dicing region is not less than 1/12 and not more than 2/3. The method for manufacturing a wide band gap semiconductor device according to claim 2, wherein a width of the p-type region in the vertical direction satisfies at least one of 10 μm or more and 80 μm or less.   The value obtained by dividing the cutting width of the wide band gap semiconductor wafer in the step of forming the plurality of chips by the width of the dicing region in a direction perpendicular to the extending direction of the dicing region is not less than 1/4. 4. The method of manufacturing a wide band gap semiconductor device according to claim 2, wherein the width is 6 or less and the cutting width satisfies at least one of 30 μm or more and 100 μm or less. 5.   The method for manufacturing a wide band gap semiconductor device according to claim 1, wherein the dicing region and the alignment mark region are formed simultaneously.   The method of manufacturing a wide band gap semiconductor device according to claim 1, wherein the wide band gap semiconductor wafer includes at least one of silicon carbide, gallium nitride, and diamond.   The method for manufacturing a wide band gap semiconductor device according to claim 1, wherein a maximum diameter of the main surface is 100 mm or more.   The method of manufacturing a wide band gap semiconductor device according to claim 1, wherein in the step of forming the alignment mark region, the alignment mark region is formed in a region surrounded by the dicing region on the main surface. A wide band gap semiconductor wafer having a dicing region formed on the main surface,
The wide band gap semiconductor wafer includes an alignment mark region located in the dicing region,
A p-type region located in the alignment mark region,
In a direction perpendicular to the extending direction of the dicing region, a value obtained by dividing the width of the p-type region by the width of the dicing region is not less than 1/12 and not more than 2/3. A wide band gap semiconductor wafer satisfying at least one of a width of the p-type region in a vertical direction of 10 μm or more and 80 μm or less. A wide band gap semiconductor wafer having a dicing region formed on the main surface,
The wide band gap semiconductor wafer includes an alignment mark region located in a region surrounded by the dicing region,
A p-type region located in the alignment mark region,
The p-type region is a wide band gap semiconductor wafer that does not exist in the dicing region.   The wide band gap semiconductor wafer according to claim 9 or 10, wherein the wide band gap semiconductor wafer includes at least one of silicon carbide, gallium nitride, and diamond.   The wide band gap semiconductor wafer according to any one of claims 9 to 11, wherein a maximum diameter of the main surface is 100 mm or more.   A wide band gap semiconductor chip manufactured by cutting the wide band gap semiconductor wafer according to any one of claims 9 to 12 along the dicing region.