JP2008159691A - Nitride semiconductor element, nitride semiconductor crystal growth substrate, and method for manufacturing same - Google Patents

Nitride semiconductor element, nitride semiconductor crystal growth substrate, and method for manufacturing same Download PDF

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JP2008159691A
JP2008159691A JP2006344572A JP2006344572A JP2008159691A JP 2008159691 A JP2008159691 A JP 2008159691A JP 2006344572 A JP2006344572 A JP 2006344572A JP 2006344572 A JP2006344572 A JP 2006344572A JP 2008159691 A JP2008159691 A JP 2008159691A
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nitride semiconductor
group iii
layer
main surface
base layer
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Hiroaki Ota
裕朗 太田
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Rohm Co Ltd
ローム株式会社
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Abstract

A group III nitride semiconductor crystal growth substrate suitable as a power device material, a method for manufacturing the same, and a group III nitride semiconductor element formed using the group III nitride semiconductor crystal growth substrate are provided. .
In this field effect transistor, an N-type GaN layer 6 and a P-type layer are stacked in order from the main surface 2A side of the GaN film 2 so that the stack interface obliquely intersects the main surface 2A of the GaN film 2. A nitride semiconductor multilayer structure portion 5 including a GaN layer 7 and an N-type GaN layer 8 is provided. Further, the end faces of the N-type GaN layer 6, the P-type GaN layer 7, and the N-type GaN layer 8 are exposed surfaces 61, exposed surfaces 71, and exposed exposed along directions parallel to the main surface 2A of the GaN film 2, respectively. A surface 81 is formed.
[Selection] Figure 1

Description

  The present invention relates to a nitride semiconductor crystal growth substrate, a nitride semiconductor element, and a method for manufacturing a nitride semiconductor crystal growth substrate using a group III nitride semiconductor.

Conventionally, power devices using silicon semiconductors are used in power amplifier circuits, power supply circuits, motor drive circuits, and the like.
However, due to the theoretical limits of silicon semiconductors, the increase in breakdown voltage, reduction in resistance, and increase in speed of silicon devices are reaching their limits, and it is becoming difficult to meet market demands.
Therefore, development of GaN devices having characteristics such as high breakdown voltage, high temperature operation, large current density, high-speed switching, and small on-resistance has been studied (for example, see Non-Patent Document 1).
Satoshi Okubo, "GaN is behind the evolution of equipment, not just shining", June 5, 2006, Nikkei Electronics, p. 51-60

  In the GaN device proposed so far, for example, an N-type AlGaN layer is further grown on the surface of the GaN layer grown along the main surface of the SiC substrate. A source region (P-type region) and a drain region (P-type region) are formed. The GaN device has a lateral structure by providing a source electrode and a drain electrode on the source region and the drain region, respectively, and providing a gate electrode on the surface of the N-type AlGaN layer via a gate insulating film. ing.

However, a GaN device having such a lateral structure has a so-called normally-on operation in which a current flows between a source and a drain through a two-dimensional electron gas that appears near the surface of the GaN layer.
As a result, there is a problem that it is not always easy to realize a normally-off operation that can be said to be essential in a power device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a group III nitride semiconductor crystal growth substrate suitable as a power device material and a method for manufacturing the same.
Another object of the present invention is to provide a group III nitride semiconductor device formed using the group III nitride semiconductor crystal growth substrate.

  In order to achieve the above object, the invention according to claim 1 is the first conductivity type, wherein the base layer and the stack interface are stacked in order from the main surface side of the base layer so as to obliquely intersect the main surface of the base layer. A first group III nitride semiconductor layer, a second conductivity type second group III nitride semiconductor layer different from the first conductivity type, and the first conductivity type third group III nitride semiconductor layer. The nitride semiconductor crystal growth substrate includes: a nitride semiconductor multilayer structure portion in which each end face of the second and third group III nitride semiconductor layers has an exposed surface parallel to the main surface of the base layer.

According to this configuration, the nitride semiconductor multilayer structure portion of the nitride semiconductor crystal growth substrate is exposed along a direction in which each end face of the first, second, and third group III nitride semiconductor layers is parallel to the main surface of the base layer. And having an exposed surface.
Therefore, for example, a gate insulating film is provided on the nitride semiconductor crystal growth substrate so as to straddle the exposed surfaces of the first, second, and third group III nitride semiconductor layers, and the second group III group is sandwiched between the gate insulating films. A gate electrode is provided so as to face the nitride semiconductor layer, a source electrode is provided so as to be electrically connected to the first group III nitride semiconductor layer, and further, electrically connected to the group III nitride semiconductor layer. By providing the drain electrode so as to be connected, a lateral MIS (Metal Insulator Semiconductor) field effect transistor can be obtained.

In addition, since the multilayer interface of the nitride semiconductor multilayer structure section has a structure that obliquely intersects the main surface of the base layer, the field effect transistor obtained using the nitride semiconductor crystal growth substrate has a normally-off operation. That is, the operation of turning off the source and the drain when no bias is applied to the gate electrode can be easily realized.
In addition, the field effect transistor is composed of a group III nitride semiconductor layer, which has features such as high breakdown voltage, high temperature operation, large current density, high speed switching, and small on-resistance compared to devices using silicon semiconductors. You can enjoy it. In particular, since a high voltage and low loss operation is possible, a good power device can be realized.

Note that a group III nitride semiconductor is a semiconductor in which a group III element and nitrogen are combined, and aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN) are representative examples. In general, it can be expressed as Al x In y Ga 1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).
For example, an operation when an N-channel type MIS field effect transistor is configured by using a first group III nitride semiconductor layer and a third group III nitride semiconductor layer as an N type and a second group III nitride semiconductor layer as a P type. explain. In this case, a bias with a positive drain side is applied between the source and the drain. At this time, since a reverse voltage is applied to the PN junction at the interface between the second and third group III nitride semiconductor layers, the source and drain are cut off. In this state, when a bias voltage that is positive with respect to the first group III nitride semiconductor layer is applied to the gate electrode, in the second group III nitride semiconductor layer, in a region near the gate insulating film facing the gate electrode. Electrons are induced in the region (channel region), and an inversion channel is formed. Through this inversion channel, the first and third group III nitride semiconductor layers conduct, and therefore the source-drain conduct. In this way, the source-drain conducts when an appropriate bias is applied to the gate electrode, while the source-drain is cut off when no bias is applied to the gate electrode. That is, a normally-off operation is realized.

Note that when the first and third group III nitride semiconductor layers are P-type and the second group III nitride semiconductor layer is N-type to form a P-channel field effect transistor, the polarity of the bias voltage is reversed. The operation is similar to that described above.
According to a second aspect of the present invention, the nitride semiconductor crystal growth substrate includes an insulating film formed on the main surface of the base layer and having an opening that exposes a part of the main surface of the base layer. The semiconductor stacked structure may be formed in a region extending from the opening to the insulating film.

In addition, as described in claim 3, the nitride semiconductor crystal growth substrate has a recess formed by digging down the main surface of the base layer, and the nitride semiconductor multilayer structure includes the base layer including the inside of the recess. The structure currently formed on the main surface of this may be sufficient.
In addition, as described in claim 4, the base layer of the nitride semiconductor crystal growth substrate may include a semiconductor base layer made of a group III nitride semiconductor, or as described in claim 5. A substrate made of a material different from that of the group III nitride semiconductor may be included. Furthermore, as described in claim 6, the base layer of the nitride semiconductor crystal growth substrate includes a substrate made of a material different from that of the group III nitride semiconductor, and a buffer layer stacked on the substrate. May be. By laminating the buffer layer on the substrate, the nitride semiconductor multilayer structure can be favorably regrown on the buffer layer.

  According to a seventh aspect of the present invention, there is provided the nitride semiconductor crystal growth substrate according to any one of the first to sixth aspects, and the exposed surfaces of the first, second, and third group III nitride semiconductor layers. A gate insulating film formed so as to straddle; a gate electrode formed so as to face the second group III nitride semiconductor layer with the gate insulating film interposed therebetween; and the first and third group III nitride semiconductor layers A nitride semiconductor device including a source electrode electrically connected to one side and a drain electrode electrically connected to the other of the first and third group III nitride semiconductor layers. With this configuration, a lateral MIS (Metal Insulator Semiconductor) field effect transistor having the above-described effects can be realized.

  The invention according to claim 8 is the nitride semiconductor crystal growth substrate according to any one of claims 1 to 6, wherein the base layer includes a conductive substrate made of a conductive material; A gate insulating film formed to straddle the exposed surfaces of the second and third group III nitride semiconductor layers, and a gate electrode formed to face the second group III nitride semiconductor layer with the gate insulating film interposed therebetween A source electrode electrically connected to one of the conductive substrate and the third nitride semiconductor layer, and a drain electrode electrically connected to the other of the conductive substrate and the third nitride semiconductor layer And a nitride semiconductor device. Also with this configuration, a lateral MIS (Metal Insulator Semiconductor) field effect transistor having the above-described effects can be realized.

  According to a ninth aspect of the present invention, there is provided a semiconductor base layer growth step for growing a semiconductor base layer made of a group III nitride semiconductor on a substrate, and a first step so that the stacked interface obliquely intersects the main surface of the semiconductor base layer. A first group III nitride semiconductor layer of conductivity type, a second group III nitride semiconductor layer of a second conductivity type different from the first conductivity type, and a third group III nitride semiconductor layer of the first conductivity type; By laminating the first, second and third group III nitride semiconductor layers in a direction parallel to the main surface of the semiconductor base layer, by laminating and forming the layers in order from the main surface side of the base layer, And a polishing step for exposing end faces of the first, second and third group III nitride semiconductor layers.

  By this method, the nitride semiconductor crystal growth substrate having the structure described in claim 1 can be manufactured. In addition, since the nitride semiconductor multilayer structure is formed by crystal growth of the semiconductor base layer, for example, in the case of manufacturing a nitride semiconductor device as described in claim 7 and claim 8, The layer thickness of the group nitride semiconductor layer, that is, the length of the channel region can be controlled with high accuracy. Furthermore, since a step of etching each semiconductor layer is not required, a nitride semiconductor element can be manufactured without physically damaging each semiconductor layer.

  According to a tenth aspect of the present invention, after the semiconductor base layer growth step, an insulating film mask having a predetermined pattern having an opening exposing a part of the main surface of the semiconductor base layer is formed on the main surface of the semiconductor base layer. A step of forming a mask, and the step of forming the stack includes growing a group III nitride semiconductor from the opening using the insulating film mask as a mask, to a region extending from the opening to the insulating film mask. 10. The method according to claim 9, further comprising: laminating the first group III nitride semiconductor layer, the second group III nitride semiconductor layer, and the third group III nitride semiconductor layer in order from the main surface side of the semiconductor base layer. This is a method for manufacturing a nitride semiconductor crystal growth substrate. By this method, a nitride semiconductor crystal growth substrate having the structure described in claim 2 can be manufactured.

  The invention according to claim 11 further includes a recess forming step of forming a recess in the main surface of the semiconductor base layer by digging down the main surface of the semiconductor base layer after the semiconductor base layer growth step, In the step, a group III nitride semiconductor is grown from the main surface of the semiconductor base layer including the main surface in the recess, whereby the first group III nitride semiconductor layer, the second III are formed on the main surface of the semiconductor base layer. 6. The method for producing a nitride semiconductor crystal growth substrate according to claim 5, comprising a step of stacking a group nitride semiconductor layer and the third group III nitride semiconductor layer in order from the main surface side of the semiconductor base layer. By this method, the nitride semiconductor crystal growth substrate having the structure described in claim 3 can be manufactured.

Moreover, invention of Claim 12 further includes the process of heat-processing the said nitride semiconductor crystal growth substrate at 500 to 1100 degreeC, The nitride semiconductor crystal growth as described in any one of Claims 9-11 A method for manufacturing a substrate.
According to this configuration, the nitride semiconductor crystal growth substrate after the polishing step for exposing the end faces of the first, second, and third group III nitride semiconductor layers is performed at 500 ° C. to 1100 ° C. . For example, if the polishing step is performed by a chemical mechanical polishing method and then the above-described heat treatment is performed, damage remaining on the end face after polishing is reduced as compared with the case where the polishing step is performed by dry etching (anisotropic etching). It is possible to make the end face in a good state.

  Furthermore, as described in claim 13, the polishing step may be performed by a chemical mechanical polishing method.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view for explaining the structure of a field effect transistor (nitride semiconductor element) according to a first embodiment of the present invention.
This field effect transistor is a lateral type MIS type field effect transistor, which is formed on a substrate 1, a GaN film 2 (semiconductor base layer) grown on the substrate 1, and a main surface 2A of the GaN film 2. An insulating film mask 4 (insulating film) that is formed and has an opening 3 exposing a part of the main surface 2A, and a region extending from the opening 3 of the insulating film mask 4 to the insulating film mask 4 is formed. The nitride semiconductor multilayer structure portion 5 is provided, and these constitute a GaN crystal growth substrate 16 (nitride semiconductor crystal growth substrate).

  The nitride semiconductor multilayer structure portion 5 includes an N-type GaN layer 6 (first group III) stacked in order from the main surface 2A side of the GaN film 2 so that the stack interface obliquely intersects the main surface 2A of the GaN film 2. A nitride semiconductor layer), a P-type GaN layer 7 (Group III nitride semiconductor layer), and an N-type GaN layer 8 (Group III nitride semiconductor layer). Further, the end faces of the N-type GaN layer 6, the P-type GaN layer 7, and the N-type GaN layer 8 are exposed surfaces 61, exposed surfaces 71, and exposed exposed along directions parallel to the main surface 2A of the GaN film 2, respectively. A surface 81 is formed.

As the substrate 1, for example, a substrate made of a material different from the group III nitride semiconductor, such as a conductive substrate such as a GaN substrate, a ZnO substrate, a Si substrate, a GaAs substrate and a SiC substrate, or an insulating substrate such as a sapphire substrate, is applied. can do.
GaN film 2 is an example of a In x Al y Ga 1-xy N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1) III -nitride semiconductor compound represented by the substrate 1 has a function as a buffer layer stacked on one. Further, the GaN film 2 may or may not contain a dopant (N-type or P-type). By laminating the GaN film 2 on the substrate 1, the nitride semiconductor multilayer structure 5 can be favorably regrown on the GaN film 2.

  When a GaN substrate is used as the substrate 1 and the GaN film 2 is formed on the surface thereof, the lattice constants of the substrate 1 and the GaN film 2 are matched, so that crystal defects in the GaN film 2 are reduced. Therefore, if the N-type GaN layer 6, the P-type GaN layer 7 and the N-type GaN layer 8 are further epitaxially grown in order on the main surface 2A of the GaN film 2, the nitride semiconductor multilayer structure portion 5 with few dislocation defects can be obtained. Can do.

The insulating film mask 4 can be configured using, for example, an oxide or a nitride. More specifically, it may be configured using silicon oxide (SiO 2 ), gallium oxide (Ga 2 O 3 ), magnesium oxide (MgO), scandium oxide (Sc 2 O 3 ), silicon nitride (SiN), or the like. it can.
On the exposed surface 61 of the N-type GaN layer 6, the exposed surface 71 of the P-type GaN layer 7, and the exposed surface 81 of the N-type GaN layer 8, the gate insulating film 10 is formed so as to straddle these exposed surfaces. A gate electrode 11 is formed to face the P-type GaN layer 7 with the gate insulating film 10 interposed therebetween.

  As the gate insulating film 10, an insulating material similar to that of the above-described insulating film mask 4 can be applied. On the other hand, examples of the gate electrode 11 include platinum (Pt), aluminum (Al), nickel-gold alloy (Ni-Au alloy), nickel-titanium-gold alloy (Ni-Ti-Au alloy), and palladium-gold alloy. A conductive material such as (Pd-Au alloy), palladium-titanium-gold alloy (Pd-Ti-Au alloy), palladium-platinum-gold alloy (Pd-Pt-Au alloy), or polysilicon can be applied. .

A region near the gate insulating film 10 in the P-type GaN layer 7 is a channel region 12 facing the gate electrode 11. In the channel region 12, an inversion channel is formed that conducts between the N-type GaN layer 6 and the N-type GaN layer 8 by applying an appropriate bias voltage to the gate electrode 11.
The nitride semiconductor multilayer structure 5 is formed on the GaN film 2 by so-called lateral epitaxial growth (ELO), and thereafter, for example, a chemical mechanical polishing method (hereinafter referred to as a CMP method). It is polished by a polishing method such as More specifically, the N-type GaN layer 6 and the P-type GaN layer 7 are formed by so-called longitudinal selective epitaxial growth, and the N-type GaN layer 8 is formed by so-called lateral selective epitaxial growth and then polished.

  When the substrate 1 having a c-plane (0001) as the main surface is used, the GaN film 2 grown by epitaxial growth on the substrate 1 is also formed with the c-plane (0001) as the main surface. When crystal growth of a GaN-based compound semiconductor is performed from the GaN film 2 exposed from the opening 3 under the condition that the r-plane (10-12) is stable, for example, the main surface of the GaN film 2 is inclined. N-type GaN layer 6, P-type GaN layer 7, and N-type GaN layer 8 are stacked with the r-plane (10-12) as the main surface. It will be.

The GaN film 2 may be grown on the substrate 1 so that the main surface 2A is the r-plane (10-12). In this case, the N-type GaN layer 6, the P-type GaN layer 7, and the N-type GaN layer 8 are laminated with the corresponding crystal plane as the main surface.
The source electrode 13 is provided on the exposed surface 61 of the N-type GaN layer 6. As a result, the source electrode 13 is electrically connected to the N-type GaN layer 6. A drain electrode 14 is provided on the exposed surface 81 of the N-type GaN layer 8. As a result, the drain electrode 14 is electrically connected to the N-type GaN layer 8. The source electrode 13 may be provided on the exposed surface 81 of the N-type GaN layer 8, and in this case, the drain electrode 14 is provided on the exposed surface 61 of the N-type GaN layer 6. That is, the source electrode 13 is electrically connected to one of the N-type GaN layer 6 and the N-type GaN layer 8, and the drain electrode 14 is connected to the other of the N-type GaN layer 6 and the N-type GaN layer 8.

  The source electrode 13 is preferably made of a metal containing at least Al. For example, the source electrode 13 can be made of a Ti—Al alloy. Similarly to the source electrode 13, the drain electrode 14 is preferably made of a metal containing Al. For example, the drain electrode 14 can be made of a Ti—Al alloy. By forming the source electrode 13 and the drain electrode 14 with a metal containing Al, good contact with a wiring layer (not shown) can be obtained. In addition, the source electrode 13 and the drain electrode 14 may be made of Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide). .

Next, the operation of this field effect transistor will be described.
A bias voltage that is positive on the drain electrode 14 side is applied between the source electrode 13 and the drain electrode 14. As a result, a reverse voltage is applied to the PN junction at the interface between the N-type GaN layer 8 and the P-type GaN layer 7, and as a result, between the N-type GaN layer 6 and the N-type GaN layer 8, that is, the source -The drain is cut off. In this state, when a predetermined voltage that is positive on the gate electrode 11 side is applied between the source electrode 13 and the gate electrode 11, a bias for the P-type GaN layer 7 is applied to the gate electrode 11. As a result, electrons are induced in the channel region 12 of the P-type GaN layer 7 to form an inversion channel. The N-type GaN layer 6 and the N-type GaN layer 8 are electrically connected via the inversion channel. Thus, conduction between the source and the drain is established. That is, when a predetermined bias is applied to the gate electrode 11, the source and the drain become conductive, and when no bias is applied to the gate electrode 11, the source and the drain are cut off. In this way, a normally-off operation is possible.

  Further, since the nitride semiconductor multilayer structure portion 5 is formed by epitaxial growth, even if a dislocation defect 15 indicated by a broken line in FIG. 1 is generated therein, the direction of the dislocation defect 15 and the source − Since the direction of the current flowing between the drains is different (substantially perpendicular), the occurrence of leakage current (leakage current) in the field effect transistor can be suppressed.

2A to 2H are schematic cross-sectional views showing a method of manufacturing the field effect transistor of FIG. 1 in the order of steps.
When the field effect transistor of FIG. 1 is manufactured, as shown in FIG. 2A, a GaN film 2 is first formed on a substrate 1 by a lateral selective epitaxial growth method (semiconductor base layer growth step). When the GaN film 2 is epitaxially grown, Si may be used, for example, when an N-type dopant is included, and Mg, C, etc. may be used, for example, when a P-type dopant is included.

  Next, as shown in FIG. 2B, an insulating film material 17 that is a material of the insulating film mask 4 is stacked on the GaN film 2 by, for example, plasma chemical vapor deposition (plasma CVD method). Then, a photoresist 24 having an opening 18 corresponding to the opening 3 is formed on the insulating film material 17. More specifically, first, a photoresist 24 is applied to the entire surface of the insulating film material 17 and patterned by photolithography to form a photoresist 24 having an opening 18 corresponding to the opening 3.

Next, as shown in FIG. 2C, the insulating film material 17 exposed from the opening 18 is etched by, for example, dry etching, and the photoresist 24 remaining on the remaining insulating film material 17 is dissolved and removed ( Mask formation step). Thereby, the insulating film mask 4 having the opening 3 is formed.
Next, as shown in FIG. 2D, the N-type GaN layer 6 is selectively epitaxially grown in the vertical direction from the main surface 2A of the GaN film 2 exposed from the opening 3, and then the N-type GaN layer 6, the P-type GaN layer 7 is selectively epitaxially grown in the vertical direction.

  More specifically, a crystal of the GaN-based compound semiconductor is grown using the exposed portion of the GaN film 2 as a nucleus under conditions (growth temperature, pressure in the chamber, etc.) that allow the GaN-based compound semiconductor to grow in the vertical direction. As a result, a ridge-shaped N-type GaN layer 6 extending along the pattern of the opening 3 is grown from the GaN film 2 exposed from the opening 3. The N-type GaN layer 6 has a pair of inclined surfaces 6A and 6B inclined with respect to the main surface 2A of the GaN film 2, and these form a ridge line portion 6C extending along the pattern of the opening 3. . At this time, the inclined surfaces 6A and 6B are r-planes of the GaN-based compound semiconductor crystal. That is, by performing crystal growth of the GaN-based compound semiconductor under the condition that the r-plane is stable, the N-type GaN layer 6 can be selectively grown in the vertical direction. For example, Si may be used as an N-type dopant when the N-type GaN layer 6 is epitaxially grown.

Also for the P-type GaN layer 7, longitudinal selective epitaxial growth of the P-type GaN layer 7 becomes possible by performing crystal growth of the GaN-based compound semiconductor by the same method as that for the N-type GaN layer 6. For example, Mg or C may be used as the P-type dopant when the P-type GaN layer 7 is epitaxially grown.
Next, as shown in FIG. 2E, the GaN-based semiconductor layer growth portion 19 is selectively epitaxially grown from the P-type GaN layer 7 in the lateral direction along the main surface 2 </ b> A of the GaN film 2. In this embodiment, the process shown in FIGS. 2D and 2E corresponds to the lamination forming process of the present invention.

  More specifically, crystal growth from the P-type GaN layer 7 is performed under conditions (growth temperature, pressure in the chamber, etc.) where the GaN-based compound semiconductor is likely to grow in the lateral direction. As a result, the GaN-based semiconductor layer growth portion 19 grows laterally from the ridge-shaped P-type GaN layer 7 and a plurality of GaN-based semiconductor layer growth portions 19 having a flat top surface are formed. As shown in FIG. 5, the adjacent ones of the plurality of GaN-based semiconductor layer growth portions 19 are joined together to obtain an integrated N-type GaN layer 8. For example, Si may be used as the N-type dopant when epitaxially growing the N-type GaN layer 8.

Since the N-type GaN layer 6, the P-type GaN layer 7 and the N-type GaN layer 8 obtained in this way inherit the dislocations from the GaN film 2, dislocation defects 15 are present in the inside thereof as indicated by broken lines in FIG. 2F. Occurs.
Next, as shown in FIG. 2G, the N-type GaN layer 6, the P-type GaN layer 7, and the N-type GaN layer 8 are polished by a CMP method along a direction parallel to the main surface 2A of the GaN film 2. (Polishing step), the N-type GaN layer 6, the P-type GaN layer 7, and the N-type GaN layer 8 are planarized so that the end faces are on the same plane. Each end face is flattened so that the end faces of the N-type GaN layer 6, the P-type GaN layer 7 and the N-type GaN layer 8 are exposed along a direction parallel to the main surface 2A of the GaN film 2, respectively. The surface 61, the exposed surface 71, and the exposed surface 81 are formed, and the nitride semiconductor multilayer structure portion 5 is obtained. Thereby, the GaN crystal growth substrate 16 is obtained.

Thereafter, the GaN crystal growth substrate 16 is heat-treated at a temperature of 500 ° C. to 1100 ° C., for example, in an N 2 atmosphere. The N-type GaN layer 6, the P-type GaN layer 7 and the N-type GaN layer 8 are polished by the CMP method and then subjected to the heat treatment described above, for example, compared with the case of polishing by dry etching (anisotropic etching). Thus, damage remaining on each exposed surface (61, 71, 81) after polishing can be reduced, and an exposed surface in a good state can be obtained.

  Then, as shown in FIG. 2H, the gate insulating film 10 is formed so as to straddle the exposed surface 61 of the N-type GaN layer 6, the exposed surface 71 of the P-type GaN layer 7, and the exposed surface 81 of the N-type GaN layer 8. A gate electrode 11 is formed to face the P-type GaN layer 7 with the gate insulating film 10 interposed therebetween. Further, the source electrode 13 is formed on the exposed surface 61 of the N-type GaN layer 6 and the drain electrode 14 is formed on the exposed surface 81 of the N-type GaN layer 8, thereby obtaining the field effect transistor having the structure shown in FIG. be able to.

As an epitaxial growth method for forming the nitride semiconductor multilayer structure portion 5, any of liquid phase epitaxial growth, vapor phase epitaxial growth, or molecular beam epitaxial growth may be applied.
Each of the plurality of nitride semiconductor multilayer structures 5 formed in a stripe shape on the substrate 1 forms a unit cell. The gate electrode 11, the source electrode 13, and the drain electrode 14 of the plurality of nitride semiconductor multilayer structures 5 are commonly connected at positions not shown. The drain electrode 14 can be shared between adjacent nitride semiconductor multilayer structures 5.

  As described above, according to this embodiment, each of the stacked interfaces of the nitride semiconductor stacked structure portion 5 of the GaN crystal growth substrate 16 has a structure that obliquely intersects the main surface 2A of the GaN film 2. For example, when the main surface 2A is the c-plane (0001), the stacked interface of the nitride semiconductor multilayer structure portion 5 is the r-plane (10-12). Therefore, the field effect transistor according to this embodiment formed using the GaN crystal growth substrate 16 having such a structure has a normally-off operation, that is, a source-drain when no bias is applied to the gate electrode 11. The operation of turning off the gap can be easily realized.

  In addition, because field effect transistors are composed of group III nitride semiconductors such as GaN, compared to devices using silicon semiconductors, high breakdown voltage, high temperature operation, large current density, high speed switching, and small on-resistance You can enjoy the features. In particular, since a high voltage and low loss operation is possible, a good power device can be realized. Further, since the nitride semiconductor multilayer structure portion 5 is formed by crystal growth from the GaN film 2, the layer thickness of the P-type GaN layer 7, that is, the length of the channel region 12 can be controlled with high accuracy. . Further, since a step of etching each GaN layer (6, 7, 8) is not required, a field effect transistor can be manufactured without physically damaging each GaN layer (6, 7, 8).

FIG. 3 is a schematic cross-sectional view for explaining the structure of a field effect transistor according to the second embodiment of the present invention. In FIG. 3, the same reference numerals as those in FIG. 1 are attached to the portions corresponding to those in FIG.
In this embodiment, the insulating film mask 4 is not formed on the main surface 2A of the GaN film 2, and the GaN film 2 is etched from the main surface 2A to the middle of the film thickness of the GaN film 2, thereby forming the recess 20 Is formed. A nitride semiconductor multilayer structure 5 is formed in a region extending from the recess 20 to the GaN film 2.

  The nitride semiconductor multilayer structure unit 5 includes an N-type GaN layer 6, a P-type GaN layer 7, and an N-type GaN that are sequentially laminated from the main surface 2A side of the GaN film 2 so that the lamination interface has a W-shaped cross section. Layer 8 is provided. More specifically, a P-type GaN layer 7 disposed in the center is formed in a W-shaped cross section, an N-type GaN layer 6 is formed in an outer region of the P-type GaN layer 7, and an N-type is formed in an inner region. A GaN layer 8 is formed, and in plan view, the N-type GaN layer 6, the P-type GaN layer 7, the N-type GaN layer 8, the P-type GaN layer 7, and the N-type GaN layer 6 are in the form of stripes in order. Is formed. Since the nitride semiconductor multilayer structure portion 5 is formed in this way, each multilayer interface of the nitride semiconductor multilayer structure portion 5 is inclined with respect to the main surface 2A of the GaN film 2.

  For example, as described above, after the GaN film 2 is formed with the c-plane (0001) as the main surface, the GaN-based compound semiconductor is formed from the GaN film 2 under the condition that, for example, the r-plane (10-12) is stable. When the crystal growth is performed, the stacked interface (7A, 7B, 7C and 7D) between the N-type GaN layer 6 and the P-type GaN layer 7 becomes the r plane (10-12), and the P-type GaN layer 7 and the N-type GaN The laminated interfaces (8A, 8B, 8C and 8D) with the layer 8 are also r-planes (10-12).

  The respective end faces of the N-type GaN layer 6, the P-type GaN layer 7, and the N-type GaN layer 8 are exposed surfaces 61, exposed surfaces 71, and exposed exposed along directions parallel to the main surface 2A of the GaN film 2, respectively. A surface 81 is formed. Other configurations are the same as those in the first embodiment. Also with this configuration, the same operation as in the first embodiment described above is possible, and the same effect as in the first embodiment can be obtained.

4A to 4H are schematic sectional views showing a method of manufacturing the field effect transistor of FIG. 3 in the order of steps.
When the field effect transistor of FIG. 3 is manufactured, as shown in FIG. 4A, first, the GaN film 2 is formed on the substrate 1 by a lateral selective epitaxial growth method (semiconductor base layer growth step).

Next, as shown in FIG. 4B, a photoresist 22 having an opening 21 corresponding to the recess 20 is formed on the GaN film 2. More specifically, first, a photoresist 22 is applied to the entire surface of the GaN film 2 and patterned by photolithography to form a photoresist 22 having an opening 21 corresponding to the recess 20.
Next, as shown in FIG. 4C, the GaN film 2 exposed from the opening 21 is etched, for example, by dry etching, and the photoresist 22 remaining on the remaining GaN film 2 is dissolved and removed (recess formation). Process). Thereby, the GaN film 2 having the recess 20 is formed.

  Next, as shown in FIG. 4D, the N-type GaN layer 6 is selectively epitaxially grown in the vertical direction from the main surface 2A of the GaN film 2 including the recess 20. At this time, a relatively low ridge-shaped N-type GaN layer 6 extending along the pattern of the recess 20 grows from the main surface 2A where the recess 20 is formed. The low ridge-shaped N-type GaN layer 6 has a pair of inclined surfaces 7B and 7C inclined with respect to the main surface 2A of the GaN film 2. On the other hand, a relatively high ridge-shaped N-type GaN layer 6 grows from the main surface 2A where the recess 20 is not formed. The high ridge-shaped N-type GaN layer 6 has a pair of inclined surfaces 7A and 7D inclined with respect to the main surface 2A of the GaN film 2. Then, after the N-type GaN layer 6 is grown, the P-type GaN layer 7 is selectively epitaxially grown in the vertical direction from the surface of the N-type GaN layer 6.

  Similarly to the N-type GaN layer 6, the P-type GaN layer 7 also grows a relatively low ridge shape layer and a relatively high ridge shape layer. The relatively low ridge-shaped P-type GaN layer 7 has a pair of inclined surfaces 8B and 8C that are inclined with respect to the main surface 2A of the GaN film 2, and has a relatively high ridge-shaped P-type. The GaN layer 7 has a pair of inclined surfaces 8A and 8D that are inclined with respect to the main surface 2A of the GaN film 2.

  Next, as shown in FIG. 4E, the GaN-based semiconductor layer growth portion 23 is selectively epitaxially grown in the lateral direction along the main surface 2A of the GaN film 2 from the P-type GaN layer 7. In this embodiment, the steps shown in FIG. 4D and FIG. 4E correspond to the layer forming step of the present invention. Then, after a plurality of GaN-based semiconductor layer growth portions 23 having a flat top surface are formed, adjacent ones of the plurality of GaN-based semiconductor layer growth portions 23 are joined together as shown in FIG. 4F. Thus, an integrated N-type GaN layer 8 is obtained. The N-type GaN layer 6, the P-type GaN layer 7 and the N-type GaN layer 8 obtained in this way inherit dislocations from the GaN film 2. Therefore, as shown by the broken line in FIG. Occurs.

Next, as shown in FIG. 4G, the N-type GaN layer 6, the P-type GaN layer 7, and the N-type GaN layer 8 are formed from the surface side of the N-type GaN layer 8 to a depth that does not reach the relatively low ridge portion of the P-type GaN layer 7. The type GaN layer 8 is polished by the CMP method along the direction parallel to the main surface 2A of the GaN film 2 (polishing step), and the N-type GaN layer 6, the P-type GaN layer 7 and the N-type GaN layer 8 are polished. It planarizes so that each end surface may become on the same plane. Each end face is flattened so that the end faces of the N-type GaN layer 6, the P-type GaN layer 7 and the N-type GaN layer 8 are exposed along a direction parallel to the main surface 2A of the GaN film 2, respectively. The surface 61, the exposed surface 71, and the exposed surface 81 are formed, and the nitride semiconductor multilayer structure portion 5 is obtained. Thereby, the GaN crystal growth substrate 16 is obtained. Thereafter, the GaN crystal growth substrate 16 is heat-treated at a temperature of 500 ° C. to 1100 ° C., for example, in an N 2 atmosphere.

  Then, as shown in FIG. 4H, the gate insulating film 10 is formed so as to straddle the exposed surface 61 of the N-type GaN layer 6, the exposed surface 71 of the P-type GaN layer 7, and the exposed surface 81 of the N-type GaN layer 8. A gate electrode 11 is formed to face the P-type GaN layer 7 with the gate insulating film 10 interposed therebetween. Further, the source electrode 13 is formed on the exposed surface 61 of the N-type GaN layer 6 and the drain electrode 14 is formed on the exposed surface 81 of the N-type GaN layer 8, thereby obtaining the field effect transistor having the structure shown in FIG. be able to.

Each of the plurality of nitride semiconductor multilayer structures 5 formed in a stripe shape on the substrate 1 forms a unit cell. The gate electrode 11, the source electrode 13, and the drain electrode 14 of the plurality of nitride semiconductor multilayer structures 5 are commonly connected at positions not shown. The source electrode 13 can be shared between adjacent nitride semiconductor multilayer structures 5.
Also in this embodiment, the source electrode 13 may be provided on the exposed surface 81 of the N-type GaN layer 8. In that case, the drain electrode 14 is provided on the exposed surface 61 of the N-type GaN layer 6.

FIG. 5 is a schematic cross-sectional view for explaining the structure of a field effect transistor according to the third embodiment of the present invention. In FIG. 5, parts corresponding to the parts shown in FIG. 1 are denoted by the same reference numerals as in FIG.
In this embodiment, the GaN film 2 is not provided, and an insulating film mask 4 having an opening 3 exposing a part of the main surface 1A is formed on the main surface 1A of the substrate 1. ing. The nitride semiconductor multilayer structure portion 5 is formed in a region extending from the opening 3 of the insulating film mask 4 to above the insulating film mask 4.

  According to this embodiment, each laminated interface of the nitride semiconductor multilayer structure portion 5 of the GaN crystal growth substrate 16 has a structure that obliquely intersects the main surface 1A of the substrate 1. For example, when the main surface 1A is the c-plane (0001), the stacked interface of the nitride semiconductor multilayer structure portion 5 is the r-plane (10-12). Other configurations are the same as those in the first embodiment. Also with this configuration, the same operation as in the first embodiment described above is possible, and the same effect as in the first embodiment can be obtained.

  The field effect transistor can be manufactured by a method similar to the method described with reference to FIGS. In this case, for example, the step shown in FIG. 2A is omitted, and in the step shown in FIG. 2B, an insulating film material 17 is laminated on the substrate 1, and a photoresist 24 is formed on the insulating film material 17. . In the step shown in FIG. 2C, after the photoresist film 24 is removed to form the insulating film mask 4, the nitride semiconductor multilayer structure portion 5 may be grown from the opening 3 of the insulating film mask 4. . Other processes are the same as those in the first embodiment.

FIG. 6 is a schematic cross-sectional view for explaining the structure of a field effect transistor according to the fourth embodiment of the present invention. 6, parts corresponding to the respective parts shown in FIG. 1 are denoted by the same reference numerals as those in FIG.
In this embodiment, the substrate 1 is a conductive substrate 25 having conductivity. As described above, for example, a substrate such as a GaN substrate, a ZnO substrate, a Si substrate, a GaAs substrate, or a SiC substrate can be used as the conductive substrate 25. Further, the source electrode 13 is not provided on the exposed surface 61 of the N-type GaN layer 6 so as to cover almost the entire region 25A of the conductive substrate 25 opposite to the side on which the GaN film 2 is formed. Further, the source electrode 13 is deposited. Other configurations are the same as those in the first embodiment. Also with this configuration, the same operation as in the first embodiment described above is possible, and the same effect as in the first embodiment can be obtained.

  The field effect transistor can be manufactured by a method similar to the method described with reference to FIGS. In this case, the conductive substrate 25 is used in place of the substrate 1, and further, for example, in the step shown in FIG. 2H, the source electrode 13 is not provided on the exposed surface 61 of the N-type GaN layer 6, and the conductive substrate 25 It may be deposited on the surface 25A. Other processes are the same as those in the first embodiment. When a plurality of field effect transistors are formed, the source electrode 13 becomes a common electrode for all of the plurality of nitride semiconductor multilayer structures 5. In addition, the drain electrode 14 may be formed on the surface 25 A of the conductive substrate 25, and in this case, the source electrode 13 is provided on the exposed surface 81 of the N-type GaN layer 8. That is, the source electrode 13 is electrically connected to one of the conductive substrate 25 and the N-type GaN layer 8, and the drain electrode 14 is connected to the other of the conductive substrate 25 and the N-type GaN layer 8.

FIG. 7 is a schematic cross-sectional view for explaining the structure of a field effect transistor according to the fifth embodiment of the present invention. In FIG. 7, portions corresponding to the respective portions shown in FIG. 1 are denoted by the same reference numerals as those in FIG.
In this embodiment, the substrate 1 is not provided. Other configurations are the same as those in the first embodiment. Also with this configuration, the same operation as in the first embodiment described above is possible, and the same effect as in the first embodiment can be obtained.

  The field effect transistor can be manufactured by a method similar to the method described with reference to FIGS. In this case, for example, after the GaN crystal growth substrate 16 is heat-treated after the step shown in FIG. 2G, the substrate 1 may be removed by a method such as a laser lift-off method, a CMP (chemical mechanical polishing) process or an etching process. . Other processes are the same as those in the first embodiment. Also in this embodiment, as in the fourth embodiment, one of the source electrode 13 and the drain electrode 14 is a surface of the GaN film 2 opposite to the side on which the nitride semiconductor multilayer structure portion 5 is grown. It may be formed so as to cover almost the entire area of 2B.

As mentioned above, although five embodiment of this invention was described, this invention can also be implemented with another form.
For example, the N-type GaN layer 6 and the N-type GaN layer 8 may each be P-type, and the P-type GaN layer 7 may be N-type.
In addition, various design changes can be made within the scope of matters described in the claims.

1 is an illustrative sectional view for explaining the structure of a field effect transistor according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view illustrating a method of manufacturing the field effect transistor of FIG. 1 in the order of steps. FIG. 2D is a schematic cross-sectional view showing the method of manufacturing the field effect transistor of FIG. 1 in the order of steps, and showing the step subsequent to FIG. FIG. 2D is a schematic cross-sectional view showing a method of manufacturing the field effect transistor of FIG. 1 in the order of steps, and showing a step subsequent to FIG. 2B. FIG. 2D is a schematic cross-sectional view showing the method for manufacturing the field-effect transistor of FIG. 1 in the order of steps, and showing a step subsequent to FIG. 2C. FIG. 2D is a schematic cross-sectional view showing a method of manufacturing the field effect transistor of FIG. 1 in the order of steps, and showing a step subsequent to FIG. 2D. FIG. 2D is a schematic cross-sectional view showing a method of manufacturing the field effect transistor of FIG. 1 in the order of steps, and showing a step subsequent to FIG. 2E. FIG. 2D is a schematic cross-sectional view showing a method of manufacturing the field effect transistor of FIG. 1 in the order of steps, and showing a step subsequent to FIG. 2F. FIG. 2D is a schematic cross-sectional view showing a method of manufacturing the field effect transistor of FIG. 1 in the order of steps, and showing a step subsequent to FIG. 2G. It is an illustration sectional view for explaining the structure of the field effect transistor concerning a 2nd embodiment of this invention. FIG. 4 is a schematic cross-sectional view showing a method of manufacturing the field effect transistor of FIG. 3 in the order of steps. FIG. 4D is a schematic cross-sectional view showing the method of manufacturing the field effect transistor of FIG. FIG. 4D is a schematic cross-sectional view showing the method of manufacturing the field effect transistor of FIG. FIG. 4D is a schematic cross-sectional view showing the method for manufacturing the field-effect transistor of FIG. 3 in the order of steps, and is a diagram showing a step subsequent to FIG. FIG. 4D is a schematic cross-sectional view showing the method of manufacturing the field effect transistor of FIG. 3 in the order of steps, and is a diagram showing a step subsequent to FIG. FIG. 4D is a schematic cross-sectional view showing the method of manufacturing the field effect transistor of FIG. FIG. 4D is a schematic cross-sectional view showing the method for manufacturing the field effect transistor of FIG. 3 in the order of steps, and is a view showing a step subsequent to FIG. FIG. 4D is a schematic cross-sectional view showing the method of manufacturing the field effect transistor of FIG. It is an illustration sectional view for explaining the structure of the field effect transistor concerning a 3rd embodiment of this invention. It is an illustration sectional view for explaining the structure of the field effect transistor concerning a 4th embodiment of this invention. It is an illustrative sectional view for explaining the structure of a field effect transistor according to a fifth embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 1A Main surface 2 GaN film 2A Main surface 3 Opening 4 Insulating film mask 5 Nitride semiconductor laminated structure 6 N-type GaN layer 7 P-type GaN layer 8 N-type GaN layer 10 Gate insulating film 11 Gate electrode 13 Source electrode 14 Drain electrode 16 GaN crystal growth substrate 20 Recess 25 Conductive substrate 61 Exposed surface 71 Exposed surface 81 Exposed surface

Claims (13)

  1. The base layer,
    The first conductivity type first group III nitride semiconductor layer, which is sequentially laminated from the main surface side of the base layer so that the stack interface obliquely intersects the main surface of the base layer, is different from the first conductivity type. A second-conductivity-type Group III nitride semiconductor layer, and a first-conductivity-type Group III-nitride semiconductor layer, each end face of the first, second, and third-group III-nitride semiconductor layers being the base layer And a nitride semiconductor multilayer structure having an exposed surface parallel to the main surface of the nitride semiconductor crystal growth substrate.
  2. An insulating film having an opening formed on a main surface of the base layer and exposing a part of the main surface of the base layer;
    The nitride semiconductor crystal growth substrate according to claim 1, wherein the nitride semiconductor multilayer structure portion is formed in a region extending from the opening to the insulating film.
  3. Having a recess formed by digging down the main surface of the base layer;
    The nitride semiconductor crystal growth substrate according to claim 1, wherein the nitride semiconductor multilayer structure portion is formed on a main surface of the base layer including the inside of the recess.
  4.   The nitride semiconductor crystal growth substrate according to claim 1, wherein the base layer includes a semiconductor base layer made of a group III nitride semiconductor.
  5.   4. The nitride semiconductor crystal growth substrate according to claim 1, wherein the base layer includes a substrate made of a material different from that of the group III nitride semiconductor.
  6.   4. The nitride semiconductor crystal growth substrate according to claim 1, wherein the base layer includes a substrate made of a material different from a group III nitride semiconductor, and a buffer layer stacked on the substrate.
  7. The nitride semiconductor crystal growth substrate according to any one of claims 1 to 6,
    A gate insulating film formed to straddle the exposed surface of the first, second and third group III nitride semiconductor layers;
    A gate electrode formed to face the second group III nitride semiconductor layer with the gate insulating film interposed therebetween;
    A source electrode electrically connected to one of the first and third group III nitride semiconductor layers;
    And a drain electrode electrically connected to the other of the first and third group III nitride semiconductor layers.
  8. The nitride semiconductor crystal growth substrate according to any one of claims 1 to 6, wherein the base layer includes a conductive substrate made of a conductive material;
    A gate insulating film formed to straddle the exposed surface of the first, second and third group III nitride semiconductor layers;
    A gate electrode formed to face the second group III nitride semiconductor layer with the gate insulating film interposed therebetween;
    A source electrode electrically connected to one of the conductive substrate and the third nitride semiconductor layer;
    And a drain electrode electrically connected to the other of the conductive substrate and the third nitride semiconductor layer.
  9. A semiconductor base layer growth step of growing a semiconductor base layer made of a group III nitride semiconductor on the substrate;
    The first conductivity type first group III nitride semiconductor layer, the second conductivity type second group III nitride semiconductor layer different from the first conductivity type, such that the stacked interface obliquely intersects the main surface of the semiconductor base layer And a layer forming step of sequentially stacking the third conductivity type Group III nitride semiconductor layer from the main surface side of the semiconductor base layer,
    By polishing the first, second and third group III nitride semiconductor layers along a direction parallel to the main surface of the semiconductor base layer, end faces of the first, second and third group III nitride semiconductor layers A method for manufacturing a nitride semiconductor crystal growth substrate.
  10. After the semiconductor base layer growth step, the method further includes a mask formation step of forming an insulating film mask having a predetermined pattern having an opening exposing a part of the main surface of the semiconductor base layer on the main surface of the semiconductor base layer,
    In the stacking step, the first group III nitride semiconductor layer is formed in a region extending from the opening to the insulating film mask by growing a group III nitride semiconductor from the opening using the insulating film mask as a mask. The manufacturing method of the nitride semiconductor crystal growth substrate of Claim 9 including the process of laminating | stacking the said 2nd group III nitride semiconductor layer and the said 3rd group III nitride semiconductor layer in order from the main surface side of the said semiconductor base layer. Method.
  11. After the semiconductor base layer growth step, further including a recess forming step of forming a recess in the main surface of the semiconductor base layer by digging down the main surface of the semiconductor base layer,
    In the stack formation step, the first group III nitride semiconductor layer is formed on the main surface of the semiconductor base layer by growing a group III nitride semiconductor from the main surface of the semiconductor base layer including the main surface in the recess. The method for manufacturing a nitride semiconductor crystal growth substrate according to claim 9, comprising a step of sequentially stacking the second group III nitride semiconductor layer and the third group III nitride semiconductor layer from the main surface side of the semiconductor base layer. .
  12.   The method for producing a nitride semiconductor crystal growth substrate according to any one of claims 9 to 11, further comprising a step of heat-treating the nitride semiconductor crystal growth substrate at 500 ° C to 1100 ° C.
  13.   The method for manufacturing a nitride semiconductor crystal growth substrate according to claim 9, wherein the polishing step is performed by a chemical mechanical polishing method.
JP2006344572A 2006-12-21 2006-12-21 Nitride semiconductor element, nitride semiconductor crystal growth substrate, and method for manufacturing same Pending JP2008159691A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017501562A (en) * 2013-12-23 2017-01-12 インテル・コーポレーション Wide bandgap transistor on non-native semiconductor substrate and method of manufacturing the same
US10032911B2 (en) 2013-12-23 2018-07-24 Intel Corporation Wide band gap transistor on non-native semiconductor substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017501562A (en) * 2013-12-23 2017-01-12 インテル・コーポレーション Wide bandgap transistor on non-native semiconductor substrate and method of manufacturing the same
US10032911B2 (en) 2013-12-23 2018-07-24 Intel Corporation Wide band gap transistor on non-native semiconductor substrate

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