JP2004014709A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of reducing the occurrence of a defective element due to the breakage or chipping off of a crystal in chip separation. <P>SOLUTION: On a wafer 11 comprising a silicon carbide substrate and a silicon carbide layer, an upper electrode 6 is arranged side by side nearly along a direction Y which is one of cleavage directions and a direction X which is tilted from the cleavage direction by at least 5°. Then, when separating an element formed on the wafer 11 into a plurality of chips 10, the chip is cut off along a separation line 14a which is nearly parallel to the cleavage direction Y and a separation line 14b which is nearly parallel to the direction X. In this case, arranging of the electrode 6 side by side and chip separation are performed with a step formed on the silicon carbide as reference, thereby the cleavage direction is known precisely to reduce occurrence of the breakage or chipping off in the semiconductor chip in chip separation. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device using silicon carbide.
[0002]
[Prior art]
Silicon carbide (silicon carbide, SiC) is a semiconductor having a higher hardness and a wider band gap than silicon (Si), and is applied to power elements, environmental resistance elements, high-temperature operation elements, high-frequency elements, and the like. Generally, a plurality of these elements are formed on a silicon carbide substrate. The silicon carbide substrate includes an evaluation test element, an alignment key for positioning a mask used in a photo process, and the like, in addition to an element body for achieving the object.
[0003]
FIG. 7A is a cross-sectional view illustrating a Schottky diode using SiC, which is a typical switching element. FIG. 7B is a plan view showing the silicon carbide substrate in a wafer state on which a plurality of Schottky diodes are formed.
[0004]
As shown in FIG. 7A, a conventional Schottky diode is composed of a semiconductor substrate 71 made of n-type 4H-SiC, and silicon carbide made of n-type 4H-SiC provided on the semiconductor substrate 71. A layer 72, an impurity implantation layer 73 provided on the silicon carbide layer 72 and implanted with boron, a Schottky electrode 74 made of nickel (Ni) provided on the silicon carbide layer 72, An upper electrode 76 provided on the electrode 74 and laminated with titanium (Ti) and gold (Au); an ohmic electrode 75 made of nickel (Ni) formed on the lower surface of the semiconductor substrate 71; The lower electrode 75 is formed on the lower surface of the lower electrode 75 and is formed by laminating titanium (Ti) and gold (Au).
[0005]
In the present specification, for the sake of description, the direction in which Schottky electrode 74 is formed is defined as the upward direction, and the direction in which ohmic electrode 75 is formed is defined as the downward direction, as viewed from silicon carbide substrate 71.
[0006]
As shown in FIG. 7B, in a semiconductor substrate 71 in a wafer state, a plurality of Schottky diodes 70 are arranged at regular intervals. In addition, at positions P1 and P2 on the silicon carbide substrate, a Schottky electrode used as a test electrode for evaluation and an alignment key for aligning a mask in a photo process are provided.
[0007]
The provision of the test electrode for evaluation has an advantage that the impurity concentration on the surface of the silicon carbide layer 72 can be known, but the test electrode for evaluation may not exist. On the other hand, the alignment key is provided for positioning a mask used in a photolithography process, and is indispensable for forming a semiconductor element requiring a photolithography process.
[0008]
[Problems to be solved by the invention]
However, in the conventional device using silicon carbide, the following problems have occurred.
[0009]
Chip separation can be easily performed with silicon, but chip separation and cutting are difficult with silicon carbide due to high hardness, and separation and cutting using cleavage are not easy.
[0010]
Therefore, dicing is used to separate and cut silicon carbide. For example, as shown in FIG. 7B, a semiconductor substrate 71 in a wafer state having a plurality of elements can be cut by dicing at separation lines 79a and 79b to obtain a silicon carbide semiconductor element 70 in a chip state.
[0011]
In order to perform dicing, it is necessary to arrange the elements in such a manner that a margin is provided in addition to the margin of the separation lines 79a and 79b. Here, as the interval x, y between the adjacent upper electrodes 76 is larger, it is easier to cut, and the element failure is less likely to occur. On the other hand, in order to obtain as many elements as possible, it is preferable to form more Schottky diodes on the wafer while keeping the distances x and y as small as possible.
[0012]
However, in the above-mentioned conventional method, even if dicing is performed in consideration of the above-described points, a crystal crack or a chip generated on a cut surface is large and often affects the element operation region. For this reason, although the chip normally operates before the chip separation, an operation failure may occur after the chip separation, which causes a reduction in yield.
[0013]
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device with less defective elements by taking measures for accurately separating chips.
[0014]
[Means for Solving the Problems]
According to the method of manufacturing a semiconductor device of the present invention, there is provided a step (a) of forming a semiconductor layer made of silicon carbide on a wafer by epitaxial growth, and forming a plurality of electrodes on the semiconductor layer in at least one cleavage direction. A step (b) of juxtaposition along a first electrode arrangement direction having an inclination of 5 degrees or less and a second electrode arrangement direction having an inclination of more than 5 degrees from the cleavage direction, and separating the wafer into chips (C).
[0015]
Thus, at the time of chip separation, at least the first electrode arrangement direction is substantially along the cleavage direction, so that separation can be performed more easily.
[0016]
After the step (a) or the step (a), a step indicating a crystal orientation is formed on at least a part of the upper surface of the semiconductor layer. In the step (b), the electrodes are juxtaposed based on the step. be able to.
[0017]
In the step (b), the first electrode is arranged in the second electrode arrangement direction in such a manner that the column interval is larger than the first electrode arrangement direction in the first electrode arrangement direction. Since the cutting margin in the second electrode arrangement direction, which is more difficult to separate than the electrode arrangement direction, can be set larger, it is possible to suppress the occurrence of crystal breakage or chipping caused by the separation to the element formation region. be able to.
[0018]
After the above-mentioned step (a) and before the above-mentioned step (c), a pattern for positioning the test electrode for evaluation and the mask is arranged on the electrode of the semiconductor layer which is juxtaposed in the second electrode arrangement direction. Preferably, it is provided on the area between the rows.
[0019]
The surface of the silicon carbide surface that is in contact with the semiconductor layer may be a (00001) plane, a (000-1) plane, or an off-cut plane inclined within 10 degrees from any one of these planes. It is preferable that
[0020]
The cleavage direction may be a <11-20> direction.
[0021]
The first electrode arrangement direction is a direction inclined by θ degrees (θ degree ≦ 5 degrees) from the cleavage direction. In the wafer, the row interval of the electrodes arranged in parallel along the first electrode arrangement direction is provided. Is defined as x, and the maximum length in the cleavage direction is defined as L.
tanθ <x / L
Is preferably satisfied.
[0022]
In the step (c), the wafer is separated along the first electrode disposition direction by a separation line having a tilt of 5 degrees or less from the cleavage direction, so that a direction closer to the cleavage direction can be ensured. Can be used for separation.
[0023]
In the step (c), the wafer can be separated based on the steps.
[0024]
In the step (c), in the first electrode disposing direction, the wafer can be separated by a scribing method along the cleavage direction, so that the necessary cutting width can be set small. Cracks and chips can also be reduced.
[0025]
In the step (c), the wafer is preferably cut by a dicing method in the second electrode arrangement direction.
[0026]
The first electrode arrangement direction is a direction inclined by θ degrees (θ degrees ≦ 5 degrees) from the cleavage direction, and the separation line in the first electrode arrangement direction is δ degrees (δ degree) from the cleavage direction. (Degrees ≦ 5 degrees). In the wafer, when the row spacing of the electrodes arranged along the first electrode juxtaposition direction is x, and the maximum length in the cleavage direction is L, The second and third equations below
tan δ <(x / L)
tan | θ-δ | <(x / L)
Is preferably satisfied.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
(Device juxtaposition along the cleavage direction, chip separation)
1A and 1B are a cross-sectional view showing a structure of a silicon carbide semiconductor element in a wafer state and a plan view showing an arrangement of each element on a wafer in the embodiment. Here, in order to simplify the description, a Schottky diode in which one electrode per element is viewed as one when viewed from above will be described.
[0028]
As shown in FIG. 1A, the Schottky diode 9 in the wafer state of the present embodiment includes a semiconductor substrate 1 made of n-type 4H—SiC and an n-type 4H provided on the semiconductor substrate 1. -SiC epitaxial layer 2, boron-implanted impurity-implanted layer 3 provided in a region surrounding side of operation region 8 in silicon carbide layer 2, A Schottky electrode 4 made of nickel (Ni) provided over the impurity implantation layer 3 around the periphery thereof, and titanium (Ti) and gold (Au) provided on the Schottky electrode 4 , An ohmic electrode 5 made of nickel (Ni) formed on the lower surface of the semiconductor substrate 1, and titanium (Ni) formed on the lower surface of the ohmic electrode 5. i) gold (Au) and is composed of the lower electrode 7 for being stacked.
[0029]
Here, as the semiconductor substrate, an off-cut substrate whose main surface is inclined by about 8 degrees in the [11-20] direction from the (000) silicon surface is used. The upper electrode (anode electrode) 6 is provided for wire bonding, and is formed by sequentially laminating a gold (Au) film on a titanium (Ti) film. A region of the impurity injection layer 3 formed so as to overlap with the Schottky electrode 4 functions as a guard ring.
[0030]
The Schottky diodes 9 having the above structure are regularly arranged on the wafer as shown in FIG. Although the planar shape of the upper electrode 6 is represented by a square, the four corners may actually be rounded. Of course, the same applies to the Schottky electrode 4 formed thereunder.
[0031]
As shown in the lower part of FIG. 1B, it is assumed that the silicon carbide crystal has cleavage directions A, B, and C. The direction Y indicating the [11-20] direction corresponds to the direction A, and the direction X indicating the [1-100] direction is orthogonal to the direction A and inclined at an angle of 30 ° from the directions B and C. Direction. The upper electrode 6 is juxtaposed along a direction Y ′ substantially parallel to the cleavage direction Y (for example, a direction whose inclination from the cleavage direction Y is within 5 °) and a direction X ′ substantially parallel to the direction X. Here, the direction X ′ is a direction inclined at least more than 5 ° from the cleavage direction Y. Illustration of the directions Y ′ and X ′ is omitted.
[0032]
When the wafer 11 is separated into a plurality of chips 10, cutting is performed along the separation lines 14a and 14b. The separation line 14a is substantially parallel to the cleavage direction Y (for example, a direction whose inclination from the direction Y is within 5 °), and the separation line 14b is substantially parallel to the direction X (for example, the inclination from the direction X is Direction within 5 °). Here, the separation lines 14a and 14b are perpendicular to each other, and the interval between two adjacent separation lines 14a and the interval between two adjacent separation lines 14b are, for example, 2 mm.
[0033]
Reference numeral 13 schematically shows an alignment key for positioning in a photo process.
[0034]
(Device juxtaposition and chip separation based on steps)
Next, a method of arranging elements and separating chips will be described based not on the orientation flat but on a step which is conventionally considered to be preferably suppressed.
[0035]
In this embodiment, when forming the silicon carbide epitaxial layer 2 on the semiconductor substrate 1, at a temperature of 1500 ° C. or more, a source gas having a carbon / silicon ratio of 1 or more is grown at a growth pressure of 100 Torr (1.33). × 10 ⁴ By supplying at Pa) or more, steps parallel to the [1-100] direction, that is, the X direction are formed. Here, if this step has a height of 10 nm or more, it is visible.
[0036]
Alternatively, at a temperature of 1500 ° C. or more, 700 Torr (9.31 × 10 ⁴ The steps parallel to the [1-100] direction can also be formed by performing high-temperature heat treatment in a hydrogen atmosphere at a reduced pressure below Pa).
[0037]
If the separation line 14b is made substantially parallel to the X direction based on this step, the separation line 14a orthogonal to the separation line 14b becomes substantially parallel to the cleavage direction Y.
[0038]
In a conventional semiconductor device using silicon carbide, the device is separated on the basis of the orientation flat. However, cracking or chipping affects the vicinity of the operation region of the device, often causing device failure. This is due to the fact that the orientation flat is often shifted from the plane orientation of the crystal. Therefore, in the present invention, attention has been focused on steps that have conventionally been considered preferable to suppress, and it has been conceived that instead of arranging elements based on the orientation flat and performing chip separation, the steps may be used as references. Was. Since the steps faithfully represent the plane orientation of the silicon carbide crystal, the steps corresponding to the crystal planes are formed and used as a reference so that the cleavage direction can be reliably known without the need for an orientation flat at the substrate end. it can.
[0039]
In the example described above, the steps can be formed on the entire surface of the epitaxial layer. However, in the present invention, the plane orientation of silicon carbide is indicated on a part of the surface of the epitaxial layer by another method. A shape may be prepared, and a direction corresponding to the cleavage direction may be obtained based on the shape.
[0040]
As described above, when cutting is performed by juxtaposing the upper electrodes 6 on the basis of the steps, the separation can be performed more reliably by further applying the following conditions.
[0041]
(Interval of element arrangement on wafer)
It is preferable that the row spacing x of the electrode rows 15a arranged in the Y 'direction as shown in FIG. 1 is larger than the row spacing y of the electrode rows 15b arranged in the X' direction, which will be described below. .
[0042]
FIG. 2 is a plan view for explaining the intervals at which silicon carbide semiconductor elements are arranged on the wafer. Here, a plurality of Schottky electrodes (not shown) and an upper electrode 6 covering the upper surface of the Schottky electrode are formed on the wafer 11. The wafer 11 is cut at the separation lines 14a and 14b to become the chips 10. It should be noted that some hatching, alignment keys, and the like are not shown for easy viewing.
[0043]
In FIG. 2, the lengths of the sides of the upper electrode 6 in the directions X ′ and Y ′ are indicated as x1 and y1. Further, in the wafer 11, the interval between two adjacent separation lines 14a is indicated as X1, and the interval between two adjacent separation lines 14b is indicated as Y1.
[0044]
In order for the chips 10 separated from the wafer 11 to operate normally, the following equations (1) and (2) are required even in the state of the wafer 11.
X1> x1 (1)
Y1> y1 (2)
Must be satisfied.
[0045]
Further, the row interval y of the electrode rows 15b of the elements arranged side by side in the direction X ′ is given by the following equation (3).
y = Y1-y1 (3)
Meet.
[0046]
The row spacing x between the electrode rows 15a of the elements arranged in the direction Y ′ is expressed by the following equation (4).
x = X1-x1 (4)
Meet.
[0047]
Here, in the present embodiment, the following expression (5)
y ≧ x (5)
It is preferable that
[0048]
In other words, the row interval y between the electrode rows 15b of the elements juxtaposed in the X 'direction substantially parallel to the direction X (the direction different from the cleavage direction by more than 5 °) is the direction Y' substantially parallel to the cleavage direction Y (the cleavage direction). It is preferable that the distance be larger than the line interval x of the electrode lines 15b of the elements juxtaposed in the direction within 5 ° from Y). Here, the column interval x is a value in consideration of the width of the margin when cutting at the separation line 14a, and the column interval y is a value in consideration of the width of the margin when cutting at the separation line 14b. . In other words, it can be rephrased that it is preferable to make the width of the margin of the separation line 14b larger than the width of the margin of the separation line 14a. The reason will be described below.
[0049]
The separation and cutting of the element along the separation line 14a is relatively easy because it is performed in a direction substantially corresponding to the cleavage direction Y, and the crystal is not easily cracked or chipped in an unintended direction. On the other hand, it is difficult to separate and cut the element along the separation line 14b along the X direction different from the cleavage direction, as compared with the case in the Y direction, and the crystal is easily cracked or chipped.
[0050]
If the crystal cracks or chips generated at this time extend beyond the region set as the arrangement interval of the upper electrodes to the region where the upper electrode 6 is formed, the silicon carbide semiconductor element may not be able to operate normally. . For example, when the silicon carbide semiconductor device is a Schottky diode, the rectification characteristics of the diode are affected, which causes a reduction in reverse breakdown voltage and device breakdown.
[0051]
From the above, in order to reduce the influence of the cracks and chipping, the column spacing y including the cutting margin when cutting in a direction different from the cleavage direction is set when the cutting is performed in a direction substantially parallel to the cleavage direction. It can be said that it is preferable to be larger than the column interval x including the margin.
[0052]
For example, if x1 = y1 = 1.6 mm, X1 = 2.0 mm, and Y1 = 2.1 mm, x = 0.4 mm and y = 0.5 mm. Here, when the wafer 11 is cut along the separation lines 14a and 14b by dicing, the length X2 of one side of the chip 10 in the X ′ direction is about 1.8 mm, and the length Y2 of one side in the Y ′ direction is about 1 mm. 0.9 mm.
[0053]
Further, as another numerical example, even when x1 = 1.6 mm, y1 = 1.5 mm, and X1 = Y1 = 2.0 mm, x = 0.4 mm and y = 0.5 mm. The occurrence of defects in the chip 10 can be suppressed.
[0054]
(Placement of test electrodes and alignment keys for evaluation)
The evaluation test electrode 32 and the alignment key 32 for positioning the mask are preferably formed between the electrode rows 15b of the elements juxtaposed in the X direction, which will be described below.
[0055]
FIG. 3 is a plan view for explaining the arrangement of the evaluation test electrodes 32 and the alignment keys 31 on the wafer. The hatching of the upper electrode 6 is omitted for easy viewing.
[0056]
Generally, in a manufacturing process of a silicon carbide semiconductor device, mask alignment is performed a plurality of times. At this time, it is necessary to arrange the alignment key 32 on the wafer 11 for positioning on the order of microns. Further, providing the test electrode 31 for evaluation on the wafer 11 has an advantage that the impurity concentration on the surface of the silicon carbide epitaxial layer can be known. However, the alignment key 32 and the test electrode 31 for evaluation have nothing to do with the original operation of the silicon carbide semiconductor device, and are necessary in the state of the wafer 11 but are not required after the chip separation. Therefore, in order to increase the number of chips obtained after chip separation, it can be said that it is desirable to arrange the alignment key 32 and the test electrode 31 for evaluation at a position different from the position where the upper electrode 6 is arranged.
[0057]
Considering this, as the area for disposing the alignment key 32 and the test electrode 31 for evaluation, the area A with the column interval x sandwiched between the upper electrodes 6 adjacent in the X ′ direction and the area in the Y ′ direction A region B sandwiched between adjacent upper electrodes 6 and having a column interval y and a region C sandwiched between diagonally adjacent upper electrodes 6 and having a column interval x and a column interval y can be considered. .
[0058]
In order to form the alignment key 31 and the test electrode 32 for evaluation, there is a case where both the X ′ direction and the Y ′ direction require a region of 100 μm or more (100 μm square region). A region where both intervals are large is suitable. Therefore, when the column interval y is set to be larger than the column interval x as described above, it can be said that the regions B and C having the column interval y are preferable.
[0059]
(Wafer cutting method)
In the wafer shown in FIG. 1, it is preferable that the separation at the separation line 14a in the cleavage direction Y is performed by scribing and the cutting at the separation line 14b in the direction X is performed by dicing, which will be described below.
[0060]
FIG. 4 is a plan view for explaining a wafer cutting method.
[0061]
The scribing method is a method in which the surface of the silicon carbide layer exposed on the upper surface of the wafer 11 is scratched and divided along the scratch, and is suitable for separating the separation line 14a substantially parallel to the cleavage direction Y. In the separation by scribing, the width of the necessary cutting margin is small, so that there is no waste compared with dicing. When the surface of the silicon carbide layer is scratched, a chip of about 10 to 20 μm may be generated around the separation line 14a, but since the crystal is separated along the cleavage direction, the cracks and chips of the crystal are not easily expanded. . However, if there is room to increase the column interval x including the width of the margin of the separation line 14a, the separation may be performed by dicing.
[0062]
On the other hand, since the separation line 14b is along a direction different from the cleavage direction, if the separation is attempted by the scribing method, a crack may be generated to break the wafer 11 and the element may be broken. Therefore, cutting by dicing is preferable. For separation by dicing, a cutout 41 having a width of about 200 μm is provided on the separation line 14b. If the column interval y is provided in consideration of the width of the cutting margin 41 of this degree, dicing is performed, and the chip of the crystal may reach the periphery of the cutting margin 41 but may not reach the operating region. Disappears. Accordingly, element column separation in the direction X that is not parallel to the cleavage direction can be reliably performed, and operation failure of the element can be suppressed.
[0063]
By selecting a cutting method as described above, the number of elements can be increased by further reducing the column interval x in the cleavage direction Y. On the other hand, in the direction X different from the cleavage direction, element column separation can be reliably performed.
[0064]
(Specification of cleavage plane direction, juxtaposition direction of upper electrode and separation direction)
In the above, the arrangement directions Y ′ and X ′ of the upper electrode 6 and the directions toward the separation lines 14a and 14b are described with respect to the directions Y and X. Hereinafter, the angles of those directions will be specifically described.
[0065]
FIG. 5 is a plan view for explaining the angle from the cleavage direction Y on the wafer to the direction Y 'of juxtaposing the upper electrodes and the direction of the separation line 14a. FIG. 5 schematically shows a circular wafer 11 on which an orientation flat is formed. For the sake of explanation, only a part of the upper electrode 6 is shown on the wafer 11, and the upper electrodes 6a, 6b, 6c and 6d are further distinguished. Then, a cleavage line 51 along the cleavage direction Y, an electrode juxtaposition line 52 along a direction Y ′ at an angle θ ° from the cleavage direction Y, and a separation line 14a along an angle δ ° from the cleavage direction Y are formed. Show.
[0066]
The upper electrodes 6 of the element are juxtaposed along a direction Y ′ at an angle θ ° (where θ ≦ 5 °, more preferably θ ≦ 2 °) with respect to the cleavage direction Y. At this time, the maximum length L in the cleavage direction Y and the interval x between the electrode rows 15a are expressed by the following equation (6).
tanθ <x / L (6)
Is preferably satisfied.
[0067]
When Expression (6) is satisfied, the cleavage line 51 in the cleavage direction Y does not contact any of the upper electrodes 6a, 6b, 6c, and 6d, and falls within the range of the width x. That is, the cleavage line can be sandwiched between two adjacent electrode rows 15a.
[0068]
Further, the separation line 14a for separating the wafer 11 is along the direction of an angle δ ° (where δ ≦ 5 degrees, more preferably δ ≦ 2 degrees) with respect to the cleavage direction Y. At this time, with respect to the maximum length L in the cleavage direction Y and the row interval x of the electrode row 15a, the following equations (7) and (8)
tan δ <(x / L) (7)
tan | θ-δ | <(x / L) (8)
It is preferable that the following expressions hold.
[0069]
When the expressions (7) and (8) are satisfied, the separation line 14a does not contact any of the upper electrodes 6a, 6b, 6c, and 6d, and falls within the range of the width x. That is, since the wafer can be separated within the row interval x of the electrode row 15a, the separation can be performed more reliably, and the cracking and chipping of the substrate can be suppressed.
[0070]
(Other embodiments)
Further, in the above-described embodiment, the case of the 4H-SiC substrate on which 4H-SiC is deposited as the semiconductor substrate has been described. May be a 15R-SiC substrate. Further, a Si (111) substrate or a Si (001) substrate on which 3C-SiC is deposited may be used. In the case of a Si (111) substrate, a plurality of elements are juxtaposed in parallel in the <1-10> direction, and in the case of a Si (001) substrate, a plurality of elements are substantially parallel to the <100> direction. Be juxtaposed. Of course, other combinations may be used, and a laminated structure of two or more layers may be used.
[0071]
Further, in the above-described embodiment, the off-cut direction of the silicon carbide surface whose main surface is a surface off-cut from the (0 0 0 1) surface is the [11 1-20] direction. The direction may be in the <1-20> direction, or may be in the <1-1100> direction. At this time, the direction parallel to the step formed on the surface is parallel to the cleavage direction.
[0072]
In the present invention, the juxtaposition of elements and the separation of chips may be performed along a plane parallel to the <11-20> direction, that is, a cleavage plane. As a plane parallel to the <11-20> direction, for example, a {1-1100} plane may be mentioned.
[0073]
Further, the main surface of the semiconductor substrate or the epitaxial layer made of silicon carbide is off-cut from the (000-1) plane, that is, the carbon plane, in addition to the plane that is offcut by about 8 degrees from the (00001) plane. It may be a face. Further, the present invention can be applied to other surfaces as long as the surfaces can separate the substrate along the cleavage direction. Further, the angle of the off-cut is not limited to 8 degrees, and may not be off-cut, or may be another angle within 10 degrees.
[0074]
Although the cleavage direction is defined as the Y direction and the direction orthogonal thereto is defined as the X direction, the X direction does not have to be the orthogonal direction.
[0075]
In the above-described embodiment, the Schottky diode has been described. However, the present invention can be applied to MOS transistors, pn diodes, MES transistors, and other conceivable elements.
[0076]
For example, FIG. 6 is a plan view showing an example of an arrangement of silicon carbide semiconductor elements (vertical MOS transistors) on a wafer. In the semiconductor device shown in FIG. 6, a MOS transistor 64 is formed on a wafer 61 so that a gate upper wiring electrode 62 connecting a gate electrode and a source upper wiring electrode 63 connecting a source electrode are exposed. Although not shown, a drain electrode is formed on the lower surface of the wafer 61. Here, in each MOS transistor 64, two electrodes are exposed on the upper surface, but the present invention can be applied to an element having such a plurality of electrodes.
[0077]
Further, in the above embodiment, in the separated chip, one element is formed for one chip, and the configuration in which the element has one upper electrode has been described. However, a plurality of elements may be formed in the separated chip of the present invention.
[0078]
In the above embodiment, the rectangular upper electrode is shown. However, the upper electrode may be of any other shape, or may be rounded to reduce the electric field concentration.
[0079]
In the present invention, the electrode material and the shape and configuration of each element are not particularly limited.
[0080]
In the above-described embodiment, the separation method using scribing or dicing has been described. However, a more appropriate separation method using a method suitable for separation in a direction substantially along the cleavage direction or separation along a direction that is not parallel to the cleavage direction. If there are methods, they may be used.
[0081]
In the above-described embodiment, when the upper electrodes 6 are juxtaposed along the cleavage direction Y and the cutting is performed along the cleavage direction Y, the conditions such as the element arrangement interval and the separation method are further set. Applied. However, in the present invention, all the conditions are not necessarily applied because each condition is independent. That is, an example in which the arrangement intervals of the elements are the same in the x-interval and the y-interval, and other conditions are independently applied is also possible.
[0082]
【The invention's effect】
In the present invention, the plurality of silicon carbide semiconductor elements provided on the wafer are juxtaposed in a direction substantially parallel to at least one of the cleavage directions, thereby suppressing cracking and chipping during chip separation. Can be.
[0083]
In addition, when chips are formed by separating a wafer, separation is performed in a direction substantially parallel to at least one of the cleavage directions, thereby facilitating column separation of element rows arranged substantially parallel to the cleavage direction. Can be
[0084]
Further, by forming a step indicating the crystal orientation on at least a part of the wafer, the elements can be juxtaposed on the basis of the step. Further, by selecting the distance between the element rows, the arrangement position of the evaluation electrodes and the alignment keys, the cutting method, and the like, the chip separation can be performed more reliably.
[Brief description of the drawings]
FIGS. 1A and 1B are a cross-sectional view showing a structure of a silicon carbide semiconductor device in a wafer state and a plan view showing an arrangement of each device on a wafer in an embodiment.
FIG. 2 is a plan view for explaining intervals at which silicon carbide semiconductor elements are arranged in a wafer.
FIG. 3 is a plan view for explaining an arrangement of an evaluation test electrode and an alignment key on a wafer.
FIG. 4 is a plan view for explaining a wafer cutting method.
FIG. 5 is a plan view for explaining an angle from a cleavage direction Y of the wafer to a direction Y ′ of juxtaposition of upper electrodes and a direction of a separation line 14a.
FIG. 6 is a plan view showing an example of an arrangement of silicon carbide semiconductor elements (vertical MOS transistors) on a wafer.
FIGS. 7A and 7B are a cross-sectional view showing a conventional Schottky diode using silicon carbide and a plan view of a state of a wafer.
[Explanation of symbols]
1 semiconductor substrate
2 Epitaxial layer
3 Impurity injection layer
4 Schottky electrode
5 Ohmic electrode
6 Upper electrode
6a Upper electrode
6b Upper electrode
6c Upper electrode
6d upper electrode
7 Lower electrode
8 Operating area
9 Schottky diode
10 chips
11 Wafer
12 Upper electrode
13 Alignment key
14a Separation line
14b Separation line
15a electrode row
15b electrode row
31 Alignment key
32 Test electrode for evaluation
51 Cleavage line
52 electrode juxtaposition line
61 wafer
62 Gate upper wiring electrode
63 Source upper wiring electrode
64 MOS transistors

Claims (12)

(A) forming a semiconductor layer made of silicon carbide on a wafer by epitaxial growth;
A plurality of electrodes are formed on the semiconductor layer in at least one of a first electrode arrangement direction having an inclination from the cleavage direction of 5 degrees or less and a second electrode arrangement direction having an inclination of more than 5 degrees from the cleavage direction. (B) juxtaposing along;
A method for manufacturing a semiconductor device, comprising: (c) separating the wafer into chips. The method for manufacturing a semiconductor device according to claim 1, wherein:
Forming a step showing a crystal orientation on at least a part of the upper surface of the semiconductor layer after the step (a) or the step (a);
The method of manufacturing a semiconductor device, wherein in the step (b), the electrodes are juxtaposed on the basis of the steps. The method for manufacturing a semiconductor device according to claim 1, wherein:
In the step (b), a column interval of the electrodes arranged in the second electrode arrangement direction is made larger than a column interval of the electrodes arranged in the first electrode arrangement direction. A method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device according to claim 1, wherein:
After the above-mentioned step (a) and before the above-mentioned step (c), a pattern for positioning the test electrode for evaluation and the mask is arranged on the electrode of the semiconductor layer which is juxtaposed in the second electrode arrangement direction. A method for manufacturing a semiconductor device, wherein the method is provided on a region between columns. A method for manufacturing a semiconductor device according to claim 1, wherein:
The surface of the silicon carbide surface that is in contact with the semiconductor layer may be a (00001) plane, a (000-1) plane, or an off-cut plane inclined within 10 degrees from any one of these planes. A method of manufacturing a semiconductor device. A method for manufacturing a semiconductor device according to claim 1, wherein:
The method for manufacturing a semiconductor device, wherein the cleavage direction is a <11-20> direction. A method for manufacturing a semiconductor device according to claim 1, wherein:
The first electrode arrangement direction is a direction inclined by θ degrees (θ degrees ≦ 5 degrees) from the cleavage direction,
In the above-mentioned wafer, the following first formula tanθ <x / L, where x is the column interval of the electrodes juxtaposed along the first electrode arrangement direction and L is the maximum length in the cleavage direction.
A method for manufacturing a semiconductor device, characterized in that: A method for manufacturing a semiconductor device according to claim 1, wherein:
In the step (c), a method of manufacturing a semiconductor device, comprising separating the wafer along a separation line having a tilt of 5 degrees or less from the cleavage direction along the first electrode arrangement direction. The method of manufacturing a semiconductor device according to claim 1,
In the step (c), a method of manufacturing a semiconductor device, comprising separating the wafer based on the steps. The method for manufacturing a semiconductor device according to claim 8, wherein:
In the step (c), the wafer is separated by a scribing method along the cleavage direction in the first electrode arrangement direction. The method for manufacturing a semiconductor device according to claim 8, wherein:
In the step (c), the wafer is cut by a dicing method in the second electrode arrangement direction. The method of manufacturing a semiconductor device according to claim 8, wherein:
The first electrode arrangement direction is a direction inclined by θ degrees (θ degrees ≦ 5 degrees) from the cleavage direction,
The separation line in the first electrode arrangement direction is a direction inclined by δ degrees (δ degrees ≦ 5 degrees) from the cleavage direction,
In the above-mentioned wafer, when the column interval of the electrodes juxtaposed along the first electrode juxtaposition direction is x and the maximum length in the cleavage direction is L, the following second and third expressions tanδ < (X / L)
tan | θ-δ | <(x / L)
A method for manufacturing a semiconductor device, characterized in that:

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