JP2016541057A5 - - Google Patents

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Publication number
JP2016541057A5
JP2016541057A5 JP2016530912A JP2016530912A JP2016541057A5 JP 2016541057 A5 JP2016541057 A5 JP 2016541057A5 JP 2016530912 A JP2016530912 A JP 2016530912A JP 2016530912 A JP2016530912 A JP 2016530912A JP 2016541057 A5 JP2016541057 A5 JP 2016541057A5
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JP
Japan
Prior art keywords
vector data
data sample
sample set
input
resulting output
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Pending
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JP2016530912A
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English (en)
Japanese (ja)
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JP2016541057A (ja
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Priority claimed from US14/082,081 external-priority patent/US9977676B2/en
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Publication of JP2016541057A publication Critical patent/JP2016541057A/ja
Publication of JP2016541057A5 publication Critical patent/JP2016541057A5/ja
Pending legal-status Critical Current

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JP2016530912A 2013-11-15 2014-11-13 ベクトルデータメモリに記憶される出力ベクトルデータのインフライト並び替えを提供するために実行ユニットとベクトルデータメモリとの間でデータフローパスにおいて並び替え回路を利用するベクトル処理エンジン（ｖｐｅ）および関連するベクトルプロセッサシステムと方法 Pending JP2016541057A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/082,081 US9977676B2 (en) 2013-11-15 2013-11-15 Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory, and related vector processor systems and methods
US14/082,081 2013-11-15
PCT/US2014/065412 WO2015073646A1 (en) 2013-11-15 2014-11-13 Vector processing engine employing reordering circuitry in data flow paths between vector data memory and execution units, and related method

Publications (2)

Publication Number Publication Date
JP2016541057A JP2016541057A (ja) 2016-12-28
JP2016541057A5 true JP2016541057A5 (enExample) 2018-08-02

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JP2016530912A Pending JP2016541057A (ja) 2013-11-15 2014-11-13 ベクトルデータメモリに記憶される出力ベクトルデータのインフライト並び替えを提供するために実行ユニットとベクトルデータメモリとの間でデータフローパスにおいて並び替え回路を利用するベクトル処理エンジン（ｖｐｅ）および関連するベクトルプロセッサシステムと方法

Country Status (6)

Country Link
US (1) US9977676B2 (enExample)
EP (1) EP3069233A1 (enExample)
JP (1) JP2016541057A (enExample)
KR (1) KR20160085335A (enExample)
CN (1) CN105765523B (enExample)
WO (1) WO2015073646A1 (enExample)

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US9619227B2 (en) 2013-11-15 2017-04-11 Qualcomm Incorporated Vector processing engines (VPEs) employing tapped-delay line(s) for providing precision correlation / covariance vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods
US9684509B2 (en) 2013-11-15 2017-06-20 Qualcomm Incorporated Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory, and related vector processing instructions, systems, and methods
US9792118B2 (en) 2013-11-15 2017-10-17 Qualcomm Incorporated Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods
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KR102287614B1 (ko) * 2015-02-12 2021-08-10 한국전자통신연구원 길이가 64800이며, 부호율이 2/15인 ldpc 부호어 및 16-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법
KR102287630B1 (ko) * 2015-02-17 2021-08-10 한국전자통신연구원 길이가 16200이며, 부호율이 3/15인 ldpc 부호어 및 16-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법
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US9880845B2 (en) 2013-11-15 2018-01-30 Qualcomm Incorporated Vector processing engines (VPEs) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations, and related vector processor systems and methods
US9619227B2 (en) 2013-11-15 2017-04-11 Qualcomm Incorporated Vector processing engines (VPEs) employing tapped-delay line(s) for providing precision correlation / covariance vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods
US9684509B2 (en) 2013-11-15 2017-06-20 Qualcomm Incorporated Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory, and related vector processing instructions, systems, and methods

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