JP2019521445A5 - - Google Patents

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Publication number
JP2019521445A5
JP2019521445A5 JP2019500593A JP2019500593A JP2019521445A5 JP 2019521445 A5 JP2019521445 A5 JP 2019521445A5 JP 2019500593 A JP2019500593 A JP 2019500593A JP 2019500593 A JP2019500593 A JP 2019500593A JP 2019521445 A5 JP2019521445 A5 JP 2019521445A5
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JP
Japan
Prior art keywords
processing
data
lane
lanes
processing lanes
Prior art date
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Pending
Application number
JP2019500593A
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English (en)
Japanese (ja)
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JP2019521445A (ja
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Publication date
Priority claimed from US15/209,057 external-priority patent/US10592468B2/en
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Publication of JP2019521445A publication Critical patent/JP2019521445A/ja
Publication of JP2019521445A5 publication Critical patent/JP2019521445A5/ja
Pending legal-status Critical Current

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JP2019500593A 2016-07-13 2017-05-19 Ｓｉｍｄアーキテクチャにおけるレーンのシャッフルのためのシャッフラー回路 Pending JP2019521445A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/209,057 US10592468B2 (en) 2016-07-13 2016-07-13 Shuffler circuit for lane shuffle in SIMD architecture
US15/209,057 2016-07-13
PCT/US2017/033663 WO2018013219A1 (en) 2016-07-13 2017-05-19 Shuffler circuit for lane shuffle in simd architecture

Publications (2)

Publication Number Publication Date
JP2019521445A JP2019521445A (ja) 2019-07-25
JP2019521445A5 true JP2019521445A5 (enExample) 2020-06-18

Family

ID=58779363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019500593A Pending JP2019521445A (ja) 2016-07-13 2017-05-19 Ｓｉｍｄアーキテクチャにおけるレーンのシャッフルのためのシャッフラー回路

Country Status (6)

Country Link
US (1) US10592468B2 (enExample)
EP (1) EP3485385B1 (enExample)
JP (1) JP2019521445A (enExample)
KR (1) KR102118836B1 (enExample)
CN (1) CN109478175B (enExample)
WO (1) WO2018013219A1 (enExample)

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US10957095B2 (en) * 2018-08-06 2021-03-23 Intel Corporation Programmable ray tracing with hardware acceleration on a graphics processor
US10963300B2 (en) * 2018-12-06 2021-03-30 Raytheon Company Accelerating dataflow signal processing applications across heterogeneous CPU/GPU systems
US11397624B2 (en) * 2019-01-22 2022-07-26 Arm Limited Execution of cross-lane operations in data processing systems
US11294672B2 (en) * 2019-08-22 2022-04-05 Apple Inc. Routing circuitry for permutation of single-instruction multiple-data operands
US11256518B2 (en) 2019-10-09 2022-02-22 Apple Inc. Datapath circuitry for math operations using SIMD pipelines
US20210349717A1 (en) * 2020-05-05 2021-11-11 Intel Corporation Compaction of diverged lanes for efficient use of alus
US20220197649A1 (en) * 2020-12-22 2022-06-23 Advanced Micro Devices, Inc. General purpose register hierarchy system and method
US11360897B1 (en) * 2021-04-15 2022-06-14 Qualcomm Incorporated Adaptive memory access management
CN115793958A (zh) * 2021-09-10 2023-03-14 腾讯科技（深圳）有限公司 一种混洗数据的处理方法、相关装置、设备以及存储介质
CN115061731B (zh) * 2022-06-23 2023-05-23 摩尔线程智能科技(北京)有限责任公司 混洗电路和方法、以及芯片和集成电路装置

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CA2078912A1 (en) * 1992-01-07 1993-07-08 Robert Edward Cypher Hierarchical interconnection networks for parallel processing
US20040054877A1 (en) * 2001-10-29 2004-03-18 Macy William W. Method and apparatus for shuffling data
US7343389B2 (en) 2002-05-02 2008-03-11 Intel Corporation Apparatus and method for SIMD modular multiplication
US9557994B2 (en) * 2004-07-13 2017-01-31 Arm Limited Data processing apparatus and method for performing N-way interleaving and de-interleaving operations where N is an odd plural number
US7761694B2 (en) * 2006-06-30 2010-07-20 Intel Corporation Execution unit for performing shuffle and other operations
GB2444744B (en) 2006-12-12 2011-05-25 Advanced Risc Mach Ltd Apparatus and method for performing re-arrangement operations on data
US8078836B2 (en) 2007-12-30 2011-12-13 Intel Corporation Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits
CN103959240B (zh) * 2011-12-15 2017-05-17 英特尔公司 使用混洗表和掩码存储表经由矢量指令优化程序循环的方法
CN104185837B (zh) * 2011-12-23 2017-10-13 英特尔公司 在不同的粒度等级下广播数据值的指令执行单元
US9218182B2 (en) 2012-06-29 2015-12-22 Intel Corporation Systems, apparatuses, and methods for performing a shuffle and operation (shuffle-op)
US9342479B2 (en) 2012-08-23 2016-05-17 Qualcomm Incorporated Systems and methods of data extraction in a vector processor
US20140149480A1 (en) 2012-11-28 2014-05-29 Nvidia Corporation System, method, and computer program product for transposing a matrix
US9823924B2 (en) * 2013-01-23 2017-11-21 International Business Machines Corporation Vector element rotate and insert under mask instruction
US9405539B2 (en) 2013-07-31 2016-08-02 Intel Corporation Providing vector sub-byte decompression functionality

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