JP2019521445A - Ｓｉｍｄアーキテクチャにおけるレーンのシャッフルのためのシャッフラー回路 - Google Patents

Ｓｉｍｄアーキテクチャにおけるレーンのシャッフルのためのシャッフラー回路 Download PDF

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JP2019521445A
JP2019521445A JP2019500593A JP2019500593A JP2019521445A JP 2019521445 A JP2019521445 A JP 2019521445A JP 2019500593 A JP2019500593 A JP 2019500593A JP 2019500593 A JP2019500593 A JP 2019500593A JP 2019521445 A JP2019521445 A JP 2019521445A
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processing
data
lane
lanes
processing lanes
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JP2019521445A5 (enExample
Inventor
リアン・ハン
シアンドン・ジン
リン・チェン
ユン・ドゥ
アレクセイ・ヴラディミロヴィチ・ボード
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4013—Coupling between buses with data restructuring with data re-ordering, e.g. Endian conversion
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
  • Executing Machine-Instructions (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2019500593A 2016-07-13 2017-05-19 Ｓｉｍｄアーキテクチャにおけるレーンのシャッフルのためのシャッフラー回路 Pending JP2019521445A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/209,057 2016-07-13
US15/209,057 US10592468B2 (en) 2016-07-13 2016-07-13 Shuffler circuit for lane shuffle in SIMD architecture
PCT/US2017/033663 WO2018013219A1 (en) 2016-07-13 2017-05-19 Shuffler circuit for lane shuffle in simd architecture

Publications (2)

Publication Number Publication Date
JP2019521445A true JP2019521445A (ja) 2019-07-25
JP2019521445A5 JP2019521445A5 (enExample) 2020-06-18

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JP2019500593A Pending JP2019521445A (ja) 2016-07-13 2017-05-19 Ｓｉｍｄアーキテクチャにおけるレーンのシャッフルのためのシャッフラー回路

Country Status (6)

Country Link
US (1) US10592468B2 (enExample)
EP (1) EP3485385B1 (enExample)
JP (1) JP2019521445A (enExample)
KR (1) KR102118836B1 (enExample)
CN (1) CN109478175B (enExample)
WO (1) WO2018013219A1 (enExample)

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US10957095B2 (en) * 2018-08-06 2021-03-23 Intel Corporation Programmable ray tracing with hardware acceleration on a graphics processor
US10963300B2 (en) * 2018-12-06 2021-03-30 Raytheon Company Accelerating dataflow signal processing applications across heterogeneous CPU/GPU systems
US11397624B2 (en) * 2019-01-22 2022-07-26 Arm Limited Execution of cross-lane operations in data processing systems
US11294672B2 (en) * 2019-08-22 2022-04-05 Apple Inc. Routing circuitry for permutation of single-instruction multiple-data operands
US11256518B2 (en) 2019-10-09 2022-02-22 Apple Inc. Datapath circuitry for math operations using SIMD pipelines
US20210349717A1 (en) * 2020-05-05 2021-11-11 Intel Corporation Compaction of diverged lanes for efficient use of alus
US20220197649A1 (en) * 2020-12-22 2022-06-23 Advanced Micro Devices, Inc. General purpose register hierarchy system and method
US11360897B1 (en) * 2021-04-15 2022-06-14 Qualcomm Incorporated Adaptive memory access management
CN115793958A (zh) * 2021-09-10 2023-03-14 腾讯科技（深圳）有限公司 一种混洗数据的处理方法、相关装置、设备以及存储介质
CN115061731B (zh) * 2022-06-23 2023-05-23 摩尔线程智能科技(北京)有限责任公司 混洗电路和方法、以及芯片和集成电路装置

Citations (5)

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JP2007526536A (ja) * 2003-06-30 2007-09-13 インテル コーポレイション データをシャッフルするための方法及び装置
US20090172358A1 (en) * 2007-12-30 2009-07-02 Zeev Sperber In-lane vector shuffle instructions
US20130339664A1 (en) * 2011-12-23 2013-12-19 Elmoustapha Ould-Ahmed-Vall Instruction execution unit that broadcasts data values at different levels of granularity
US20140059323A1 (en) * 2012-08-23 2014-02-27 Qualcomm Incorporated Systems and methods of data extraction in a vector processor
JP2016510461A (ja) * 2013-01-23 2016-04-07 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ Ｖｅｃｔｏｒｅｌｅｍｅｎｔｒｏｔａｔｅａｎｄｉｎｓｅｒｔｕｎｄｅｒｍａｓｋ命令を処理するためのコンピュータ・プログラム、コンピュータ・システム及び方法

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CA2078912A1 (en) * 1992-01-07 1993-07-08 Robert Edward Cypher Hierarchical interconnection networks for parallel processing
US7343389B2 (en) 2002-05-02 2008-03-11 Intel Corporation Apparatus and method for SIMD modular multiplication
US9557994B2 (en) * 2004-07-13 2017-01-31 Arm Limited Data processing apparatus and method for performing N-way interleaving and de-interleaving operations where N is an odd plural number
US7761694B2 (en) * 2006-06-30 2010-07-20 Intel Corporation Execution unit for performing shuffle and other operations
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US9218182B2 (en) 2012-06-29 2015-12-22 Intel Corporation Systems, apparatuses, and methods for performing a shuffle and operation (shuffle-op)
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Publication number Priority date Publication date Assignee Title
JP2007526536A (ja) * 2003-06-30 2007-09-13 インテル コーポレイション データをシャッフルするための方法及び装置
US20090172358A1 (en) * 2007-12-30 2009-07-02 Zeev Sperber In-lane vector shuffle instructions
US20130339664A1 (en) * 2011-12-23 2013-12-19 Elmoustapha Ould-Ahmed-Vall Instruction execution unit that broadcasts data values at different levels of granularity
US20140059323A1 (en) * 2012-08-23 2014-02-27 Qualcomm Incorporated Systems and methods of data extraction in a vector processor
JP2016510461A (ja) * 2013-01-23 2016-04-07 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ Ｖｅｃｔｏｒｅｌｅｍｅｎｔｒｏｔａｔｅａｎｄｉｎｓｅｒｔｕｎｄｅｒｍａｓｋ命令を処理するためのコンピュータ・プログラム、コンピュータ・システム及び方法

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Publication number Publication date
US10592468B2 (en) 2020-03-17
KR20190028426A (ko) 2019-03-18
KR102118836B1 (ko) 2020-06-03
WO2018013219A1 (en) 2018-01-18
BR112019000120A8 (pt) 2023-01-31
BR112019000120A2 (pt) 2019-04-09
CN109478175B (zh) 2022-07-12
CN109478175A (zh) 2019-03-15
US20180018299A1 (en) 2018-01-18
EP3485385B1 (en) 2020-04-22
EP3485385A1 (en) 2019-05-22

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