JP2016520991A - 半導体ウエハをプラズマ・ダイシングするための方法及び装置 - Google Patents
半導体ウエハをプラズマ・ダイシングするための方法及び装置 Download PDFInfo
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- JP2016520991A JP2016520991A JP2016500656A JP2016500656A JP2016520991A JP 2016520991 A JP2016520991 A JP 2016520991A JP 2016500656 A JP2016500656 A JP 2016500656A JP 2016500656 A JP2016500656 A JP 2016500656A JP 2016520991 A JP2016520991 A JP 2016520991A
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
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- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S414/00—Material or article handling
- Y10S414/135—Associated with semiconductor wafer handling
- Y10S414/139—Associated with semiconductor wafer handling including wafer charging or discharging means for vacuum chamber
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Abstract
Description
1)破損及び欠けが減少する
2)切り口寸法を20ミクロンより十分小さくなるまで減少させることができる
3)ダイの数が増加したとき、処理時間が著しくは長くならない
4)より薄いウエハには、処理時間が減少する
5)ダイ・トポロジが直線的なフォーマットに限定されない。
壁を有する処理チャンバを設けるステップと、
処理チャンバの壁に隣接してプラズマ源を設けるステップと、
処理チャンバ内に加工物サポートを設けるステップと、
前記加工物サポート上に加工物を載せるステップであって、前記加工物は、サポート・フィルム、フレーム及び基板を有する、ステップと、
前記加工物の上にカバー・リングを設けるステップであって、前記カバー・リングは、少なくとも1つの穴の開いた領域を有する、ステップと、
プラズマ源を使用してプラズマを発生するステップと、
発生されたプラズマを使用して前記加工物を処理するステップとを含む。
壁を有する処理チャンバを設けるステップと、
処理チャンバの壁に隣接してプラズマ源を設けるステップと、
処理チャンバ内に加工物サポートを設けるステップと、
前記加工物サポート上に加工物を載せるステップであって、前記加工物は、サポート・フィルム、フレーム及び基板を有する、ステップと、
前記加工物の上にカバー・リングを設けるステップであって、前記カバー・リングは、少なくとも1つの穴の開いた領域及び少なくとも1つの穴の開けられていない領域を有する、ステップと、
プラズマ源を使用してプラズマを発生するステップと、
発生されたプラズマを使用して前記加工物を処理するステップとを含む。
基板を処理するステップと、
少なくとも1つのウエハの性質(たとえば、材料のエッチング速度、選択性比率、特徴プロフィールなど)を測定するステップと、
少なくとも1つの測定された性質に基づき、機械的隔壁(690)(たとえば、隔壁間隔、隔壁から基板までの距離、隔壁厚さ及び/又は貫通穴サイズ、間隔、形状、及び/又はアスペクト比など)を調節するステップとである。別のウエハが処理され、そして必要な場合、機械的隔壁(690)が、所望のウエハ性質(1つ又は複数)を獲得するために、繰り返される。
Claims (38)
- 基板をプラズマ処理するための方法であって、
壁を有する処理チャンバを設けるステップと、
前記処理チャンバの前記壁に隣接してプラズマ源を設けるステップと、
前記処理チャンバ内に加工物サポートを設けるステップと、
前記加工物サポート上に加工物を載せるステップであって、前記加工物は、サポート・フィルム、フレーム及び前記基板を有する、ステップと、
前記加工物の上にカバー・リングを設けるステップであって、前記カバー・リングは、少なくとも1つの穴の開いた領域を有する、ステップと、
前記プラズマ源を使用してプラズマを発生するステップと、
前記発生されたプラズマを使用して前記加工物を処理するステップとを含む、方法。 - 前記カバー・リングは、開口部をさらに含む、請求項1に記載の方法。
- 前記カバー・リングは、前記基板に重ならない、請求項2に記載の方法。
- 前記カバー・リングの前記開口部は、サイズが前記基板の直径より少なくとも0.1mm大きい、請求項2に記載の方法。
- 前記カバー・リングの前記開口部は、サイズが前記基板の直径より少なくとも1mm大きい、請求項2に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、プラズマが前記基板の周囲の外側で前記加工物に接触させることが可能である、請求項1に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、前記基板に重ならない、請求項1に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、前記フィルムに重なる、請求項1に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、前記フレームに重なる、請求項1に記載の方法。
- 前記加工物サポート内に静電チャックをさらに含み、
前記静電チャックは、少なくとも1つのクランプ電極を有し、
前記クランプ電極は、前記カバー・リングの前記穴の開いた領域に重なる、請求項1に記載の方法。 - 前記静電チャックの前記クランプ電極は、前記カバー・リングの前記穴の開いた領域に完全に重なる、請求項10に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、前記加工物が前記加工物サポートと熱的に接触しているところで前記加工物の一部に重なる、請求項1に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、前記基板によって覆われた前記加工物のエリア中を除き、前記加工物に重なる、請求項12に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、前記加工物のクランプされていない部分に重ならない、請求項12に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、前記加工物の外側部分に重ならず、前記加工物の前記外側部分は、前記静電チャックの最外部の密閉バンドの外側にある、請求項12に記載の方法。
- 基板をプラズマ処理するための方法であって、
壁を有する処理チャンバを設けるステップと、
前記処理チャンバの前記壁に隣接してプラズマ源を設けるステップと、
前記処理チャンバ内に加工物サポートを設けるステップと、
前記加工物サポート上に加工物を載せるステップであって、前記加工物は、サポート・フィルム、フレーム及び前記基板を有する、ステップと、
前記加工物の上にカバー・リングを設けるステップであって、前記カバー・リングは、少なくとも1つの穴の開いた領域及び少なくとも1つの穴の開けられていない領域を有する、ステップと、
前記プラズマ源を使用してプラズマを発生するステップと、
前記発生されたプラズマを使用して前記加工物を処理するステップとを含む、方法。 - 前記カバー・リングは、開口部をさらに含む、請求項16に記載の方法。
- 前記カバー・リングは、前記基板に重ならない、請求項17に記載の方法。
- 前記カバー・リングの前記開口部は、サイズが前記基板の直径より少なくとも0.1mm大きい、請求項17に記載の方法。
- 前記カバー・リングの前記開口部は、サイズが前記基板の直径より少なくとも1mm大きい、請求項17に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、プラズマが前記加工物に接触させることが可能である、請求項16に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、前記基板に重ならない、請求項16に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、前記フィルムに重なる、請求項16に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、前記フレームに重なる、請求項16に記載の方法。
- 前記加工物サポート内に静電チャックをさらに含み、
前記静電チャックは、少なくとも1つのクランプ電極を有し、
前記クランプ電極は、前記カバー・リングの前記穴の開いた領域に重なる、請求項16に記載の方法。 - 前記静電チャックの前記クランプ電極は、前記カバー・リングの前記穴の開いた領域に完全に重なる、請求項25に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、前記加工物が前記加工物サポートと熱的に接触していないところでは前記加工物に重ならない、請求項16に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、前記加工物のクランプされていない部分に重ならない、請求項16に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、前記加工物の外側部分に重ならず、前記加工物の前記外側部分は、前記静電チャックの最外部の密閉バンドの外側にある、請求項16に記載の方法。
- 前記カバー・リングの前記穴の開けられていない領域は、プラズマが、前記カバー・リングの前記穴の開けられていない領域によって覆われた前記加工物と接触するのを防止する、請求項16に記載の方法。
- 前記カバー・リングの前記穴の開けられていない領域の一部は、前記カバー・リングの前記穴の開いた領域と同一平面上にならないように位置付けられる、請求項16に記載の方法。
- 前記カバー・リングの前記穴の開いた領域が、前記加工物から第1の距離に位置付けられるステップと、
前記カバー・リングの前記穴の開けられていない領域が、前記加工物から第2の距離に位置付けられるステップとをさらに含み、
前記第1の距離は、前記第2の距離より長い、請求項31に記載の方法。 - 前記カバー・リングの下に第1のイオン密度と、
前記基板において第2のイオン密度とをさらに含み、
前記第1のイオン密度は、前記第2のイオン密度より低い、請求項16に記載の方法。 - 前記カバー・リングの前記穴の開いた領域の下の第1のイオン密度と、
前記基板における第2のイオン密度とをさらに含み、
前記第1のイオン密度は、前記第2のイオン密度より低い、請求項16に記載の方法。 - 前記カバー・リングの前記穴の開いた領域は、イオン・フラックスが少なくとも10パーセントだけ減衰される、請求項16に記載の方法。
- 前記カバー・リングの前記穴の開いた領域は、イオン・フラックスが少なくとも30パーセントだけ減衰される、請求項16に記載の方法。
- 前記カバー・リングの前記穴の開けられていない領域の下の第1のプラズマ密度と、
前記基板における第2のプラズマ密度とをさらに含み、
前記第1のプラズマ密度は、前記第2のプラズマ密度より低い、請求項16に記載の方法。 - 前記カバー・リングの前記穴の開けられていない領域の下の前記加工物における第1のプラズマ密度と、
前記カバー・リングの前記穴の開いた領域の下の第2のプラズマ密度と、
前記基板における第3のプラズマ密度とをさらに含み、
前記第1のプラズマ密度は、前記第2のプラズマ密度より低く、
前記第2のプラズマ密度は、前記第3のプラズマ密度より低い、請求項16に記載の方法。
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JP2012164927A (ja) * | 2011-02-09 | 2012-08-30 | Toppan Printing Co Ltd | エッチング装置 |
WO2012125560A2 (en) * | 2011-03-14 | 2012-09-20 | Plasma-Therm, Llc | Method and apparatus for plasma dicing a semi-conductor wafer |
WO2012166264A2 (en) * | 2011-05-31 | 2012-12-06 | Applied Materials, Inc. | Dynamic ion radical sieve and ion radical aperture for an inductively coupled plasma (icp) reactor |
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TW201448027A (zh) | 2014-12-16 |
US20130230971A1 (en) | 2013-09-05 |
JP6320505B2 (ja) | 2018-05-09 |
CN105144352B (zh) | 2018-04-03 |
WO2014158886A1 (en) | 2014-10-02 |
TWI543255B (zh) | 2016-07-21 |
EP2973668A1 (en) | 2016-01-20 |
CN105144352A (zh) | 2015-12-09 |
US8691702B2 (en) | 2014-04-08 |
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