JP2016514906A - フィンベースのトランジスタアーキテクチャ上のプレーナデバイス - Google Patents
フィンベースのトランジスタアーキテクチャ上のプレーナデバイス Download PDFInfo
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
Description
[概要]
[方法論およびアーキテクチャ]
[例示システム]
[さらなる複数の例示的実施形態]
上記複数のフィンの第1のセットおよび上記分離層によって提供されるトポグラフィの上方に形成される第1のトランジスタデバイスと、上記複数のフィンの第2のセットおよび上記分離層によって提供されるトポグラフィの上方に形成される第2のトランジスタデバイスと、を備えるトランジスタアーキテクチャであって、上記複数のフィンは、上記半導体基板から形成されており、上記分離層は、上記複数のフィンの高さ未満の厚みを有し、上記第1のトランジスタデバイスは、上記複数のフィンの第1のセットの上方に形成される半導体層と、上記半導体層の上記平坦な面の上方に形成されるゲート本体と、を含み、上記半導体層は平坦な面を含み、上記複数のフィンの第1のセットをマージする、トランジスタアーキテクチャである。
Claims (25)
- 半導体基板の面から延在する複数のフィンとともにパターニングされた半導体基板と、
前記半導体基板の上方に形成される分離層と、
前記複数のフィンの第1のサブセットの上方に形成され、平坦な面を有する半導体本体と、
前記半導体本体の前記平坦な面の上方に形成される第1のゲート本体と、を備える集積回路であって、
前記分離層は、前記複数のフィンの高さ未満の厚みを有し、
前記半導体本体は、複数のフィンの前記第1のサブセットをマージする、集積回路。 - 前記複数のフィンは、前記半導体基板から形成される、請求項1に記載の集積回路。
- 前記半導体基板および前記複数のフィンは、複数の異なる層である、請求項1に記載の集積回路。
- 前記半導体本体は、シリコン(Si)、シリコンゲルマニウム(SiGe)、および炭化ケイ素(SiC)のうちの少なくとも1つを含む、請求項1に記載の集積回路。
- 前記半導体本体は、エピタキシャルシリコン(Si)を含む、請求項1に記載の集積回路。
- 前記複数のフィンの第2のサブセットの上方に形成される第2のゲート本体をさらに備えており、
複数のフィンの前記第1のサブセットおよび前記第2のサブセットは、互いに隣接しており、
前記第1のゲート本体および前記第2のゲート本体は、互いに電気的に分離されている、請求項1に記載の集積回路。 - 当該集積回路は、約100〜200nmの範囲内のZ幅を有する、請求項1に記載の集積回路。
- 当該集積回路は、約200〜300nmの範囲内のZ幅を有する、請求項1に記載の集積回路。
- 当該集積回路は、プレーナ型金属酸化物半導体電界効果トランジスタ(MOSFET)を備える、請求項1から8のいずれか一項に記載の集積回路。
- 集積回路を形成する方法であって、
半導体基板の面から延在する複数のフィンとともにパターニングされた半導体基板の上方に分離層を形成する段階と、
平坦な面を有する半導体層を前記複数のフィンの第1のサブセットの上方に形成する段階と、
前記半導体層の前記平坦な面の上方に第1のゲート本体を形成する段階と、を備え、
前記分離層は、前記複数のフィンの高さ未満の厚みを有し、
前記半導体層は、複数のフィンの前記第1のサブセットをマージする、方法。 - 前記半導体基板の上方に前記分離層を形成する段階は、
前記半導体基板の上方に前記分離層を堆積する段階と、
前記分離層の厚みを前記複数のフィンの高さまで減少すべく、前記分離層を平坦化する段階と、
前記分離層の厚みを前記複数のフィンの高さ未満に減少すべく、前記分離層をエッチングする段階と、を含む、請求項10に記載の方法。 - 複数のフィンの前記第1のサブセットの上方に前記半導体層を形成する段階は、
化学気相成長(CVD)プロセス、有機金属気相成長(MOVPE)プロセス、分子線エピタキシ(MBE)プロセス、原子層堆積(ALD)プロセス、およびそれら任意の組み合わせのうちの少なくとも1つを使用する段階を含む、請求項10に記載の方法。 - 複数のフィンの前記第1のサブセットの上方に前記半導体層を形成する段階は、
複数のフィンの前記第1のサブセットの上方に前記半導体層を堆積する段階と、
前記平坦な面を提供すべく、前記半導体層を平坦化する段階と、を含む、請求項10に記載の方法。 - 前記半導体層を平坦化する段階は、化学機械的平面化(CMP)プロセス、エッチバックプロセス、およびそれら任意の組み合わせのうちの少なくとも1つを使用する段階を含む、請求項13に記載の方法。
- 複数のフィンの前記第1のサブセットの上方に前記半導体層を堆積する段階の前に、複数のフィンの前記第1のサブセットの上方に前記半導体層を形成する段階はさらに、
複数のフィンの第2のサブセットの上方に遮断層を形成する段階を含み、
前記遮断層は、複数のフィンの前記第1のサブセットの上方に前記半導体層を堆積する段階において、複数のフィンの前記第2のサブセットを保護する、請求項13に記載の方法。 - 前記遮断層は、二酸化ケイ素(SiO2)、窒化シリコン(Si3N4)、およびレジスト材料のうちの少なくとも1つを含む、請求項15に記載の方法。
- 複数のフィンの前記第2のサブセットの上方に前記遮断層を形成する段階は、
前記分離層および前記複数のフィンによって提供されるトポグラフィの上方に前記遮断層を堆積する段階と、
複数のフィンの前記第1のサブセットを覆うところの前記遮断層を除去する段階と、を含む、請求項15に記載の方法。 - 前記複数のフィンの第2のサブセットの上方に第2のゲート本体を形成する段階をさらに備え、
複数のフィンの前記第1のサブセットおよび前記第2のサブセットは、互いに隣接しており、
前記第1のゲート本体および前記第2のゲート本体は、互いに電気的に分離されている、請求項10に記載の方法。 - 前記第1のゲート本体および前記第2のゲート本体は同時に形成される、請求項18に記載の方法。
- 請求項10から19のいずれか一項に記載の方法によって形成される、集積回路。
- 請求項1から9のいずれか一項に記載の集積回路を備える、システムオンチップ(SOC)。
- 半導体基板の面から延在する複数のフィンの第1のセットと第2のセットとを有する半導体基板と、
前記半導体基板の上方に形成される分離層と、
複数のフィンの前記第1のセットおよび前記分離層によって提供されるトポグラフィの上方に形成される第1のトランジスタデバイスと、
複数のフィンの前記第2のセットおよび前記分離層によって提供されるトポグラフィの上方に形成される第2のトランジスタデバイスと、を備え、
前記複数のフィンは、前記半導体基板から形成されており、
前記分離層は、前記複数のフィンの高さ未満の厚みを有し、
前記第1のトランジスタデバイスは、
平坦な面を含み、複数のフィンの前記第1のセットの上方に形成される半導体層と、
前記半導体層の前記平坦な面の上方に形成されるゲート本体と、を含み、
前記半導体層は、複数のフィンの前記第1のセットをマージする、トランジスタアーキテクチャ。 - 前記第1のトランジスタデバイスは、約100〜300nmの範囲内のZ幅を有する、請求項22に記載のトランジスタアーキテクチャ。
- 前記第2のトランジスタデバイスは、フィンベースの電界効果トランジスタ(finFET)を含む、請求項22または23に記載のトランジスタアーキテクチャ。
- 前記第2のトランジスタデバイスは、トライゲート金属酸化物半導体電界効果トランジスタ(MOSFET)を含む、請求項22または23に記載のトランジスタアーキテクチャ。
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PCT/US2013/034729 WO2014163603A1 (en) | 2013-03-30 | 2013-03-30 | Planar device on fin-based transistor architecture |
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US (2) | US9356023B2 (ja) |
JP (1) | JP6224818B2 (ja) |
KR (1) | KR102126771B1 (ja) |
CN (2) | CN105009294B (ja) |
DE (1) | DE112013006645B4 (ja) |
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US9391065B1 (en) | 2015-06-29 | 2016-07-12 | Globalfoundries Inc. | Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode |
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US9570555B1 (en) * | 2015-10-29 | 2017-02-14 | International Business Machines Corporation | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices |
EP3182461B1 (en) * | 2015-12-16 | 2022-08-03 | IMEC vzw | Method for fabricating finfet technology with locally higher fin-to-fin pitch |
US9786505B2 (en) * | 2015-12-30 | 2017-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device using dummy fins for smooth profiling |
US10522365B2 (en) * | 2016-01-27 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for reducing scratch defects in chemical mechanical planarization |
US10644156B2 (en) * | 2018-03-12 | 2020-05-05 | Globalfoundries Inc. | Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices |
US11069693B2 (en) * | 2018-08-28 | 2021-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for improving control gate uniformity during manufacture of processors with embedded flash memory |
KR20220019197A (ko) | 2020-08-07 | 2022-02-16 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
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US10115721B2 (en) | 2018-10-30 |
TWI610443B (zh) | 2018-01-01 |
CN110098186B (zh) | 2023-08-04 |
WO2014163603A1 (en) | 2014-10-09 |
TWI552350B (zh) | 2016-10-01 |
KR20150136060A (ko) | 2015-12-04 |
TW201507158A (zh) | 2015-02-16 |
GB2526959A8 (en) | 2016-03-16 |
CN105009294A (zh) | 2015-10-28 |
CN110098186A (zh) | 2019-08-06 |
US20140291766A1 (en) | 2014-10-02 |
TW201639168A (zh) | 2016-11-01 |
KR102126771B1 (ko) | 2020-06-26 |
US9356023B2 (en) | 2016-05-31 |
GB201514055D0 (en) | 2015-09-23 |
GB2526959B (en) | 2018-10-24 |
GB2526959A (en) | 2015-12-09 |
DE112013006645T5 (de) | 2015-11-19 |
DE112013006645B4 (de) | 2020-12-03 |
CN105009294B (zh) | 2018-12-25 |
JP6224818B2 (ja) | 2017-11-01 |
US20160276346A1 (en) | 2016-09-22 |
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