JP2016509280A5 - - Google Patents

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Publication number
JP2016509280A5
JP2016509280A5 JP2015549407A JP2015549407A JP2016509280A5 JP 2016509280 A5 JP2016509280 A5 JP 2016509280A5 JP 2015549407 A JP2015549407 A JP 2015549407A JP 2015549407 A JP2015549407 A JP 2015549407A JP 2016509280 A5 JP2016509280 A5 JP 2016509280A5
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JP
Japan
Prior art keywords
memory transfer
transfer mode
transfer operation
memory
gpu
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JP2015549407A
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English (en)
Japanese (ja)
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JP2016509280A (ja
JP6009692B2 (ja
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Priority claimed from US13/725,393 external-priority patent/US9245496B2/en
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Publication of JP2016509280A5 publication Critical patent/JP2016509280A5/ja
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Publication of JP6009692B2 publication Critical patent/JP6009692B2/ja
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JP2015549407A 2012-12-21 2013-11-21 グラフィックスプロセッシングユニットベースのメモリ転送動作を行うためのマルチモードメモリアクセス技法 Active JP6009692B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/725,393 US9245496B2 (en) 2012-12-21 2012-12-21 Multi-mode memory access techniques for performing graphics processing unit-based memory transfer operations
US13/725,393 2012-12-21
PCT/US2013/071283 WO2014099249A1 (en) 2012-12-21 2013-11-21 Multi-mode memory access techniques for performing graphics processing unit-based memory transfer operations

Publications (3)

Publication Number Publication Date
JP2016509280A JP2016509280A (ja) 2016-03-24
JP2016509280A5 true JP2016509280A5 (enExample) 2016-05-12
JP6009692B2 JP6009692B2 (ja) 2016-10-19

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JP2015549407A Active JP6009692B2 (ja) 2012-12-21 2013-11-21 グラフィックスプロセッシングユニットベースのメモリ転送動作を行うためのマルチモードメモリアクセス技法

Country Status (7)

Country Link
US (1) US9245496B2 (enExample)
EP (1) EP2936492B1 (enExample)
JP (1) JP6009692B2 (enExample)
KR (1) KR101667508B1 (enExample)
CN (1) CN104871246B (enExample)
ES (1) ES2907227T3 (enExample)
WO (1) WO2014099249A1 (enExample)

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US10310860B2 (en) * 2016-07-29 2019-06-04 International Business Machines Corporation Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor
US10175905B2 (en) * 2016-09-13 2019-01-08 Apple Inc. Systems and methods for dynamically switching memory performance states
KR102022481B1 (ko) * 2017-12-06 2019-09-18 연세대학교 산학협력단 Gpu 사용량을 이용한 고성능 컴퓨팅 시스템의 체크포인트 생성 방법
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KR102520412B1 (ko) * 2018-09-19 2023-04-12 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작방법
US10642764B1 (en) * 2019-03-01 2020-05-05 Western Digital Technologies, Inc. Data transfer command latency of a host device
US20220129198A1 (en) * 2019-07-12 2022-04-28 Hewlett-Packard Development Company, L.P. Data updates for controllers
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US11843772B2 (en) 2019-12-06 2023-12-12 Ati Technologies Ulc Video encode pre-analysis bit budgeting based on context and features
WO2021120132A1 (zh) * 2019-12-19 2021-06-24 华为技术有限公司 一种存储系统及数据交叉方法
JP7334358B2 (ja) * 2020-02-03 2023-08-28 株式会社ソニー・インタラクティブエンタテインメント レンダリング前にインターリーブスクリーン領域に対して事前テストを行うことによってジオメトリの効率的なマルチgpuレンダリングを行うシステム及び方法
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KR102641532B1 (ko) * 2022-10-20 2024-02-28 (주)한국플랫폼서비스기술 사생활 보호 딥러닝 프레임워크 응용 컴퓨팅 장치 및 그 방법
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