KR101667508B1 - 그래픽 프로세싱 유닛 기반 메모리 전송 동작들을 수행하는 다중모드 메모리 액세스 기법들 - Google Patents

그래픽 프로세싱 유닛 기반 메모리 전송 동작들을 수행하는 다중모드 메모리 액세스 기법들 Download PDF

Info

Publication number
KR101667508B1
KR101667508B1 KR1020157018907A KR20157018907A KR101667508B1 KR 101667508 B1 KR101667508 B1 KR 101667508B1 KR 1020157018907 A KR1020157018907 A KR 1020157018907A KR 20157018907 A KR20157018907 A KR 20157018907A KR 101667508 B1 KR101667508 B1 KR 101667508B1
Authority
KR
South Korea
Prior art keywords
memory transfer
transfer mode
memory
gpu
transfer operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020157018907A
Other languages
English (en)
Korean (ko)
Other versions
KR20150099781A (ko
Inventor
앤드류 에반 그루버
타오 왕
샴부 칸델왈
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20150099781A publication Critical patent/KR20150099781A/ko
Application granted granted Critical
Publication of KR101667508B1 publication Critical patent/KR101667508B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/455—Image or video data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Memory System (AREA)
  • Image Generation (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)
KR1020157018907A 2012-12-21 2013-11-21 그래픽 프로세싱 유닛 기반 메모리 전송 동작들을 수행하는 다중모드 메모리 액세스 기법들 Active KR101667508B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/725,393 US9245496B2 (en) 2012-12-21 2012-12-21 Multi-mode memory access techniques for performing graphics processing unit-based memory transfer operations
US13/725,393 2012-12-21
PCT/US2013/071283 WO2014099249A1 (en) 2012-12-21 2013-11-21 Multi-mode memory access techniques for performing graphics processing unit-based memory transfer operations

Publications (2)

Publication Number Publication Date
KR20150099781A KR20150099781A (ko) 2015-09-01
KR101667508B1 true KR101667508B1 (ko) 2016-10-18

Family

ID=49759568

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020157018907A Active KR101667508B1 (ko) 2012-12-21 2013-11-21 그래픽 프로세싱 유닛 기반 메모리 전송 동작들을 수행하는 다중모드 메모리 액세스 기법들

Country Status (7)

Country Link
US (1) US9245496B2 (enExample)
EP (1) EP2936492B1 (enExample)
JP (1) JP6009692B2 (enExample)
KR (1) KR101667508B1 (enExample)
CN (1) CN104871246B (enExample)
ES (1) ES2907227T3 (enExample)
WO (1) WO2014099249A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190066712A (ko) * 2017-12-06 2019-06-14 연세대학교 산학협력단 Gpu 사용량을 이용한 고성능 컴퓨팅 시스템의 체크포인트 생성 방법

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11243816B2 (en) * 2014-03-30 2022-02-08 UniversiteitGent Program execution on heterogeneous platform
JP6412708B2 (ja) * 2014-04-01 2018-10-24 株式会社ソニー・インタラクティブエンタテインメント プロセッシングシステムおよびマルチプロセッシングシステム
US10417990B2 (en) * 2014-10-16 2019-09-17 Nvidia Corporation Efficient binding of resource groups in a graphics application programming interface
US9818170B2 (en) * 2014-12-10 2017-11-14 Qualcomm Incorporated Processing unaligned block transfer operations
WO2016167807A1 (en) 2015-04-17 2016-10-20 Hewlett-Packard Development Company, L.P. Memory mode categorizations
US10163180B2 (en) 2015-04-29 2018-12-25 Qualcomm Incorporated Adaptive memory address scanning based on surface format for graphics processing
US9947277B2 (en) * 2015-05-20 2018-04-17 Apple Inc. Devices and methods for operating a timing controller of a display
WO2017049583A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Gpu-cpu two-path memory copy
US9864705B2 (en) 2015-11-01 2018-01-09 International Business Machines Corporation Dynamic access method switching for open data sets
US10034407B2 (en) * 2016-07-22 2018-07-24 Intel Corporation Storage sled for a data center
US10310860B2 (en) * 2016-07-29 2019-06-04 International Business Machines Corporation Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor
US10175905B2 (en) * 2016-09-13 2019-01-08 Apple Inc. Systems and methods for dynamically switching memory performance states
US10430915B2 (en) * 2017-12-28 2019-10-01 Nvidia Corporation Multi-GPU frame rendering
US11252429B2 (en) * 2018-04-27 2022-02-15 Ati Technologies Ulc Low-latency consumption of an encoded video bitstream
US10877906B2 (en) * 2018-09-17 2020-12-29 Micron Technology, Inc. Scheduling of read operations and write operations based on a data bus mode
KR102520412B1 (ko) * 2018-09-19 2023-04-12 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작방법
US10642764B1 (en) * 2019-03-01 2020-05-05 Western Digital Technologies, Inc. Data transfer command latency of a host device
US20220129198A1 (en) * 2019-07-12 2022-04-28 Hewlett-Packard Development Company, L.P. Data updates for controllers
US11237873B2 (en) * 2019-08-29 2022-02-01 Microsoft Technology Licensing, Llc Hardware acceleration for function processing
US11843772B2 (en) 2019-12-06 2023-12-12 Ati Technologies Ulc Video encode pre-analysis bit budgeting based on context and features
CN114651243B (zh) * 2019-12-19 2025-12-12 华为技术有限公司 一种存储系统及数据交叉方法
WO2021158483A1 (en) * 2020-02-03 2021-08-12 Song Interactive Entertainment Inc. System and method for efficient multi-gpu rendering of geometry by pretesting against interleaved screen regions before rendering
US11960404B2 (en) * 2020-09-23 2024-04-16 Advanced Micro Devices, Inc. Method and apparatus for reducing the latency of long latency memory requests
KR102641532B1 (ko) * 2022-10-20 2024-02-28 (주)한국플랫폼서비스기술 사생활 보호 딥러닝 프레임워크 응용 컴퓨팅 장치 및 그 방법
US12314585B2 (en) * 2023-06-05 2025-05-27 SanDisk Technologies, Inc. Multi-tenant device read command service balancing

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1191445A2 (en) 2000-09-20 2002-03-27 Broadcom Corporation Memory controller with programmable configuration
US7580042B2 (en) 2005-08-09 2009-08-25 Samsung Electronics Co., Ltd. Systems and methods for storing and fetching texture data using bank interleaving
US20130179645A1 (en) 2012-01-06 2013-07-11 International Business Machines Corporation Equalizing bandwidth for multiple requesters using a shared memory system

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396597A (en) 1992-04-03 1995-03-07 International Business Machines Corporation System for transferring data between processors via dual buffers within system memory with first and second processors accessing system memory directly and indirectly
US5948081A (en) 1997-12-22 1999-09-07 Compaq Computer Corporation System for flushing queued memory write request corresponding to a queued read request and all prior write requests with counter indicating requests to be flushed
US6756986B1 (en) 1999-10-18 2004-06-29 S3 Graphics Co., Ltd. Non-flushing atomic operation in a burst mode transfer data storage access environment
US6564304B1 (en) 2000-09-01 2003-05-13 Ati Technologies Inc. Memory processing system and method for accessing memory including reordering memory requests to reduce mode switching
US6819327B2 (en) 2001-05-18 2004-11-16 Sun Microsystems, Inc. Signature analysis registers for testing a computer graphics system
JP2003323339A (ja) * 2002-03-01 2003-11-14 Sony Computer Entertainment Inc メモリアクセス装置、半導体デバイス、メモリアクセス制御方法、コンピュータプログラム及び記録媒体
US8035647B1 (en) 2006-08-24 2011-10-11 Nvidia Corporation Raster operations unit with interleaving of read and write requests using PCI express
US8327092B2 (en) 2009-09-21 2012-12-04 Freescale Semiconductor, Inc. Memory device configurable as interleaved or non-interleaved memory
KR101639574B1 (ko) * 2009-12-30 2016-07-14 삼성전자주식회사 적응적 뱅크 어드레스를 제공하는 디스플레이 시스템 및 그것의 어드레스 맵핑 방법
JP5678273B2 (ja) * 2010-03-01 2015-02-25 パナソニックＩｐマネジメント株式会社 メモリコントローラ
KR101620460B1 (ko) * 2010-05-04 2016-05-13 삼성전자주식회사 인터커넥트, 그것을 포함하는 버스 시스템 그리고 버스 시스템의 동작 방법
US9465728B2 (en) * 2010-11-03 2016-10-11 Nvidia Corporation Memory controller adaptable to multiple memory devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1191445A2 (en) 2000-09-20 2002-03-27 Broadcom Corporation Memory controller with programmable configuration
US7580042B2 (en) 2005-08-09 2009-08-25 Samsung Electronics Co., Ltd. Systems and methods for storing and fetching texture data using bank interleaving
US20130179645A1 (en) 2012-01-06 2013-07-11 International Business Machines Corporation Equalizing bandwidth for multiple requesters using a shared memory system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190066712A (ko) * 2017-12-06 2019-06-14 연세대학교 산학협력단 Gpu 사용량을 이용한 고성능 컴퓨팅 시스템의 체크포인트 생성 방법
KR102022481B1 (ko) 2017-12-06 2019-09-18 연세대학교 산학협력단 Gpu 사용량을 이용한 고성능 컴퓨팅 시스템의 체크포인트 생성 방법

Also Published As

Publication number Publication date
KR20150099781A (ko) 2015-09-01
EP2936492A1 (en) 2015-10-28
WO2014099249A1 (en) 2014-06-26
US20140176586A1 (en) 2014-06-26
US9245496B2 (en) 2016-01-26
ES2907227T3 (es) 2022-04-22
JP2016509280A (ja) 2016-03-24
EP2936492B1 (en) 2022-01-26
JP6009692B2 (ja) 2016-10-19
CN104871246A (zh) 2015-08-26
CN104871246B (zh) 2017-09-29

Similar Documents

Publication Publication Date Title
KR101667508B1 (ko) 그래픽 프로세싱 유닛 기반 메모리 전송 동작들을 수행하는 다중모드 메모리 액세스 기법들
US9449410B2 (en) Intra-frame timestamps for tile-based rendering
CN108463804B (zh) 自适应上下文切换
US9818170B2 (en) Processing unaligned block transfer operations
CN106575442B (zh) 使用通过自适应着色的纹理查找的带宽缩减
EP3357034B1 (en) Graphics processing unit preemption with pixel tile level granularity
US12444119B2 (en) Rasterization of compute workloads
US20200258187A1 (en) Parallel data transfer to increase bandwidth for accelerated processing devices

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
A302 Request for accelerated examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PA0302 Request for accelerated examination

St.27 status event code: A-1-2-D10-D17-exm-PA0302

St.27 status event code: A-1-2-D10-D16-exm-PA0302

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

U11 Full renewal or maintenance fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-OTH-PR1001 (AS PROVIDED BY THE NATIONAL OFFICE)

Year of fee payment: 10