JP6009692B2 - グラフィックスプロセッシングユニットベースのメモリ転送動作を行うためのマルチモードメモリアクセス技法 - Google Patents

グラフィックスプロセッシングユニットベースのメモリ転送動作を行うためのマルチモードメモリアクセス技法 Download PDF

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JP6009692B2
JP6009692B2 JP2015549407A JP2015549407A JP6009692B2 JP 6009692 B2 JP6009692 B2 JP 6009692B2 JP 2015549407 A JP2015549407 A JP 2015549407A JP 2015549407 A JP2015549407 A JP 2015549407A JP 6009692 B2 JP6009692 B2 JP 6009692B2
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memory transfer
transfer mode
memory
gpu
transfer operation
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JP2016509280A (ja
JP2016509280A5 (enExample
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グルバー、アンドリュー・イバン
ワン、タオ
カーンデルワル、シャンブー
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/455—Image or video data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Memory System (AREA)
  • Image Generation (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)
JP2015549407A 2012-12-21 2013-11-21 グラフィックスプロセッシングユニットベースのメモリ転送動作を行うためのマルチモードメモリアクセス技法 Active JP6009692B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/725,393 US9245496B2 (en) 2012-12-21 2012-12-21 Multi-mode memory access techniques for performing graphics processing unit-based memory transfer operations
US13/725,393 2012-12-21
PCT/US2013/071283 WO2014099249A1 (en) 2012-12-21 2013-11-21 Multi-mode memory access techniques for performing graphics processing unit-based memory transfer operations

Publications (3)

Publication Number Publication Date
JP2016509280A JP2016509280A (ja) 2016-03-24
JP2016509280A5 JP2016509280A5 (enExample) 2016-05-12
JP6009692B2 true JP6009692B2 (ja) 2016-10-19

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JP2015549407A Active JP6009692B2 (ja) 2012-12-21 2013-11-21 グラフィックスプロセッシングユニットベースのメモリ転送動作を行うためのマルチモードメモリアクセス技法

Country Status (7)

Country Link
US (1) US9245496B2 (enExample)
EP (1) EP2936492B1 (enExample)
JP (1) JP6009692B2 (enExample)
KR (1) KR101667508B1 (enExample)
CN (1) CN104871246B (enExample)
ES (1) ES2907227T3 (enExample)
WO (1) WO2014099249A1 (enExample)

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WO2017049583A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Gpu-cpu two-path memory copy
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US10091904B2 (en) * 2016-07-22 2018-10-02 Intel Corporation Storage sled for data center
US10310860B2 (en) * 2016-07-29 2019-06-04 International Business Machines Corporation Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor
US10175905B2 (en) * 2016-09-13 2019-01-08 Apple Inc. Systems and methods for dynamically switching memory performance states
KR102022481B1 (ko) * 2017-12-06 2019-09-18 연세대학교 산학협력단 Gpu 사용량을 이용한 고성능 컴퓨팅 시스템의 체크포인트 생성 방법
US10430915B2 (en) * 2017-12-28 2019-10-01 Nvidia Corporation Multi-GPU frame rendering
US11252429B2 (en) * 2018-04-27 2022-02-15 Ati Technologies Ulc Low-latency consumption of an encoded video bitstream
US10877906B2 (en) * 2018-09-17 2020-12-29 Micron Technology, Inc. Scheduling of read operations and write operations based on a data bus mode
KR102520412B1 (ko) * 2018-09-19 2023-04-12 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작방법
US10642764B1 (en) * 2019-03-01 2020-05-05 Western Digital Technologies, Inc. Data transfer command latency of a host device
US20220129198A1 (en) * 2019-07-12 2022-04-28 Hewlett-Packard Development Company, L.P. Data updates for controllers
US11237873B2 (en) 2019-08-29 2022-02-01 Microsoft Technology Licensing, Llc Hardware acceleration for function processing
US11843772B2 (en) 2019-12-06 2023-12-12 Ati Technologies Ulc Video encode pre-analysis bit budgeting based on context and features
WO2021120132A1 (zh) * 2019-12-19 2021-06-24 华为技术有限公司 一种存储系统及数据交叉方法
JP7334358B2 (ja) * 2020-02-03 2023-08-28 株式会社ソニー・インタラクティブエンタテインメント レンダリング前にインターリーブスクリーン領域に対して事前テストを行うことによってジオメトリの効率的なマルチｇｐｕレンダリングを行うシステム及び方法
US11960404B2 (en) * 2020-09-23 2024-04-16 Advanced Micro Devices, Inc. Method and apparatus for reducing the latency of long latency memory requests
KR102641532B1 (ko) * 2022-10-20 2024-02-28 (주)한국플랫폼서비스기술 사생활 보호 딥러닝 프레임워크 응용 컴퓨팅 장치 및 그 방법
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Also Published As

Publication number Publication date
ES2907227T3 (es) 2022-04-22
WO2014099249A1 (en) 2014-06-26
JP2016509280A (ja) 2016-03-24
US9245496B2 (en) 2016-01-26
CN104871246A (zh) 2015-08-26
KR101667508B1 (ko) 2016-10-18
KR20150099781A (ko) 2015-09-01
EP2936492B1 (en) 2022-01-26
EP2936492A1 (en) 2015-10-28
CN104871246B (zh) 2017-09-29
US20140176586A1 (en) 2014-06-26

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