JP2016505971A5 - - Google Patents

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Publication number
JP2016505971A5
JP2016505971A5 JP2015549790A JP2015549790A JP2016505971A5 JP 2016505971 A5 JP2016505971 A5 JP 2016505971A5 JP 2015549790 A JP2015549790 A JP 2015549790A JP 2015549790 A JP2015549790 A JP 2015549790A JP 2016505971 A5 JP2016505971 A5 JP 2016505971A5
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JP
Japan
Prior art keywords
prediction mask
value
bitway
line
prediction
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JP2015549790A
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English (en)
Japanese (ja)
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JP2016505971A (ja
JP6212133B2 (ja
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Priority claimed from US13/721,317 external-priority patent/US9304932B2/en
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Publication of JP2016505971A publication Critical patent/JP2016505971A/ja
Publication of JP2016505971A5 publication Critical patent/JP2016505971A5/ja
Application granted granted Critical
Publication of JP6212133B2 publication Critical patent/JP6212133B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2015549790A 2012-12-20 2013-12-20 マルチビットウェイ予測マスクを有する命令キャッシュ Expired - Fee Related JP6212133B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/721,317 2012-12-20
US13/721,317 US9304932B2 (en) 2012-12-20 2012-12-20 Instruction cache having a multi-bit way prediction mask
PCT/US2013/077020 WO2014100632A1 (en) 2012-12-20 2013-12-20 Instruction cache having a multi-bit way prediction mask

Publications (3)

Publication Number Publication Date
JP2016505971A JP2016505971A (ja) 2016-02-25
JP2016505971A5 true JP2016505971A5 (enExample) 2016-08-04
JP6212133B2 JP6212133B2 (ja) 2017-10-11

Family

ID=49956453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015549790A Expired - Fee Related JP6212133B2 (ja) 2012-12-20 2013-12-20 マルチビットウェイ予測マスクを有する命令キャッシュ

Country Status (5)

Country Link
US (1) US9304932B2 (enExample)
EP (1) EP2936303B1 (enExample)
JP (1) JP6212133B2 (enExample)
CN (1) CN104854557B (enExample)
WO (1) WO2014100632A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GR20150100422A (el) 2015-09-28 2017-05-15 Arm Limited Αποθηκευση δεδομενων
CN110832466B (zh) * 2017-07-14 2023-03-10 华为技术有限公司 读、部分写数据方法以及相关装置
US11620229B2 (en) 2020-02-21 2023-04-04 SiFive, Inc. Data cache with prediction hints for cache hits

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US5287467A (en) 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5604909A (en) 1993-12-15 1997-02-18 Silicon Graphics Computer Systems, Inc. Apparatus for processing instructions in a computing system
JP3589485B2 (ja) * 1994-06-07 2004-11-17 株式会社ルネサステクノロジ セットアソシアティブ方式のメモリ装置およびプロセッサ
US5848433A (en) * 1995-04-12 1998-12-08 Advanced Micro Devices Way prediction unit and a method for operating the same
US5781789A (en) * 1995-08-31 1998-07-14 Advanced Micro Devices, Inc. Superscaler microprocessor employing a parallel mask decoder
US5826071A (en) 1995-08-31 1998-10-20 Advanced Micro Devices, Inc. Parallel mask decoder and method for generating said mask
US5794028A (en) * 1996-10-17 1998-08-11 Advanced Micro Devices, Inc. Shared branch prediction structure
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US5845102A (en) * 1997-03-03 1998-12-01 Advanced Micro Devices, Inc. Determining microcode entry points and prefix bytes using a parallel logic technique
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US6016533A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Way prediction logic for cache array
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US6356990B1 (en) 2000-02-02 2002-03-12 International Business Machines Corporation Set-associative cache memory having a built-in set prediction array
US6584549B2 (en) * 2000-12-29 2003-06-24 Intel Corporation System and method for prefetching data into a cache based on miss distance
US20020194462A1 (en) * 2001-05-04 2002-12-19 Ip First Llc Apparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache line
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US20050050278A1 (en) 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. Low power way-predicted cache
JP3834323B2 (ja) 2004-04-30 2006-10-18 日本電気株式会社 キャッシュメモリおよびキャッシュ制御方法
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