JP2016209305A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of further improving various types of performance operations by terminally reducing the number of wires.SOLUTION: Performance control means 22 for controlling a lamp performance outputs serial drive signals SDATA0 and SDATA1 along with clock signals CK0 and CK1 via a serial port So. The performance control means includes: transmission means 47 that acquires a serial drive signal SDATAi and a clock signal CKi in synchronization with a sampling signal Φ, and collectively outputs the acquisition signal with other acquisition signals to a differential signal wire as composite serial signals TX+ and TX-; and reception means 60 that extract all the acquisition signals from the composite serial signals TX+ and TX- and restore the sampling signal Φ.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine that can stably execute advanced sound effects and the like.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

JP 2009-11368 A JP 2013-118974 A

  This type of gaming machine is generally divided into a frame-side member that is used for a long time and a board-side member that is changed for each model, and the board-side member is attached to the frame-side member installed in the game hall. Completed. At the time of this attaching operation, the old board-side member is removed from the frame-side member, and a new board-side member is attached. Therefore, it is necessary to insert and remove a large number of wires, and this replacement work is desired to be reduced. In general, the frame side member includes an effect lamp, an effect button, a speaker, and the like arranged in the game frame, and the board side member includes a liquid crystal display device and the like.

  By the way, in recent gaming machines, not only image effects, but also lamp effects and sound effects are desired to be advanced and rich in effect operations. In response to such requests, the board side members and the frame side members The number of wires has become enormous, and this point has become a work burden when manufacturing and replacing gaming machines. Here, it is conceivable to adopt a serial transmission method instead of parallel transmission (for example, Patent Document 1 and Patent Document 2). In addition, there was a limit in upgrading lamp production and voice production due to other and manufacturing cost relationships.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a gaming machine that can extremely reduce the number of wirings and can further enhance various performance operations.

  In order to achieve the above object, the present invention is a gaming machine that executes all or a part of an effect of an image effect, a lamp effect, or a sound effect corresponding to a lottery result of a predetermined lottery process. The production control means for controlling the production operation is configured to output a serial drive signal defining production content together with a clock signal via a serial port, and the serial drive signal and the clock signal are used as sampling signals. Synchronously acquiring every predetermined time and transmitting the acquired signal together with other acquired signals as a composite serial signal to a pair of differential signal lines; and the transmitting means through the pair of differential signal lines And receiving means for extracting all acquired signals from the composite serial signal and restoring the sampling signal.

  In the present invention, it is preferable that a plurality of serial drive signals and clock signals are output via a plurality of serial ports, and all of these are output from the transmission means as composite serial signals. In this case, a plurality of clock signals are output corresponding to a plurality of serial drive signals via a plurality of serial ports, or a common clock signal is output corresponding to a plurality of serial drive signals. Preferably it is done.

  In any case, it is preferable that the serial drive signal output from the predetermined serial port includes a serial signal that defines the drive mode of the effect motor, and the other acquired signals include an audio effect. It is preferable that an audio serial signal having a multi-bit length that defines the contents of the audio and an audio clock signal are included.

  The present invention is preferably applied to a gaming machine that is divided into a board-side member that is changed for each model and a frame-side member that can be used in common with different models. The means is arranged on the frame side member, while the receiving means is arranged to be arranged on the frame side member.

  When adopting such a configuration, it is preferable that all signals transmitted from the board-side member to the frame-side member are transmitted by the transmitting means. Moreover, it is preferable that all signals transmitted / received between the board side member and the frame side member are transmitted by a pair of differential signal lines and another one or a pair of serial signal lines.

  In any case, it is preferable that the acquired signal includes a plurality of clock signals, and the frequency of the sampling signal is set to be twice or more the highest frequency of the plurality of clock signals, more preferably 10 It should be at least twice, even more preferably at least 30 times.

  According to the gaming machine of the present invention described above, the number of wirings can be reduced and various performance operations can be further enhanced.

It is a perspective view which shows the pachinko machine of a present Example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram illustrating a circuit configuration of an effect control unit. The schematic internal configuration of the audio processor and the connection relationship with other circuits are illustrated. It is drawing explaining the structure and operation | movement of a transmitter and a receiver. It is drawing explaining the structure of a frame relay board | substrate and a lamp drive board | substrate. It is drawing explaining the structure of a sensor board | substrate. It is drawing explaining the structure of a lamp & motor drive board | substrate. It is drawing explaining a deformation | transformation structure.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, a total of five speakers (not shown) are arranged on the left and right positions and the lower side of the upper and middle portions of the glass door 6. The two speakers SPR1, SPL1, SPR2, and SPL2 arranged in the upper part and the middle part are each configured to output stereo sound of left and right channels, and the lower speaker SPD is configured to output heavy bass.

  In addition, a volume switch VSW capable of adjusting the volume of the effect sound by the player is disposed below the glass door 6. The volume switch VSW is a directional key having a + contact and a −contact on the left and right, and enables multistage volume adjustment. The operation for adjusting the volume is permitted only during the production standby in which the audio production is not executed. In response to the operation of the volume switch VSW, the confirmation production sound is output and the setting level is displayed. It is displayed on the screen.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided on the surface of the game board 5 in an annular shape, and a central opening HO is provided at the approximate center thereof. A display device DS composed of a large liquid crystal color display (LCD) is disposed in the central opening HO.

  The display device DS is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. This display device DS has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. In the special symbol display portions Da to Dc, there is a case where a reach effect that expects a big hit state is invited, and in the special symbol display portions Da to Dc and the surroundings, an appropriate notice effect is executed.

  In the game area where the game ball falls and moves, a symbol start port 15, a big winning port 16, a normal winning port 17, and a gate 18 are arranged. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball. When the game ball passes through the symbol start port 15, a series of image effects accompanied by the special symbol changing operation is started on the special symbol display portions Da to Dc, assuming that the game ball has won. Corresponding to this image effect, a sound effect with background music and effect sound, and a lamp effect in which the lamp blinks are executed.

  The symbol start port 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a, and when the stop symbol after fluctuation of the normal symbol display unit 17 displays a winning symbol, a predetermined time is displayed. The opening / closing claw 15a is opened only until a predetermined number of game balls are detected.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the selected lottery random value is displayed and stopped.

  The special winning opening 16 includes an opening / closing plate 16a that opens and closes in the front-rear direction. The operation of the special winning opening 16 is not particularly limited, but in a typical big hit state, a predetermined time elapses after the opening / closing plate 16a of the special winning opening 16 is opened, or a predetermined number (for example, ten) of games. When the ball wins, the opening / closing plate 16a is closed. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. As shown in the figure, this pachinko machine GM mainly receives the AC 24V and outputs various DC voltages, power abnormality signals ABN1, ABN2, system reset signal (power reset signal) SYS, and the like, and game control operations. Based on the main control board 21 that performs overall control, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD ′ received from the effect control board 22 The image control board 23 for driving the display device DS, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21, and paying out the game balls. It is mainly composed of a launch control board 25 that responds and launches a game ball.

  The control command CMD output from the main control board 21 is transmitted to the effect control board 22, and the control command CMD ′ output from the effect control board 22 receiving the command is sent to the image control board via the image interface board 28. 23. Note that the image interface board 28 and the image control board 23 are formed by stacking two circuit boards by directly connecting a male connector and a female connector without going through a wiring cable. The control command CMD ″ output from the main control board 21 is transmitted to the payout control board 24 via the main board relay board 32.

  These control commands CMD, CMD ′, and CMD ”are all 16 bits long, but the control commands related to the main control board 21 and the payout control board 24 are transmitted in parallel every 8 bits. On the other hand, the control command CMD ′ transmitted from the effect control board 22 to the image control board 23 is transmitted in parallel in a 16-bit length, so that the notice effects including the movable notice effect are diversified. Even when a large number of control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  The main control board 21, the production control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. In view of this, the control boards 21 to 24 and the circuits mounted on the interface board 28 and the operations realized by the circuits are collectively referred to as functions. In this specification, the main control section 21 and the effect control section 22 are used. , Image control unit 23 and payout control unit 24. That is, in this embodiment, the image control board 23 and the image interface board 28 constitute the image control unit 23. All or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 is a sub-control unit.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  3, the frame side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, a frame relay board 35, a lamp drive board 36, and a lamp & motor drive board. 37 and the sensor board 26 are included, and these circuit boards are respectively fixed at appropriate positions of the front frame 3.

  The PS conversion circuit (shift register 74) shown in FIG. 8 is mounted on the sensor board 26, and a number of switch signals (sensor signals) SN received from various sensors and chance buttons 11 are converted into serial signals and framed. It is output to the relay board 35. This PS (parallel to serial) conversion operation is executed based on a 2-bit signal (CLK, LT) received from the frame relay board 35, and more specifically, a large number of switch signals latched in synchronization with the acquisition signal LT. Are serially output in synchronization with the subsequent transfer clock signal CLK (see FIG. 8C). The serial sensor signal SN output from the sensor board 26 is transmitted to the board-side frame relay board 34 and the effect control unit 22 via the frame relay board 35.

  The frame relay board 35 is composed of two digital amplifiers 70 (70a, 70b) for driving five speakers SPR1, SPL1, SPR2, SPL2, and SPD, and a clock signal combined with various types of serial signals. A clockless serial receiver 50 that receives the composite serial signal in the form of differential signals TX + and TX− is mounted. Corresponding to this configuration, a clockless serial transmitter 47 is arranged in the effect control unit 22, and the frame-side frame relay board 35 is connected to the differential signal via the board-side frame relay board 34. Receives TX +, TX-.

  The configurations of the transmitter 47 and the receiver 50 that transmit and receive the differential signals TX + and TX− will be described later with reference to FIG. 6. In this embodiment, the differential signals TX + and TX− (composite) transmitted from the transmitter 47 are used. The serial signal includes a 5-bit signal (LRCLK, SCLK, SD0 to SD2) supplied to the digital amplifiers 70a and 70b, and a 4-bit signal (CLR1, CK1, ENABL1) supplied to the LED driver Dr of the lamp driving board 36. , SDATA1), a 4-bit signal (CLR0, MCK0, ENABL0, SDATA0) transmitted to the LED driver Dr and motor driver Dr of the lamp & motor drive board 37, and a 2-bit signal (CK, LT).

  Therefore, in the present embodiment, the number of wires between the frame relay board 35 and the frame relay board 34 is such that the signal line for the differential signal 2 bits and the signal line of the serial sensor signal SN output from the sensor board 26 A total of four ground lines will suffice. In the configuration so far, 10 audio signal lines for five speakers, a total of 8 signal lines for two channels for the driver Dr that drives the lamp group and the motor group, and the sensor board 26 and the transmission / reception line A total of 22 wires were required, including the ground wire.

  However, according to the configuration of the present embodiment, the number of signal wirings excluding the ground is suppressed to 1/7, and a great effect is exhibited in manufacturing work and replacement work. Further, since only three signal lines are required for the connection connector C4, the connection connector C4 and the connection connector C3 can be shared. In this sense, not only the manufacturing work and the replacement work, but also the manufacturing cost is excellent. Demonstrate.

  Based on the above, the description of the frame side member GM1 will be continued. The LED group of the first channel CH1 is connected to the lamp drive board 36, and the drive data SDATA1 defining these lighting states is other signals. Along with CLR1, CK1, and ENABLE1, they are transmitted from the effect control board 22 to the frame relay board 35 as part of the differential signals TX + and TX−.

  Then, the 4-bit data (SDATA1, CLR1, CK1, ENABLE) cut out by the clockless serial receiver 50 is transmitted to the plurality of LED drivers Dr mounted on the lamp driving board 36, and the LEDs that receive them are received. The driver Dr drives and drives the lamp group of the first channel CH1 based on the drive data SDATA1. In addition to the original drive data that defines the blinking state, the drive data SDATA1 is numbered to the address data numbered for each LED driver Dr and the internal registers R1 to Rm of the driver Dr that controls the lighting mode. The registered register address is also included. This also applies to drive data SDATA0 and drive data SDATA2 to SDATA3 described below.

  The lamp & motor drive board 37 is connected to the LED group of the 0th channel CH0 and the motor group MO (see FIG. 9), and the drive data SDATA0 defining these operations is also connected to other signals CLR0, CK0, Along with ENABLE0, it is transmitted from the effect control board 22 to the frame relay board 35 as part of the differential signals TX + and TX−. Then, the 4-bit data (SDATA0, CLR0, CK0, ENABLE0) cut out by the clockless serial receiver 50 is passed through the lamp driving board 36 to the lamp & motor driving board 37, and is transferred to the lamp driving board 36. It is transmitted to the mounted LED driver Dr and motor driver Dr.

  Here, the motor driver Dr and the LED driver Dr mounted on the lamp & motor drive board 37 have the same configuration as the LED driver Dr mounted on the lamp drive board 36, and based on the 1-bit drive data SDATA0. Each of them drives one or a plurality of effect motors MO and LED lamp groups. That is, the drive data SDATA0 serves as both motor drive data and LED drive data. The drive data SDATA0 includes the address data of the driver Dr described above and the register addresses of the internal registers R1 to Rm of the driver Dr. (See FIG. 9).

  Next, the main control board 21, the effect control board 22, and the image control board 23 are fixed to the back of the game board 5 together with the display device DS and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place. As described above, the connection connector C4 requires only four contact points even if a ground line is added, so that it is not only easy to attach and detach, but it is also possible to eliminate contact even if the replacement work of the panel side member GM2 is repeated. Is greatly reduced. Compared with the 22 wires that have been required so far, the wiring is easy and the arrangement space for the wires and the connection connector C4 is greatly reduced, which is advantageous in terms of device design.

  The other components of the frame-side member GM1 will be described. The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power supply relay board 33 outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages to the effect control unit 22 as they are. The effect control unit 22 outputs the received system reset signal SYS to the image control unit 23 as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been turned on to the power supply board 20, and the one-chip microcomputer of the effect control unit 22 and the image control unit 23 by this power supply reset signal. The power is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. On the other hand, the effect control unit 22 and the image control unit 23 execute the effect operation in a dependent manner based on the control command from the main control unit 21, so that the power supply board 20 is avoided in order to avoid complication of the circuit configuration. The system reset signal SYS output from is used.

  Next, the board-side member GM2 will be described. The reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and from the CPUs of the control units 21 and 24, a fixed time is provided. Each CPU is forcibly reset unless a clear pulse is received. In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As illustrated, the effect control unit 22 receives a control command CMD and a strobe signal STB from the main control unit 21. The effect control unit 22 supplies drive data SDATA2 and SDATA3 as serial signals to the LED driver (motor driver) Dr mounted on the lamp drive board 29 and the lamp & motor drive board 30 together with other control signal 3 bits. doing. In this embodiment, the LED driver Dr and the motor driver Dr mounted on the lamp driving board 29 and the lamp & motor driving board 30 have the same configuration as the LED driver Dr mounted on the lamp driving board 36.

  As shown in FIGS. 3 and 4A, the effect control unit 22 sends the control command CMD ′ and the strobe signal STB ′ to the image control unit 23, the system reset signal SYS received from the power supply board 20, and 2 It outputs various types of DC voltage (12V, 5V). The image control unit 23 drives the display device DS based on the control command CMD 'to execute various image effects. The display device DS emits light by an LED backlight, and is driven by receiving five pairs of LVDS (Low voltage differential signaling) signals and a backlight power supply voltage (12 V) from the image interface board 28. Has been.

  Next, the configuration of the effect control unit 22 described above will be described in more detail with reference to FIG. As shown in FIG. 4A, the effect control unit 22 receives three types of DC voltages (5V, 12V, and 32V) from the power supply board 20 via the power supply relay board 33. Here, the DC voltage 5V is distributed to the lamp driving board 29, the lamp & motor driving board 30, the image interface board 28, and the image control board 23 as the power supply voltage of the digital logic circuit to operate each digital circuit. Yes. The direct current voltage 32V is stepped down to the direct current voltage 13V in the DC / DC converter and used as a drive power source for the effect motors M1 to Mn.

  As shown in FIG. 4A, the effect control unit 22 ′ may be referred to as a one-chip microcomputer 40 (effect control CPU 40) that executes processing such as voice effect, lamp effect, notice effect by effect movable body, and data transfer. ), A control memory (flash memory) 41 for storing the control program of the presentation control CPU 40, and a voice processor (voice synthesis circuit) that reproduces and outputs a voice signal based on an instruction (voice command SND) from the presentation control CPU 40 ) 42, an audio memory 43 that stores compressed audio data and SAC data that are original data of an audio signal to be reproduced, and a watchdog timer WDT that forcibly clears the effect control CPU 40 when the clear pulse stops. Configured.

  The one-chip microcomputer 40, the flash memory 41, and the audio memory 43 operate at a power supply voltage 3.3V, and the audio processor 42 operates at a power supply voltage 3.3V and a power supply voltage 1.8V. As a result, significant power savings have been achieved. Here, 1.8V is the power supply voltage of the computer core unit of the voice processor 42, and 3.3V is the power supply voltage of the I / O unit.

  As shown in FIG. 5B, the audio processor 42 of the present embodiment includes a large number of audio control registers RG0 to RGn that can be accessed from the effect control CPU 40, a sound control module 52 that comprehensively controls the audio reproduction operation, The main generator 53 that decodes the phrase compressed data read from the audio memory 43 and mixes the decoded data of the plurality of phrase reproduction channels CH0 to CH63 at an appropriate volume ratio, and a desired frequency by digital filter processing An effect unit 54 that realizes an equalizer function that realizes characteristics and a compressor function that changes input / output gain characteristics, a total volume TV that defines the final volume, and four types of signals SCLK, LRCLK, SD0 to SD2 for serial transmission Generated digital IF section And it is configured to include a 5, a.

  Then, the audio processor 42 having such a configuration accesses the audio memory 43 based on an instruction received from the effect control CPU 40 to the audio control registers RG0 to RGn (setting value by the audio command SND), and transmits a necessary audio signal. Playback and output. As shown in FIG. 4A, the audio processor 42 and the audio memory 43 are connected to each other by a 26-bit audio address bus and a 16-bit audio data bus. Therefore, data of 1 Gbit (= 226 * 16) can be stored in the audio memory 43.

  In the case of the present embodiment, the compressed audio data stored in the audio memory 43 is phrase compressed data specified by a phrase number (000H to 1FFFH) having a 13-bit length, and is a sequence of background music. (BGM), a group of effect sounds (notice sounds), and the like are stored in a maximum of 8192 types (= 213), each corresponding to a phrase number. The phrase number is specified by the set value of the voice command SND transmitted from the effect control CPU 40 to the voice control registers RG0 to RGn of the voice processor 42.

  The voice command SND is a plurality (2 or 3) bytes long, and is used for a write purpose of transmitting a predetermined set value to any one of the many voice control registers RG0 to RGn built in the voice processor 42. The However, the voice command SND of the present embodiment is used not only for a write application for writing a set value such as a phrase number, but also for a read application for reading status information (error information) STS from a predetermined voice control register RGi. The predetermined audio control register RGi to be accessed is specified by a 1-byte register address.

  By the way, setting (Write) of the set value to the audio control register RGi is not necessarily performed individually for each audio control register, and a group of SAC data stored in the audio memory 43 is designated. A series of setting operations for the voice control registers RGi to RGj can be completed. Here, the SAC data is an aggregate of a maximum of 512 pieces (up to 1024 bytes) in which the register address (1 byte) of the voice control register RGi is associated with the set value (multiple bytes) in the voice control register RGi. Means.

  In the present embodiment, only a necessary set of such SAC data is stored in advance in the audio memory 43 (see FIG. 5B), and one set of SAC data is 13-bit information that is single ID information. It is specified by the SAC number of the degree. Therefore, in the case of the present embodiment, the voice command SND for write use specifies a SAC number and specifies a set of SAC data, or specifies a set value and a register address individually.

  As shown in FIG. 5 (b), the main part of the connection relation is described. The effect control CPU 40 and the audio processor 42 are capable of transmitting the lower management data buses CD0 to CD7 capable of transmitting / receiving 1-byte data and the operation management data 2. Bit-length operation management data lines (address buses) A0 to A1, 2-bit length control signal lines WR and RD capable of controlling read / write operations, and a chip select signal line CS for selecting the audio processor 42 And connected with.

  The operation management data lines A0 to A1 are realized by an address bus of the effect control CPU 40. Then, when the production control CPU 40 executes, for example, an IOREAD operation or an IOWRITE operation by program processing, the control signals WR and RD and the chip select signal CS are appropriately changed, and the audio specified by the lower data buses CD0 to CD7. A read / write (R / W) operation with the control register RGi is realized.

  Specifically, as shown in the time chart of FIG. 5A, the register address of the audio control register RGi and the write data to the audio control register RGi are transmitted in parallel through the lower data buses CD0 to CD7, respectively. The Whether the 1 byte transmitted in parallel is a register address or write data (write data) is specified by the operation management data A0 to A1.

  For example, as shown in FIG. 5A, the operation management data (address data A0 to A1) is changed from [00] to [01], while 1-byte data of the data bus is changed to [voice control register RGi. A predetermined voice command SND is transmitted by transiting from “register address” → [write data to voice control register RGi]. When the write data is a plurality of bytes long as in the case of transmitting the SAC number (13 bits), the operation management data A0 to A1 of [01] are changed from [00] → [01] → [01]. → Send the data of multiple bytes while repeating [01].

  The voice command SND transmitted in this way is subsequently validated as long as there is no communication abnormality. However, if a communication error is recognized, such as data having a plurality of bytes inconsistent with each other, the voice command SND is not activated. Then, the error flag of the voice control register RGn is set. This error flag (status information STS) is produced by changing the operation management data A0 to A1 of the address bus from [01] to [10]. The control CPU 40 can receive it by the Read operation.

  As described above, in this embodiment, error information (abnormality of a plurality of bits) is obtained in the final cycle in which the operation management data A0 to A1 are changed from [00] → [01] →... [01] → [10]. FFH) can be obtained. Then, by retransmitting the voice command SND that could not be properly transmitted in parallel, the voice effect can be appropriately advanced. Therefore, according to the configuration of the present embodiment, it is possible to reliably eliminate the unnaturalness that the sound effect suddenly stops.

  By the way, as described above, in this embodiment, the left and right speakers SPR1, SPL1, SPR2, SPL2 at the upper and middle parts of the gaming machine and one speaker SPD at the lower part of the gaming machine are arranged. There are a total of five types of audio signals to be transmitted. Therefore, in the normal configuration in which the digital amplifier 70 for driving the speaker is arranged in the effect control unit 22, ten wires are required from the effect control unit 22 (board side member GM2) to the speaker (frame side member GM1). Further, when the sound processor 42 is abnormal, it is necessary to silence the speaker under the control of the effect control CPU, and it is also necessary to transmit a MUTE signal for stopping the operation of the digital amplifier, which requires a total of 11 signal wirings. .

  Therefore, in this embodiment, the digital amplifier 70 is disposed on the frame relay board 35 (see FIG. 3), and the MUTE signal output from the effect CPU and the 5-bit length serial signal output from the audio processor 42 are The signal is transmitted from the effect control unit 22 to the frame relay board 35 in the form of composite serial signals TX + and TX− combined with the serial signal. Specifically, the 5-bit length signals excluding the MUTE signal are the audio clock SCLK, the channel control signal LRCLK, and the 3-bit length serial signals SD0 to SD2. Note that a 1-bit long MUTE signal is supplied in common to the two digital amplifiers 70a and 70b, and silences all the speakers when an abnormality occurs.

  SD0 output from the audio processor 42 is a serial signal for PCM data specifying the stereo signals R and L of the left and right speakers SPR1 and SPL1 arranged at the upper part of the gaming machine, and SD1 is arranged in the middle part of the gaming machine. SD2 is a serial signal for PCM data that specifies stereo signals R and L of left and right speakers SPR2 and SPL2, and SD2 is a serial signal for PCM data that specifies a monaural signal of a heavy bass speaker SPD disposed at the lower part of the gaming machine. It is.

  The audio processor 42 transmits the audio signal L of the left channels SPL1 and SPL2 while maintaining the channel control signal LRCLK at the L level, and maintains the channel control signal LRCLK at the H level while maintaining the channel control signal LRCLK at the H level. The audio signal R of SPR2 is transmitted (see FIG. 5C). On the other hand, since there is one heavy bass speaker SPD in this embodiment, a monaural audio signal is transmitted.

  Such serial signals SD0 to SD2 are acquired by the digital amplifier 70 (70a or 70b) in synchronization with the rising edge of the audio clock SCLK. In the digital amplifier 70, parallel conversion is performed for each predetermined bit length, D-class amplification is performed after DA conversion, and the signals are supplied to the speakers SPR1, SPL1, SPR2, SPL2, and SPD. FIG. 7 shows a digital amplifier (70a, 70b), a 5-bit signal (SCLK, LRCLK, SD0 to SD2), a 1-bit MUTE signal, and five speakers (SPR1, SPL1, SPR2). , SPL2, SPD).

  Referring back to FIG. 4, the one-chip microcomputer 40 has a plurality of parallel input / output ports PIO (Pi1, Pi2, Po1, Po2, Pi, Po) and a plurality of serial input / outputs operating in a clock synchronous manner. Port SIO (Si, So) is incorporated. Here, the parallel output port Po (1) designates a SAC number, activates the simple access controller of the sound control module 52, and sets a group of set values as a group of audio control registers RGi (FIG. 5B). And (2) a serial transmission operation for individually writing an operation instruction and phrase number to the audio processor 42 in the corresponding audio control register RGi. The parallel input port Pi is a part that realizes (3) a serial reception operation of reading status information STS from a predetermined audio control register RGi.

  Further, the control command CMD and the strobe signal STB from the main control unit 21 are input to the parallel input port Pi1 via the input buffer 44, and the control command CMD ′ and the strobe signal STB ′ are input from the parallel output port Po1. Is output.

  The control command CMD acquired by the effect control unit 22 from the main control unit 21 includes (1) abnormality notification and other notification control commands, and (2) various effect operations resulting from winning at the symbol start opening. A control command (variation pattern command) for specifying an outline and a control command (design specifying command) for specifying a symbol type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the effect control unit 22 acquires the variation pattern command, the effect lottery is subsequently performed, and the effect outline specified by the acquired variation pattern command is further specified. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking the LED group and a sound effect preparation operation by the speaker are performed, and the image control unit 23 is synchronized with the effect operation by the lamp and the speaker. The control command CMD ′ relating to the rendered image effect is output via the output buffer 45.

  In order to realize such an image effect synchronized with the effect operation, the effect control unit 22 transmits a 16-bit control command CMD ′ together with a strobe signal (interrupt signal) STB ′ to the image control unit 23 through the parallel output port Po1. Are output to the image interface board 28 via the output buffer 45. When the design control command 22 receives a design designation command, a notification control command related to the display device DS, or other control command, the production control unit 22 interrupts the control command in a state of collecting the control command in a 16-bit length. Along with the signal STB ′, it is output to the image interface board 28 via the output buffer 45.

  On the other hand, the parallel output port Po2 is configured to output the enable signals ENABLE0 to ENABLE3, the clear signals CLR0 to CLR3, the MUTE signal for stopping the operation of the digital amplifier, and the acquisition signal LT transmitted to the sensor board 26. Has been. Here, the permission signal ENABLEi is a control signal that collectively permits the operations of the plurality of drivers Dr mounted on the LED lamps and the drive boards 36, 37, 29, and 30 of the effect motor, and the clear signal CLRi includes a plurality of clear signals CLRi. This is a control signal for simultaneously resetting the built-in registers R1 to Rm of the driver Dr to zero.

  As shown in FIG. 4, the one-chip microcomputer 40 is also provided with a serial input / output port SIO (Si, So) that operates in a clock synchronous manner. Here, the serial input port Si is used for outputting the transfer clock CLK to the sensor substrate 26 and acquiring the serial sensor signal SN transmitted in synchronization with the transfer clock CLK. As illustrated, the serial sensor signal SN is transmitted to the serial input port Si via the input buffer 46.

  On the other hand, the serial output port So is configured to include four-channel serial output ports So0 to So3, and is connected to a plurality of drivers Dr mounted on the drive boards 36, 37, 29, and 30 of LED lamps and effect motors. The necessary data to be transmitted is serially output. That is, the serial output ports So0 to So3 receive the 4-channel serial drive data SDATA0 to SDATA3 to be transmitted to the corresponding lamp drive boards 37, 36, 29, and 30 based on the clock synchronization method, and the clock signals CK0 to CK3. It is output with.

  As described above, the serial drive data SDATA0 to SDATA3 are mostly brightness data (lamp drive data) for adjusting the light emission brightness of each LED by PWM control (pulse width modulation). , M1 to Mn are also included.

  In the case of the present embodiment, the panel side member GM2 includes a lamp driving board 29 that drives and drives the lamp group of the second channel CH2, and a lamp and motor drive that drives the lamp group and the effect motors M1 to Mn of the third channel CH3. A substrate 30 is disposed. A plurality of LED drivers Dr and motor drivers Dr are arranged on these drive boards 29 and 30. From the one-chip microcomputer 40 via the output buffers 48 and 49, a clock signal CKi and serial drive are provided. Data SDATAi, permission signal ENABLEi, and clear signal CLRi are received, and appropriate lamp effects and motor effects are executed based on these signals (i = 2 to 3). The operation of the driver Dr is the same as the operation of the driver of the lamp & motor drive board 30 described later with reference to FIG. 9, and the effect motors MO and M1 to Mn function as appropriate movable notice effects.

  In the present embodiment, the serial drive data SDATA0 to DATA1 of the 0th channel CH0 and the first channel CH1 are supplied to the clockless serial transmitter 47 together with the corresponding clock signals CK0 to CK1. The transmitter 47 also receives a MUTE signal output from the parallel output port Po2, a 5-bit signal 5-bit signal (LRCLK, SCLK, SD0 to SD2) output from the audio processor 42, and a serial input port Si. An output transfer clock CLK is also supplied. These 16-bit signals are transmitted to the clockless serial receiver 50 as a part of the composite serial signals TX + and TX− as described above.

  FIG. 6C illustrates a connection relationship between the clockless serial transmitter 47 and the clockless serial receiver 50. The differential signal terminals DFTX + and DFTX between the transmitter 47 and the receiver 50 of this embodiment are illustrated. -Are each connected in a DC cut state through an AC coupling capacitor of about 0.1 μF.

  FIG. 6A illustrates the internal configuration of a transmission IC that implements the transmitter 47 and the receiver 50 of this embodiment. This transmission IC is designed so that digital RGB signals (8 bits each) of LCD (liquid crystal display) can be serially transmitted with only a pair of composite serial signals TX + and TX−, and the CDR (Clock Data Recovery) part is provided. Built-in. The serial transmission speed is defined by the frequency of the sampling clock Φ supplied to the parallel clock terminal PCLK of the transmitter 47, and a 36-bit composite serial signal is transferred at high speed during one cycle of the sampling clock Φ ( (Refer FIG.6 (b)).

  Here, the 36-bit length to be transmitted is divided into original transfer data 28 bits and additional bits 8 bits for realizing the CDR function and the like. In this embodiment, only 16 bits described below are used from the maximum 28 bits of transfer data.

  In addition, this transmission IC receives a composite serial signal TX +, TX− from the differential signal terminals DFTX +, DFTX−, or a transmission mode in which the composite serial signals TX +, TX− are output from the differential signal terminals DFTX +, DFTX−. The reception mode can be selected. Specifically, when the TX_XRX terminal is set to H level, it functions as the transmitter 47, and when the TX_XRX terminal is set to L level, it functions as the receiver 50. The DFSET1 terminal, the DFSET0 terminal, and the F_XS terminal have different roles depending on whether the transmission IC is the transmitter 47 or the receiver 59, but are appropriately set to exhibit necessary performance. . The same applies to other terminals not mentioned in the following description.

  In any case, this transmission IC is originally designed for an LCD, and apart from a 3 × 8-bit digital RGB terminal, a vertical synchronization signal terminal VS, a horizontal synchronization signal terminal HS, and an enable terminal DE are provided. Although present, these terminals are not used in this embodiment. In other words, in this embodiment, appropriate 16 bits of the 3 × 8 bit long digital RGB terminals are utilized, and 8-bit signals for the channels CH0 to CH1 of the drive boards 36 and 37 are connected to these 16-bit terminals. (CLR0-CLR1, ENABLE0-ENABLE1, SDATA0-SDATA1, CK0-CK1), transfer clock CLK, acquisition signal LT, MUTE signal, and 5-bit output signal (LRCLK, SCLK, SD0-SD2) of the voice processor (Hereinafter, these 16 bits may be referred to as stream data).

  As described above, in this transmission IC, when the sampling clock Φ having an appropriate frequency is supplied to the parallel clock terminal PCLK of the transmitter 47, the above-described stream data is acquired as parallel data in synchronization with the sampling clock Φ. These are subjected to PS (parallel to serial) conversion and output as composite serial signals TX + and TX− in a clockless manner. In other words, in this embodiment, the clock signals CK0 to CK1 transmitted to the driver Dr of the drive boards 36 and 37, the transfer clock CLK transmitted to the sensor board 26, the audio clock SCLK transmitted to the digital amplifier 70, and the like. All these synchronous clock signals are sampled by the transmitter 47 as parallel data.

  Therefore, the relationship between the frequency of the synchronous clock signal (CK0 to CK1, CLK, SCLK) and the frequency Fs of the sampling clock Φ is important. That is, the acquisition timing of the synchronous clock signal may be shifted by the sampling period 1 / Fs at the maximum, and this acquisition deviation hinders the function that each synchronous clock signal (CK0 to CK1, CLK, SCLK) should originally perform. There is also a possibility to do. That is, there is a possibility that an acquisition omission that misses a change in the synchronous clock signal occurs.

  Therefore, in this embodiment, the frequency Fs of the sampling clock Φ is set to be significantly higher than the frequency of each synchronous clock signal (CK0 to CK1, CLK, SCLK), thereby avoiding the possibility of the above-described acquisition omission. Yes. Specifically, in this embodiment, the sampling clock Φ is set to about 70 MHz, while the frequency of each of the above-described synchronous clock signals (CK0 to CK1, CLK, SCLK) is set to 2 MHz (1/35) or less. doing.

  Therefore, for example, the maximum value (about 14.3 nS≈1 / 70 MHz) of the synchronization clock signal acquisition rate with a duty ratio of 50% and a frequency of 2 MHz is ±± at most with respect to the pulse width (250 nS) of the synchronous clock signal. It is suppressed to about 5.7%, and the function as a synchronous clock is not impaired. Note that the frequency of each synchronous clock signal (CK0 to CK1, CLK, SCLK) does not necessarily need to be set to 2 MHz or less. If the frequency is 1/10 or less of the sampling clock Φ, the acquisition deviation due to the sampling clock Φ is synchronous. It is suppressed to about 20% of the pulse width of the clock signal, and no particular problem occurs.

In the following description, assuming that the sampling clock Φ is 70 MHz, the 16-bit stream data acquired at intervals of about 14.3 nS (≈ 1/70 MHz) is transferred serial data 28 along with other 12 bits of NULL data. 36 bits including 8 bits added to this are serially transferred from the transmitter 47 to the receiver 50. In this embodiment, 36 bits (substantially 28 bits) are transmitted approximately every 14.3 nS, so the serial transfer rate is 36 × 70 × 10 ⁶ = 2.52 Gbsp, and the effective rate is 28 × 70 ×. 10 ⁶ = 1.89 Gbsp.

  The composite serial signals TX + and TX− having such a configuration are acquired by the receiver 50, which is the frame side member GM1, and subjected to SP (serial to parallel) conversion, thereby restoring 16-bit length stream data. In addition, the sampling clock Φ is restored via the CDR unit. Therefore, the sampling cycle on the transmission side can be grasped on the reception side by the restored sampling clock, and can be used as a latch pulse or the like. However, in this embodiment, the restored latch pulse is not used.

  FIG. 7 illustrates the circuit configuration of the frame relay board 35 and the lamp driving board 36. As shown in the figure, some of the outputs CLK and LT of the receiver 50 are transferred to the sensor substrate 26, and the other parts LRCLK, SCLK, SD0 to SD2, and MUTE are supplied to the digital amplifiers 70a and 70b. In the internal circuits of the digital amplifiers 70a and 70b, the serial signals SD0 to SD2 are restored to PCM audio data in synchronization with the audio clock SCLK, and D as the left and right audio signals SPR and SPL according to the level of the LRCLK signal. Class amplified.

  The 8-bit signals (CLR0-CLR1, ENABLE0-ENABLE1, SDATA0-SDATA1, CK0-CK1) of the 0th channel and the 1st channel are transmitted to the lamp driving board 35 via the buffer circuit 71. On the other hand, the frame relay board 35 also receives the serial sensor signal SN from the sensor board 26, and is transmitted to the board side frame relay board 34 via the buffer circuit 72.

  As shown in FIG. 7, the lamp driving board 36 transmits the 4-bit signals (CLR1, ENABLE1, SDATA1, CK1) of the first channel to the plurality of LED drivers Dr. Then, the LED driver Dr lights a necessary LED lamp with a specified luminance based on the received drive data SDATA1. On the other hand, the lamp drive board 36 transmits the 4-bit signals (CLR0, ENABLE0, SDATA0, CK0) of the 0th channel to the lamp & motor drive board 37 via the buffer circuit 73.

  FIG. 8 is a diagram for explaining the circuit configuration and operation of the sensor substrate 26. As shown in FIG. 8A, the sensor substrate 26 is configured around a shift register 74, an input buffer circuit 75, and a filter circuit 76. Although not limited at all, as the shift register 74, for example, TC74HSC165F (Toshiba) whose internal circuit is shown in FIG. 8B is used. Further, as described with reference to FIG. 7, the sensor substrate 26 receives the transfer clock CLK and the acquisition signal LT via the serial receiver 50 of the frame relay substrate 35.

  As shown in FIG. 8, the input buffer circuit 75 includes a pull-up resistor R and an inverter IN, and logically inverts a switch signal received from the chance button 11 or the security sensor. Further, a switch signal having a total length of 7 bits is supplied to the seven input terminals (B to H) of the shift register 74 via the input buffer circuit 75. The input terminal (A) of the least significant bit is connected to the ground.

  The filter circuit 76 constitutes a CR low-pass filter composed of resistors R1 and R2 of about 50 to 100Ω and capacitors C1 and C2 of about 50 to 100 pF. Various switch signals are supplied to the parallel input terminals B to H of the shift register 74, and the data of the parallel input terminals A to H are synchronized with the falling timing of the acquisition signal LT received from the frame relay board 35. To the internal register of the shift register 74.

  As shown in the figure, in this embodiment, the serial input terminal INPUT and the prohibition terminal INHIBIT of the shift register 74 are fixed at the L level. Therefore, when the transfer clock CLK is supplied, the data acquired in the shift register 74 is output as the serial sensor signal SN in synchronization with the rising edge of the transfer clock CLK. The output serial switch signal SN is transmitted to the effect control board 22 via the frame relay boards 35 and 34 and supplied to the serial input port Si of the one-chip microcomputer 40 (FIG. 4). Then, the serial input port Si sequentially acquires the serial switch signal SN in synchronization with the falling edge of the transfer clock CLK output by itself.

  FIG. 9A is a block diagram showing a circuit configuration of a lamp & motor drive board 37 that drives the lamp group of the 0th channel CH0 and the effect motor group MO. As shown in the figure, the lamp & motor drive board 37 includes a buffer circuit 80 that receives 4-bit length data ENABLE0, SDATA0, CK0, and CLR0 from the frame relay board 35, and a plurality of 4-bit length data that is received from the buffer circuit 80. And a driver Dr to Dr. Although the LED lamp is directly driven by the driver Dr, the effect motor MO is driven by a motor driver 81 that amplifies the output of the driver Dr.

  As described above, in this embodiment, the motor driver Dr and the lamp driver Dr all have the same configuration, and the enable signal ENABLE0 and the clear signal output from the parallel output port Po2 of the one-chip microcomputer 40. The CLR0, the serial drive data SDATA0 output from the serial output port So0 of the one-chip microcomputer 40, and the clock signal CK0 are commonly received and operated. The serial drive data SDATA0 includes a lamp drive signal and a motor drive signal.

  As described above, the enable signal ENABLE0 is a control signal that collectively defines whether or not the drivers Dr to Dr shown in FIG. 9 are permitted to operate, and the clear signal CLRi is the built-in register R1 of all the drivers Dr to Dr. This is a control signal for resetting .about.Rm all at once.

  The illustrated driver Dr has, for example, an address terminal (A0-A4) having a 5-bit length, and is configured so that an address can be appropriately assigned. In addition, by setting the control data Di (8-bit length) for the built-in control registers R1 to Rm and setting the control data Di (8-bit length), each output of the 24-bit length output terminal is appropriately gradation controlled. It has become. Note that the register numbers of the control registers R1 to Rm are 8 bits long, and the address terminals (A0 to A4) having a length of 5 bits are set to H / L levels in advance in this embodiment. The address ADRi of the driver Dr is a fixed value.

  FIG. 9B is a time chart showing the operation procedure of the driver Dr, which is realized by the control of the one-chip microcomputer 40 (production control CPU 40). As shown in the figure, first, after the built-in registers R1 to Rm of all the drivers Dr are cleared by the clear signal CLR0, the enable signal ENABLE0 becomes the enable level.

  Next, serial drive data SDATA0 is output under the control of the one-chip microcomputer 40. As the output procedure of the serial drive data SDATA0, first, (1) the address number ADRi (8-bit length) of the driver Dr to which the control data Di is to be written is output, followed by (2) the control at the driver Dr. The register numbers (8-bit length) of the control registers R1 to Rm to which data Di is to be written, and (3) the control data Di (8-bit length set value) to be written to the control register Ri are respectively clock signals. Output in synchronization with CK0.

  If the first register number Ri is designated for a series of control registers R1 to Rm, the subsequent control data (set values) D1, D2, R3... Are represented by Ri, Ri + 1, Ri + 2. The control data is recognized and processed by the driver Dr.

Accordingly, the output procedure of the serial drive data SDATA0, necessarily, have to configure the settings for all of the control registers Ri without, for example, if the write process to a series of M control register _{R i ~R} i _{+ M-1} The serial drive data SDATA0 having a total length of 8 × (M + 2) bits is sufficient for M pieces of control data and two pieces of address data, and this embodiment adopts such a configuration.

  Further, the driver Dr is configured so that a maximum of 8 × 3 LED lamps can be connected (except for a series connection), and there are at least 24 internal registers (M = 24) that define lighting modes of these LED lamps. In this embodiment, the serial drive data for one driver Dr is suppressed to 208 bits (= 8 × (M + 2)), which is the minimum bit length. This relationship is the same for the driver Dr that drives the effect motor.

  Then, when output processing of a total of 8 × (M + 2) bits for a predetermined driver Dr is completed, output processing of a total of 8 × (M + 2) bits for another driver Dr is continued. Therefore, for example, even when there are five drivers Dr connected in parallel, the serial drive data SDATA0 has a length of 5 × 8 × (M + 2) = 5 × 8 × 26 = 1040 bits as a whole.

  Incidentally, as described above, in this embodiment, the frequency of the clock signal CK0 is suppressed to 2 MHz, for example, in order to significantly reduce the frequency Fs of the sampling clock Φ of the transmitter 47 shown in FIG. Therefore, there is a possibility that the transmission time of the above 1040-bit serial drive data SDATA0 becomes a problem.

However, in reality, time that becomes a control burden of the production control CPU 40 is not consumed. That is, the transmission time of the serial drive data SDATA0 is about 1040 / (2 × 10 ⁶ ) = 0.5 mS at most for all of the five drivers Dr. If the drive data SDATA0 is set in the transmission data register of the serial output port So0, instead of being restricted by all of the 5 mS transmission processing, there is no problem because the process can be shifted to other processes thereafter.

  Note that each time 1-byte serial data is transmitted through the serial output port So0, the presentation control CPU does not adopt a configuration in which the next 1-byte data is written in the transmission data register, but a plurality of bytes of drive data is received. It is also preferable to secure a temporarily storable FIFO buffer and to automatically supply the next drive data from the FIFO buffer to the transmission data register each time 1-byte drive data is transmitted. In the case of adopting such a configuration, it is sufficient for the effect control CPU to write a plurality of bytes of parallel data collectively in the FIFO buffer when the FIFO (First In First Out) buffer becomes empty. There is no problem even if the number of drivers Dr connected in parallel increases significantly.

  As mentioned above, although the Example of this invention was described in detail, the specific description content does not limit this invention at all. For example, in the embodiment, it has been described that the frequency of the synchronous clock signal (CK0 to CK1, CLK, SCLK) is preferably 1/10 or less of the sampling clock Φ. It is not limited.

  For example, if the highest frequency of all the signals combined in the composite serial signal is set to the clock signals CK0 to CKn of the drive data, and the clock signals CK0 to CKn of the drive data are shared by a single clock signal CK (common clock) Signal CK) and sampling clock Φ can be N times (N> 1) the frequency of a single clock signal CK and the phases of each other can be matched to reliably eliminate the problem of acquisition leakage. it can.

  FIG. 10 illustrates the relationship, showing the common clock signal CK having the highest frequency and the sampling clock Φ obtained by multiplying the frequency by two, and the x portion indicates the sampling timing. Then, it is shown that the drive data SDATA and the common clock CK are acquired in synchronization with the rising edge of the sampling clock Φ and become the drive data SDATA ′ and the common clock CK ′.

  As shown in the figure, in the case of adopting this configuration, the frequency of all signals including the clock signals (CK0 to CKn) is sufficient to be 1/2 or less of the sampling clock Φ. However, since the acquisition timing is delayed (phase shift), the frequency of all signals including the clock signals (CK0 to CKn) is preferably 1/10 or less of the sampling clock Φ.

  Even if the clock signals CK0 to CKn of the drive data are not shared, the frequency ratio is set to an integer ratio and the maximum frequency is set to 1/2 or less (preferably 1/10 or less) of the sampling clock Φ. If the phases are aligned, the problem of acquisition omission can be solved as in the case of FIG.

  In the above embodiment, the signal line of the serial sensor signal SN is a single end signal, but it goes without saying that it may be a differential signal. Further, although the transmitter 47 and the receiver 50 are used for serial transmission from the board side member GM2 to the frame side member GM1, it goes without saying that they may be used in other parts. Further, for the sake of convenience, the bullet ball game machine has been described, but it is needless to say that it can also be suitably applied to other game machines including a spinning cylinder game machine.

GM gaming machine 22 effect control means 47 transmission means 50 reception means Φ clock signal TX +, TX− composite serial signal So serial port SDATAi serial drive signal CKi clock signal

Claims (9)

A gaming machine that performs all or part of the rendering operation of the image effect, the lamp effect, or the sound effect corresponding to the lottery result of the predetermined lottery process,
The production control means for controlling the production operation is configured to output a serial drive signal defining production content together with a clock signal via a serial port.
Transmitting means for acquiring the serial drive signal and the clock signal every predetermined time in synchronization with a sampling signal, and outputting the acquired signal together with other acquired signals to a pair of differential signal lines as a composite serial signal When,
Receiving means for extracting all acquired signals from the composite serial signal and restoring the sampling signal, connected to the transmitting means through the pair of differential signal lines. A gaming machine.   The gaming machine according to claim 1, wherein a plurality of serial drive signals and clock signals are output via a plurality of serial ports, and all of them are output from the transmission means as composite serial signals.   Via multiple serial ports, multiple clock signals are output corresponding to multiple serial drive signals, or a common clock signal is output corresponding to multiple serial drive signals The gaming machine according to claim 2.   The gaming machine according to claim 1 or 2, wherein the serial drive signal output from the predetermined serial port includes a serial signal that defines a drive mode of the effect motor.   The gaming machine according to any one of claims 1 to 4, wherein the other acquired signals include a multi-bit audio serial signal that defines the content of an audio effect and an audio clock signal. It is a gaming machine divided into a board side member that is changed for each model and a frame side member that can be used in common with different models,
The gaming machine according to claim 1, wherein the transmission unit is arranged on the frame side member, and the reception unit is arranged on the frame side member.   The gaming machine according to claim 6, wherein all signals transmitted from the board-side member to the frame-side member are transmitted by the transmitting means.   All the signals transmitted and received between the board side member and the frame side member are transmitted by a pair of differential signal lines and another one or a pair of serial signal lines. The gaming machine described. The acquisition signal includes a plurality of clock signals,
The gaming machine according to claim 1, wherein a frequency of the sampling signal is set to be twice or more a maximum frequency of the plurality of clock signals.

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