JP2013150740A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine that is free from waste in transmission processing of serial data and its control operation.SOLUTION: A presentation control part 22' for performing a lamp presentation includes: a control circuit board 22 for controlling a lamp presentation; a plurality of lamp driving boards 37, ... each mounted with the driving circuit of the same structure for performing a lamp presentation by driving a lamp; and a relay board 29 for receiving a lamp driving signal as a serial signal from the control circuit board and for transferring it to all lamp driving boards. At least a part of the address numbers of the driving circuit DRi mounted on the lamp driving board is each regulated on the basis of the address signal received from the relay board 29, while the lamp driving signal is transmitted by specifying the driving circuit for receiving it.

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine that can stably execute various powerful effects.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

  The above-mentioned performance operation is centered on the image production on the liquid crystal display device. In conjunction with this image production, a lamp production that blinks various lamps, an audio production that outputs a sound that excites the player, Movable effects such as moving animals are executed. As the game effects are enriched, the wiring becomes more complicated and the power consumption increases. Therefore, a circuit configuration capable of suppressing the number of wirings and power consumption as much as possible is required.

  In addition, in this type of gaming machine, individuality for each model is emphasized, but there is a demand for a device configuration that can unify circuit boards as much as possible while having individuality rich in variations for each model. For example, if the circuit board can be shared between a model that greatly increases the number of lamps and appeals the lamp effect, and a model that suppresses the number of lamps and distributes the power consumption with room for other effects, the production cost Can be suppressed.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a gaming machine that can suppress the number of wires and power consumption and can share many circuit boards.

  In order to achieve the above object, the present invention comprises a main control unit that centrally controls a game operation by lottery determination as to whether or not to generate a gaming state advantageous to a player based on a predetermined switch signal; An effect control unit that executes a lamp effect for causing a plurality of lamps to emit light based on a control command output by the main control unit, wherein the effect control unit includes the lamp A control circuit board for controlling the presentation, a plurality of lamp driving boards each equipped with a drive circuit having the same configuration for driving the lamp to execute the lamp presentation, and receiving the lamp driving signal from the control circuit board as a serial signal And a relay board that transfers this to all the lamp drive boards, and at least part of the address numbers of the drive circuits mounted on the lamp drive board is received from the relay board. Each is defined on the basis of the address signal, the lamp driving signal is transmitted to identify the driver circuit to receive it.

  In the present invention, since the lamp driving signal is transmitted as a serial signal, the number of wirings does not increase correspondingly, no matter how much the lamp effect is enriched. In addition, a plurality of lamp drive boards each equipped with a drive circuit having the same configuration for driving a lamp to execute a lamp effect, and a lamp drive signal received as a serial signal from the control circuit board, all of the lamp drive boards are received. Therefore, it is possible to use a common lamp driving board, and it is possible to deal with a large number of models simply by changing the relay board.

  Preferably, the address signal is fixedly set in advance based on a hardware configuration of the relay board or an upstream circuit board, and the address number is defined by a plurality of bits, and all or a part of the address number is defined. Bits are defined by the address signal and the remaining bits are defined in the lamp driving board.

  Preferably, the drive circuit operates in response to a serial signal including the lamp drive signal, a control signal indicating that the serial signal is being transmitted, and a serial signal transmission clock signal. It is. The serial signal preferably includes the lamp driving signal and an address number for specifying a driving circuit to receive the lamp driving signal. In this case, the number of wirings is determined. Further suppression can be achieved.

  If the serial signal is generated in a general-purpose computer circuit of the control circuit board, the circuit configuration can be simplified. Preferably, the drive circuit includes a control register that determines a drive mode, and desired control data is set in a predetermined control register based on the lamp drive signal.

  It is preferable that the driving mode includes, in addition to the lighting / extinguishing state of the lamp, the presence / absence of a fade operation until the lighting / extinguishing state and / or the light emission duty ratio by PWM control. In this case, the lamp effect can be further enriched.

  The general-purpose computer circuit should preferably operate with a power supply voltage of 3.5 V or less, and the control circuit board operates with a power supply voltage of 3.5 V or less and generates a sound signal for sound production. It is preferable that a circuit is mounted.

  As described above, according to the gaming machine of the present invention, it is possible to realize a gaming machine that can suppress the number of wires and power consumption and can share many circuit boards.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a circuit diagram which shows the connection relation of a lamp connection board | substrate and a lamp drive board | substrate. It is a block diagram illustrating a circuit configuration of an effect control unit. It is a block diagram which illustrates the internal structure of a motor / lamp drive board | substrate. It is a block diagram which illustrates the internal structure of a digital amplifier. It is a block diagram which illustrates the circuit structure of an image control part. 2 is a diagram illustrating an internal configuration and operation of a power supply sequence circuit.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, at the upper left and right positions and the lower side of the glass door 6, all three speakers are arranged. The two speakers arranged in the upper part are each configured to output sound of the left and right channels R and L, and the lower speaker is configured to output heavy bass.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided on the surface of the game board 5 in an annular shape, and a central opening HO is provided at the approximate center thereof. A movable effect body (not shown) is housed in a concealed state below the central opening HO, and at the time of a movable notice effect, the movable effect body rises into an exposed state so that a predetermined reliability can be obtained. The notice effect is realized. Here, the notice effect is an effect that informs indefinitely that a big hit state advantageous to the player will occur, and the reliability of the notice effect means the probability that the big hit state will result.

  A main display device DS1 composed of a large liquid crystal color display (LCD) is disposed in the central opening HO, and a movable sub display device composed of a small liquid crystal color display is disposed on the right side of the main display device DS1. DS2 is arranged.

  The main display device DS1 is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. The display device DS1 has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. In the special symbol display portions Da to Dc, there is a case where a reach effect that expects a big hit state is invited, and in the special symbol display portions Da to Dc and the surroundings, an appropriate notice effect is executed.

  The sub display device DS2 normally displays the image information in a stationary state in which the display screen is inclined at an angle that is easy for the player to see. However, at the time of a predetermined notice effect, while moving to the left side of the figure while changing the inclination angle to an angle that is easy for the player to see, a predetermined notice image is displayed.

  That is, the sub display device DS2 of the embodiment functions not only as a display device but also as a movable effect body that executes a notice effect. Here, the announcement effect by the sub display device DS2 is set with high reliability, and the player pays attention to the moving operation of the sub display device DS2 with a great sense of expectation.

  In the game area in which the game ball falls and moves, the first symbol start port 15a, the second symbol start port 15b, the first big winning port 16a, the second big winning port 16b, the normal winning port 17 and the gate 18 are arranged. It is installed. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  On the upper part of the first symbol starting port 15a, there is arranged an effect stage 14 configured to be able to win a prize in the first symbol starting port 15 after the game ball entering from the introduction port IN moves in a seesaw shape or a roulette shape. Yes. And when a game ball wins the 1st symbol starting port 15, it is comprised so that the fluctuation | variation operation | movement of the special symbol display parts Da-Dc will be started.

  The second symbol start port 15b is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws. When the stop symbol after fluctuation of the normal symbol display unit 19 displays a winning symbol, a predetermined symbol is displayed. The opening / closing claw is opened only for a time or until a predetermined number of game balls are detected.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the selected lottery random value is displayed and stopped.

  The first big prize opening 16a is configured with a slide board that advances and retreats in the front-rear direction, and the second big prize opening 16b is configured with an opening / closing plate that is pivotally supported at the lower end and opens forward. . The operation of the first grand prize opening 16a and the second big prize opening 16b is not particularly limited. In this embodiment, the first big prize opening 16a corresponds to the first symbol start opening 15a, and the second big prize opening 16b is comprised corresponding to the 1st symbol starting port 15b.

  That is, when a game ball is won at the first symbol start opening 15a, the changing operation of the special symbol display portions Da to Dc is started. After that, when the predetermined big hit symbol is aligned with the special symbol display portions Da to Dc, the first big hit A special game is started, and the slide board of the first big winning opening 16a is opened forward to facilitate the winning of a game ball.

  On the other hand, when a predetermined big hit symbol is aligned with the special symbol display portions Da to Dc as a result of the fluctuating motion started by winning the game ball in the second symbol start opening 15b, a special game corresponding to the second big hit is started, The open / close plate of the two major winning openings 16b is opened to facilitate the winning of game balls. The game value of a special game (hit state) varies according to the jackpot symbols to be arranged, but which game value is given depends on the lottery result according to the winning timing of the game ball. Determined in advance.

  In a typical big hit state, the opening / closing plate closes when a predetermined time elapses after the opening / closing plate of the big winning opening 16 is opened or when a predetermined number (for example, 10) of game balls wins. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations, and FIGS. 4 to 8 show a part of the details in detail. As shown in FIG. 3, the pachinko machine GM receives 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. Main control board 21 that centrally handles the sound, an effect control board 22 that executes a lamp effect and a sound effect based on a control command CMD received from the main control board 21, and a control command CMD ′ received from the effect control board 22 An image control board 23 that drives the display devices DS1 and DS2 based on the control device 24, a payout control board 24 that controls the payout motor M based on the control command CMD "received from the main control board 21, and pays out a game ball; And a launch control board 25 that launches a game ball in response to a user's operation.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. The control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27 and the image interface board 28, and is output from the main control board 21. Is transmitted to the payout control board 24 via the main board relay board 32. Although the control commands CMD, CMD ′, and CMD ″ are all 16 bits long, the main control board 21 and the payout control board 24 are used. The control commands related to are transmitted in parallel every two 8 bit lengths. On the other hand, the control command CMD 'transmitted from the effect control board 22 to the image control board 23 is 16 bits in length and transmitted in parallel. Therefore, even when the notification effects including the movable notification effect are diversified and a large number of control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  By the way, in the present embodiment, the production interface board 27 and the production control board 22 are directly connected to each other by a male connector and a female connector without passing through a wiring cable, and two circuit boards are laminated. . Similarly, with respect to the image interface board 28 and the image control board 23, two circuit boards are laminated by directly connecting a male connector and a female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Therefore, in this specification, the control board 21 to 24, the circuits mounted on the interface boards 27 to 28, and the operations realized by the circuits are generically named. May be referred to as a section 22 ′, an image control section 23 ′, and a payout control section 24. That is, in this embodiment, the effect control board 22 and the effect interface board 27 constitute an effect control part 22 ′, and the image control board 23 and the image interface board 28 constitute an image control part 23 ′. . Note that all or part of the effect control unit 22 ′, the image control unit 23 ′, and the payout control unit 24 are sub-control units.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 35. Each is fixed in place on the front frame 3. On the other hand, a main control board 21, an effect control board 22, and an image control board 23 are fixed to the back of the game board 5 together with the display devices DS1 and DS2 and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power relay board 33 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The effect interface board 27 outputs the received system reset signal SYS to the effect control unit 22 'and the image control unit 23' as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been applied to the power supply board 20, and one of the effect control unit 22 ′ and the image control unit 23 ′ is generated by the power supply reset signal. The chip microcomputer is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The production control unit 22 ′ and the image control unit 23 ′ perform production operations dependently on the basis of the control command from the main control unit 21, so that the power supply board 20 is avoided in order to avoid complication of the circuit configuration. The system reset signal SYS output from is used.

  By the way, the reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and unless a regular clear pulse is received from the CPUs of the control units 21 and 24, Each CPU is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. The initialization switch SW operated by the attendant is turned on. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As described above, the effect control board 22 and the effect interface board 27 are integrated by connector connection, and the effect control unit 22 ′ is connected to each level from the power supply board 20 via the power relay board 33. A DC voltage (5V, 12V, 32V) and a system reset signal SYS are received (see FIGS. 3 and 5). Further, the effect control unit 22 'receives the control command CMD and the strobe signal STB from the main control unit 21 via the command relay board 26 (see FIGS. 3 and 5).

  Then, the effect control unit 22 ′ outputs the serial signal DATA including the lamp driving signal to a plurality of (four in the embodiment) lamp driving substrates 37... Via the lamp connection substrate 29. Thus, a large number of LED lamps and decorative lamps (lamp groups) are driven (see FIGS. 3 to 5). As shown in FIG. 4, the four lamp driving boards 37... All have the same circuit configuration, and the number thereof is appropriately increased or decreased for each model of gaming machine.

  On the other hand, the lamp connection board 29 is prepared for each type of gaming machine corresponding to the number of lamp drive boards 37... In the embodiment of FIG. It has an internal configuration corresponding to That is, the lamp connection board 29 of the embodiment is configured to have four buffer circuits BUF corresponding to the four lamp driving boards 37..., From the effect control unit 22 ′ (one-chip microcomputer 40). The received three types of signals (EN, DATA, CK) are transferred to each lamp driving substrate 37 via the buffer circuit BUF. Specifically, the three types of signals are an operation control signal EN, a serial signal DATA including a lamp driving signal, and a transfer clock signal CK.

  Further, the lamp connection board 29 has a 2-bit length address signal for specifying each lamp drive board 37 (specifically, the drive circuit DRi), DC 13V and 5V received from the effect interface board 20, and a reset signal RST. Are transmitted to each lamp drive substrate 37 together with the ground signal GND. The direct current 13V is a driving power source supplied to the lamp group, and the direct current 5V is a power source voltage of the driving circuits DR1 to DR4 that drive the lamp group. The reset signal RST is generated based on the system reset signal SYS received from the power supply board 20, and resets the power of the drive circuits DR1 to DR4 when the power is turned on.

  As shown in FIG. 4, each lamp driving substrate 37 is mounted with one driving circuit DR1 to DR4 having the same internal configuration numbered by the 5-bit data (address number) of the address terminals A0 to A4. As shown in the figure, in all the drive circuits DR1 to DR4, the lower 3 bits of the address terminal are set to 0 in advance, and the upper 2 bits are fixedly set by an address signal received from the lamp connection board 29.

  Therefore, in this embodiment, the address numbers of the drive circuits DR1 to DR4 are fixedly assigned 00000, 01000, 10000, and 11000 based on the 2-bit length address signal transmitted from the lamp connection board 29. It will be. Since the present embodiment adopts such a configuration, when changing the number of lamps according to the model of the gaming machine, the lamp connection board 29 is replaced and the number of lamp driving boards 37. It is only necessary to change, and it is not necessary to change the other circuit configuration, so that a circuit board other than the lamp connection board 29 can be shared.

  The drive circuit DR is a circuit that receives the serial signal DATA including the lamp drive signal based on the operation control signal EN and the transfer clock signal CK, converts the received lamp drive signal into parallel, and outputs it. Although a specific circuit configuration is not particularly limited, the drive circuit DR of the embodiment includes a large number of control registers R1 to Rm, and sets control data Di (8-bit length) in each of the control registers R1 to Rm ( By using the driver IC, the outputs of the 16-bit output terminals are appropriately controlled.

  Here, the register numbers of the control registers R1 to Rm are 8 bits long. As described above, the 5-bit address terminals (A0 to A4) including the 2-bit length from the lamp connection board 29 are set to the H / L level in advance, and each drive circuit DR1 to The address numbers of DR4 are 00H, 08H, 10H, and 18H in this embodiment.

  The operation contents realized by setting the control data Di in each control register R1 to Rm include not only the ON / OFF state of each output terminal but also the fade operation (fade in / out) until reaching the ON / OFF state. ) And the duty ratio (0 to 99.6%) in the PWM control of the output terminal in the ON state. Therefore, the one-chip microcomputer 40 does not need to bother to change the lamp drive signal (serial data) for PWM control at the time of brightness control or fade in / out effect, and simply changes the control data of the corresponding register Ri. As a result, the control burden is greatly reduced.

  Of course, by controlling the lamp driving signal by PWM, it is possible to implement a unique fade in / out effect different from the fixed fade operation. In short, according to this embodiment, various lamps can be used. Production is possible.

  FIG. 4B is a time chart showing a communication protocol between the one-chip microcomputer 40 and the plurality of drive circuits DR1 to DR4. As shown in the figure, the one-chip microcomputer 40 first sets the operation control signal EN to the ON state (H level), and (1) the address number ADRi (8) of the drive circuits DR1 to DR4 to which the control data Di is to be written. (2) extended to the bit length), (2) the number of the control registers R1 to Rm (8-bit length) in which the control data Di in the drive circuit DRi is to be written, and (3) the control data Di (8 The bit length set value) is output as a serial signal DATA in synchronization with the transfer clock signal CK.

  If the first register number Ri is designated for a series of control registers R1 to Rm, the subsequent control data (set values) D1, D2, R3... Are represented by Ri, Ri + 1, Ri + 2. The control data is recognized by the drive circuit DRi and automatically acquired. Therefore, it is not always necessary to set a set value in all the control registers Ri. For example, in the case of a write process to a series of M control registers Ri to Ri + M−1, M pieces of control data and two pieces of address data Therefore, a total output process of 8 × (M + 2) bits is sufficient.

  When the output of all data is completed, the one-chip microcomputer 40 may return the operation control signal EN from the ON state to the OFF state, and the drive circuit DR specified by the address number ADRi corresponds to this operation. The operation corresponding to the control data D1... Acquired in the series of control registers Ri.

  As shown in FIG. 3 and FIG. 5, the effect control unit 22 ′ drives the lamp group by outputting the lamp drive signal and the motor drive signal to the motor / lamp drive board 30 as well as a plurality of stepping motors. The configured production motor groups M1 to Mn are driven. Here, since the lamp drive signal and the motor drive signal are output as serial signals having the same configuration as the serial signal DATA of FIG. 4, no matter how the number of lamps or the number of effect motors is increased in order to enrich the effect contents, The number of wiring cables does not increase, and the device configuration is simplified. The lamp group realizes the lamp effect almost constantly, while the effect motor group suddenly starts operation to realize the movable notice effect by the movable effector.

  In addition, the effect control unit 22 ′ sends a control command CMD ′ and a strobe signal STB ′ to the image control unit 23 ′, a system reset signal SYS received from the power supply board 20, and two types of DC voltages (12V, 5V). ) (See FIGS. 3 and 5).

  The image controller 23 'drives the main display device DS1 based on the control command CMD' to execute various image effects. As shown in FIG. 5, the main display device DS1 emits light by the LED backlight, and five pairs of LVDS (Low voltage differential signaling) signals from the image interface board 28 and the backlight power supply voltage ( 12V) and is driven. The backlight of the main display device DS1 is configured to be able to control the luminance by PWM control.

  Further, the image control unit 23 ′ executes an appropriate notice effect on the sub display device DS <b> 2 as the notice effect based on the control command CMD ′. The sub display device DS2 also emits light by backlight, and is configured to be able to control its ON / OFF state.

  The sub display device DS2 is driven by the relay board 36 that receives the backlight power supply voltage (5V) and the V-by-One (registered trademark) signal from the image interface board 28, and at the time of the notice effect, the effect control unit The effect motor Mi controlled by 22 'is driven synchronously, and a movable effect is executed.

  Next, the configuration of the above-described effect control unit 22 'and image control unit 23' will be described in more detail with reference to FIG. As shown in FIG. 5, the effect interface board 27 receives three types of DC voltages (5 V, 12 V, and 32 V) from the power board 20 via the power relay board 33. Here, the DC voltage 5 V is a power supply voltage of the digital logic circuit, and the rendering interface board 27, the lamp connection board 29 and the lamp driving board 37, the motor / lamp driving board 30, the image interface board 28, and the image Power is distributed to the control board 23 to operate each digital circuit.

  However, the direct current voltage 5V is not distributed on the effect control board 22, and the direct current voltage 3.3V stepped down from 12V by the DC / DC converter and the direct current stepped down from 3.3V by the DC / DC converter. Only the voltage 1.8V is distributed from the production interface board 27 to the production control board 22. As described above, the production control board 22 of the present embodiment is driven by the power supply voltage 3.3V, so that the power can be significantly reduced compared to the case where the power supply voltage is operated at 5V. For example, even if the production interface board 27 is arranged and laminated immediately above the production control board 22, there is no problem in heat dissipation.

  The direct current voltage 12V received from the power supply board 20 by the effect interface board 27 is directly used as the power supply voltage of the digital amplifier 46 and is distributed to the motor / lamp drive board 30. On the other hand, the direct current voltage 32V received from the power supply board 20 is stepped down to the direct current voltage 13V by the DC / DC converter of the production interface board, and is supplied to the lamp connection board 29, the lamp drive board 37, and the motor / lamp drive board 30. Power distribution.

  As shown in FIG. 5, the effect control unit 22 ′ includes a one-chip microcomputer 40 that executes processing such as a sound effect, a lamp effect, a notice effect by an effect movable body, and data transfer, and a control program for the one-chip microcomputer 40. A flash memory 41 to be stored, a voice synthesis circuit 42 that reproduces and outputs a voice signal based on an instruction from the one-chip microcomputer 40, and compressed voice data that is original data of the reproduced voice signal are stored. And an audio memory 43 that is configured.

  Here, the one-chip microcomputer 40, the flash memory 41, and the voice memory 43 operate at a power supply voltage of 3.3V, and the voice synthesis circuit 42 operates at a power supply voltage of 3.3V and a power supply voltage of 1.8V. It operates and significant power saving is realized. 1.8V is the power supply voltage of the computer core part of the speech synthesis circuit, and 3.3V is the power supply voltage of the I / O part.

  The one-chip microcomputer 40 includes a plurality of parallel input / output ports PIO. The control command CMD and the strobe signal STB from the main control unit 21 are input to the first input port PO1, and the control command CMD ′ and the strobe signal STB ′ are output from the second input port PO2. Has been.

  Specifically, the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 are supplied to the first input port PO1 at the power supply voltage 3.3V in the buffer 44 of the effect interface board 27. Is converted to a logic level corresponding to, and supplied in units of 8 bits. The interrupt signal STB is supplied to the interrupt terminal of the one-chip microcomputer, and the effect control unit 22 'is configured to acquire the control command CMD by the reception interrupt process.

  The control command CMD acquired by the effect control unit 22 ′ includes (1) an abnormality notification and other notification control commands, and (2) control for specifying an outline of various effect operations resulting from winning at the symbol start opening. A command (variation pattern command) and a control command (symbol designation command) for designating a symbol type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the change pattern command is acquired, the effect control unit 22 ′ performs an effect lottery subsequently to further specify the effect outline specified by the acquired change pattern command. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking LEDs and a sound effect preparation operation by a speaker are performed, and an effect operation by a lamp or speaker is performed on the image control unit 23 ′. A control command CMD ′ relating to the synchronized image effect is output.

  In order to realize such an image effect synchronized with the effect operation, the effect control unit 22 ′ controls the 16-bit length together with the strobe signal (interrupt signal) STB ′ for the image control unit 23 ′ through the second input port PO2. The command CMD ′ is output toward the effect interface board 27. In addition, when the production control unit 22 ′ receives a design designation command, a notification control command related to the display device DS1, and other control commands, the control command is summarized in a 16-bit length. It is output toward the production interface board 27 together with the interrupt signal STB ′.

  Corresponding to the configuration of the production control board 22 described above, the production interface board 27 is provided with an output buffer 45, and a 16-bit control command CMD ′ and a 1-bit interrupt signal STB ′ are sent to the image interface. It is output to the substrate 28. These data CMD ′ and STB ′ are transmitted to the image control board 23 via the image interface board 28.

  The effect interface board 27 is provided with a digital amplifier 46 that receives the audio signal output from the audio synthesis circuit 42. As described above, the speech synthesis circuit 42 operates with power supply voltages of 3.3 V and 1.8 V, and the digital amplifier 46 performs class D amplification operation with a power supply voltage of 12 V, reducing power consumption. It is possible to produce a loud sound while suppressing it.

  The left and right speakers at the upper part of the gaming machine and the speakers at the lower part of the gaming machine are driven by the output of the digital amplifier 46. Therefore, the voice synthesis circuit 42 needs to generate a three-channel voice signal, and if this is transmitted in parallel, the wiring between the voice synthesis circuit 42 and the digital amplifier 46 becomes complicated.

  Therefore, in this embodiment, the voice synthesis circuit 42 and the digital amplifier 46 are connected by four signal lines in order to prevent deterioration of sound quality and avoid complicated wiring. In this case, the transfer clock signal SCLK, the channel control signal LRCLK, and the 2-bit length serial signals SDATA1 and SDATA2 are suppressed to a total of 4 bit signal lines. Note that the amplitude level of any signal is 3.3V.

  Here, SDATA1 is a serial signal for PCM data specifying the stereo signals R and L of the left and right speakers arranged at the upper part of the gaming machine, and SDATA2 is a monaural signal of the heavy bass speaker arranged at the lower part of the gaming machine. This is a serial signal for the PCM data to be specified. The voice synthesis circuit 342 transmits the left channel audio signal L while maintaining the channel control signal LRCLK at the L level, and maintains the channel control signal LRCLK at H level while maintaining the channel control signal LRCLK at the L level. Is transmitted. Note that since there is only one heavy bass speaker in this embodiment, a monaural audio signal is transmitted, but it is of course possible to transmit it as a stereo audio signal.

  In any case, in this embodiment, four types of audio signals can be transmitted with four cables, and therefore, signal transmission without audio deterioration due to noise can be performed with the minimum number of cables. That is, since it is serial transmission, the number of cables is far smaller than that of parallel transmission. Note that when analog transmission is employed, the number of cables is the same, but noise is superimposed on an analog signal having an amplitude of 3.3 V, and the sound quality is greatly deteriorated. On the other hand, when the amplitude level is increased, the power supply wiring becomes complicated and the power consumption increases.

  Such serial signals SDATA1 and SDATA2 are acquired by the digital amplifier 46 in synchronization with the rising edge of the clock signal SCLK. In the digital amplifier 46, parallel conversion is performed for each predetermined bit length, and after D / A conversion, D-class amplification is performed and supplied to each speaker.

  Although the internal configuration of the digital amplifier 46 is appropriate, FIG. 7 shows an internal configuration diagram when YDA171 (YAMAHA) is used as the digital amplifier. Although it is not limited to such an internal configuration, in any case, in this embodiment, since the voice synthesis circuit 42 and the digital amplifier 46 are connected by a serial line, the bit length of the PCM data (voice data) is increased. Even if the sound quality is improved, it is not necessary to change the wiring cable and the like, and the circuit configuration can be simplified.

  In addition, the effect interface board 27 is provided with buffer circuits 47 and 48 for outputting serial data output from the one-chip microcomputer 40. Here, the output buffer 47 transfers the three types of signals (EN, DATA, CK) transmitted from the one-chip microcomputer 40 to the four lamp driving boards 37 via the lamp connection board 29, This point is as described with reference to FIG. Then, in the drive circuits DR1 to DR4 of the lamp drive substrate 37, the lamp drive signal is extracted from the serial signal DATA based on the operation control signal EN and the transfer clock signal CK, and the lamp drive signal is converted into a parallel signal. As described above, the lamp group is driven.

  The other buffer circuit 48 functions as an input / output buffer and transfers the serial signal transmitted from the one-chip microcomputer 40 to the motor / lamp drive board 30 as it is, while the origin of the group of effect motors M1 to Mn. An origin sensor signal (serial signal) indicating the position is transferred to the one-chip microcomputer 40.

  In the case of the present embodiment, the serial signal transmitted from the one-chip microcomputer 40 to the buffer circuit 48 includes a lamp driving signal (serial signal) for lighting the lamp group and a motor driving signal (serial) for rotating the effect motor. Signal) is continuous. The motor / lamp drive board 30 divides the series of serial signals into 16-bit lengths and converts each 16-bit length into a parallel signal to execute a lamp effect and a movable notice effect. Specifically, a series of lamp effects is executed as the effect operation determined by lottery in response to the control command CMD, and when a motor drive signal is received, the effect motors M1 to Mn are rotated to appropriately A movable notice effect is being executed.

  FIG. 6A is a block diagram specifically showing the circuit configuration of the motor / lamp drive board 30. As shown in the figure, the motor / lamp drive board 30 includes a PS converter 50 that serially converts the origin sensor signals of the effect motors M1 to Mn, and an input buffer 51 that receives a control signal for the PS converter 50 from the one-chip microcomputer 40. A step-down unit 52 that steps down the DC voltage 13V to 12V, an input buffer 53 that receives a lamp drive signal and a motor drive signal from the one-chip microcomputer 40, and drive control units 54 and 55 that drive and control a lamp group and a production motor group. The sink driver 56 receives the drive current of each effect motor.

  Note that the PS converter 50, the input buffers 51 and 53, the drive controller 54, and the sink driver 56 operate using a DC voltage of 5V as a power supply voltage.

  The origin sensor signal is an output of an origin sensor that detects whether or not the production motors M1 to Mn are located at the origin, and each origin sensor uses a DC voltage of 12V or 5V as a power supply voltage. These 1-bit and n-bit origin sensor signals are acquired by the PS converter 51 in synchronization with the hold signal LOAD output from the one-chip microcomputer 40, and the PS converter 51 receives the transfer received from the one-chip microcomputer 40. In synchronization with the clock CK, the origin sensor signal is converted into a serial signal and transmitted to the one-chip microcomputer 40.

  As described above, in this embodiment, the one-chip microcomputer 40 can appropriately grasp whether or not each effect motor M1 to Mn is located at the origin. In addition, the possibility of misjudgment is greatly reduced by using a DC voltage (12V, 5V) of a different system from the power supply line (13V) where electromagnetic noise may be superimposed as the power supply voltage of each origin sensor. I am letting.

  Next, in the step-down unit 52, the input side 13V is used as a driving power source for each lamp, the output side 12V is used as a driving power source for the effect motors M1 to Mn, and the power source lines are separated from each other. Further, as described above, the input buffer 53 and the drive control units 54 and 55 use the DC voltage 5V generated in a completely different system from the DC voltage 13V as the power supply voltage.

  Therefore, even if the large production motor groups M1 to Mn suddenly start operation, there is a very low possibility that the lamp drive signal of each lamp is affected by power supply noise or the like. Similarly, even if the lamps are flashed violently with high luminance, the possibility that the motor drive signals of the effect motors M1 to Mn are affected by power supply noise or the like is extremely low.

  By the way, both the drive control unit 54 for the production motor and the drive control unit 55 for the lamp have the same configuration as the drive circuit DRi shown in FIG. It operates by receiving the signal DATA and the transfer clock signal CK in common. The serial signal DATA includes a lamp driving signal and a motor driving signal.

  Similarly to the drive circuit DRi in FIG. 4, the drive control units 54 and 55 also have 5-bit address terminals (A0 to A4), and are configured so that addresses can be assigned appropriately. The address terminals (A0 to A4) having a 5-bit length are fixedly assigned in advance to the H level or the L level in the motor / lamp driving board 30 as a hardware configuration. However, as in the case of the circuit configuration shown in FIG. 4, all or a part of the address terminals (A0 to A4) may be transmitted from the upstream circuit board.

  As described above, by setting the control data Di in each of the control registers R1 to Rm, not only the ON / OFF state of each output terminal but also the fade operation up to the ON / OFF state (fade in / out) The duty ratio (0 to 99.6%) in the PWM control of the output terminal in the ON state can be made. 6B is a time chart showing a communication protocol between the one-chip microcomputer 40 and the plurality of drive control units 54, 55... 55, and the operation content is related to FIG. As explained.

  Since the production motors M1 to Mn are operated as a movable notice production, the production motors M1 to Mn are normally waiting at the origin position in a concealed state. Accordingly, the drive control unit 54 retains the control data in the OFF state, and normally it is not necessary to receive control data transfer from the one-chip microcomputer 40. However, since the control drive unit of this embodiment specifies the address number ADRi and receives the control data Di, there is no influence on the drive control unit 54 that is not designated by the address number even if the serial signal is repeatedly transferred. Don't give.

  Therefore, according to the configuration of the present invention, the drive control unit 55... 55 for controlling the lamp that continuously repeats the dynamic lamp effect and the drive control unit 54 for the movable notice effect that rarely starts the notice operation. Can have the same configuration. In addition, the one-chip microcomputer 40 can handle the motor drive signal and the lamp drive signal in the same row except for determining whether or not to add the motor drive signal to the lamp drive signal. The burden can be reduced.

  In addition, by setting all or part of the drive control units 55, 55 for lamp control to the same address number, it is possible to combine the transfer processing of lighting data (control data) relating to a large number of lamps, and to provide effect control. The control burden on the unit 22 is reduced. For example, when the right and left lamp groups of the gaming machine are always caused to emit light in the same manner, a drive control unit 55R for driving the right lamp group and a drive control unit 55L for driving the left lamp group are provided. By simply setting the same address number, the lighting data transfer process can be completed in one time.

  FIG. 8 is a circuit block diagram illustrating in detail the image control unit 23 ′ (image interface board 28 and image control board 23) including the surrounding boards. As described above, the image control unit 23 'operates by receiving the control command CMD', the strobe signal STB ', and the system reset signal SYS from the effect control unit 22'. In addition, two types of DC voltages 5V and 12V are received via the production control unit.

  As shown in the figure, the image control unit 23 ′ receives a control command via the effect interface board 27 and executes an image control operation, and a flash that stores a control program of the one-chip microcomputer 60 and the like. Work of the memory 61, a VDP (Video Display Processor) 62 for driving the display devices DS1 and DS2 based on an instruction from the one-chip microcomputer 60, a graphic ROM (CGROM) 63 for storing image compression data for image production, and the VDP 62 An SDRAM (Synchronous Dynamic Random Access Memory) 64 functioning as an area (Video RAM), a watchdog timer WDT for forcibly resetting the one-chip microcomputer 60, and the like are configured.

  As shown in the figure, the output of the watchdog timer WDT is supplied to the OR circuit together with the system reset signal SYS. When one of the input signals to the OR circuit becomes an active level, the one-chip microcomputer 60 and the VDP 62 are synchronized. To be reset. Therefore, when the control operation is initialized due to the program runaway of the one-chip microcomputer 60, the operation of the VDP 62 is initialized correspondingly, and the contradictory and unnatural image effect is executed. It will not be done.

  In this embodiment, the power supply voltage of each element is minimized in order to suppress the power consumption as much as possible. The power supply voltage of each element is (1) the one-chip microcomputer 60 is 3.3V and 1.25V. (2) Flash memory 61 is 1.25V, (3) VDP62 is 3.3V, 1.8V and 1.1V, (4) CGROM 63 is 3.3V, and (5) SDRAM 64 is 1.8V. .

  As described above, in this embodiment, a large number of DC voltages are required to save power, and the supply timings of circuit elements having a plurality of power supply voltages need to be optimized. On the other hand, only two types of direct current voltages are distributed for the purpose of suppressing the number of wiring cables between the effect control unit 22 'and the image control unit 23'.

  Therefore, by arranging a plurality of DC / DC converters having control terminals and providing a power sequencer 65, a large number of DC voltages are supplied to each element at an optimal timing. FIG. 9 shows an internal configuration (a) of LM3881 (national semiconductor) as an example of the power sequencer 65 and an operation time chart (b) executed even when the power sequencer 65 is used.

  In the case of the power sequencer 65 in FIG. 9A, when the INV terminal is at the L level, the operation starts in response to the operation start command EN at the H level, and the clock defined by the capacitance connected to the TADJ terminal. The first control signal PCNT1 rises after nine cycles of the signal Clock, the second control signal PCNT2 rises after eight cycles of the clock signal, and the third control signal PCNT3 rises after another eight cycles of the clock signal.

  On the other hand, when the operation start command EN transitions to the L level, the third control signal PCNT3 falls after 9 cycles of the clock signal, the second control signal PCNT2 falls after 8 cycles of the clock signal, and further 8 cycles after the clock signal. The third control signal PCNT3 falls.

  In the present embodiment, as shown in FIG. 8, the operation start command EN is an AND logic output of two types of DC voltages supplied from the effect control unit 22 '(effect interface board 27). The first control signal PCNT1 is supplied to the operation enable terminal EN of the DC / DC converter V1 for generating 1.1V, and the second control signal PCNT2 is an operation enable for the DC / DC converter V2 for generating 3.3V. It is supplied to the terminal EN.

  The third control signal PCNT3 is converted into an AND logic output with 3.3V and supplied to the operation enable terminal EN of the DC / DC converter V3 for generating 1.8V. Each DC / DC converter described above starts the voltage conversion operation on condition that the operation enable terminal EN becomes H level.

  Therefore, as shown in FIG. 9B, the DC / DC converter V1 first functions based on 5V distributed from the effect control unit 22 'to generate the DC voltage 1.1V. This DC voltage 1.1V is a power supply voltage for the digital circuit and the built-in VRAM built in the VDP 62, and the normal operation start sequence of the VDP 62 after the power is turned on by starting the operation before other built-in circuits. Is secured.

  After the above operation, since the second control signal PCNT2 becomes H level, the DC / DC converter V2 that receives 12V distributed from the effect control unit 22 'functions to generate the DC voltage 3.3V. The DC voltage 3.3V is supplied to the DC / DC converter V4 for 1.25V. Since this converter V4 does not have an operation enable terminal, the DC voltage 1.V is started immediately. 25V is generated.

  The two types of DC voltages 3.3V and 1.25V generated by being controlled by the second control signal PCNT2 are supplied to the one-chip microcomputer 60, the flash memory 61, and the CGROM 63 at almost the same timing. Each of the circuit elements is ready for operation start without delay after power-on. At this timing, the system reset signal SYS is at the L level, and after this level has been maintained for a while, the power supply circuit of the power supply board is operating so as to change to the H level. The power will be reset.

  Finally, when the third control signal PCNT3 changes to H level, the AND logic output of the third control signal PCNT3 and 3.3V is supplied to the DC / DC converter V3 to generate a DC voltage of 1.8V. The DC voltage 1.8V is supplied to the VDP 62, the DDR SRAM 64, and the power circuit 68 for the DDR SRAM at almost the same timing, so that the DDR SRAM 64 and the DDR SRAM interface circuit in the VDP 62 can be operated in synchronization. Become. Therefore, when the system reset signal SYS changes to the H level, the VDP 62 can smoothly start the initial setting operation.

  As mentioned above, although the Example of this invention was described in detail, the concrete description content does not specifically limit this invention. For example, in the lamp drive board 37 of the embodiment, different address numbers are assigned to the respective drive circuits DRi. However, as in the case of the motor lamp drive board 30, a common address number is assigned to all or a part of the drive circuit DRi. It may be numbered. The drive circuits numbered to the same address number blink the plurality of LED lamps in synchronization, which not only increases the power of the lamp effect but also transfers the lamp drive signal (control data in the embodiment). It is possible to combine them at once, and the control burden on the production control unit 22 is reduced.

  The lamp connection board 29 of the embodiment transmits only 2 bits out of 5 bits that define the address number of the drive circuit DRi. However, the bit length of the transmitted address number is in the range of 1 to 5 bits. It can be changed as appropriate. The address number having an arbitrary bit length does not necessarily have to be transmitted from the lamp connection board 29, and may be transmitted from a circuit board located on the upstream side of the lamp driving board 37.

  Of course, the application of the present invention is not necessarily limited to a ball game machine.

GM gaming machine 22 'presentation control unit 37 lamp drive board 29 relay board DR drive circuit

Claims (10)

Based on a control command output by the main control unit, the main control unit for randomly controlling whether or not to generate a gaming state advantageous to the player based on a predetermined switch signal, and controlling the game operation centrally An effect control unit that executes a lamp effect for causing a number of lamps to emit light, and a gaming machine configured to include:
The effect control unit includes a control circuit board for controlling the lamp effect, a plurality of lamp drive boards each having a drive circuit having the same configuration for driving the lamp and executing the lamp effect, and the control circuit board. A relay board that receives the lamp drive signal as a serial signal and transfers it to all the lamp drive boards,
At least a part of the address number of the driving circuit mounted on the lamp driving board is defined based on an address signal received from the relay board, and the lamp driving signal is transmitted by specifying the driving circuit that should receive it. A gaming machine characterized by being made.   The gaming machine according to claim 1, wherein the address signal is fixedly set in advance based on a hardware configuration of a relay board or a circuit board on the upstream side thereof.   The gaming machine according to claim 1 or 2, wherein the address number is defined by a plurality of bits, all or part of the address number is defined by the address signal, and the remaining bits are defined by the lamp driving board.   4. The drive circuit operates in response to a serial signal including the lamp drive signal, a control signal indicating that the serial signal is being transmitted, and a serial signal transmission clock signal. A gaming machine according to any one of the above.   The gaming machine according to claim 4, wherein the serial signal includes the lamp drive signal and an address number that identifies a drive circuit that should receive the lamp drive signal.   The gaming machine according to claim 1, wherein the serial signal is generated in a general-purpose computer circuit of the control circuit board. The drive circuit includes a control register that determines a drive mode,
The gaming machine according to any one of claims 1 to 6, wherein desired control data is set in a predetermined control register based on the lamp driving signal.   The game according to claim 7, wherein the driving mode includes, in addition to the lamp on / off state, presence / absence of a fade operation until the lamp is on / off and / or a light emission duty ratio by PWM control. Machine.   The gaming machine according to claim 6, wherein the general-purpose computer circuit operates with a power supply voltage of 3.5 V or less. The gaming machine according to any one of claims 1 to 9, wherein a dedicated computer circuit that operates with a power supply voltage of 3.5 V or less to generate an audio signal for audio production is mounted on the control circuit board.

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