JP2013135986A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of processing transmission of serial data and controlling operation thereof with economy.SOLUTION: A serial signal relating to excitement creating actions with lamps and movable excitement creating actions is so configured as to be selectively obtained by means of a plurality of driving circuits 54, 55 of the same configuration connected in parallel to a transmission line thereof. The driving circuits 54, 55 are so configured as to output appropriate driving data to lamps and motors based on set values in a plurality of control registers. A performance control unit is so configured as to transmit first address data for specifying the driving circuit to obtain control data prior to transmission of the control data being set values in the control registers, and transmit second address data for specifying the control register of the driving circuit specified by the first address data. The driving circuit specified by the first address data obtains control data from a series of serial signals and then stores it in the control register specified by the second address, and outputs a lamp driving signal and a motor driving signal based on the stored control data.

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine that can stably execute various powerful effects.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a gaming state is determined by a jackpot lottery executed on the condition that a game ball wins at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

  The above-mentioned performance operation is centered on the image production on the liquid crystal display device. In conjunction with this image production, a lamp production that blinks various lamps, an audio production that outputs a sound that excites the player, Movable effects such as moving animals are executed. And as these game effects are enriched, it takes time for each control operation, so it is desirable to optimize the circuit configuration and control operation.

  Considering the lamp production from this point of view, in the conventional configuration in which lighting data defining the lighting / extinguishing state of each lamp is transmitted as a series of serial data, a series of serial data with a fixed overall length can only be transmitted at any time. Therefore, there is a waste of transmission time for transmitting unused dummy data, and there is a waste of control processing of such transmission processing.

  That is, for example, even when it is desired to switch the execution timing of the lamp effect for each predetermined number of lamp groups, there is a waste of having to always transmit fixed-length lighting data including dummy data. In addition, assuming that a lamp effect and a movable effect are provided, the lamp effect is executed almost constantly, whereas the movable effect is rarely executed, but always transmits fixed-length data. Therefore, it cannot be said that the control operation is rational.

  Here, if a configuration that can individually control lighting of a group of lamps grouped into a plurality of sections and a configuration that can uniformly realize the control of moving objects and lamps with the minimum necessary data transmission can be realized. Time can be allocated to other image effects and the like, which is extremely suitable. If such a configuration can be realized, for example, it is possible to control the image effect, the lamp effect, the movable effect, and the sound effect in a unified manner with a single control board.

  The present invention has been made in view of the above-described problems, and there is no waste in serial data transmission processing and control operation thereof, and it is possible to uniformly realize the effect control of movable objects and lamps. It aims at providing the gaming machine which has.

  In order to achieve the above object, the present invention comprises a main control unit that centrally controls a game operation by lottery determination as to whether or not to generate a gaming state advantageous to a player based on a predetermined switch signal; An effect control unit that executes an effect operation including a lamp effect that causes a lamp to emit light and a movable effect that drives a movable body based on a control command output by the main control unit. The production control unit is configured to output a series of serial signals in which a lamp drive signal for lamp production and a movable body drive signal for movable production are collected, and transmission of the series of serial signals. The drive circuit is configured to be selectively obtainable by a plurality of drive circuits connected in parallel to the path, and the drive circuit is configured to output appropriate drive data to the lamp or the movable body based on the set values in the plurality of control registers. The presentation control unit is identified by first address data and first address data that identify a drive circuit from which the control data is to be acquired prior to transmission of control data that is a set value to the control register. The second address data specifying the control register of the driving circuit to be transmitted is transmitted. The driving circuit specified by the first address data acquires control data from a series of serial signals and specified by the second address. And a lamp driving signal and a movable body driving signal based on the stored control data are output.

  In the present invention, since a plurality of drive circuits are connected in parallel to a series of serial signal transmission paths, a serial signal having a minimum data length can be obtained. That is, when a plurality of drive circuits are connected in series as in the conventional configuration, it is necessary to always fix the total length of transmission data, including dummy data that is not used, but according to the configuration of the present invention. For example, since only the data to be used needs to be transmitted, there is no waste in transmission processing and control operations for that purpose.

  Therefore, according to the present invention, it is possible to individually control lighting of a group of lamps grouped into a plurality of sections with a minimum amount of data transmission, and to achieve unified control of effects on movable objects and lamps. You can also As the plurality of drive circuits, circuit elements having the same configuration are typically used.

  The drive circuit receives a 3-bit signal composed of a series of serial signals, a control signal indicating that serial signals are being transmitted, and a serial signal transmission clock signal from the effect control unit. It is preferable to operate, and the transmission line with the effect control unit can be minimized.

  In addition, it is preferable that the address value of the drive circuit corresponding to the first address data is fixedly set in advance by the voltage value supplied to the address terminal of the drive circuit. The control burden on the production control unit is reduced.

  More specifically, a drive board on which the plurality of drive circuits are mounted is provided separately from an effect control board constituting the effect control unit, and a buffer for receiving the 3-bit length signal supplied from the effect control board. Preferably, a circuit is provided on the driving substrate, and the plurality of driving circuits are connected in parallel to the buffer circuit and receive a series of serial signals.

  The drive board receives sensor signals from N origin sensors that detect origin positions of a plurality of N movable bodies (motors in the embodiment) that execute a movable effect, and serially converts them to an effect control board. It is preferable that a PS conversion unit that outputs the signal is mounted, and a control signal that defines the operation timing of serial conversion and a transmission clock signal of the serially converted sensor signal are transmitted from the effect control board to the PS conversion unit. Preferably it is supplied.

  It is preferable that all or part of the plurality of drive circuits have the same address value, and drive circuits that perform the same operation should have the same address value. Also, typically, the ramp effect is executed almost routinely until reaching the lottery result notifying operation of whether or not to generate a gaming state advantageous to the player, while the movable effect is not related to the notifying operation. Prior to this, it is executed at a special timing for notifying the lottery result.

  As described above, according to the gaming machine of the present invention, there is no waste in serial data transmission processing and its control operation, and it is possible to uniformly realize the effect control of movable objects and lamps.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram illustrating a circuit configuration of an effect control unit. It is a block diagram which illustrates the internal structure of a digital amplifier. It is a block diagram which illustrates the internal structure of a motor / lamp drive board | substrate. It is a block diagram which illustrates the circuit structure of an image control part. 2 is a diagram illustrating an internal configuration and operation of a power supply sequence circuit. It is a block diagram which illustrates the internal structure of VDP. It is a figure explaining the connection relation between VDP and a main display apparatus. It is drawing explaining the connection relation of VDP and a sub display apparatus. It is drawing explaining the modification of this invention. It is drawing explaining another modification of this invention.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, at the upper left and right positions and the lower side of the glass door 6, all three speakers are arranged. The two speakers arranged in the upper part are each configured to output sound of the left and right channels R and L, and the lower speaker is configured to output heavy bass.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided on the surface of the game board 5 in an annular shape, and a central opening HO is provided at the approximate center thereof. A movable effect body (not shown) is housed in a concealed state below the central opening HO, and at the time of a movable notice effect, the movable effect body rises into an exposed state so that a predetermined reliability can be obtained. The notice effect is realized. Here, the notice effect is an effect that informs indefinitely that a big hit state advantageous to the player will occur, and the reliability of the notice effect means the probability that the big hit state will result.

  A main display device DS1 composed of a large liquid crystal color display (LCD) is disposed in the central opening HO, and a movable sub display device composed of a small liquid crystal color display is disposed on the right side of the main display device DS1. DS2 is arranged.

  The main display device DS1 is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. The display device DS1 has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. In the special symbol display portions Da to Dc, there is a case where a reach effect that expects a big hit state is invited, and in the special symbol display portions Da to Dc and the surroundings, an appropriate notice effect is executed.

  The sub display device DS2 normally displays the image information in a stationary state in which the display screen is inclined at an angle that is easy for the player to see. However, at the time of a predetermined notice effect, while moving to the left side of the figure while changing the inclination angle to an angle that is easy for the player to see, a predetermined notice image is displayed.

  That is, the sub display device DS2 of the embodiment functions not only as a display device but also as a movable effect body that executes a notice effect. Here, the announcement effect by the sub display device DS2 is set with high reliability, and the player pays attention to the moving operation of the sub display device DS2 with a great sense of expectation.

  In the game area in which the game ball falls and moves, the first symbol start port 15a, the second symbol start port 15b, the first big winning port 16a, the second big winning port 16b, the normal winning port 17 and the gate 18 are arranged. It is installed. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  On the upper part of the first symbol starting port 15a, there is arranged an effect stage 14 configured to be able to win a prize in the first symbol starting port 15 after the game ball entering from the introduction port IN moves in a seesaw shape or a roulette shape. Yes. And when a game ball wins the 1st symbol starting port 15, it is comprised so that the fluctuation | variation operation | movement of the special symbol display parts Da-Dc will be started.

  The second symbol start port 15b is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws. When the stop symbol after fluctuation of the normal symbol display unit 19 displays a winning symbol, a predetermined symbol is displayed. The opening / closing claw is opened only for a time or until a predetermined number of game balls are detected.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the selected lottery random value is displayed and stopped.

  The first big prize opening 16a is configured with a slide board that advances and retreats in the front-rear direction, and the second big prize opening 16b is configured with an opening / closing plate that is pivotally supported at the lower end and opens forward. . The operation of the first grand prize opening 16a and the second big prize opening 16b is not particularly limited. In this embodiment, the first big prize opening 16a corresponds to the first symbol start opening 15a, and the second big prize opening 16b is comprised corresponding to the 1st symbol starting port 15b.

  That is, when a game ball is won at the first symbol start opening 15a, the changing operation of the special symbol display portions Da to Dc is started. After that, when the predetermined big hit symbol is aligned with the special symbol display portions Da to Dc, the first big hit A special game is started, and the slide board of the first big winning opening 16a is opened forward to facilitate the winning of a game ball.

  On the other hand, when a predetermined big hit symbol is aligned with the special symbol display portions Da to Dc as a result of the fluctuating motion started by winning the game ball in the second symbol start opening 15b, a special game corresponding to the second big hit is started, The open / close plate of the two major winning openings 16b is opened to facilitate the winning of game balls. The game value of a special game (hit state) varies according to the jackpot symbols to be arranged, but which game value is given depends on the lottery result according to the winning timing of the game ball. Determined in advance.

  In a typical big hit state, the opening / closing plate closes when a predetermined time elapses after the opening / closing plate of the big winning opening 16 is opened or when a predetermined number (for example, 10) of game balls wins. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations, and FIG. 4 shows a part of it in detail. As shown in FIG. 3, the pachinko machine GM receives 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. Main control board 21 that centrally handles the sound, an effect control board 22 that executes a lamp effect and a sound effect based on a control command CMD received from the main control board 21, and a control command CMD ′ received from the effect control board 22 An image control board 23 that drives the display devices DS1 and DS2 based on the control device 24, a payout control board 24 that controls the payout motor M based on the control command CMD "received from the main control board 21, and pays out a game ball; And a launch control board 25 that launches a game ball in response to a user's operation.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. The control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27 and the image interface board 28, and is output from the main control board 21. Is transmitted to the payout control board 24 via the main board relay board 32. Although the control commands CMD, CMD ′, and CMD ″ are all 16 bits long, the main control board 21 and the payout control board 24 are used. The control commands related to are transmitted in parallel every two 8 bit lengths. On the other hand, the control command CMD 'transmitted from the effect control board 22 to the image control board 23 is 16 bits in length and transmitted in parallel. Therefore, even when the notification effects including the movable notification effect are diversified and a large number of control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  By the way, in the present embodiment, the production interface board 27 and the production control board 22 are directly connected to each other by a male connector and a female connector without passing through a wiring cable, and two circuit boards are laminated. . Similarly, with respect to the image interface board 28 and the image control board 23, two circuit boards are laminated by directly connecting a male connector and a female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Therefore, in this specification, the control board 21 to 24, the circuits mounted on the interface boards 27 to 28, and the operations realized by the circuits are generically named. May be referred to as a section 22 ′, an image control section 23 ′, and a payout control section 24. That is, in this embodiment, the effect control board 22 and the effect interface board 27 constitute an effect control part 22 ′, and the image control board 23 and the image interface board 28 constitute an image control part 23 ′. . Note that all or part of the effect control unit 22 ′, the image control unit 23 ′, and the payout control unit 24 are sub-control units.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 35. Each is fixed in place on the front frame 3. On the other hand, a main control board 21, an effect control board 22, and an image control board 23 are fixed to the back of the game board 5 together with the display devices DS1 and DS2 and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power relay board 33 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The effect interface board 27 outputs the received system reset signal SYS to the effect control unit 22 'and the image control unit 23' as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been applied to the power supply board 20, and one of the effect control unit 22 ′ and the image control unit 23 ′ is generated by the power supply reset signal. The chip microcomputer is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The production control unit 22 ′ and the image control unit 23 ′ perform production operations dependently on the basis of the control command from the main control unit 21, so that the power supply board 20 is avoided in order to avoid complication of the circuit configuration. The system reset signal SYS output from is used.

  By the way, the reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and unless a regular clear pulse is received from the CPUs of the control units 21 and 24, Each CPU is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As described above, the effect control board 22 and the effect interface board 27 are integrated by connector connection, and the effect control unit 22 ′ is connected to each level from the power supply board 20 via the power relay board 33. A DC voltage (5V, 12V, 32V) and a system reset signal SYS are received (see FIGS. 3 and 4). The effect control unit 22 'receives the control command CMD and the strobe signal STB from the main control unit 21 via the command relay board 26 (see FIGS. 3 and 4).

  Then, the effect control unit 22 ′ drives a lamp group composed of a large number of LED lamps and electrical lamps by outputting a lamp drive signal to the lamp drive substrate 29. Further, by outputting a lamp drive signal and a motor drive signal to the motor / lamp drive board 30, the lamp group is driven and the effect motor groups M1 to Mn configured by a plurality of stepping motors are driven. Note that the lamp drive signal and the motor drive signal are both serial signals, and no matter how much the number of lamps or production motors is increased in order to enrich the production contents, the number of wiring cables will not increase, and the equipment configuration will be Simplified.

  The lamp group realizes the lamp effect almost constantly, while the effect motor group suddenly starts operation and realizes the movable notice effect by the movable effector. As described above, the movable effect body includes the sub display device DS2.

  In addition, the effect control unit 22 ′ sends a control command CMD ′ and a strobe signal STB ′ to the image control unit 23 ′, a system reset signal SYS received from the power supply board 20, and two types of DC voltages (12V, 5V). ) Is output (see FIGS. 3 and 4).

  The image controller 23 'drives the main display device DS1 based on the control command CMD' to execute various image effects. As shown in FIG. 4, the main display device DS <b> 1 emits light by the LED backlight, and from the image interface board 28, five pairs of LVDS (Low voltage differential signaling) signals and the backlight power supply voltage ( 12V) and is driven. The backlight of the main display device DS1 is configured to be able to control the luminance by PWM control.

  Further, the image control unit 23 ′ executes an appropriate notice effect on the sub display device DS <b> 2 as the notice effect based on the control command CMD ′. The sub display device DS2 also emits light by backlight, and is configured to be able to control its ON / OFF state.

  The sub display device DS2 is driven by the relay board 36 that receives the backlight power supply voltage (5V) and the V-by-One (registered trademark) signal from the image interface board 28, and at the time of the notice effect, the effect control unit The effect motor Mi controlled by 22 'is driven synchronously, and a movable effect is executed. The LVDS signal and the V-by-One signal will be described in detail later with reference to FIGS.

  Next, the configurations of the effect control unit 22 'and the image control unit 23' described above will be described in more detail with reference to FIG. As shown in FIG. 4, the production interface board 27 receives three types of DC voltages (5V, 12V, and 32V) from the power supply board 20 via the power supply relay board 33. Here, the DC voltage 5V is distributed to the rendering interface board 27, the lamp driving board 29, the motor / lamp driving board 30, the image interface board 28, and the image control board 23 as the power supply voltage of the digital logic circuit. The digital circuit is operating.

  However, the direct current voltage 5V is not distributed on the effect control board 22, and the direct current voltage 3.3V stepped down from 12V by the DC / DC converter and the direct current stepped down from 3.3V by the DC / DC converter. Only the voltage 1.8V is distributed from the production interface board 27 to the production control board 22.

  In this way, the production control board 22 of the present embodiment is driven by the power supply voltage of 3.3V or lower because all the circuits are driven. Therefore, even if the production interface board 27 is arranged and laminated immediately above the production control board 22, there is no problem in heat dissipation. However, in the embodiment, the direct current voltage 12V received from the power supply board 20 by the effect interface board 27 is directly used as the power supply voltage of the digital amplifier 46, and the motor / lamp drive board 30 and the lamp drive board. 29 is distributed to become the power supply voltage of each lamp group. On the other hand, the direct current voltage 32V received from the power supply board 20 is stepped down to the direct current voltage 13V in the DC / DC converter of the production interface board and distributed to the motor / lamp drive board 30.

  As shown in FIG. 4, the effect control unit 22 ′ includes a one-chip microcomputer 40 that executes processing such as a sound effect, a lamp effect, a notice effect by the effect movable body, and data transfer, and a control program for the one-chip microcomputer 40. A flash memory 41 to be stored, a voice synthesis circuit 42 that reproduces and outputs a voice signal based on an instruction from the one-chip microcomputer 40, and compressed voice data that is original data of the reproduced voice signal are stored. And an audio memory 43 that is configured.

  Here, the one-chip microcomputer 40, the flash memory 41, and the voice memory 43 operate at a power supply voltage of 3.3V, and the voice synthesis circuit 42 operates at a power supply voltage of 3.3V and a power supply voltage of 1.8V. It operates and significant power saving is realized. Here, 1.8V is the power supply voltage of the computer core part of the speech synthesis circuit, and 3.3V is the power supply voltage of the I / O part.

  The one-chip microcomputer 40 includes a plurality of parallel input / output ports PIO. The control command CMD and the strobe signal STB from the main control unit 21 are input to the first input port PO1, and the control command CMD ′ and the strobe signal STB ′ are output from the second input port PO2. Has been.

  Specifically, the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 are supplied to the first input port PO1 at the power supply voltage 3.3V in the buffer 44 of the effect interface board 27. Is converted to a logic level corresponding to, and supplied in units of 8 bits. The interrupt signal STB is supplied to the interrupt terminal of the one-chip microcomputer, and the effect control unit 22 'is configured to acquire the control command CMD by the reception interrupt process.

  The control command CMD acquired by the effect control unit 22 ′ includes (1) an abnormality notification and other notification control commands, and (2) control for specifying an outline of various effect operations resulting from winning at the symbol start opening. A command (variation pattern command) and a control command (symbol designation command) for designating a symbol type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the change pattern command is acquired, the effect control unit 22 ′ performs an effect lottery subsequently to further specify the effect outline specified by the acquired change pattern command. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking LEDs and a sound effect preparation operation by a speaker are performed, and an effect operation by a lamp or speaker is performed on the image control unit 23 ′. A control command CMD ′ relating to the synchronized image effect is output.

  In order to realize such an image effect synchronized with the effect operation, the effect control unit 22 ′ controls the 16-bit length together with the strobe signal (interrupt signal) STB ′ for the image control unit 23 ′ through the second input port PO2. The command CMD ′ is output toward the effect interface board 27. In addition, when the production control unit 22 ′ receives a design designation command, a notification control command related to the display device DS1, and other control commands, the control command is summarized in a 16-bit length. It is output toward the production interface board 27 together with the interrupt signal STB ′.

  Corresponding to the configuration of the production control board 22 described above, the production interface board 27 is provided with an output buffer 45, and a 16-bit control command CMD ′ and a 1-bit interrupt signal STB ′ are sent to the image interface. It is output to the substrate 28. These data CMD ′ and STB ′ are transmitted to the image control board 23 via the image interface board 28.

  The effect interface board 27 is provided with a digital amplifier 46 that receives the audio signal output from the audio synthesis circuit 42. As described above, the speech synthesis circuit 42 operates with power supply voltages of 3.3 V and 1.8 V, and the digital amplifier 46 performs class D amplification operation with a power supply voltage of 12 V, reducing power consumption. It is possible to produce a loud sound while suppressing it.

  The left and right speakers at the upper part of the gaming machine and the speakers at the lower part of the gaming machine are driven by the output of the digital amplifier 46. Therefore, the voice synthesis circuit 42 needs to generate a three-channel voice signal, and if this is transmitted in parallel, the wiring between the voice synthesis circuit 42 and the digital amplifier 46 becomes complicated.

  Therefore, in this embodiment, the voice synthesis circuit 42 and the digital amplifier 46 are connected by four signal lines in order to prevent deterioration of sound quality and avoid complicated wiring. In this case, the transfer clock signal SCLK, the channel control signal LRCLK, and the 2-bit length serial signals SDATA1 and SDATA2 are suppressed to a total of 4 bit signal lines. Note that the amplitude level of any signal is 3.3V.

  Here, SDATA1 is a serial signal for PCM data specifying the stereo signals R and L of the left and right speakers arranged at the upper part of the gaming machine, and SDATA2 is a monaural signal of the heavy bass speaker arranged at the lower part of the gaming machine. This is a serial signal for the PCM data to be specified. The voice synthesis circuit 342 transmits the left channel audio signal L while maintaining the channel control signal LRCLK at the L level, and maintains the channel control signal LRCLK at H level while maintaining the channel control signal LRCLK at the L level. Is transmitted. Note that since there is only one heavy bass speaker in this embodiment, a monaural audio signal is transmitted, but it is of course possible to transmit it as a stereo audio signal.

  In any case, in this embodiment, four types of audio signals can be transmitted with four cables, and therefore, signal transmission without audio deterioration due to noise can be performed with the minimum number of cables. That is, since it is serial transmission, the number of cables is far smaller than that of parallel transmission. Note that when analog transmission is employed, the number of cables is the same, but noise is superimposed on an analog signal having an amplitude of 3.3 V, and the sound quality is greatly deteriorated. On the other hand, when the amplitude level is increased, the power supply wiring becomes complicated and the power consumption increases.

  Such serial signals SDATA1 and SDATA2 are acquired by the digital amplifier 46 in synchronization with the rising edge of the clock signal SCLK. In the digital amplifier 46, parallel conversion is performed for each predetermined bit length, and after D / A conversion, D-class amplification is performed and supplied to each speaker.

  Although the internal configuration of the digital amplifier 46 is appropriate, FIG. 5 shows an internal configuration diagram when YDA171 (YAMAHA) is used as the digital amplifier. Although it is not limited to such an internal configuration, in any case, in this embodiment, since the voice synthesis circuit 42 and the digital amplifier 46 are connected by a serial line, the bit length of the PCM data (voice data) is increased. Even if the sound quality is improved, it is not necessary to change the wiring cable and the like, and the circuit configuration can be simplified.

  In addition, the effect interface board 27 is provided with buffer circuits 47 and 48 for outputting serial data output from the one-chip microcomputer 40. Here, the output buffer 47 transfers the lamp driving signal (serial signal) transmitted from the one-chip microcomputer 40 to a shift register circuit disposed on the lamp driving substrate 29. A shift register circuit (not shown) on the lamp driving substrate 29 converts the lamp driving signal into a parallel signal and drives the LED lamp group.

  The other buffer circuit 48 functions as an input / output buffer and transfers the serial signal transmitted from the one-chip microcomputer 40 to the motor / lamp drive board 30 as it is, while the origin of the group of effect motors M1 to Mn. An origin sensor signal (serial signal) indicating the position is transferred to the one-chip microcomputer 40.

  In the case of the present embodiment, the serial signal transmitted from the one-chip microcomputer 40 to the buffer circuit 48 includes a lamp driving signal (serial signal) for lighting the lamp group and a motor driving signal (serial) for rotating the effect motor. Signal) is continuous. The motor / lamp drive board 30 divides the series of serial signals into 16-bit lengths and converts each 16-bit length into a parallel signal to execute a lamp effect and a movable notice effect. Specifically, a series of lamp effects is executed as the effect operation determined by lottery in response to the control command CMD, and when a motor drive signal is received, the effect motors M1 to Mn are rotated to appropriately A movable notice effect is being executed.

  FIG. 6A is a block diagram specifically showing the circuit configuration of the motor / lamp drive board 30. As shown in the figure, the motor / lamp drive board 30 includes a PS converter 50 that serially converts the origin sensor signals of the effect motors M1 to Mn, and an input buffer 51 that receives a control signal for the PS converter 51 from the one-chip microcomputer 40. A step-down unit 52 that steps down the DC voltage 13V to 12V, an input buffer 53 that receives a lamp drive signal and a motor drive signal from the one-chip microcomputer 40, and drive control units 54 and 55 that drive and control a lamp group and a production motor group. The sink driver 56 receives the drive current of each effect motor.

  Note that the PS converter 50, the input buffers 51 and 53, the drive controller 54, and the sink driver 56 operate using a DC voltage of 5V as a power supply voltage.

  The origin sensor signal is an output of an origin sensor that detects whether or not the production motors M1 to Mn are located at the origin, and each origin sensor uses a DC voltage of 12V or 5V as a power supply voltage. These 1-bit and n-bit origin sensor signals are acquired by the PS converter 51 in synchronization with the hold signal LOAD output from the one-chip microcomputer 40, and the PS converter 51 receives the transfer received from the one-chip microcomputer 40. In synchronization with the clock CK, the origin sensor signal is converted into a serial signal and transmitted to the one-chip microcomputer 40.

  As described above, in this embodiment, the one-chip microcomputer 40 can appropriately grasp whether or not each effect motor M1 to Mn is located at the origin. In addition, the possibility of misjudgment is greatly reduced by using a DC voltage (12V, 5V) of a different system from the power supply line (13V) where electromagnetic noise may be superimposed as the power supply voltage of each origin sensor. I am letting.

  Next, in the step-down unit 52, the input side 13V is used as a driving power source for each lamp, the output side 12V is used as a driving power source for the effect motors M1 to Mn, and the power source lines are separated from each other. Further, as described above, the input buffer 53 and the drive control units 54 and 55 use the DC voltage 5V generated in a completely different system from the DC voltage 13V as the power supply voltage.

  Therefore, even if the large production motor groups M1 to Mn suddenly start operation, there is a very low possibility that the lamp drive signal of each lamp is affected by power supply noise or the like. Similarly, even if the lamps are flashed violently with high luminance, the possibility that the motor drive signals of the effect motors M1 to Mn are affected by power supply noise or the like is extremely low.

  By the way, the drive control unit 54 for the production motor and the drive control unit 55 for the lamp have the same configuration. From the one-chip microcomputer 40, the operation control signal EN, the serial signal DATA, and the transfer clock signal CK Are operating in common. The serial signal DATA includes a lamp driving signal and a motor driving signal.

  The drive control units 54 and 55 have, for example, 5-bit length address terminals (A0 to A4), and are configured so that addresses can be appropriately assigned. In this embodiment, the address terminals (A0 to A4) having a 5-bit length are fixedly assigned in advance to the H level or the L level as a hardware configuration.

  The drive control units 54 and 55 are configured to have a large number of internal control registers R1 to Rm, and by setting (writing) control data Di (8-bit length) in each of the control registers R1 to Rm, Each output of the 16-bit output terminal is appropriately controlled.

  The register numbers of the control registers R1 to Rm are 8 bits long. In this embodiment, the address terminals (A0 to A4) having a 5-bit length are set in advance to the H / L level, and the addresses ADRi of the elements 54 and 55 are fixed values.

  The operation contents realized by setting the control data Di in each control register R1 to Rm include not only the ON / OFF state of each output terminal but also the fade operation (fade in / out) until reaching the ON / OFF state. ) And the duty ratio (0 to 99.6%) in the PWM control of the output terminal in the ON state. Therefore, the one-chip microcomputer 40 does not need to bother to change the lamp drive signal (serial data) for PWM control at the time of brightness control or fade in / out presentation, and simply changes the control data of the corresponding register Ri. As a result, the control burden is greatly reduced.

  Of course, by controlling the lamp drive signal with PWM, it is possible to perform fade-in / out effects different from fixed fade operations. In short, according to this embodiment, various lamp effects are possible. It becomes. When such various lamp effects are executed, there is a concern that considerable high-frequency noise is superimposed on the output signal of the drive control unit 55, but it is difficult to affect the effect motors M1 to Mn as described above. It is.

  FIG. 6B is a time chart showing a communication protocol between the one-chip microcomputer 40 and the plurality of drive control units 54, 55... As shown in the figure, the one-chip microcomputer 40 first sets the operation control signal EN to the ON state (H level), and (1) the address number ADRi () of the drive control units 54 to 55 to which the control data Di is to be written. (8 bits long), (2) the number of control registers R1 to Rm to write control data Di in the drive control unit (8 bits long), (3) control data Di (8 bits) to be written to the control register Ri Is output as a serial signal in synchronization with the transfer clock signal CK.

  If the first register number Ri is designated for a series of control registers R1 to Rm, the subsequent control data (set values) D1, D2, R3... Are represented by Ri, Ri + 1, Ri + 2. The control data is recognized by the drive control units 54 and 55 and automatically acquired. Therefore, it is not always necessary to set a set value in all the control registers Ri. For example, in the case of a write process to a series of M control registers Ri to Ri + M−1, M pieces of control data and two pieces of address data Therefore, a total output process of 8 × (M + 2) bits is sufficient.

  When the output of all data is completed, the one-chip microcomputer 40 may return the operation control signal EN from the ON state to the OFF state, and the drive control unit identified by the address number ADRi corresponds to this operation. The operation corresponding to the control data D1... Acquired in the series of control registers Ri.

  Since the production motors M1 to Mn are operated as a movable notice production, the production motors M1 to Mn are normally waiting at the origin position in a concealed state. Accordingly, the drive control unit 54 retains the control data in the OFF state, and normally it is not necessary to receive control data transfer from the one-chip microcomputer 40. However, since the control drive unit of this embodiment specifies the address number ADRi and receives the control data Di, there is no influence on the drive control unit 54 that is not designated by the address number even if the serial signal is repeatedly transferred. Don't give.

  Therefore, according to the configuration of the present invention, the drive control unit 55... 55 for controlling the lamp that continuously repeats the dynamic lamp effect and the drive control unit 54 for the movable notice effect that rarely starts the notice operation. Can have the same configuration. In addition, the one-chip microcomputer 40 can handle the motor drive signal and the lamp drive signal in the same row except for determining whether or not to add the motor drive signal to the lamp drive signal. The burden can be reduced.

  Further, by setting all or a part of the drive control units 55, 55 for lamp control to the same address value, it is possible to collect the lighting data (control data) transfer processing related to a large number of lamps, and to produce the effect control. The control burden on the unit 22 is reduced. For example, when the right and left lamp groups of the gaming machine are always caused to emit light in the same manner, a drive control unit 55R for driving the right lamp group and a drive control unit 55L for driving the left lamp group are provided. Only by setting the same address value, the lighting data transfer process can be completed at once.

  FIG. 7 is a circuit block diagram illustrating in detail the image control unit 23 ′ (the image interface board 28 and the image control board 23) including the surrounding boards. As described above, the image control unit 23 'operates by receiving the control command CMD', the strobe signal STB ', and the system reset signal SYS from the effect control unit 22'. In addition, two types of DC voltages 5V and 12V are received via the production control unit.

  As shown in the figure, the image control unit 23 ′ receives a control command via the effect interface board 27 and executes an image control operation, and a flash that stores a control program of the one-chip microcomputer 60 and the like. Work of the memory 61, a VDP (Video Display Processor) 62 for driving the display devices DS1 and DS2 based on instructions from the one-chip microcomputer 60, a graphic ROM (CGROM) 63 for storing compressed image data for image production, and the VDP 62 An SDRAM (Synchronous Dynamic Random Access Memory) 64 functioning as a region (Video RAM), a watchdog timer WDT for forcibly resetting the one-chip microcomputer 60, and the like are configured.

  As shown in the figure, the output of the watchdog timer WDT is supplied to the OR circuit together with the system reset signal SYS. When one of the input signals to the OR circuit becomes an active level, the one-chip microcomputer 60 and the VDP 62 are synchronized. To be reset. Therefore, when the control operation is initialized due to the program runaway of the one-chip microcomputer 60, the operation of the VDP 62 is initialized correspondingly, and the contradictory and unnatural image effect is executed. It will not be done.

  In this embodiment, the power supply voltage of each element is minimized in order to suppress the power consumption as much as possible. The power supply voltage of each element is (1) the one-chip microcomputer 60 is 3.3V and 1.25V. (2) Flash memory 61 is 1.25V, (3) VDP62 is 3.3V, 1.8V and 1.1V, (4) CGROM 63 is 3.3V, and (5) SDRAM 64 is 1.8V. .

  As described above, in this embodiment, a large number of DC voltages are required to save power, and the supply timings of circuit elements having a plurality of power supply voltages need to be optimized. On the other hand, only two types of direct current voltages are distributed for the purpose of suppressing the number of wiring cables between the effect control unit 22 'and the image control unit 23'.

  Therefore, by arranging a plurality of DC / DC converters having control terminals and providing a power sequencer 65, a large number of DC voltages are supplied to each element at an optimal timing. FIG. 8 shows an internal configuration (a) of LM3881 (national semiconductor) as an example of the power sequencer 65 and an operation time chart (b) executed even when the power sequencer 65 is used.

  In the case of the power sequencer 65 in FIG. 8A, when the INV terminal is at the L level, the operation starts in response to the operation start command EN at the H level, and the clock defined by the capacitance connected to the TADJ terminal. The first control signal PCNT1 rises after nine cycles of the signal Clock, the second control signal PCNT2 rises after eight cycles of the clock signal, and the third control signal PCNT3 rises after another eight cycles of the clock signal.

  On the other hand, when the operation start command EN transitions to the L level, the third control signal PCNT3 falls after 9 cycles of the clock signal, the second control signal PCNT2 falls after 8 cycles of the clock signal, and further 8 cycles after the clock signal. The third control signal PCNT3 falls.

  In the present embodiment, as shown in FIG. 7, the operation start command EN is an AND logic output of two types of DC voltages supplied from the effect control unit 22 '(effect interface board 27). The first control signal PCNT1 is supplied to the operation enable terminal EN of the DC / DC converter V1 for generating 1.1V, and the second control signal PCNT2 is an operation enable for the DC / DC converter V2 for generating 3.3V. It is supplied to the terminal EN.

  The third control signal PCNT3 is converted into an AND logic output with 3.3V and supplied to the operation enable terminal EN of the DC / DC converter V3 for generating 1.8V. Each DC / DC converter described above starts the voltage conversion operation on condition that the operation enable terminal EN becomes H level.

  Therefore, as shown in FIG. 8B, the DC / DC converter V1 first functions based on 5V distributed from the effect control unit 22 'to generate the DC voltage 1.1V. This DC voltage 1.1V is a power supply voltage for the digital circuit and the built-in VRAM built in the VDP 62, and the normal operation start sequence of the VDP 62 after the power is turned on by starting the operation before other built-in circuits. Is secured.

  After the above operation, since the second control signal PCNT2 becomes H level, the DC / DC converter V2 that receives 12V distributed from the effect control unit 22 'functions to generate the DC voltage 3.3V. The DC voltage 3.3V is supplied to the DC / DC converter V4 for 1.25V. Since this converter V4 does not have an operation enable terminal, the DC voltage 1.V is started immediately. 25V is generated.

  The two types of DC voltages 3.3V and 1.25V generated by being controlled by the second control signal PCNT2 are supplied to the one-chip microcomputer 60, the flash memory 61, and the CGROM 63 at almost the same timing. Each of the circuit elements is ready for operation start without delay after power-on. At this timing, the system reset signal SYS is at the L level, and after this level has been maintained for a while, the power supply circuit of the power supply board is operating so as to change to the H level. The power will be reset.

  Finally, when the third control signal PCNT3 changes to H level, the AND logic output of the third control signal PCNT3 and 3.3V is supplied to the DC / DC converter V3 to generate a DC voltage of 1.8V. The DC voltage 1.8V is supplied to the VDP 62, the DDR SRAM 64, and the power circuit 68 for the DDR SRAM at almost the same timing, so that the DDR SRAM 64 and the DDR SRAM interface circuit in the VDP 62 can be operated in synchronization. Become. Therefore, when the system reset signal SYS changes to the H level, the VDP 62 can smoothly start the initial setting operation.

  FIG. 9 is a block diagram showing the internal configuration of the VDP 62 and the connection relationship between the SDRA 64, the CGROM 63, and the one-chip microcomputer. Based on an instruction from the one-chip microcomputer 60, the VDP 62 separates a series of variation effect image data groups executed by the main display device DS1 and a notice effect image data group executed by the sub display device DS2. Generated and output. The image data group for variation effect is finally generated by the display controller 78a and output to the LVDS_I / F unit 75, and the image data group for notice effect is finally generated by the display controller 78b and is generated by the DRGB_I / F unit 76. It is configured to be output to.

  Here, each of the image data group for change effect and the image data group for notice effect is configured by combining moving image data that continuously changes and still image data that does not move continuously. In addition, the RGB pixels constituting the image data group for fluctuating effects are each 8 bits long (256 gradations), and realize high-quality image effects on the main display device DS1. On the other hand, the sub-display device DS2 exclusively performs the notice effect, so each of the RGB pixels is 6 bits long (64 gradations) in order to reduce the communication data amount and save space such as control burden and cable wiring. Yes.

  As shown in the figure, the one-chip microcomputer 60 and the VDP 62 are connected via a CPU_I / F unit, and the command memory 70 stores in advance a large number of command lists that specify a series of image effects. The command list is classified into a variable effect and a notice effect, and various types of lists are prepared to increase the variety of effects.

  The one-chip microcomputer 60 accesses the system control register 71 when necessary, and sets a start address of a predetermined command list that specifies a series of image effects to be executed. Then, the command parser (syntax analyzer) 72 analyzes the command list specified by the system control register 71 and passes the internal code corresponding to the analysis result to the internal modules such as the moving picture decoder 73 and the still picture decoder 74. . Then, each internal module starts an operation to secure necessary image data in a VRAM (Video RAM) area, and at the same time, frame image data is transferred to an LVDS_IF unit (LVDS transmission unit) 75 or a DRGB_IF unit. Output to 76. The LVDS_IF unit 75 is a part that converts the frame image data into an LVDS signal and outputs it. The DRGB_IF unit 76 is a part that outputs the digital RGB signal together with a control signal such as a horizontal / vertical synchronization signal. The DRGB_IF unit 76 outputs the digital RGB signals in 8-bit lengths, but in this embodiment, only the 6-bit length digital RGB signals excluding the lower 2 bits are transmitted in order to reduce the amount of communication data. doing. Therefore, as an internal operation of the VDP 62, it is not necessary to generate a 6-bit digital RGB signal, and the control burden is not increased.

  By the way, in this embodiment, in order to facilitate a series of drawing operations by the VDP 62 at high speed, the CGROM 63 includes moving image compression data for specifying a series of moving images that change at high speed, still compression data for specifying a still image, Is memorized separately. The still compressed data read from the CGROM 63 via the ROM_I / F unit or the CG memory controller is expanded by the still image decoder 74 and temporarily stored in the built-in VRAM 77. On the other hand, the moving image compressed data read from the CGROM 63 is configured to be decompressed by the moving image decoder 73 and temporarily stored in the SDRAM 64.

  That is, in this embodiment, since the external SDRAM 64 is used as the VRAM, there is no limit on the memory capacity as in the case of using the built-in RAM. It is also possible to continuously decode the moving image compressed data and secure it in advance of the SDRAM, so that image processing can be realized at high speed. In addition, the RAM 63 of the present embodiment is particularly composed of a DDRS2 DRAM (Double-Data-Rate2 SDRAM), which realizes data transfer at a higher speed than that of the SDRAM, and generates two uncommon image data at a high speed. be able to.

  The image data secured in the VRAM areas 64 and 77 in this way is read by the display controllers 78a and 78b, and is output from the LVDS / IF unit 75 and the DRGB / IF unit 76 after gamma correction and the like.

  FIG. 10 shows the relevant part (LVDS transmission unit 75) of FIGS. 7 and 9 in more detail regarding the connection relationship between the VDP 62 having the above-described internal configuration and the main display device DS1. As shown in the figure, the main display device DS1 according to the present embodiment includes a built-in LVDS reception unit (LVDS_I / F) 81 corresponding to the LVDS transmission unit (LVDS_I / F) 75 of the VDP 62.

  As shown in FIG. 10A, the LVDS_I / F unit (LVDS transmission unit) 75 is a part that converts parallel data including 24 bits of RGB data into an LVDS (low voltage differential signaling) signal. LVDS means a low-voltage differential transmission system for high-speed transmission of RGB data and the like with low noise and low power. In this embodiment, several mA is applied to a pair of signal transmission lines (one twisted pair line). While a low level signal current is supplied from the transmission side, this signal current is received by a terminating resistor of about 100Ω provided on the reception side. Therefore, although the voltage amplitude is a low level of about several hundred mV, reliable signal transmission is realized by changing the current direction corresponding to the logic level (H / L).

  In this embodiment, as shown in FIG. 10A, a total of 28-bit parallel data (TA0 to TA0) including all 24-bit RGB signals (each 8 bits long) and horizontal / vertical synchronization signals. TA6, TB0 to TB6, TC0 to TC6, TD0 to TD6) are converted into four pairs of differential signals in the LVDS transmission unit 75. Then, a differential signal of a pair of transfer clocks is added to this and transmitted to the main display device DS1 through five twisted pair lines.

  7 and 10A, these four pairs of differential signals are evaluated from the standpoint of the main display device DS1, and (RXIN0 +, RXIN0-), (RXIN1 +, RXIN1-), (RXIN2 +, RXIN2). −), (RXIN3 +, RXIN3 +), (RXCLK +, RXCLK−).

  As shown in FIG. 10B, during the period of the transfer clock RXCLK, the twisted pair lines (RXIN0 +, RXIN0−) serially transfer G0 → R5 → R4 → R3 → R2 → R1 → R0 to obtain the twisted pair line. In (RXIN1 +, RXIN1-), B1 → B0 → G5 → G4 → G3 → G2 → G1 are serially transferred, and in twisted pair lines (RXIN2 +, RXIN2-), DE → (VS) → (HS) → B5 → B4 → B3 → B2 is serially transferred, and NA → B7 → B6 → G7 → G6 → R7 → R6 is serially transferred on the twisted pair line (RXIN3 +, RXIN3-).

  Here, R0 to R7 are 8-bit length data indicating the luminance of the red pixel, G0 to G7 are 8-bit length data indicating the luminance of the green pixel, and B0 to B7 are 8-bit length data indicating the luminance of the blue pixel. It is. In addition, (VS) and (HS) indicate vertical synchronization timing and horizontal synchronization timing, and DE means DATA ENABLE. Note that NA is unused.

  The main display device DS1 that receives the four pairs of differential signals described above is provided with an LVDS receiver 81 corresponding to the LVDS transmitter 75 of the VDP 62. A series of serial data is converted into parallel data, and four sets of parallel data RA0 to RA6, RB0 to RB6, RC0 to RC6, and RD0 to RD6 are obtained. As apparent from the serial data string shown in FIG. 10B, the parallel data RA0 to RA6 are specifically 7 bits of R0 to R5 and G0, and other parallel data are also shown in FIG. 10B. This corresponds to the serial data shown.

  Then, the main display device realizes screen display based on the RGB gradation data extracted from these. In this way, in this embodiment, the pixel data is 8 bits for each RGB (256 gradations), and a full color image effect can be realized.

  In addition, since the LVDS signal is used for signal transmission between the VDP 62 and the main display device DS1, the voltage amplitude is low enough (several hundred mV), and the rise time and fall time of the digital signal are correspondingly short. Can be realized, and an image effect transitioning to a high speed can be realized smoothly. Moreover, since it is not affected by common mode noise, an unnatural pixel does not occur.

  Further, since the number of cables is small, space saving and cost reduction are realized, and signal transmission can be performed with a low level voltage, so that power saving can be achieved. Therefore, by utilizing these advantages, it is possible to enrich game effects by arranging more movable effects bodies. Incidentally, in the present embodiment, a large number of movable effects bodies including a sub display device are mounted and the number of LED lamps is greatly increased by taking advantage of the space, cost, and power consumption.

  Since the twisted pair lines (RXIN3 +, RXIN3-) are configured to serially transfer NA → B7 → B6 → G7 → G6 → R7 → R6, the twisted pair lines (RXIN3 +, RXIN3-) are not used, or In addition, by serially transferring NULL data through the twisted pair lines (RXIN3 +, RXIN3-), it is easy to suppress 64 gradations of 6 bits for each of RGB.

  Incidentally, as shown in FIG. 7, in addition to the LVDS signal described above, two types of DC voltages (12V, 3.3V) and a PWM control signal VBR are transmitted to the main display device DS1 from the image interface board 28. Has been.

  Here, the direct-current voltage 3.3V is a power supply voltage of the electronic circuit of the display device DS1 including the LVDS receiver 81, and the power is reduced by the low power supply voltage. On the other hand, the DC voltage 12V is a power supply voltage of the liquid crystal backlight unit BL composed of LED lamps. In this embodiment, the backlight unit BL is configured by a plurality of LED lamps connected in series, and the cold cathode tube is not used. Therefore, the circuit configuration can be simplified, the power can be reduced, and the performance can be improved. .

  That is, in order to use a cold cathode tube, an inverter circuit that converts a high voltage of about 32 V DC to an AC voltage of about 1000 V at a frequency of about 30 kHz to 45 kHz is required, and the installation space is large and the power consumption is high. However, in this embodiment, all of these problems are solved.

  That is, since the backlight unit BL of this embodiment is a DC drive of 12V, it does not become a noise source, an inverter circuit is unnecessary, and power consumption is reduced to half or less.

  Further, the display device DS1 of the present embodiment incorporates a drive circuit that receives a DC voltage of 12 V and supplies a drive current of about 40 to 65 mA to a plurality of LED lamps. This drive circuit is configured so that the dimming of the LED lamp can be controlled by the PWM control signal VBR. For example, for a gaming machine in which a player is not seated, the backlight can be turned off. But power saving is realized.

  Note that the PWM control signal VBR of the embodiment has a voltage amplitude of 3.3 V and is configured so that the duty ratio can be arbitrarily set in the range of 0 to 100%. And the brightness | luminance of a backlight can be changed to a desired level by changing a duty ratio suitably in the state which sent regulation current (40-65mA) to LED of an energized state.

  FIG. 11 shows the relevant portions (76, 66, 80) of FIG. 7 and FIG. 9 in more detail regarding the connection relationship between the VDP 62 and the sub display device DS2. Specifically, in addition to the DRGB_I / F unit 76 of the VDP 62, a V-by-One transmission unit 66 arranged on the image interface board 28 and a V-by-One arranged on the relay board 36. The receiver 80 of the system is described. Although not particularly limited, in this embodiment, THCV 213 is used as the transmission unit 66 and THCV 214 is used as the reception unit 80.

  As shown in FIG. 11, the DRGB_I / F unit 76 of the VDP 62 outputs 18-bit digital RGB data D17 to D0, a 3-bit control signal SYC such as a horizontal / vertical synchronization signal, and an enable signal DE. It is configured to Here, the enable signal DE indicates that the digital RGB data D17 to D0 is being output when it is at the H level, and that the control signal SYC is being output when the enable signal DE is at the L level. Show.

  By the way, in the present embodiment, RGB data is not each 8-bit configuration, but dare to make each 6-bit length (64 gradations) while suppressing the amount of transmission data and increasing the transmission speed, This is because the device configuration such as wiring between the VDP 62 and the transmission unit 66 and the control operation are simplified. In this embodiment, since the sub-display device DS2 is used to perform the movable effect and the notice effect, there is no problem even if the gradation level is lowered. By adopting the above configuration, other game members are enriched. be able to.

  FIG. 11 shows an internal configuration of the transmission unit 66 (THCV 213) and the reception unit 80 (THCV 214), and a connection relationship between the two elements. As shown in the figure, the transmission unit 66 and the reception unit 80 realize transmission of pixel data through a pair of twisted pair lines (TXOUT +, TXOUT−), and do not transmit a transfer clock. Therefore, the number of cable wires and the number of connector terminals can be reduced, and cost reduction and space saving can be realized. In addition, there is an advantage that high-frequency noise associated with transmission of the transfer clock does not occur.

  Further, in this embodiment, the handshake function is automatically realized by taking the LOCKN output of the receiving unit 80 to the INIT terminal of the transmitting unit 66. That is, in a state where data transmission is not in progress, the LOCKN output becomes L level to notify the transmission unit 66 that a predetermined number of serial data should be transmitted, and in response to this, the transmission unit 66 performs transmission processing. Run.

  The transmission process is realized by serially converting the RGB data D17 to D0 and the control signal SYC received from the VDP 62, adding an enable signal DE thereto, and serially outputting them to the twisted pair lines (TXOUT +, TXOUT−). Upon receiving this serial signal, the receiving unit 80 performs parallel conversion on the RGB data D17 to D0 and the control signal SYC and outputs them together with the enable signal DE to the sub display device DS2 to execute an appropriate image effect.

  In this embodiment, it is sufficient to transmit RGB data (8 bits each) of 64 gradations, so that high-speed transmission is not necessary, and stable serial communication can be realized by the above-described handshake operation. Therefore, there is no fear that the character is unnaturally deformed or noise is displayed on the display screen of the sub display device DS2 in the notice effect. In addition, the receiving unit 80 has a clock data recovery (CDR) function. Specifically, the receiving unit 80 detects each edge of serial data to be transferred, so that each serial can be used without using a transfer clock. Since data is acquired accurately, stable serial communication is realized in this sense.

  Incidentally, as shown in FIG. 11, the image interface board 28 outputs two types of DC voltages 5V and 3.3V to the relay board 36. The DC voltage 3.3V is used as a power supply voltage for the logic circuit of the receiver 80 and the sub display device DS2. On the other hand, the DC voltage 5V causes the LED backlight BL of the sub display device DS2 to emit light via the LED driver disposed on the relay board 36.

  The LED driver boosts the DC voltage 5V to about 25 to 35V and supplies it to the LED lamp group. The backlight BL is composed of about 10 LED lamps connected in series, and each LED lamp emits light with a drive current of about 15 to 25 mA. However, it is not always necessary to connect the LED lamps in series, and a configuration in which all LED lamps are connected in parallel, or a configuration in which series connection and parallel connection of LED lamps are combined can be adopted. In such a case, it is not always necessary to boost the DC voltage 5V, and the LED driver can be omitted or simplified.

  As described above, in this embodiment, the backlight BL of the sub-display device DS2 is not used for the cold cathode tube but the LED backlight BL is used, so that the circuit configuration can be simplified and the power consumption can be reduced. . Note that the backlight light can also be PWM controlled by controlling the LED driver.

  Although the embodiments of the present invention have been described in detail above, the specific contents do not particularly limit the present invention. For example, in the embodiment, the VDP 62 and the main display device DS1 include the LVDS transmission unit 75 and the LVDS reception unit 81 (see FIG. 12A). It is also possible to adopt the configuration of b) to FIG. That is, it is also preferable that all or part of the LVDS transmitter 75 and the LVDS receiver 81 are external circuits. In any case, since the transmission path is composed of an LVDS signal path, simplification of the circuit configuration is maintained. However, the configurations shown in FIGS. 12A and 12C are particularly desirable.

  Further, for example, in the embodiment, the V-by-One transmitter 66 and the receiver 80 are external circuits (see FIG. 13A), but instead of this, FIG. The configuration of 13 (d) can also be adopted. That is, it is also preferable to incorporate all or part of the transmission unit 66 and the reception unit 80 in the VDP 62 or the sub display device DS2. In any case, the transmission path is composed of a V-by-One signal path, so that the circuit configuration is extremely simplified.

  Further, the sub display device DS2 of the present embodiment is not limited to the one provided on the game board, and is provided at a predetermined position of the frame side member, for example, a predetermined position of the upper plate 8, a predetermined position of the glass door 6, or the like. May be. In this case, the signal transmission path from the VDP 62 provided on the control board on the back side of the game board becomes longer than the transmission path to the main display device DS1, and if the transmission path becomes longer, the possibility of being affected by noise increases. By adopting the V-by-One method of the present case, not only the circuit configuration can be simplified, but also the noise resistance performance can be improved, and malfunctions caused by noise can be suppressed and stable drawing can be performed.

  Of course, the application of the present invention is not necessarily limited to a ball game machine.

GM gaming machine 22 'effect control unit 54 drive circuit 55 drive circuit

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine having a configuration in which serial data transmission processing and control operations are not wasted.

In order to achieve the above object, the present invention comprises a main control unit that centrally controls a game operation by lottery determination as to whether or not to generate a gaming state advantageous to a player based on a predetermined switch signal; An effect control unit that executes an effect operation including a lamp effect for causing a lamp to emit light based on a control command output by the main control unit, wherein the effect control unit includes: A serial signal including control data and address data for specifying a drive signal for the production operation and a serial signal transmission clock signal are output, and the serial signal transmission path is configured to output the serial signal. The production control unit is configured to be selectively obtainable by a plurality of drive circuits connected in parallel, and the effect control unit includes first address data for specifying a drive circuit from which the control data is to be obtained, and a first address And the second address data specifying the control register of the drive circuit specified by the data, and the drive circuit specified by the first address data obtains control data from a series of serial signals, The drive signal is stored in the control register specified by the second address and the drive signal is output based on the control data stored in the control register.

  Therefore, according to the present invention, it is possible to individually control lighting of a group of lamps grouped into a plurality of sections with the minimum necessary data transmission. As the plurality of drive circuits, circuit elements having the same configuration are typically used.

  As described above, according to the gaming machine of the present invention, there is no waste in serial data transmission processing and control operations.

Claims (8)

Based on a control command output by the main control unit, the main control unit for randomly controlling whether or not to generate a gaming state advantageous to the player based on a predetermined switch signal, and controlling the game operation centrally An effect control unit that executes an effect operation including a lamp effect that causes the lamp to emit light and a movable effect that drives the movable body, and a gaming machine configured to include:
The production control unit is configured to output a series of serial signals in which a lamp drive signal for lamp production and a movable body drive signal for movable production are combined, and is parallel to a transmission path of the series of serial signals. It is configured to be selectively obtainable by a plurality of connected drive circuits,
The drive circuit is configured to output appropriate drive data to a lamp or a movable body based on set values in a plurality of control registers,
The production control unit, prior to transmission of control data that is a set value to the control register, the first address data that specifies the drive circuit from which the control data is to be acquired, and the drive specified by the first address data Configured to transmit second address data specifying a control register of the circuit;
The drive circuit specified by the first address data acquires control data from a series of serial signals and stores the control data in the control register specified by the second address, as well as the lamp drive signal and movable based on the stored control data. A gaming machine configured to output a body drive signal.   The drive circuit receives a 3-bit signal composed of a series of serial signals, a control signal indicating that serial signals are being transmitted, and a serial signal transmission clock signal from the effect control unit. The gaming machine according to claim 1, which is operating.   The gaming machine according to claim 1 or 2, wherein an address value of the driving circuit corresponding to the first address data is fixedly set in advance by a voltage value supplied to an address terminal of the driving circuit. A drive board on which the plurality of drive circuits are mounted is provided separately from the effect control board constituting the effect control unit,
A buffer circuit for receiving the 3-bit signal supplied from the effect control board is provided on the driving board, and the plurality of driving circuits are connected in parallel to the buffer circuit to receive a series of serial signals. The gaming machine according to claim 2.   The drive board receives a sensor signal from N origin sensors that detect origin positions of a plurality of N movable bodies that execute a movable effect, and converts the signal serially and outputs it to the effect control board. The gaming machine according to claim 4, on which is mounted.   The gaming machine according to claim 5, wherein the PS conversion unit is supplied with a control signal defining operation timing of serial conversion and a transmission clock signal of the serially converted sensor signal from the effect control board.   The gaming machine according to claim 1, wherein all or part of the plurality of drive circuits are set to have the same address value.   The ramp effect is executed almost routinely until the lottery result notifying operation for determining whether or not a game state advantageous to the player is generated, while the movable effect is performed prior to the notifying operation. The gaming machine according to claim 1, wherein the gaming machine is configured to be executed at a special timing to be notified.

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