JP2016195197A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing a parasitic capacitance caused by a protection film on a gate electrode.SOLUTION: A semiconductor device having a first region R1 and a second region R2, comprises: a semiconductor laminate 101; a lower electrode 121; a first insulating film 122; a source electrode 107 provided on the semiconductor laminate 101; a drain electrode 105; a gate electrode 106; a first protection film 102 provided at an exposure part of an upper surface of the semiconductor laminate; a second insulating film 142 provided on a surface of the first insulating film and on a part of an upper surface of the first protection film; a second protection film 112 provided on surfaces of the second insulating film 142, the first protection film 102, the source electrode 107, the gate electrode 106, and the drain electrode 105; an upper electrode 123 provided above the lower electrode 121; and a third protection film 141 provided on surfaces of the upper electrode 123 and the second protection film 112. The second insulating film 142 contains silicon oxide.SELECTED DRAWING: Figure 2

Description

  Embodiments described herein relate generally to a semiconductor device.

By using an MMIC amplifier having an FET including a HEMT (High Electron Mobility Transistor) and a MESFET (Metal Semiconductor Field Effect Transistor) and an MIM (Metal Insulator Metal) capacitor, the radar device and the microwave communication device can be downsized. .
In a semiconductor device such as an MMIC amplifier in which an MIM capacitor and an HEMT are formed on the same substrate, the insulating film of the MIM capacitor is made to have a desired film thickness, and the gate protective film of the HEMT is made thin to reduce parasitic capacitance. Is desirable.

JP 2010-129690 A

  Provided is a semiconductor device capable of reducing parasitic capacitance caused by a protective film on a gate electrode.

  According to the embodiment, a semiconductor device having a first region having an MIM capacitor and a second region having a field effect transistor adjacent to the first region, wherein the semiconductor is stacked on the substrate. A body, a lower electrode provided on an upper surface of a part of the semiconductor stacked body in the first region, a first insulating film provided on a surface of the lower electrode in the first region, and the second region Provided between the source electrode provided on the semiconductor laminate, the drain electrode provided on the semiconductor laminate in the second region, and the source electrode and drain electrode in the second region. The source electrode, the drain electrode, and the gate electrode among the gate electrode, the upper surface of the semiconductor stacked body in the first region, the region where the lower electrode is not provided, and the second region A first protective film provided in a region that is not provided; and a second insulating film provided on a surface of the first insulating film and a part of the first protective film in the first region; A second protective film provided on the surface of the second insulating film, on the upper surface of the first protective film, on the surface of the source electrode, on the surface of the gate electrode, and on the surface of the drain electrode; A semiconductor device comprising: an upper electrode provided on the upper surface of the second protective film above the electrode; and a third protective film provided on the surface of the upper electrode and on the surface of the second protective film Is provided. The semiconductor stacked body constituting the second region includes an electron supply layer and a channel layer, and the second insulating film includes silicon oxide.

1 is a plan view of a semiconductor device according to a first embodiment. (A) is a schematic cross-sectional view along the line А-А in FIG. FIG. 5B is a circuit diagram illustrating parasitic capacitance in the vicinity of the gate electrode. 3A to 3D are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 3A is a schematic cross-sectional view illustrating the process up to the formation of the semiconductor stacked body. FIG. 3B is a schematic cross-sectional view illustrating the formation up to the separation region. FIG. 3C is a schematic cross-sectional view illustrating the process up to the formation of the lower electrode. FIG. 3D is a schematic cross-sectional view illustrating the process up to the formation of the insulating film. 4A to 4D are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4A is a schematic cross-sectional view illustrating the process up to the formation of the first insulating film. FIG. 4B is a schematic cross-sectional view illustrating the process up to the formation of the first protective film. 4C and 4D are schematic cross-sectional views for explaining the process up to the formation of the second insulating film. 5A to 5D are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 5A is a schematic cross-sectional view illustrating the process up to the formation of the first protective film. FIG. 5B is a schematic cross-sectional view illustrating the process up to the formation of the ohmic electrode. FIG. 5C is a schematic cross-sectional view illustrating the process up to the formation of the gate electrode. FIG. 5D is a schematic cross-sectional view illustrating the process up to the formation of the pad electrode. 6A to 6C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6A is a schematic cross-sectional view illustrating the process up to the formation of the second protective film. FIG. 6B is a schematic cross-sectional view illustrating the process up to the formation of the upper electrode. FIG. 6C is a schematic cross-sectional view illustrating the formation up to the formation of the third protective film. It is a schematic cross-sectional view illustrating a semiconductor device according to a comparative example. It is a schematic cross section of a semiconductor device according to a second embodiment. FIGS. 9A and 9B are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. FIG. 9A is a schematic cross-sectional view illustrating the process up to the formation of the upper electrode. FIG. 9B is a schematic cross-sectional view illustrating the process up to the formation of the second protective film. 10A to 10D are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third embodiment. FIGS. 10A and 10B are schematic cross-sectional views illustrating the process up to the formation of the first protective film. FIG. 10C is a schematic cross-sectional view illustrating the process up to the formation of the ohmic electrode. FIG. 10D is a schematic cross-sectional view illustrating the process up to the formation of the gate electrode. 11A to 11C are schematic cross-sectional views illustrating the method for manufacturing a semiconductor device according to the third embodiment. FIG. 11A is a schematic cross-sectional view illustrating the formation up to the formation of the lower electrode and the pad electrode. FIGS. 11B and 11C are schematic cross-sectional views for explaining the process up to the formation of the first insulating film. FIGS. 12A and 12B are schematic cross-sectional views illustrating the process up to the formation of the second insulating film in the method for manufacturing the semiconductor device according to the third embodiment. FIG. 13A is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. FIG. 13B is a schematic cross-sectional view illustrating the formation of the first protective film in the method for manufacturing a semiconductor device according to the fifth embodiment. FIG. 14A is a schematic cross-sectional view of the semiconductor device according to the sixth embodiment. FIG. 14B is a schematic cross-sectional view illustrating the process up to the formation of the first protective film in the semiconductor device manufacturing method according to the sixth embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a plan view of the semiconductor device according to the present embodiment.
In the semiconductor device according to the present embodiment, the MIM capacitor and the HEMT are formed on the same substrate.

First, the configuration of the semiconductor device 100 according to the present embodiment will be described.
As illustrated in FIG. 1, the semiconductor device 100 according to the present embodiment includes a HEMT 110 provided on a substrate 101. The HEMT 110 includes a finger-shaped source electrode 107, a finger-shaped drain electrode 105, and a gate electrode 106 between the source electrode 107 and the drain electrode 105. Further, the semiconductor device 100 includes an MIM capacitor 104 provided on the substrate 101. An isolation region 103 is provided between the MIM capacitor 104 and the HEMT 110.

FIG. 2A is a schematic cross-sectional view along the line А-А in FIG.
As shown in FIG. 2, the semiconductor device 100 according to the present embodiment includes an MIM capacitor region R <b> 1 and a HEMT region R <b> 2 that is a part of the HEMT 110.

In the lowermost layer of the semiconductor device 100 according to the present embodiment, the semiconductor stacked body 101 is provided over the entire surface of the MIM capacitor region R1 and the HEMT region R2. The semiconductor stacked body 101 is formed by stacking a substrate 101a, a buffer layer 101e, a channel layer 101b, and an electron supply layer 101c in this order.
The buffer layer 101e is a semiconductor containing, for example, gallium nitride (GaN). The channel layer 101b is a semiconductor containing gallium nitride, for example. The electron supply layer 101c is, for example, a semiconductor that forms a heterojunction with the channel layer 101b and includes, for example, Al _0.2 Ga _0.8 N.

The electrons that have moved from the electron supply layer 101c to the channel layer 101b form a two-dimensional electron gas layer (2DEG) 101d on the channel layer 101b, and become a high mobility and high density electron gas.
The buffer layer 101e, the channel layer 101b, and the electron supply layer 101c around the MIM capacitor region R1 and the HEMT region R2 are provided with an isolation region 103 whose resistance is increased by ion implantation or the like. Thereby, in the HEMT region R2, it is possible to suppress leakage of electrons that have moved from the electron supply layer 101c to the channel layer 101b to other circuit elements such as an MIM capacitor.

  In the MIM capacitor region R1, a lower electrode 121 is provided on a part of the upper surface of the semiconductor stacked body 101. A first insulating film 122 is provided on the surface of the lower electrode 121 and on a part of the upper surface of the semiconductor stacked body 101.

  In the HEMT region R2, a source electrode 107, a gate electrode 106, and a drain electrode 105 are provided on the semiconductor stacked body 101 in order from the MIM capacitor region R1 side.

  A source electrode 107, a drain electrode 105, or a gate electrode 106 is provided on a part of the semiconductor stacked body 101 where the lower electrode 121 is not provided in the MIM capacitor region R1 and on the semiconductor stacked body 101 in the HEMT region R2. A first protective film 102 is provided in a portion that does not exist.

A second insulating film 142 is provided on the surface of the first insulating film 122 and on a part of the upper surface of the first protective film. The second insulating film 142 includes, for example, silicon oxide (SiO ₂ ).
On the entire surface of the MIM capacitor region R1 and the HEMT region R2, that is, on the surface of the second insulating film 142, on the upper surface of the first protective film 102, on the surface of the source electrode 107, on the surface of the gate electrode 106, and on the surface of the drain electrode 105 A second protective film 112 is provided.

  An upper electrode 123 is provided on the upper surface of the second protective film 112 above the lower electrode 121. A third protective film 141 is provided on the surface of the upper electrode 123 and the surface of the second protective film 112.

  A part of the source electrode 107 is adjacent to the first protective film 102 through the boundary surface 131. The source electrode 107 is formed of an ohmic electrode 118 provided on the semiconductor stacked body 101 and a pad electrode 119 provided thereon. The length of the pad electrode 119 in the direction from the source electrode 107 to the drain electrode 105 is smaller than the length of the ohmic electrode 118 in the direction from the source electrode 107 to the drain electrode 105, and has a convex shape when viewed from the direction perpendicular to the paper surface. doing. The pad electrode 119 is provided to reduce the wiring resistance value to the source electrode 107.

  The gate electrode 106 is formed of a gate electrode lower portion 108 provided on the semiconductor stacked body 101 and a gate electrode upper portion 109 provided thereon. The length of the gate electrode upper portion 109 in the direction from the source electrode 107 to the drain electrode 105 is larger than the length of the gate electrode lower portion 108 in the direction from the source electrode 107 to the drain electrode 105, and is substantially as viewed from the direction perpendicular to the paper surface. T-shaped. The gate electrode upper portion 109 is provided to reduce the wiring resistance value to the gate electrode lower portion 108.

The drain electrode 105 is formed of an ohmic electrode 128 provided on the semiconductor stacked body 101 and a pad electrode 129 provided thereon. The length of the pad electrode 129 in the direction from the source electrode 107 to the drain electrode 105 is smaller than the length of the ohmic electrode 128 in the direction from the source electrode 107 to the drain electrode 105, and has a convex shape when viewed from the direction perpendicular to the paper surface. doing. The pad electrode 129 is provided to reduce the wiring resistance value to the drain electrode 105.
The lower electrode 121, the upper electrode 123, the separation region 103, the source electrode 107, the gate electrode 106, and the drain electrode 105 extend in a direction perpendicular to the paper surface.

The thickness of the source electrode 107 is approximately the same as the thickness of the drain electrode 105. The gate electrode 106 is thinner than the source electrode 107.
The film thickness t102 of the first protective film 102 is, for example, 200 to 500 mm.
The film thickness of the ohmic electrode 118 is approximately the same as the film thickness of the ohmic electrode 128 and is thicker than the film thickness of the first protective film 102.
The total film thickness of the film thickness t105 of the second protective film 112 on the gate electrode 106 and the film thickness t104 of the third protective film 141 is, for example, 500 mm.
The film thickness t101 of the first insulating film 122 sandwiched between the lower electrode 121 and the upper electrode 123, the film thickness t106 of the second insulating film 142, and the film thickness t103 of the second protective film 112 can obtain a desired breakdown voltage. , Each dielectric constant is designed in consideration.
In the semiconductor device 100 according to the present embodiment, an example in which one MIM capacitor 104 is provided is shown, but the present invention is not limited to this.

Next, a method for manufacturing the semiconductor device 100 according to the present embodiment will be described.
FIG. 3A is a schematic cross-sectional view illustrating the process up to the formation of the semiconductor stacked body.
First, the buffer layer 101e, the channel layer 101b, and the electron supply layer 101c are laminated and formed in this order on the substrate 101a using the MOCVD (Metal Organic Chemical Vapor Deposition) method, the MBE (EMolecular Beam Epitaxy) method, or the like.

FIG. 3B is a schematic cross-sectional view illustrating the formation up to the separation region.
When the buffer layer 101e, the channel layer 101b, and the electron supply layer 101c are formed of a semiconductor containing gallium nitride, for example, argon (Аr) ions or the like are implanted into a desired portion to form the isolation region 103. The isolation region 103 can electrically isolate the MIM capacitor region R1 and the HEMT region R2.

  Note that the isolation region 103 specifies a range to be removed by lithography, and after selectively removing a part of the semiconductor stacked body 101 by performing etching, the removed portion includes, for example, silicon nitride (SiN) or the like. Alternatively, the insulating material may be embedded.

FIG. 3C is a schematic cross-sectional view illustrating the process up to the formation of the lower electrode.
For example, titanium (Ti) and nickel (Ni) are vapor-deposited in this order on the upper surface of a part of the semiconductor stacked body 101 in the MIM capacitor region R1 to form the lower electrode 121. Further, for example, platinum (Pt) may be used instead of nickel (Ni).

FIG. 3D is a schematic cross-sectional view illustrating the process up to the formation of the insulating film.
For example, silicon nitride (SiN) is deposited on the upper surface of the semiconductor stacked body 101 and the surface of the lower electrode 121 to form the insulating film 172.

FIG. 4A is a schematic cross-sectional view illustrating the process up to the formation of the first insulating film.
A region to be removed is specified by lithography, and etching is performed to selectively remove the insulating film 172 and form the insulating film 122. The film thickness (t101) of the insulating film 122 which is the remaining part of the insulating film 172 maintains the film thickness of the insulating film 172 over the lower electrode 121.

FIG. 4B is a schematic cross-sectional view illustrating the process up to the formation of the first protective film.
For example, silicon nitride (SiN) is deposited on the upper surface of the semiconductor stacked body 101, the upper surface of the isolation region 103, and the surface of the first insulating film 122 to form the first protective film 152. The film thickness t102 of the first protective film 152 is, for example, 200 to 500 mm.

FIG. 4C is a schematic cross-sectional view illustrating the process up to the formation of the second insulating film.
On the surface of the first insulating film 122 and the upper surface of the first protective film 152, for example, silicon oxide (SiO ₂ ) is deposited using a plasma CVD (Chemical Vapor Deposition) method to form the insulating film 173.
The silicon oxide etch rate is about 10 times the silicon nitride etch rate.

FIG. 4D is a schematic cross-sectional view illustrating the process up to the formation of the second insulating film.
In the insulating film 173, a range to be removed by lithography is specified, and the insulating film 173 is selectively removed by etching to form the second insulating film 142. At this time, the etching rate of the insulating film 173 containing silicon oxide is about 10 times the etching rate of the first protective film 152 containing silicon nitride. Therefore, the unnecessary insulating film 173 is removed, and the first protective film 102 remains without being removed. The portion of the insulating film 173 that remains without being removed is referred to as a second insulating film 142. The film thickness of the second insulating film 142 on the lower electrode 121 is set to t106.

FIG. 5A is a schematic cross-sectional view illustrating the process up to the formation of the first protective film.
In the insulating film 152 in the HEMT region R2, a range to be removed by lithography is specified, and the insulating film 152 is selectively removed by performing etching. The remainder is the first protective film 102. In addition, the removed portions are defined as openings 161, 162, and 163 in order from the MIM capacitor region R1 side.

FIG. 5B is a schematic cross-sectional view illustrating the process up to the formation of the ohmic electrode.
In the opening 161 on the semiconductor stacked body 101, for example, aluminum (Аl), titanium (Ti), platinum (Pt), and gold (Аu) are deposited in this order to form the ohmic electrode 118. At the same time, for example, aluminum, titanium, platinum, and gold are vapor-deposited in this order in the opening 163 to form the ohmic electrode 128. Thereafter, annealing is performed at about 600 ° C. to about 700 ° C.

FIG. 5C is a schematic cross-sectional view illustrating the process up to the formation of the gate electrode.
In the opening 162 on the semiconductor stacked body 101, for example, nickel (Ni) and gold (Аu) are deposited to form the gate electrode 106 including the gate electrode lower part 108 and the gate electrode upper part 109.

FIG. 5D is a schematic cross-sectional view illustrating the process up to the formation of the pad electrode.
A metal is vapor-deposited on a part of the upper surface of the ohmic electrodes 118 and 128 to form pad electrodes 119 and 129, and a source electrode 107 and a drain electrode 105 including the ohmic electrodes 118 and 128 and the pad electrodes 119 and 129 are formed.

FIG. 6A is a schematic cross-sectional view illustrating the process up to the formation of the second protective film.
For example, silicon nitride is deposited on the entire surface of the wafer, that is, the entire surface of the MIM capacitor region R1 and the HEMT region R2, to form the second protective film 112. At this time, in order to reduce the parasitic capacitance C12 generated by the second protective film 112 on the gate electrode 106, the second protective film 112 is formed thin.

FIG. 6B is a schematic cross-sectional view illustrating the process up to the formation of the upper electrode.
A metal is deposited on the second protective film 112 above the lower electrode 121 to form the upper electrode 123.

FIG. 6C is a schematic cross-sectional view illustrating the formation up to the formation of the third protective film.
For example, silicon nitride is deposited on the entire surface of the wafer, that is, the entire surface of the MIM capacitor region R1 and the HEMT region R2, thereby forming the third protective film 141. At this time, the second protective film 112 and the third protective film 141 are formed thin in order to reduce the parasitic capacitance C12 generated by the second protective film 112 and the third protective film 141 on the gate electrode 106.

Next, the operation of the semiconductor device 100 according to this embodiment will be described.
As shown in FIG. 2A, in the MIM capacitor region R1, the lower electrode 121 and the upper electrode 123, and the first insulating film 122, the second insulating film 142, and the second protective film 112 sandwiched therebetween. Thus, the capacitor C11 is formed. When the total thickness of the film thickness t101 of the first insulating film 122, the film thickness t106 of the second insulating film, and the film thickness t103 of the second protective film 112 is increased, the withstand voltage V11 of the capacitor C11 increases, The capacity value is lowered. The capacity is adjusted to a desired value by the film thickness and the electrode area.
Since the second protective film 112 extends to the HEMT region R2 while maintaining the same film thickness, it is preferable to keep the film thickness t103 constant.
A material having a relative dielectric constant smaller than that of the first insulating film 122 may be used as the material of the second insulating film 142.

For example, when silicon oxide having a relative dielectric constant lower than that of silicon nitride is used as the material of the second insulating film 142, a desired capacitance per unit area can be obtained even if the required film thickness is reduced.
As a result, the film thickness required to obtain a desired capacity per unit area, compared to the case where the first insulating film 122, the second insulating film 142, and the second protective film 112 are all formed of silicon nitride. Can be formed thinly.

For example, the relative dielectric constant of silicon nitride is 7.0, the relative dielectric constant of silicon oxide is 3.5, and the material of the first insulating film 122, the second protective film 112, and the second insulating film 142 is silicon nitride. In the case of a product, the total film thickness of the film thickness t101 and the film thickness t103 is 100 nanometers, and the film thickness t106 is 100 nanometers to obtain a desired capacity per unit area. It is.
On the other hand, when the material of the second insulating film 142 is changed to silicon oxide, the film thickness t106 is 50 nanometers. That is, the film thickness t106 can be reduced by 50 nanometers.

In the HEMT region R2, a parasitic capacitance C12 is generated by the second protective film 112 and the third protective film 141 on the gate electrode 106. As shown in FIG. 2B, the parasitic capacitance C12 includes a gate C / drain D capacitance C _gd , a gate G / source S capacitance C _gs, and a drain D / source S capacitance C _ds . The capacitance value of the parasitic capacitance C12 varies depending on the total thickness of the film thickness t105 of the second protective film 112 and the film thickness t104 of the third protective film 141. If the total thickness of the film thickness t105 and the film thickness t104 is increased, the parasitic capacitance C12 is increased, and the gain and efficiency of the semiconductor device 100 are reduced.

  Therefore, the total film thickness of the film thickness t105 and the film thickness t104 is formed thin, and the deterioration of the high frequency characteristics due to the parasitic capacitance C12 is suppressed. For example, the total film thickness of the film thickness t105 and the film thickness t104 is formed thinner than the total film thickness of the film thickness t101, the film thickness t106, and the film thickness t103. The total film thickness of the film thickness t105 and the film thickness t104 is, for example, 500 mm.

Next, effects of the semiconductor device 100 according to the present embodiment will be described.
In the semiconductor device 100 according to the present embodiment, silicon oxide having a relative dielectric constant lower than that of silicon nitride is used as the material of the second insulating film 142, and the total of the film thickness t101, the film thickness t106, and the film thickness t103. The film thickness is such that the desired breakdown voltage can be obtained. Further, the total film thickness of the film thickness t105 and the film thickness t104 is formed thin.

  Thereby, in the HEMT region R2, a semiconductor device capable of reducing the parasitic capacitance C12 caused by the second protective film 112 and the third protective film 141 on the gate electrode 106 can be provided. For example, when the parasitic capacitance C12 decreases by 20%, the gain of the semiconductor device 100 increases by 1 dB. In the MIM capacitor region R1, a desired breakdown voltage can be ensured without requiring a large film thickness as a total film thickness of the film thickness t101, the film thickness t106, and the film thickness t103.

  In the semiconductor device 100 according to the present embodiment, an example in which a HEMT is provided is shown, but the present invention is not limited to this, and a field effect transistor other than a HEMT may be used.

(Comparative example)
FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device according to this comparative example.
As shown in FIG. 7, the semiconductor device 200 according to this comparative example is different from the first embodiment described above in that the insulating film 211 extends to the HEMT region R2. Thus, the film thickness t202 of the insulating film 211 on the lower electrode 221 is approximately equal to the total film thickness of the film thickness t203 of the insulating film 211 on the gate electrode 206 and the film thickness t205 of the second protective film 212. It has become.

  When the film thickness t202 of the insulating film 211 in the MIM capacitor region R1 is formed to such a thickness that a desired breakdown voltage can be obtained, the film thickness t203 of the insulating film 211 on the gate electrode 206 in the HEMT region R2 is also t202. The film thickness is about the same, and the influence of the parasitic capacitance C22 generated thereby becomes large. On the other hand, when the film thickness t203 is formed thin in order to reduce the influence of the parasitic capacitance C22, it is difficult to obtain a desired breakdown voltage in the HEMT region R2.

  That is, in the semiconductor device 200 according to this comparative example, it is difficult to secure a desired breakdown voltage in the MIM capacitor region R1 and reduce the parasitic capacitance caused by the protective film on the gate electrode in the HEMT region R2.

(Second Embodiment)
FIG. 8 is a schematic cross-sectional view of the semiconductor device according to the present embodiment.
The semiconductor device 300 according to the present embodiment differs from the semiconductor device 100 according to the first embodiment described above in the following (a) to (c).
(А) An upper electrode 323 is provided on the second insulating film 342 in the MIM capacitor region R1.
(B) A second protective film 312 is provided so as to cover the upper electrode 323.
(C) Because of the above (b), a protective film corresponding to the third protective film 141 shown in FIG. 2A is not provided.
Other configurations in the present embodiment are the same as those in the first embodiment.

Next, a method for manufacturing the semiconductor device 300 according to the present embodiment will be described.
Up to the formation of the pad electrodes 119 and 129 (see FIG. 5D) is the same as the method for manufacturing the semiconductor device according to the first embodiment described above.

FIG. 9A is a schematic cross-sectional view illustrating the process up to the formation of the upper electrode 323.
Above the lower electrode 321, a metal is deposited on the second insulating film 342 to form the upper electrode 323.

FIG. 9B is a schematic cross-sectional view illustrating the process up to the formation of the second protective film 312.
For example, silicon nitride is deposited on the entire surface of the wafer, that is, on the entire surface of the MIM capacitor region R1 and the HEMT region R2, thereby forming the second protective film 312. At this time, in order to reduce the parasitic capacitance generated by the second protective film 312 over the gate electrode 306, the second protective film 312 is formed thin. The film thickness t303 of the second protective film 312 on the gate electrode 306 is, for example, 500 mm.
The manufacturing method other than the above in this embodiment is the same as that in the first embodiment.

Next, the operation of the semiconductor device 300 according to this embodiment will be described.
As shown in FIG. 8, in the MIM capacitor region R1, a capacitor C31 is formed by the lower electrode 321 and the upper electrode 323, and the first insulating film 322 and the second insulating film 342 sandwiched therebetween. . When the total film thickness t301 of the first insulating film 322 and the film thickness t306 of the second insulating film is increased, the withstand voltage V31 of the capacitor C31 increases and the capacitance value per unit area decreases. The capacity is adjusted to a desired value by the film thickness and the electrode area.

Therefore, in order to obtain a desired breakdown voltage even if the required film thickness is reduced, silicon oxide having a relative dielectric constant lower than that of silicon nitride is used as the material of the second insulating film 342.
Thereby, compared with the case where all the materials of the first insulating film 322 and the second insulating film 342 are formed of silicon nitride, a film thickness necessary for obtaining a desired breakdown voltage can be formed thin.

  In the HEMT region R2, a parasitic capacitance C32 is generated by the second protective film 312 on the gate electrode 306. The capacitance value of the parasitic capacitance C32 varies depending on the film thickness t303 of the second protective film 312. When the film thickness t303 is formed thick, the parasitic capacitance C32 increases, and the gain and efficiency of the semiconductor device 300 decrease.

Therefore, the film thickness t303 is formed thin to suppress the deterioration of the high frequency characteristics due to the parasitic capacitance C32. The film thickness t303 is, for example, 500 mm.
Operations other than those described above in the present embodiment are the same as those in the first embodiment described above.

Next, effects of the semiconductor device 300 according to the present embodiment will be described.
The semiconductor device 300 according to the present embodiment does not require the third protective film 141 shown in FIG. 1 compared to the semiconductor device 100 according to the first embodiment described above. Thereby, the process of forming a 3rd protective film can be reduced. In addition, the protective film over the gate electrode 306 can be formed thinner to further reduce the parasitic capacitance.
The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

(Third embodiment)
A method for manufacturing the semiconductor device 400 in the present embodiment will be described.
Up to the formation of the isolation region 103 (see FIG. 3B) is the same as the semiconductor device manufacturing method according to the first embodiment described above.

FIG. 10A is a schematic cross-sectional view illustrating the process up to the formation of the first protective film.
On the semiconductor stacked body 401 and the isolation region 403, for example, silicon nitride (SiN) is deposited to form an insulating film 452. The film thickness t402 of the insulating film 452 is, for example, 200 to 500 mm.

FIG. 10B is a schematic cross-sectional view illustrating the process up to the formation of the openings 461, 462, 463, and 464.
In the insulating film 452, a range to be removed by lithography is specified, and the insulating film 452 is selectively removed by performing etching. The remainder is the first protective film 402. The removed portion in the MIM capacitor region R1 is referred to as an opening 464. The removed portions in the HEMT region R2 are referred to as openings 461, 462, and 463 in order from the MIM capacitor region R1 side.

FIG. 10C is a schematic cross-sectional view illustrating the process up to the formation of the ohmic electrode.
In the opening 461 on the semiconductor stacked body 101, for example, aluminum (Аl), titanium (Ti), platinum (Pt), and gold (Аu) are deposited in this order to form the ohmic electrode 418. At the same time, for example, aluminum, titanium, platinum, and gold are vapor-deposited in this order in the opening 463 to form the ohmic electrode 428. Thereafter, annealing is performed at about 600 ° C. to about 700 ° C.

FIG. 10D is a schematic cross-sectional view illustrating the process up to the formation of the gate electrode.
In the opening 462 on the semiconductor stacked body 401, for example, nickel (Ni) and gold (Аu) are deposited to form the gate electrode 406 including the gate electrode lower portion 408 and the gate electrode upper portion 409.

FIG. 11A is a schematic cross-sectional view illustrating the formation up to the formation of the lower electrode and the pad electrode.
A lower electrode 421 is formed by vapor-depositing a metal on a part of the upper surface of the semiconductor stacked body 401 in the MIM capacitor region R2. At the same time, a metal is deposited on a part of the upper surface of the ohmic electrode 418 to form a pad electrode 419, and a source electrode 407 including the ohmic electrode 418 and the pad electrode 419 is formed. At the same time, a metal is deposited on a part of the upper surface of the ohmic electrode 428 to form a pad electrode 429, and a drain electrode 405 including the ohmic electrode 428 and the pad electrode 429 is formed.

FIG. 11B is a schematic cross-sectional view illustrating the process up to the formation of the first insulating film.
For example, silicon nitride is deposited on the entire surface of the MIM capacitor region R1 and the HEMT region R2 to form the first insulating film 472. The etching rate of the first insulating film 472 with respect to the etching solution is set higher than the etching rate of the first protective film 402 with respect to the etching solution.

FIG. 11C is a schematic cross-sectional view illustrating the process up to the formation of the first insulating film.
In the first insulating film 472, a range to be removed by lithography is specified, and etching is performed to selectively remove the first insulating film 472. At this time, the etching rate of the first insulating film 472 is about 30 times the etching rate of the first protective film 402 that has already been annealed. Accordingly, the first insulating film 472 within the range to be removed is removed, and the first protective film 402 remains without being removed. The first insulating film 472 that remains without being removed is referred to as a first insulating film 422.

FIG. 12A is a schematic cross-sectional view illustrating the process up to the formation of the second insulating film in the semiconductor device manufacturing method according to the present embodiment.
For example, silicon oxide (SiO 2) is deposited on the entire surfaces of the MIM capacitor region R 1 and the HEMT region R 2 to form the second insulating film 472.

FIG. 12B is a schematic cross-sectional view illustrating the process up to the formation of the second insulating film in the semiconductor device manufacturing method according to the present embodiment.
A range to be removed by lithography is specified, and etching is performed to selectively remove the second insulating film 472 and form a second insulating film 442. The film thickness of the second insulating film 442 on the lower electrode 421 is set to t406.

From the formation of the second protective film (see FIG. 6 (a)) to the formation of the third protective film (see FIG. 6 (c)) is the same as in the first embodiment.
Other configurations, manufacturing methods, operations, and effects in the present embodiment are the same as those in the first embodiment described above.

(Fourth embodiment)
A method for manufacturing a semiconductor device in the present embodiment will be described.
Up to the formation of the second insulating film (see FIG. 12B) is the same as the semiconductor device manufacturing method according to the third embodiment described above.

Subsequent formation of the upper electrode (see FIG. 9A) is the same as the method for manufacturing the semiconductor device according to the second embodiment described above.
The configuration, operation, and effect of the semiconductor device in this embodiment are the same as those in the second embodiment.

(Fifth embodiment)
FIG. 13A is a schematic cross-sectional view of the semiconductor device according to the present embodiment.
Compared with the semiconductor device according to the third embodiment described above, the semiconductor device 600 according to the present embodiment includes a gap between the semiconductor stacked body 601 and the lower electrode 621, and between the semiconductor stacked body 601 and the first insulating film 622. A difference is that the first protective film 602 is also provided between the semiconductor stacked body 601 and the second insulating film 642.

Next, a method for manufacturing the semiconductor device 600 according to the present embodiment will be described.
Up to the formation of the insulating film 452 (see FIG. 10A) is the same as the semiconductor device manufacturing method according to the third embodiment described above.

FIG. 13B is a schematic cross-sectional view illustrating the formation of the first protective film in the method for manufacturing the semiconductor device according to the present embodiment.
In the insulating film 452 shown in FIG. 10A, a range to be removed by lithography is specified, and the insulating film 452 is selectively removed by etching, and the remaining portion is used as the first protective film 602. The subsequent formation of the ohmic electrode (see FIG. 10C) is the same as in the third embodiment.

Next, effects of the semiconductor device 600 according to the present embodiment will be described.
In the method for manufacturing the semiconductor device 600 according to the present embodiment, as shown in FIG. 13B, the semiconductor stacked body 601 is covered by covering the semiconductor stacked body 601 in the MM capacitor region R1 with the first protective film insulating film 602. Can protect the surface.
Other configurations, manufacturing methods, operations, and effects of the present embodiment are the same as those of the third embodiment described above.

(Sixth embodiment)
FIG. 14A is a schematic cross-sectional view of the semiconductor device according to the sixth embodiment.
Compared with the semiconductor device according to the fourth embodiment described above, the semiconductor device 700 according to this embodiment includes a gap between the semiconductor stacked body 701 and the lower electrode 721, and between the semiconductor stacked body 701 and the first insulating film 722. The difference is that the first protective film 702 is also provided between the semiconductor stacked body 701 and the second insulating film 742.
Configurations, operations, and effects other than those described above in the present embodiment are the same as those in the fourth embodiment described above.

Next, a method for manufacturing the semiconductor device 700 according to this embodiment will be described.
Up to the formation of the insulating film (see FIG. 10A) is the same as the method for manufacturing the semiconductor device according to the fourth embodiment described above.

FIG. 14B is a schematic cross-sectional view for explaining the formation of the first protective film in the method for manufacturing the semiconductor device according to the present embodiment.
In the insulating film 452 shown in FIG. 10A, a range to be removed by lithography is specified, and the insulating film 452 is selectively removed by etching, and the remaining portion is used as the first protective film 702. The subsequent formation of the ohmic electrode (see FIG. 10C) is the same as that of the fourth embodiment described above.

Next, effects of the semiconductor device 700 according to the present embodiment will be described.
In the method for manufacturing the semiconductor device 700 according to this embodiment, as shown in FIG. 14B, the semiconductor stacked body 701 is covered by covering the semiconductor stacked body 701 in the MM capacitor region R1 with the first protective film insulating film 702. Can protect the surface.
Other configurations, manufacturing methods, operations, and effects in the present embodiment are the same as those in the fourth embodiment described above.

  According to the embodiment described above, it is possible to provide a semiconductor device capable of reducing the parasitic capacitance caused by the protective film on the gate electrode.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalents thereof.

100, 200, 300, 400, 600, 700 Semiconductor device 101, 201, 301, 401, 601, 701 Semiconductor stack, 101a, 301a, 401a, 601a, 701a Substrate, 101b, 301b, 401b, 601b, 701b Channel Layer, 101c, 301c, 401c, 601c, 701c electron supply layer, 101d, 301d, 401d, 601d, 701d two-dimensional electron gas layer, 101e, 301e, 401e, 601e, 701e buffer layer, 102, 202, 302, 402, 452, 602, 702 First protective film, 103, 303, 403, 603, 703 Separation region, 161, 162, 163, 164, 461, 462, 463, 464, 661, 662, 663, 664, 761, 762, 763, 764 opening 105, 205, 305, 405, 605, 705 Drain electrode, 106, 206, 306, 406, 606, 706 Gate electrode, 107, 207, 307, 407, 607, 707 Source electrode, 108, 208, 308, 408 , 608, 708 Lower gate electrode, 109, 209, 309, 409, 609, 709 Upper gate electrode, 118, 318, 418, 618, 718, 128, 328, 428, 628, 728 Ohmic electrode, 119, 319, 419 , 619, 719, 129, 329, 429, 629, 729 Pad electrode, 112, 212, 312, 412, 612, 712 Second protective film, 141, 341, 441, 641 Third protective film, 121, 221, 321 , 421, 621, 721 Lower electrode, 122, 142, 21, 322, 422, 622, 722, 152, 352, 172, 372 Insulating film, 123, 223, 323, 423, 623, 723 Upper electrode, 131, 231, 331, 431, 631, 731 Interface, 132, 232, 332, 432, 632, 732 End face, 133, 233, 333, 433, 633, 733 End face, 104 MIM capacitor, R1 MIM capacitor area, R2 HEMT area, C11, C21, C31 capacitor, C12, C22, C32 Parasitic Capacitance, C _gd gate-drain capacitance, C _gs gate-source capacitance, C _ds drain-source capacitance, G gate, D drain, S source, t101, t102, t103, t104, t105, t106, t202, t203 , T205, t301, t303, 401, t403 thickness, V11, V31 breakdown voltage

Claims (10)

A semiconductor device comprising: a first region having an MIM capacitor; and a second region having a field effect transistor adjacent to the first region,
A semiconductor laminate in which a semiconductor is laminated on a substrate;
A lower electrode provided on an upper surface of a part of the semiconductor stacked body in the first region;
A first insulating film provided on a surface of the lower electrode in the first region;
A source electrode provided on the semiconductor laminate in the second region;
A drain electrode provided on the semiconductor laminate in the second region;
A gate electrode provided between the source electrode and the drain electrode in the second region;
Of the upper surface of the semiconductor stacked body in the first region, the region where the lower electrode is not provided and the source electrode, the drain electrode and the gate electrode are not provided in the second region. A first protective film provided in the region;
A second insulating film provided on a surface of the first insulating film and a part of the upper surface of the first protective film in the first region;
A second protective film provided on the surface of the second insulating film, on the upper surface of the first protective film, on the surface of the source electrode, on the surface of the gate electrode, and on the surface of the drain electrode;
An upper electrode provided on the upper surface of the second protective film above the lower electrode;
A third protective film provided on the surface of the upper electrode and on the surface of the second protective film;
With
The semiconductor stacked body constituting the second region includes an electron supply layer and a channel layer,
The second insulating film is a semiconductor device containing silicon oxide.   The semiconductor device according to claim 1, wherein the semiconductor stacked body further includes an isolation region between the first region and the second region.   The semiconductor device according to claim 2, wherein the isolation region is an electrically insulating layer into which ions are implanted.   The semiconductor device according to claim 1, further comprising a buffer layer provided between the substrate and the semiconductor.   The semiconductor device according to claim 1, wherein at least one of the first protective film, the second protective film, and the third protective film includes silicon nitride.   2. The semiconductor device according to claim 1, wherein a total film thickness of the second protective film and the third protective film is 500 angstroms or less.   2. The semiconductor device according to claim 1, wherein the lower electrode is provided on a region of the upper surface of the semiconductor stack in the first region that is not covered with the first protective film.   The semiconductor device according to claim 1, wherein the first protective film covers a surface of the semiconductor stacked body in the first region, and the lower electrode is provided on the first protective film. A semiconductor device comprising: a first region having an MIM capacitor; and a second region having a field effect transistor adjacent to the first region,
A semiconductor laminate in which a semiconductor is laminated on a substrate;
A lower electrode provided above the semiconductor stack in the first region;
A first insulating film provided on a surface of the lower electrode in the first region;
A source electrode provided on the semiconductor laminate in the second region;
A drain electrode provided on the semiconductor laminate in the second region;
A gate electrode provided between the source electrode and the drain electrode in the second region;
First protection provided in at least a partial region of the upper surface of the semiconductor stacked body in the first region, and a portion of the second region where the source electrode, the drain electrode, or the gate electrode is not provided. A membrane,
A second insulating film provided on the surface of the first insulating film and on an upper surface of a part of the first protective film;
An upper electrode provided on the upper surface of the second insulating film above the lower electrode;
A first electrode provided on a surface of the upper electrode; on a surface of the second insulating film; on an upper surface of the first protective film; on a surface of the source electrode; on a surface of the gate electrode; and on a surface of the drain electrode. Two protective films;
With
The second region of the semiconductor includes at least an electron supply layer and a channel layer,
The second insulating film is a semiconductor device containing silicon oxide.   The semiconductor device according to claim 1, wherein the first protective film covers a surface of the semiconductor stacked body in the first region, and the lower electrode is provided on the first protective film.

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