JP2016195195A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2016195195A
JP2016195195A JP2015074813A JP2015074813A JP2016195195A JP 2016195195 A JP2016195195 A JP 2016195195A JP 2015074813 A JP2015074813 A JP 2015074813A JP 2015074813 A JP2015074813 A JP 2015074813A JP 2016195195 A JP2016195195 A JP 2016195195A
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electrode
region
semiconductor device
protective film
semiconductor
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一考 高木
Kazutaka Takagi
一考 高木
博幸 桜井
Hiroyuki Sakurai
博幸 桜井
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing a parasitic capacitance caused by a protection film on a gate electrode.SOLUTION: A semiconductor device 100 having a first region R1 and a second region R2 adjacent to the first region R1, comprises: a semiconductor laminate 101; a lower electrode 121; an insulating film 122; a source electrode 107; a drain electrode 105; a gate electrode 106; a first protection film 102 provided on a surface of the insulating film 122 and at an exposure part of the semiconductor laminate 101; an upper electrode 123 provided on an upper surface of the first protection film 102 above the lower electrode 121; and a second protection film 112 provided on surfaces of the upper electrode 123, the first protection film 102, the source electrode 107, the gate electrode 106, and the drain electrode 105. A film thickness of the second protection film 112 on the gate electrode 106 is smaller than a sum of a film thickness of the insulating film 122 and a film thickness of the first protection film 102, between the lower electrode 121 and the upper electrode 123.SELECTED DRAWING: Figure 2

Description

本発明の実施形態は、半導体装置に関する。   Embodiments described herein relate generally to a semiconductor device.

ＨＥＭＴ(High Electron Mobility Transistor)やＭＥＳＦＥＴ(Metal Semiconductor Field Effect Transistor)を含むＦＥＴ及びＭＩＭ（Metal Insulator Metal）キャパシタを有するＭＭＩＣ増幅器を用いることにより、レーダー装置やマイクロ波通信機器を小型化することができる。
ＭＩＭキャパシタとＨＥＭＴとを同一基板上に形成したＭＭＩＣ増幅器等の半導体装置においては、ＭＩＭキャパシタの絶縁膜を所望の膜厚とすると共に、ＨＥＭＴのゲート保護膜を薄くし、寄生容量を低減することが望ましい。 By using an MMIC amplifier having an FET including a HEMT (High Electron Mobility Transistor) and a MESFET (Metal Semiconductor Field Effect Transistor) and an MIM (Metal Insulator Metal) capacitor, the radar device and the microwave communication device can be downsized. .
In a semiconductor device such as an MMIC amplifier in which an MIM capacitor and an HEMT are formed on the same substrate, the insulating film of the MIM capacitor is made to have a desired film thickness, and the gate protective film of the HEMT is made thin to reduce parasitic capacitance. Is desirable.

特開２０１０−１２９６９０号公報JP 2010-129690 A

ゲート電極上の保護膜に起因する寄生容量を低減可能な半導体装置を提供する。   Provided is a semiconductor device capable of reducing parasitic capacitance caused by a protective film on a gate electrode.

実施形態によれば、ＭＩＭキャパシタを有する第１領域と、前記第１領域に隣接し電界効果トランジスタを有する第２領域と、を有する半導体装置であって、基板上に半導体が積層された半導体積層体と、前記第１領域の前記半導体積層体の一部の上面上に設けられた下部電極と、前記第１領域の前記下部電極の表面上及び前記半導体積層体上に設けられた絶縁膜と、前記第２領域の前記半導体積層体上に設けられたソース電極と、前記第２領域の前記半導体積層体上に設けられたドレイン電極と、前記第２領域の前記ソース電極と前記ドレイン電極との間に設けられたゲート電極と、前記絶縁膜の表面上、前記第１領域内の前記半導体積層体上の前記下部電極が堆積されていない部分及び前記第２領域内の前記半導体積層体上の前記ソース電極、前記ドレイン電極又は前記ゲート電極が設けられていない部分に設けられた第１保護膜と、前記下部電極の上方の前記第１保護膜の上面上に設けられた上部電極と、前記上部電極の表面上、前記第１保護膜の表面上、前記ソース電極の表面上、前記ゲート電極の表面上及び前記ドレイン電極の表面上に設けられた第２保護膜と、を備えた半導体装置が提供される。前記半導体の前記第２領域には、少なくとも電子供給層及びチャネル層を含み、前記ゲート電極上の前記第２保護膜の膜厚は、前記下部電極及び前記上部電極との間の、前記絶縁膜の膜厚と前記第１保護膜の膜厚との和よりも小さい。   According to the embodiment, a semiconductor device having a first region having an MIM capacitor and a second region having a field effect transistor adjacent to the first region, wherein the semiconductor is stacked on the substrate. A lower electrode provided on a top surface of a part of the semiconductor stack in the first region, and an insulating film provided on a surface of the lower electrode in the first region and on the semiconductor stack. A source electrode provided on the semiconductor laminate in the second region, a drain electrode provided on the semiconductor laminate in the second region, the source electrode and the drain electrode in the second region, On the surface of the insulating film, on the surface of the semiconductor stack in the first region where the lower electrode is not deposited, and on the semiconductor stack in the second region The source of A first protective film provided on a portion where no electrode, the drain electrode or the gate electrode is provided; an upper electrode provided on an upper surface of the first protective film above the lower electrode; and the upper electrode And a second protective film provided on the surface of the first protective film, on the surface of the source electrode, on the surface of the gate electrode, and on the surface of the drain electrode. Is done. The second region of the semiconductor includes at least an electron supply layer and a channel layer, and the film thickness of the second protective film on the gate electrode is the insulating film between the lower electrode and the upper electrode Smaller than the sum of the thickness of the first protective film and the thickness of the first protective film.

第１の実施形態に係る半導体装置の平面図である。1 is a plan view of a semiconductor device according to a first embodiment. （а）は、図１のА―А線に沿った模式断面図である。（ｂ）は、ゲート電極近傍の寄生容量を説明する回路図である。(A) is a schematic cross-sectional view along the line А-А in FIG. FIG. 5B is a circuit diagram illustrating parasitic capacitance in the vicinity of the gate electrode. （а）は、第１の実施形態に係る半導体装置の製造方法の内、半導体積層体の形成までを説明する模式断面図である。（ｂ）は、第１の実施形態に係る半導体装置の製造方法の内、分離領域の形成を説明する模式断面図である。（ｃ）は、第１の実施形態に係る半導体装置の製造方法の内、下部電極の形成を説明する模式断面図である。（ｄ）は、第１の実施形態に係る半導体装置の製造方法の内、絶縁膜の形成を説明する模式断面図である。(A) is a schematic cross section explaining to the formation of a semiconductor laminated body among the manufacturing methods of the semiconductor device concerning a 1st embodiment. FIG. 5B is a schematic cross-sectional view illustrating the formation of the isolation region in the semiconductor device manufacturing method according to the first embodiment. (C) is a schematic cross section explaining formation of a lower electrode among the manufacturing methods of the semiconductor device concerning a 1st embodiment. FIG. 6D is a schematic cross-sectional view illustrating the formation of the insulating film in the method for manufacturing the semiconductor device according to the first embodiment. （а）は、第１の実施形態に係る半導体装置の製造方法の内、絶縁膜の形成を説明する模式断面図である。（ｂ）は、第１の実施形態に係る半導体装置の製造方法の内、第１保護膜の形成を説明する模式断面図である。（ｃ）は、第１の実施形態に係る半導体装置の製造方法の内、第１保護膜の形成を説明する模式断面図である。(A) is a schematic cross section explaining formation of an insulating film among the manufacturing methods of the semiconductor device concerning a 1st embodiment. FIG. 5B is a schematic cross-sectional view illustrating the formation of the first protective film in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6C is a schematic cross-sectional view illustrating the formation of the first protective film in the method for manufacturing the semiconductor device according to the first embodiment. （а）は、第１の実施形態に係る半導体装置の製造方法の内、オーミック電極の形成を説明する模式断面図である。（ｂ）は、第１の実施形態に係る半導体装置の製造方法の内、ゲート電極の形成を説明する模式断面図である。(A) is a schematic cross section explaining formation of an ohmic electrode among the manufacturing methods of the semiconductor device concerning a 1st embodiment. FIG. 5B is a schematic cross-sectional view illustrating the formation of the gate electrode in the method for manufacturing the semiconductor device according to the first embodiment. （а）は、第１の実施形態に係る半導体装置の製造方法の内、上部電極及びパッド電極の形成を説明する模式断面図である。（ｂ）は、第１の実施形態に係る半導体装置の製造方法の内、第２保護膜の形成を説明する模式断面図である。(A) is a schematic cross section explaining formation of an upper electrode and a pad electrode in a manufacturing method of a semiconductor device concerning a 1st embodiment. FIG. 6B is a schematic cross-sectional view illustrating the formation of a second protective film in the method for manufacturing a semiconductor device according to the first embodiment. 第１の実施形態の比較例に係る半導体装置を説明する模式断面図である。It is a schematic cross section explaining a semiconductor device according to a comparative example of the first embodiment.

以下、図面を参照しつつ、本発明の実施形態について説明する。
（第１の実施形態）
図１は、本実施形態に係る半導体装置の平面図である。
本実施形態に係る半導体装置は、同一基板上にＭＩＭキャパシタ及びＨＥＭＴを形成している。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a plan view of the semiconductor device according to the present embodiment.
In the semiconductor device according to the present embodiment, the MIM capacitor and the HEMT are formed on the same substrate.

先ず、本実施形態に係る半導体装置１００の構成について説明する。
図１に示すように、本実施形態に係る半導体装置１００は、基板１０１上に設けられたＨＥＭＴ１１０を有する。ＨＥＭＴ１１０は、フィンガー形状のソース電極１０７と、フィンガー形状のドレイン電極１０５と、ソース電極１０７とドレイン電極１０５との間のゲート電極１０６と、を有する。さらに、半導体装置１００は、基板１０１上に設けられたＭＩＭキャパシタ１０４を有する。ＭＩＭキャパシタ１０４とＨＥＭＴ１１０との間には、分離領域１０３が設けられている。 First, the configuration of the semiconductor device 100 according to the present embodiment will be described.
As illustrated in FIG. 1, the semiconductor device 100 according to the present embodiment includes a HEMT 110 provided on a substrate 101. The HEMT 110 includes a finger-shaped source electrode 107, a finger-shaped drain electrode 105, and a gate electrode 106 between the source electrode 107 and the drain electrode 105. Further, the semiconductor device 100 includes an MIM capacitor 104 provided on the substrate 101. An isolation region 103 is provided between the MIM capacitor 104 and the HEMT 110.

図２（а）は、図１のА―А線に沿った模式断面図である。
図２に示すように、本実施形態に係る半導体装置１００は、ＭＩＭキャパシタ領域Ｒ１と、ＨＥＭＴ１１０の一部であるＨＥＭＴ領域Ｒ２と、を有する。 FIG. 2A is a schematic cross-sectional view along the line А-А in FIG.
As shown in FIG. 2, the semiconductor device 100 according to the present embodiment includes an MIM capacitor region R <b> 1 and a HEMT region R <b> 2 that is a part of the HEMT 110.

半導体装置１００の最下層には、ＭＩＭキャパシタ領域Ｒ１及びＨＥＭＴ領域Ｒ２の全面に渡って半導体積層体１０１が設けられている。半導体積層体１０１は、基板１０１а、バッファ層１０１ｅ、チャネル層１０１ｂ及び電子供給層１０１ｃがこの順に積層されて形成されている。
バッファ層１０１ｅは、例えば、窒化ガリウム（ＧａＮ）を含む半導体である。チャネル層１０１ｂは、例えば、窒化ガリウムを含む半導体である。電子供給層１０１ｃは、例えば、チャネル層１０１ｂとヘテロ接合を構成し、例えば、Ａｌ０．２Ｇａ０．８Ｎを含む半導体である。 In the lowermost layer of the semiconductor device 100, the semiconductor stacked body 101 is provided over the entire surface of the MIM capacitor region R1 and the HEMT region R2. The semiconductor stacked body 101 is formed by stacking a substrate 101a, a buffer layer 101e, a channel layer 101b, and an electron supply layer 101c in this order.
The buffer layer 101e is a semiconductor containing, for example, gallium nitride (GaN). The channel layer 101b is a semiconductor containing gallium nitride, for example. The electron supply layer 101c is, for example, a semiconductor that forms a heterojunction with the channel layer 101b and includes, for example, Al 0.2 Ga 0.8 N.

電子供給層１０１ｃからチャネル層１０１ｂへ移動した電子は、チャネル層１０１ｂ上に２次元電子ガス層（２ＤＥＧ：two-dimensional electron gas）１０１ｄを形成し、高移動度かつ高密度の電子ガスとなる。
ＭＩＭキャパシタ領域Ｒ１とＨＥＭＴ領域Ｒ２周辺のバッファ層１０１ｅ、チャネル層１０１ｂ及び電子供給層１０１ｃは、イオン注入などにより高抵抗化された分離領域１０３が設けられている。これにより、ＨＥＭＴ領域Ｒ２において、電子供給層１０１ｃからチャネル層１０１ｂへ移動した電子が、ＭＩＭキャパシタなどの他の回路要素に漏れることを抑制することができる。 The electrons that have moved from the electron supply layer 101c to the channel layer 101b form a two-dimensional electron gas layer (2DEG) 101d on the channel layer 101b, and become a high mobility and high density electron gas.
The buffer layer 101e, the channel layer 101b, and the electron supply layer 101c around the MIM capacitor region R1 and the HEMT region R2 are provided with an isolation region 103 whose resistance is increased by ion implantation or the like. Thereby, in the HEMT region R2, it is possible to suppress leakage of electrons that have moved from the electron supply layer 101c to the channel layer 101b to other circuit elements such as an MIM capacitor.

ＭＩＭキャパシタ領域Ｒ１内においては、半導体積層体１０１の一部の上面上に下部電極１２１が設けられている。下部電極１２１の表面上及び半導体積層体１０１の一部の上面上に絶縁膜１２２が設けられている。   In the MIM capacitor region R1, a lower electrode 121 is provided on a part of the upper surface of the semiconductor stacked body 101. An insulating film 122 is provided on the surface of the lower electrode 121 and on a part of the upper surface of the semiconductor stacked body 101.

ＨＥＭＴ領域Ｒ２内においては、半導体積層体１０１上にＭＩＭキャパシタ領域Ｒ１側から順に、ソース電極１０７、ゲート電極１０６及びドレイン電極１０５が設けられている。   In the HEMT region R2, a source electrode 107, a gate electrode 106, and a drain electrode 105 are provided on the semiconductor stacked body 101 in order from the MIM capacitor region R1 side.

ＭＩＭキャパシタ領域Ｒ１の絶縁膜１２２の表面上と半導体積層体１０１上、及びＨＥＭＴ領域Ｒ２のソース電極１０７、ドレイン電極１０５又はゲート電極１０６が設けられていない半導体積層体１０１上の部分に、第１保護膜１０２が設けられている。   On the surface of the insulating film 122 in the MIM capacitor region R1 and the semiconductor stacked body 101, and on the semiconductor stacked body 101 where the source electrode 107, the drain electrode 105, or the gate electrode 106 of the HEMT region R2 is not provided, the first A protective film 102 is provided.

下部電極１２１の上方の第１保護膜１０２の上面上に上部電極１２３が設けられている。上部電極１２３の表面上、電極が堆積されていない第１保護膜１０２の表面上、ソース電極１０７の表面上、ゲート電極１０６の表面上、及び、ドレイン電極１０５の表面上に第２保護膜１１２が設けられている。   An upper electrode 123 is provided on the upper surface of the first protective film 102 above the lower electrode 121. The second protective film 112 is formed on the surface of the upper electrode 123, on the surface of the first protective film 102 where no electrode is deposited, on the surface of the source electrode 107, on the surface of the gate electrode 106, and on the surface of the drain electrode 105. Is provided.

ソース電極１０７の一部は、境界面１３１を介して第１保護膜１０２と隣接している。ソース電極１０７は、半導体積層体１０１上に設けられたオーミック電極１１８及びその上に設けられたパッド電極１１９とから形成されている。パッド電極１１９のソース電極１０７からドレイン電極１０５へ向かう方向の長さは、オーミック電極１１８のＭＩＭキャパシタ領域Ｒ１からＨＥＭＴ領域Ｒ２へ向かう方向の長さよりも小さく、紙面に垂直な方向から見て凸型をしている。パッド電極１１９は、ソース電極１０７への配線抵抗値を低くするために設けられている。   A part of the source electrode 107 is adjacent to the first protective film 102 through the boundary surface 131. The source electrode 107 is formed of an ohmic electrode 118 provided on the semiconductor stacked body 101 and a pad electrode 119 provided thereon. The length of the pad electrode 119 in the direction from the source electrode 107 to the drain electrode 105 is smaller than the length of the ohmic electrode 118 in the direction from the MIM capacitor region R1 to the HEMT region R2, and is convex when viewed from the direction perpendicular to the paper surface. I am doing. The pad electrode 119 is provided to reduce the wiring resistance value to the source electrode 107.

ゲート電極１０６は、半導体積層体１０１上に設けられたゲート電極下部１０８及びその上に設けられたゲート電極上部１０９とから形成されている。ゲート電極上部１０９のソース電極１０７からドレイン電極１０５へ向かう方向の長さは、ゲート電極下部１０８のソース電極１０７からドレイン電極１０５へ向かう方向の長さよりも大きく、紙面に垂直な方向から見て略Ｔ字型をしている。ゲート電極上部１０９は、ゲート電極下部１０８への配線抵抗値を低くするために設けられている。   The gate electrode 106 is formed of a gate electrode lower portion 108 provided on the semiconductor stacked body 101 and a gate electrode upper portion 109 provided thereon. The length of the gate electrode upper portion 109 in the direction from the source electrode 107 to the drain electrode 105 is larger than the length of the gate electrode lower portion 108 in the direction from the source electrode 107 to the drain electrode 105, and is substantially as viewed from the direction perpendicular to the paper surface. T-shaped. The gate electrode upper portion 109 is provided to reduce the wiring resistance value to the gate electrode lower portion 108.

ドレイン電極１０５は、半導体積層体１０１上に設けられたオーミック電極１２８及びその上に設けられたパッド電極１２９とから形成されている。パッド電極１２９のソース電極１０７からドレイン電極１０５へ向かう方向の長さは、オーミック電極１２８のソース電極１０７からドレイン電極１０５へ向かう方向の長さよりも小さく、紙面に垂直な方向から見て凸型をしている。パッド電極１２９は、ドレイン電極１０５への配線抵抗値を低くするために設けられている。
下部電極１２１、上部電極１２３、分離領域１０３、ソース電極１０７、ゲート電極１０６及びドレイン電極１０５は、紙面に垂直な方向に延びている。 The drain electrode 105 is formed of an ohmic electrode 128 provided on the semiconductor stacked body 101 and a pad electrode 129 provided thereon. The length of the pad electrode 129 in the direction from the source electrode 107 to the drain electrode 105 is smaller than the length of the ohmic electrode 128 in the direction from the source electrode 107 to the drain electrode 105, and has a convex shape when viewed from the direction perpendicular to the paper surface. doing. The pad electrode 129 is provided to reduce the wiring resistance value to the drain electrode 105.
The lower electrode 121, the upper electrode 123, the separation region 103, the source electrode 107, the gate electrode 106, and the drain electrode 105 extend in a direction perpendicular to the paper surface.

ソース電極１０７の膜厚は、ドレイン電極１０５の膜厚と同程度である。ゲート電極１０６の膜厚は、ソース電極１０７の膜厚よりも薄い。
第１保護膜１０２の膜厚ｔ１０２は、例えば、２００〜５００Åである。
オーミック電極１１８の膜厚は、オーミック電極１２８の膜厚と同程度であり、第１保護膜１０２の膜厚よりも厚い。
ゲート電極１０６上の第２保護膜１１２の膜厚ｔ１０３は、例えば、５００Åである。
下部電極１２１と上部電極１２３に挟まれた絶縁膜１２２の膜厚ｔ１０１と第１保護膜１０２の膜厚ｔ１０２との合計の膜厚は、ゲート電極１０６上の第２保護膜１１２の膜厚ｔ１０３よりも厚く、例えば、２０００Åである。
なお、本実施形態に係る半導体装置１００においては、ＭＩＭキャパシタ１０４が１個設けられている例を示したが、これには限定されない。 The thickness of the source electrode 107 is approximately the same as the thickness of the drain electrode 105. The gate electrode 106 is thinner than the source electrode 107.
The film thickness t102 of the first protective film 102 is, for example, 200 to 500 mm.
The film thickness of the ohmic electrode 118 is approximately the same as the film thickness of the ohmic electrode 128 and is thicker than the film thickness of the first protective film 102.
The film thickness t103 of the second protective film 112 on the gate electrode 106 is, for example, 500 mm.
The total thickness of the film thickness t101 of the insulating film 122 sandwiched between the lower electrode 121 and the upper electrode 123 and the film thickness t102 of the first protective film 102 is the film thickness t103 of the second protective film 112 on the gate electrode 106. It is thicker, for example 2000 mm.
In the semiconductor device 100 according to the present embodiment, an example in which one MIM capacitor 104 is provided is shown, but the present invention is not limited to this.

次に、本実施形態に係る半導体装置１００の製造方法について説明する。
図３（а）は、本実施形態に係る半導体装置の製造方法の内、基板１０１の形成までを説明する模式断面図である。
先ず、基板１０１а上に、バッファ層１０１ｅ、チャネル層１０１ｂ及び電子供給層１０１ｃをＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition)法やＭＢＥ(EMolecular Beam Epitaxy)法などを用いて、この順番に積層し形成する。 Next, a method for manufacturing the semiconductor device 100 according to the present embodiment will be described.
FIG. 3A is a schematic cross-sectional view illustrating the process up to the formation of the substrate 101 in the semiconductor device manufacturing method according to the present embodiment.
First, the buffer layer 101e, the channel layer 101b, and the electron supply layer 101c are laminated and formed in this order on the substrate 101a using the MOCVD (Metal Organic Chemical Vapor Deposition) method, the MBE (EMolecular Beam Epitaxy) method, or the like.

図３（ｂ）は、本実施形態に係る半導体装置の製造方法の内、分離領域１０３の形成を説明する模式断面図である。
バッファ層１０１ｅ、チャネル層１０１ｂ及び電子供給層１０１ｃが窒化ガリウムを含む半導体で形成されている場合には、例えば、アルゴン（Аｒ）イオンなどを所望の部分に注入して分離領域１０３を形成する。 FIG. 3B is a schematic cross-sectional view for explaining the formation of the isolation region 103 in the semiconductor device manufacturing method according to the present embodiment.
When the buffer layer 101e, the channel layer 101b, and the electron supply layer 101c are formed of a semiconductor containing gallium nitride, for example, argon (Аr) ions or the like are implanted into a desired portion to form the isolation region 103.

なお、分離領域１０３は、リソグラフィにより除去する範囲を特定し、エッチングを施すことにより半導体積層体１０１の一部を選択的に除去した後、除去した部分に、例えば、シリコン窒化物（ＳｉＮ）などの絶縁材料を埋め込んで形成してもよい。   Note that the isolation region 103 specifies a range to be removed by lithography, and after selectively removing a part of the semiconductor stacked body 101 by performing etching, the removed portion includes, for example, silicon nitride (SiN) or the like. Alternatively, the insulating material may be embedded.

図３（ｃ）は、本実施形態に係る半導体装置の製造方法の内、下部電極１２１の形成を説明する模式断面図である。
ＭＩＭキャパシタ領域Ｒ１の半導体積層体１０１の一部の上面上に、例えば、チタン（Ｔｉ）、ニッケル（Ｎｉ）をこの順番で蒸着して下部電極１２１を形成する。また、例えば、ニッケル（Ｎｉ）に代わってプラチナ（Ｐｔ）を使用してもよい。 FIG. 3C is a schematic cross-sectional view illustrating the formation of the lower electrode 121 in the method for manufacturing the semiconductor device according to the present embodiment.
For example, titanium (Ti) and nickel (Ni) are vapor-deposited in this order on the upper surface of a part of the semiconductor stacked body 101 in the MIM capacitor region R1 to form the lower electrode 121. Further, for example, platinum (Pt) may be used instead of nickel (Ni).

図３（ｄ）は、本実施形態に係る半導体装置の製造方法の内、絶縁膜１７２の形成を説明する模式断面図である。
ウエハ全面、つまり半導体積層体１０１の上面上及び下部電極１２１の表面上に、例えば、シリコン窒化物（ＳｉＮ）を堆積して絶縁膜１７２を形成する。このとき、下部電極１２１上の絶縁膜１７２の膜厚は、所望の耐圧が得られる程度の膜厚で形成する。 FIG. 3D is a schematic cross-sectional view illustrating the formation of the insulating film 172 in the semiconductor device manufacturing method according to the present embodiment.
For example, silicon nitride (SiN) is deposited on the entire surface of the wafer, that is, on the upper surface of the semiconductor stacked body 101 and the surface of the lower electrode 121 to form an insulating film 172. At this time, the insulating film 172 over the lower electrode 121 is formed to have a thickness enough to obtain a desired withstand voltage.

図４（а）は、本実施形態に係る半導体装置の製造方法の内、絶縁膜１２２の形成を説明する模式断面図である。
リソグラフィにより除去する範囲を特定し、エッチングを施すことにより絶縁膜１７２を選択的に除去し、絶縁膜１２２を形成する。絶縁膜１７２の残部である絶縁膜１２２の膜厚は、下部電極１２１上の絶縁膜１７２の膜厚を維持する。 FIG. 4A is a schematic cross-sectional view illustrating the formation of the insulating film 122 in the semiconductor device manufacturing method according to the present embodiment.
A region to be removed is specified by lithography, and etching is performed to selectively remove the insulating film 172 and form the insulating film 122. The film thickness of the insulating film 122 which is the remaining part of the insulating film 172 maintains the film thickness of the insulating film 172 over the lower electrode 121.

図４（ｂ）は、本実施形態に係る半導体装置の製造方法の内、第１保護膜１５２の形成を説明する模式断面図である。
ウエハ全面、つまり半導体積層体１０１の上面上、分離領域１０３上面上及び絶縁膜１２２の表面上に、例えば、シリコン窒化物（ＳｉＮ）を堆積して絶縁膜１５２を形成する。絶縁膜１５２の膜厚ｔ１０２は、例えば、２００〜５００Åである。 FIG. 4B is a schematic cross-sectional view illustrating the formation of the first protective film 152 in the semiconductor device manufacturing method according to the present embodiment.
An insulating film 152 is formed by depositing, for example, silicon nitride (SiN) on the entire wafer surface, that is, on the upper surface of the semiconductor stacked body 101, the upper surface of the isolation region 103, and the surface of the insulating film 122. The film thickness t102 of the insulating film 152 is, for example, 200 to 500 mm.

図４（ｃ）は、本実施形態に係る半導体装置の製造方法の内、第１保護膜１０２の形成を説明する模式断面図である。
ＨＥＭＴ領域Ｒ２内の絶縁膜１５２において、リソグラフィにより除去する範囲を特定し、エッチングを施すことにより絶縁膜１５２を選択的に除去する。残部を第１保護膜１０２とする。また、除去された部分をＭＩＭキャパシタ領域Ｒ１側から順番に開口部１６１、１６２及び１６３とする。 FIG. 4C is a schematic cross-sectional view illustrating the formation of the first protective film 102 in the method for manufacturing a semiconductor device according to the present embodiment.
In the insulating film 152 in the HEMT region R2, a range to be removed by lithography is specified, and the insulating film 152 is selectively removed by performing etching. The remainder is the first protective film 102. In addition, the removed portions are defined as openings 161, 162, and 163 in order from the MIM capacitor region R1 side.

図５（а）は、本実施形態に係る半導体装置の製造方法の内、オーミック電極１１８及びオーミック電極１２８の形成を説明する模式断面図である。
半導体積層体１０１上の開口部１６１内に、例えば、アルミニウム（Аｌ）、チタン（Ｔｉ）、プラチナ（Ｐｔ）、金（Аｕ）をこの順番で蒸着してオーミック電極１１８を形成する。同時に、開口部１６３内に、例えば、アルミニウム、チタン、プラチナ、金をこの順番で蒸着してオーミック電極１２８が形成される。その後、約６００℃から約７００℃でアニール処理を行う。 FIG. 5A is a schematic cross-sectional view illustrating the formation of the ohmic electrode 118 and the ohmic electrode 128 in the method for manufacturing the semiconductor device according to the present embodiment.
In the opening 161 on the semiconductor stacked body 101, for example, aluminum (Аl), titanium (Ti), platinum (Pt), and gold (Аu) are deposited in this order to form the ohmic electrode 118. At the same time, for example, aluminum, titanium, platinum, and gold are vapor-deposited in this order in the opening 163 to form the ohmic electrode 128. Thereafter, annealing is performed at about 600 ° C. to about 700 ° C.

図５（ｂ）は、本実施形態に係る半導体装置の製造方法の内、ゲート電極１０６の形成を説明する模式断面図である。
半導体積層体１０１上の開口部１６２内に、例えば、ニッケル（Ｎｉ）、金（Аｕ）を蒸着してゲート電極下部１０８及びゲート電極上部１０９からなるゲート電極１０６を形成する。 FIG. 5B is a schematic cross-sectional view illustrating the formation of the gate electrode 106 in the semiconductor device manufacturing method according to the present embodiment.
In the opening 162 on the semiconductor stacked body 101, for example, nickel (Ni) and gold (Аu) are deposited to form the gate electrode 106 including the gate electrode lower part 108 and the gate electrode upper part 109.

図６（а）は、本実施形態に係る半導体装置の製造方法の内、上部電極１２３、パッド電極１１９及びパッド電極１２９の形成を説明する模式断面図である。
下部電極１２１の上方の第１保護膜１０２上に金属を蒸着して上部電極１２３を形成する。同時に、オーミック電極１１８、１２８の一部の上面上に金属を蒸着してパッド電極１１９、１２９を形成し、オーミック電極１１８、１２８とパッド電極１１９、１２９からなるソース電極１０７とドレイン電極１０５を形成する。 FIG. 6A is a schematic cross-sectional view illustrating the formation of the upper electrode 123, the pad electrode 119, and the pad electrode 129 in the semiconductor device manufacturing method according to this embodiment.
An upper electrode 123 is formed by depositing metal on the first protective film 102 above the lower electrode 121. At the same time, metal is vapor-deposited on a part of the upper surface of the ohmic electrodes 118 and 128 to form the pad electrodes 119 and 129, and the source electrode 107 and the drain electrode 105 including the ohmic electrodes 118 and 128 and the pad electrodes 119 and 129 are formed. To do.

図６（ｂ）は、本実施形態に係る半導体装置の製造方法の内、第２保護膜１１２の形成を説明する模式断面図である。
ウエハ全面、つまりＭＩＭキャパシタ領域Ｒ１及びＨＥＭＴ領域Ｒ２の全表面上に、例えば、シリコン窒化物を堆積して第２保護膜１１２を形成する。このとき、ゲート電極１０６上の第２保護膜１１２により発生する寄生容量Ｃ１２の影響を小さくするため、第２保護膜１１２は薄く形成する。第２保護膜１１２の膜厚ｔ１０３は、例えば、５００Åである。 FIG. 6B is a schematic cross-sectional view illustrating the formation of the second protective film 112 in the semiconductor device manufacturing method according to the present embodiment.
For example, silicon nitride is deposited on the entire surface of the wafer, that is, the entire surface of the MIM capacitor region R1 and the HEMT region R2, to form the second protective film 112. At this time, in order to reduce the influence of the parasitic capacitance C12 generated by the second protective film 112 on the gate electrode 106, the second protective film 112 is formed thin. The film thickness t103 of the second protective film 112 is, for example, 500 mm.

次に、本実施形態に係る半導体装置１００の動作について説明する。
図２（а）に示すように、ＭＩＭキャパシタ領域Ｒ１においては、下部電極１２１及び上部電極１２３と、それらの間に挟まれた絶縁膜１２２及び第１保護膜１０２により、コンデンサＣ１１が形成されている。絶縁膜１２２の膜厚ｔ１０１と第１絶縁膜の膜厚ｔ１０２の合計の膜厚を大きくすると、コンデンサＣ１１の耐圧Ｖ１１は高くなり、単位面積当たりの容量値は低くなる。膜厚と電極面積により容量を所望の値に合わせる。 Next, the operation of the semiconductor device 100 according to this embodiment will be described.
As shown in FIG. 2A, in the MIM capacitor region R1, a capacitor C11 is formed by the lower electrode 121 and the upper electrode 123, and the insulating film 122 and the first protective film 102 sandwiched therebetween. Yes. When the total film thickness t101 of the insulating film 122 and the film thickness t102 of the first insulating film is increased, the withstand voltage V11 of the capacitor C11 increases and the capacitance value per unit area decreases. The capacity is adjusted to a desired value by the film thickness and the electrode area.

第１保護膜１０２は、同程度の膜厚のままＨＥＭＴ領域Ｒ２まで延びているので、膜厚ｔ１０２を一定とし、膜厚ｔ１０１を変化させて所望の耐圧を得た方がよい。   Since the first protective film 102 extends to the HEMT region R2 with the same film thickness, it is preferable to obtain a desired breakdown voltage by changing the film thickness t101 while keeping the film thickness t102 constant.

ＨＥＭＴ領域Ｒ２においては、ゲート電極１０６上の第２保護膜１１２により寄生容量Ｃ１２が発生する。図２（ｂ）に示すように、寄生容量Ｃ１２は、ゲートＧ・ドレインＤ間容量Ｃｇｄ、ゲートＧ・ソースＳ間容量Ｃｇｓ及びドレインＤ・ソースＳ間容量Ｃｄｓを含む。寄生容量Ｃ１２の容量値は、第２保護膜１１２の膜厚ｔ１０３により変化する。膜厚ｔ１０３を厚く形成すると寄生容量Ｃ１２が大きくなり、半導体装置１００の利得や効率が低下する。 In the HEMT region R2, a parasitic capacitance C12 is generated by the second protective film 112 on the gate electrode. As shown in FIG. 2B, the parasitic capacitance C12 includes a gate C / drain D capacitance C gd , a gate G / source S capacitance C gs, and a drain D / source S capacitance C ds . The capacitance value of the parasitic capacitance C12 varies depending on the film thickness t103 of the second protective film 112. When the film thickness t103 is formed thick, the parasitic capacitance C12 increases, and the gain and efficiency of the semiconductor device 100 decrease.

そこで、本実施形態に係る半導体装置１００においては、絶縁膜１２２の膜厚ｔ１０１と第１保護膜１０２の膜厚ｔ１０２の合計の膜厚を、所望の耐圧が得られる膜厚以上の膜厚で形成する。これを満たす膜厚ｔ１０１と膜厚ｔ１０２の合計の膜厚は、例えば、２０００Å程度であり、このときの耐圧は、約１００Ｖである。
膜厚ｔ１０３は薄く形成し、寄生容量Ｃ１２による高周波特性の低下を抑制する。例えば、膜厚ｔ１０３を、膜厚ｔ１０１よりも薄く形成する。第２保護膜１１２の膜厚ｔ１０３は、例えば、５００Åである。 Therefore, in the semiconductor device 100 according to the present embodiment, the total thickness of the film thickness t101 of the insulating film 122 and the film thickness t102 of the first protective film 102 is a film thickness that is equal to or greater than a film thickness that provides a desired breakdown voltage. Form. The total film thickness of the film thickness t101 and the film thickness t102 satisfying this is, for example, about 2000 mm, and the withstand voltage at this time is about 100V.
The film thickness t103 is formed thin and suppresses a decrease in high frequency characteristics due to the parasitic capacitance C12. For example, the film thickness t103 is formed thinner than the film thickness t101. The film thickness t103 of the second protective film 112 is, for example, 500 mm.

次に、本実施形態に係る半導体装置１００の効果について説明する。
本実施形態に係る半導体装置１００においては、絶縁膜１２２の膜厚ｔ１０１を、所望の耐圧が得られる膜厚以上の膜厚で形成している。また、第２保護膜１１２の膜厚ｔ１０３を薄く形成している。 Next, effects of the semiconductor device 100 according to the present embodiment will be described.
In the semiconductor device 100 according to the present embodiment, the film thickness t101 of the insulating film 122 is formed with a film thickness equal to or larger than a film thickness at which a desired breakdown voltage can be obtained. Further, the thickness t103 of the second protective film 112 is formed thin.

これにより、ＨＥＭＴ領域Ｒ２においては、ゲート電極１０６上の第２保護膜１２２に起因する寄生容量Ｃ１２を低減可能な半導体装置を提供することができる。例えば、寄生容量Ｃ１２が２０％低下すると、半導体装置１００の利得は１ｄＢ増加する。また、ＭＩＭキャパシタ領域Ｒ１においては、所望の耐圧を確保することができる。   Thereby, in the HEMT region R2, a semiconductor device that can reduce the parasitic capacitance C12 caused by the second protective film 122 on the gate electrode 106 can be provided. For example, when the parasitic capacitance C12 decreases by 20%, the gain of the semiconductor device 100 increases by 1 dB. Further, a desired breakdown voltage can be ensured in the MIM capacitor region R1.

なお、本実施形態に係る半導体装置１００においては、ＨＥＭＴが設けられている例を示したが、これには限定されず、ＨＥＭＴ以外の電界効果トランジスタでもよい。   In the semiconductor device 100 according to the present embodiment, an example in which a HEMT is provided is shown, but the present invention is not limited to this, and a field effect transistor other than a HEMT may be used.

（第１の実施形態の比較例）
図７は、本比較例に係る半導体装置を説明する模式断面図である。
図７に示すように、本比較例に係る半導体装置２００は、前述の第１の実施形態と比べて、絶縁膜２１１がＨＥＭＴ領域Ｒ２まで延びている点が異なっている。これにより、下部電極２２１上の絶縁膜２１１の膜厚ｔ２０２と、ゲート電極２０６上の絶縁膜２１１の膜厚ｔ２０３及び第２保護膜２１２の膜厚ｔ２０５の合計の膜厚が同程度の膜厚となっている。 (Comparative example of the first embodiment)
FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device according to this comparative example.
As shown in FIG. 7, the semiconductor device 200 according to this comparative example is different from the first embodiment described above in that the insulating film 211 extends to the HEMT region R2. Thus, the film thickness t202 of the insulating film 211 on the lower electrode 221 is approximately equal to the total film thickness of the film thickness t203 of the insulating film 211 on the gate electrode 206 and the film thickness t205 of the second protective film 212. It has become.

ＭＩＭキャパシタ領域Ｒ１における絶縁膜２１１の膜厚ｔ２０２を、所望の耐圧が得られる程の膜厚で形成した場合には、ＨＥＭＴ領域Ｒ２におけるゲート電極２０６上の絶縁膜２１１の膜厚ｔ２０３もｔ２０２と同程度の膜厚となり、これにより発生した寄生容量Ｃ２２による影響が大きくなる。一方、寄生容量Ｃ２２による影響を小さくするため、膜厚ｔ２０３を薄く形成した場合には、ＨＥＭＴ領域Ｒ２において、所望の耐圧を得ることが難しくなる。   When the film thickness t202 of the insulating film 211 in the MIM capacitor region R1 is formed to such a thickness that a desired breakdown voltage can be obtained, the film thickness t203 of the insulating film 211 on the gate electrode 206 in the HEMT region R2 is also t202. The film thickness is about the same, and the influence of the parasitic capacitance C22 generated thereby becomes large. On the other hand, when the film thickness t203 is formed thin in order to reduce the influence of the parasitic capacitance C22, it is difficult to obtain a desired breakdown voltage in the HEMT region R2.

すなわち、本比較例に係る半導体装置２００においては、ＭＩＭキャパシタ領域Ｒ１において所望の耐圧を確保し、ＨＥＭＴ領域Ｒ２においてゲート電極上の保護膜に起因する寄生容量を低減することは難しい。   That is, in the semiconductor device 200 according to this comparative example, it is difficult to secure a desired breakdown voltage in the MIM capacitor region R1 and reduce the parasitic capacitance caused by the protective film on the gate electrode in the HEMT region R2.

これに対して第１の実施形態によれば、ゲート電極上の保護膜に起因する寄生容量を低減可能として高周波特性を高めると共に、回路構成上必要なＭＩＭキャパシタの容量を有する半導体装置を提供することができる。従って、第１の実施形態に係る半導体装置は、レーダー装置やマイクロ波通信機器に広く用いることができる。   On the other hand, according to the first embodiment, there is provided a semiconductor device that can reduce the parasitic capacitance caused by the protective film on the gate electrode to improve the high frequency characteristics and have the capacitance of the MIM capacitor necessary for the circuit configuration. be able to. Therefore, the semiconductor device according to the first embodiment can be widely used for radar devices and microwave communication devices.

以上、本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明及びその等価物の範囲に含まれる。   As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalents thereof.

１００、２００ 半導体装置、１０１、２０１ 積層体、１０１а 基板、１０１ｂ チャネル層、１０１ｃ 電子供給層、１０１ｄ ２次元電子ガス層、１０１ｅ バッファ層、１０２、２０２ 第１保護膜、１０３ 分離領域、１０４ ＭＩＭキャパシタ、１１０ ＨＥＭＴ、１０５、２０５ ドレイン電極、１０６、２０６ ゲート電極、１０７、２０７ ソース電極、１０８、２０８ ゲート電極下部、１０９、２０９ ゲート電極上部、１１８、１２８ オーミック電極、１１９、１２９ パッド電極、１１２、２１２ 第２保護膜、１２１、２２１ 下部電極、１２２、２２１ 絶縁膜、１２３、２２３ 上部電極、１３１、２３１ 境界面、１３２、２３２ 端面、１３３、２３３ 端面、１５２、１７２ 絶縁膜、Ｒ１ ＭＩＭキャパシタ領域、Ｒ２ ＨＥＭＴ領域、Ｃ１１ コンデンサ、Ｃ１２、Ｃ２２ 寄生容量、Ｃｇｄ ゲート・ドレイン間容量、Ｃｇｓ ゲート・ソース間容量、Ｃｄｓ ドレイン・ソース間容量、Ｇ ゲート、Ｄ ドレイン、Ｓ ソース、ｔ１０１、ｔ１０２、ｔ１０３、ｔ２０２、ｔ２０３、ｔ２０５ 膜厚、Ｖ１１ 耐圧 100, 200 Semiconductor device, 101, 201 Laminate, 101a substrate, 101b channel layer, 101c electron supply layer, 101d two-dimensional electron gas layer, 101e buffer layer, 102, 202 first protective film, 103 isolation region, 104 MIM capacitor 110 HEMT, 105, 205 Drain electrode, 106, 206 Gate electrode, 107, 207 Source electrode, 108, 208 Lower gate electrode, 109, 209 Upper gate electrode, 118, 128 Ohmic electrode, 119, 129 Pad electrode, 112, 212 Second protective film, 121, 221 Lower electrode, 122, 221 Insulating film, 123, 223 Upper electrode, 131, 231 Interface, 132, 232 End face, 133, 233 End face, 152, 172 Insulating film, R1 MIM capacitor region , R2 HEMT region C11 capacitor, C12, C22 parasitic capacitance, C gd gate-drain capacitance, C gs the gate-source capacitance, C ds drain-source capacitance, G gate, D a drain, S source, t101, t102, t103, t202 , t203, t205 film thickness, V11 breakdown voltage

Claims (7)

ＭＩＭキャパシタを有する第１領域と、前記第１領域に隣接し電界効果トランジスタを有する第２領域と、を有する半導体装置であって、
基板上に半導体が積層された半導体積層体と、
前記第１領域の前記半導体積層体の一部の上面上に設けられた下部電極と、
前記第１領域の前記下部電極の表面上及び前記半導体積層体上に設けられた絶縁膜と、
前記第２領域の前記半導体積層体上に設けられたソース電極と、
前記第２領域の前記半導体積層体上に設けられたドレイン電極と、
前記第２領域の前記ソース電極と前記ドレイン電極との間に設けられたゲート電極と、
前記絶縁膜の表面上、前記第１領域内の前記半導体積層体上の前記下部電極が堆積されていない部分及び前記第２領域内の前記半導体積層体上の前記ソース電極、前記ドレイン電極又は前記ゲート電極が設けられていない部分に設けられた第１保護膜と、
前記下部電極の上方の前記第１保護膜の上面上に設けられた上部電極と、
前記上部電極の表面上、前記第１保護膜の表面上、前記ソース電極の表面上、前記ゲート電極の表面上及び前記ドレイン電極の表面上に設けられた第２保護膜と、
を備え、
前記半導体の前記第２領域には、少なくとも電子供給層及びチャネル層を含み、
前記ゲート電極上の前記第２保護膜の膜厚は、前記下部電極及び前記上部電極との間の、前記絶縁膜の膜厚と前記第１保護膜の膜厚との和よりも小さい半導体装置。 A semiconductor device comprising: a first region having an MIM capacitor; and a second region having a field effect transistor adjacent to the first region,
A semiconductor laminate in which a semiconductor is laminated on a substrate;
A lower electrode provided on an upper surface of a part of the semiconductor stacked body in the first region;
An insulating film provided on a surface of the lower electrode in the first region and on the semiconductor stacked body;
A source electrode provided on the semiconductor laminate in the second region;
A drain electrode provided on the semiconductor laminate in the second region;
A gate electrode provided between the source electrode and the drain electrode in the second region;
On the surface of the insulating film, the portion where the lower electrode on the semiconductor stacked body in the first region is not deposited and the source electrode, the drain electrode, or the above on the semiconductor stacked body in the second region A first protective film provided in a portion where the gate electrode is not provided;
An upper electrode provided on the upper surface of the first protective film above the lower electrode;
A second protective film provided on the surface of the upper electrode, on the surface of the first protective film, on the surface of the source electrode, on the surface of the gate electrode, and on the surface of the drain electrode;
With
The second region of the semiconductor includes at least an electron supply layer and a channel layer,
The thickness of the second protective film on the gate electrode is smaller than the sum of the thickness of the insulating film and the thickness of the first protective film between the lower electrode and the upper electrode. . 前記基板上の前記第１領域と前記第２領域との間に設けられた分離領域をさらに備えた請求項１記載の半導体装置。   The semiconductor device according to claim 1, further comprising an isolation region provided between the first region and the second region on the substrate. 前記分離領域は、イオンの注入により形成された請求項２記載の半導体装置。   The semiconductor device according to claim 2, wherein the isolation region is formed by ion implantation. 前記基板と前記半導体との間に設けられたバッファ層をさらに備えた請求項１記載の半導体装置。   The semiconductor device according to claim 1, further comprising a buffer layer provided between the substrate and the semiconductor. 前記第１保護膜又は前記第２保護膜のうち少なくとも一方は、シリコン窒化物を含む請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein at least one of the first protective film and the second protective film contains silicon nitride. 前記絶縁膜の膜厚と前記第１保護膜の膜厚との合計の膜厚は、２０００オングストローム以下である請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a total thickness of the insulating film and the first protective film is 2000 angstroms or less. 前記第２保護膜の膜厚は、５００オングストローム以下である請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the thickness of the second protective film is 500 angstroms or less.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021090657A1 (en) * 2019-11-05 2021-05-14 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device and electronic apparatus
WO2021146229A1 (en) * 2020-01-14 2021-07-22 Cree, Inc. Group iii hemt and capacitor that share structural features

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021090657A1 (en) * 2019-11-05 2021-05-14 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device and electronic apparatus
WO2021146229A1 (en) * 2020-01-14 2021-07-22 Cree, Inc. Group iii hemt and capacitor that share structural features
US11257940B2 (en) 2020-01-14 2022-02-22 Cree, Inc. Group III HEMT and capacitor that share structural features
CN115244683A (en) * 2020-01-14 2022-10-25 沃孚半导体公司 Group III HEMTs and capacitors sharing structural features

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